# Power MOSFET, N Channel, 24 V, 240 A, 1160 µohm, TO-262, Through Hole

![Product image](https://novapart.co/image/farnell:2148049/)

**URL**: https://novapart.co/products/AUIRF1324WL../power-mosfet-n-channel-24-v-240-a-1160-ohm-to-262
**SKU**: AUIRF1324WL..
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.4400
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:240A; Drain Source Voltage Vds:24V; On Resistance Rds(on):0.00116ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2V; Pow

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | AEC-Q101 |
| Power Dissipation | 300W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-262 |
| Drain Source Voltage Vds | 24V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 240A |
| Drain Source On State Resistance | 1160µohm |
| Gate Source Threshold Voltage Max | 2V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2148049/)

## **AUTOMOTIVE GRADE** 

AUIRF1324WL HEXFET ® Power MOSFET 

## **Features** 

Advanced Process Technology 

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D V(BR)DSS 24V<br>RDS(on)   typ. | 1.16m <br>              max. 1.30m <br>G Pe<br>ID (Silicon Limited)D (Silicon Limited)(Silicon Limited)Silicon Limited)) 382A<br>S ID (Package Limited)D (Package Limited)(Package Limited)Package Limited)ge Limited)e Limited)) 240A<br>**----- End of picture text -----**<br>


- Ultra Low On-Resistance 50% Lower Lead Resistance 

175°C Operating Temperature G **max. 1.30m**  ~~e~~ Fast Switching **ID (Silicon Limited)D (Silicon Limited)(Silicon Limited)Silicon Limited)) 382A** ~~:~~ Repetitive Avalanche Allowed up to Tjmax S **ID (Package Limited)D (Package Limited)(Package Limited)Package Limited)ge Limited)e Limited)) 240A** ~~e~~ Lead-Free, RoHS Compliant ~~e~~ Automotive Qualified * 

## **Description** 

Specifically design for automotive applications this Widelead TO262 package part has the advantage of having over 50% lower lead resistance and delivering over 20% lower Rds(on) when compared with a traditional TO-262 package housing the same silicon die. This greatly helps in reducing condition losses, achieving higher current levels or enabling a system to run cooler and have improved efficiency. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive and other applications. 

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G D S<br>Gate Drain Source<br>**----- End of picture text -----**<br>


## **Absolute Maximum Ratings** 

unctional operation of the device at these or any other condition beyond those 

indicated in the specifications is not implied. 

||**Parameter**|**Max.**|**Units**|
|---|---|---|---|
|ID @ TC = 25°C|Continuous Drain Current,VGS@ 10V(Silicon Limited)<br>~~©~~|382<br>~~©~~|A|
|ID @ TC = 100°C<br>~~Pe~~|Continuous Drain Current,VGS@ 10V(Silicon Limited)<br>~~eT~~<br>~~Pe~~|270<br>~~eT~~||
|ID @ TC = 25°C<br>~~Pe~~<br>~~**a**~~|Continuous Drain Current,VGS@ 10V(Package Limited)<br>~~Pe~~<br>~~**a**~~|240||
|IDM<br>~~Pe~~<br>~~**a**~~|Pulsed Drain Current<br>~~Pe~~<br>~~**a**~~|1530<br>~~Q~~||
|PD @TC = 25°C<br>~~**a**~~|Maximum Power Dissipation<br>~~**a**~~|300<br>~~Q~~<br>~~Q~~|W|
|~~a~~|Linear DeratingFactor<br>~~a~~<br>~~a~~|2.0<br>~~Q~~<br>~~a~~<br>~~Q~~<br>~~Q~~|W/°C<br>~~a~~|
|VGS<br>~~a~~|Gate-to-Source Voltage<br>~~a~~<br>~~a~~|± 20<br>~~Q~~<br>~~a~~<br>~~Q~~|V<br>~~a~~|
|EAS(Thermallylimited)<br>~~a~~<br>~~Ce~~|Single Pulse Avalanche Energy<br>~~a~~<br>~~G~~<br>~~Ce~~|530<br>~~Q~~<br>~~G~~|mJ<br>~~G~~|
|IAR<br>~~a~~<br>~~Ce~~|Avalanche Current<br>~~a~~<br>~~Ce~~|See Fig. 14, 15, 22a, 22b,<br>~~Q~~|A|
|EAR<br>~~Ce~~|Repetitive Avalanche Energy<br>~~Ce~~||mJ|
|dv/dt<br>~~Ce~~<br>~~pa~~|Peak Diode Recovery<br>~~Ce~~<br>~~<Q~~<br>~~pa~~|1.3<br>~~<Q~~|V/ns<br>~~<Q~~|
|TJ<br>TSTG<br>~~pa~~|Operating Junction and<br>Storage Temperature Range<br>~~pa~~|-55  to + 175|°C|
|~~pa~~|SolderingTemperature,for 10 seconds<br>~~pa~~|300(1.6mm from case)||



HEXFET[®] is a registered trademark of International Rectifier. 

***** Qualification standards can be found at http://www.irf.com/ 

www.irf.com 

1 

10/20/11 

**Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)** 

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||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Qs|Parameter|Min.|Typ.|Max.|Units|Conditions|
|V(BR)DSS|a|Drain-to-Source Breakdown Voltage|24|NN|–––|GD|–––|QO|V|GO|VGS = 0V, ID = 250μA|
|V(BR)DSS/TJ|ee|Breakdown Voltage Temp. Coefficient|–––|0.022|–––|V/°C|Reference to 25°C, ID = 5mA|
|RDS(on)|a|Static Drain-to-Source On-Resistance|–––|SQGS|1.16|GO|1.30|m|I||(©|VGS = 10V,|©|ID = 195A|
|VGS(th)|es|Gate Threshold Voltage|2.0|–––|4.0|V|VDS = VGS, ID = 250μA|
|gfs|a|Forward Transconductance|210|NNQS|–––|QOD|–––|NN|S|VDS = 10V, ID = 195A|
|RIDSSG|es|Internal Gate ResistanceDrain-to-Source Leakage Current|––––––|GS|–––2.4|QO|–––20||VDS = 24V, VGS = 0V|
|–––|–––|250|μA|VDS = 19V, VGS = 0V, TJ = 125°C|
|IGSS|ee|Gate-to-Source Forward Leakage|–––|||[|]|–––|SE|200|VGS = 20V|
|nA|
|eea|Gate-to-Source Reverse Leakage|–––|–––|-200|VGS = -20V|
|Dynamic  Electrical Characteristics @ TJ = 25°C (unless otherwise specified)|
|Parameter|Min.|Typ.|Max.|Units|Conditions|
|Qg|es|Total Gate Charge|–––|120|180|ID = 195A|
|Qgs|es|Gate-to-Source Charge|–––|58|–––|VDS =12V|
|nC|
|Qgd|Gate-to-Drain ("Miller") Charge|–––|36|–––|VGS = 10V|
|Qsync|es|Total Gate Charge Sync. (Qg - Qgd)|–––|84|–––|ID = 195A, V|®|DS =0V, VGS = 10V|
|td(on)|eses|Turn-On Delay Time|–––|18|–––|VDD = 16V|®|
|tr|es|Rise Time|–––|200|–––|ID = 195A|
|ns|
|td(off)|a|Turn-Off Delay Time|–––|75|–––|RG = 2.7|
|tf|Fall Time|–––|110|–––|VGS = 10V|
|Ciss|esa|Input Capacitance|–––|7630|–––|VGS = 0V|®|
|Coss|a|Output Capacitance|–––|3390|–––|VDS = 19V|
|Crss|a|Reverse Transfer Capacitance|–––|1960|–––|pF|ƒ = 1.0MHz,  See Fig.5|
|Coss|eff. (ER)|a|Effective Output Capacitance (Energy Related)|[–––]|4660|–––|VGS = 0V, VDS = 0V to 19V|@|See Fig.11|
|Coss|eff. (TR)|Effective Output Capacitance (Time Related)|–––|4685|–––|VGS = 0V, VDS = 0V to 19V|
|es|©|
|Diode Characteristics|
|Po|Parameter|Min.|Typ.|Max.|Units|Conditions|
|IS|Continuous Source Current|–––|–––|382|MOSFET symbol|D|
|(Body Diode)|showing  the|
|ISM|ee|Pulsed Source Current|–––|ee|–––|1530|A|integral reverse|G|
|(Body Diode)|p-n junction diode.|S|
|VtrrSD|||GS|Diode Forward VoltaReverse Recovery Timege|––––––|–––46|QO|1.369|V|(|TTJJ = 25°C= 25°C, IS = 195A|©|VR = 20V,, VGS = 0V|
|ns|
|TE|–––|45|68|TJ|= 125°C|IF = 195A|
|Qrr|Reverse Recovery Charge|–––|||395|593|nC|TJ|= 25°C|—|di/dt = 100A/μs|
|–––|fT|345|518|TJ = 125°C|
|IRRM|aee|Reverse Recovery Current|–––|||1.9|–––|A|TJ = 25°C|
|ton|Forward Turn-On Time|Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)|
|Ce|ss|

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> Notes: ~~o~~ Calculated continuous current based on maximum allowable junction ~~)~~ ISD  195A, di/dt  600A/μs, VDD V(BR)DSS, TJ  175°C. 

> temperature. Package limitation current is 240A. Note that current ® Pulse width  400μs; duty cycle  2%. 400μs; duty cycle  2%. 400μs; duty cycle  2%. 2%. 2%. 

> limitations arising from heating of the device leads may occur with © Coss eff. (TR) is a fixed capacitance that gives the same charging timeoss eff. (TR) is a fixed capacitance that gives the same charging time eff. (TR) is a fixed capacitance that gives the same charging time some lead mounting arrangements. (Refer to AN-1140 as Coss while VDS is rising from 0 to 80% VDSS.DS is rising from 0 to 80% VDSS.is rising from 0 to 80% VDSS.DSS.. while VDS is rising from 0 to 80% VDSS.DS is rising from 0 to 80% VDSS.is rising from 0 to 80% VDSS.DSS.. 

® Pulse width  400μs; duty cycle  2%. 400μs; duty cycle  2%. 400μs; duty cycle  2%. 2%. 2%. © Coss eff. (TR) is a fixed capacitance that gives the same charging timeoss eff. (TR) is a fixed capacitance that gives the same charging time eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.DS is rising from 0 to 80% VDSS.is rising from 0 to 80% VDSS.DSS.. 

@ Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. 

http://www.irf.com/technical-info/appnotes/an-1140.pdf Repetitive rating;  pulse width limited by max. junction temperature. 

 

Limited by TJmax, starting TJ = 25°C, L = 0.028mH 

RG = 50, IAS = 195A, VGS =10V. Part not recommended for use above this value. 

www.irf.com 

2 

## **Qualification Information[†]** 

|**Qualification Information[†]**|**Qualification Information[†]**|||
|---|---|---|---|
|**Qualification Level**||Automotive<br>(per AEC-Q101)††||
|||Comments:<br>This<br>part<br>number(s)<br>passed<br>Automotive<br>qualification.<br>IR’s Industrial and Consumer qualification<br>level is granted by extension of the higher Automotive level.||
|**Moisture Sensitivity Level**||TO-262<br>WideLead|TO-262<br>MSL1|
|**ESD**|Machine Model|Class M4 (+/- 425V)†††<br>AEC-Q101-002||
||Human Body Model|Class H2 (+/- 4000V)†††<br>AEC-Q101-001||
||Charged Device<br>Model|Class C5 (+/- 1125V)†††<br>AEC-Q101-005||
|**RoHS Compliant**||Yes||



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10000<br>VGS<br>TOP           15V<br>10V<br>6.5V<br>ae 5.8V<br>5.4V<br>5.0V<br>1000 4.8V<br>BOTTOM 4.5V<br>100<br>4.5V 60μs PULSE WIDTH<br>Tj = 25°C<br>10 ieee<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>10000<br>——<br>1000<br>100 | TJ = 175°C<br>CPA<br>SS eS<br>10 od<br>TJ = 25°C<br>1 pf ff} ft|<br>VDS = 15V<br>60μs PULSE WIDTH<br>0.1 fej]f] |<br>2 3 4 5 6 7 8 9<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 3.** Typical Transfer Characteristics 

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100000<br>VGS   = 0V,       f = 1 MHZ<br>Ciss   = C gs + Cgd,  C ds SHORTED<br>= C  = C<br>rss   gd<br>|a Coss   = Cds + Cgd<br>ee<br>10000 Ciss<br>C iii<br>oss<br>C rss SLOTS<br>enim<br>1000<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

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10000<br>VGS<br>TOP           15V<br>10V<br>6.5V<br>ETE TT 5.8V<br>5.4V<br>5.0V<br>1000 4.8V<br>BOTTOM 4.5V<br>100<br>4.5V<br>60μs PULSE WIDTH<br>Tj = 175°C<br>10 Gane|| LH alll<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>2.0<br>I = 195A<br>D<br>V = 10V<br>GS<br>1.5 pe<br>aa<br>1.0<br>cape ae<br>0.5<br>0.0<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>14.0<br>I = 195A<br>D<br>12.0 Po EEL<br>V = 19V<br>DS<br>V = 12V<br>an DS Lf<br>10.0<br>|<br>8.0 an aV408<br>SRREE/Ann<br>6.0<br>4.0 S4neneeee<br>2.0<br>0.0 PEC<br>0 20 40 60 80 100 120 140 160 180<br> QG,  Total Gate Charge (nC)<br>ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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10000<br>1000<br>T = 175°C<br>J<br>100<br>TJ = 25J = 25= 25 ° C<br>10<br>V GS  = 0V<br>1.0<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode<br>Forward Voltage<br>400<br>Limited By Package<br>300 pst<br>200 oneTN,TN,<br>100 PLT TEN<br>0 TTT TN TN |<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>ISD, Reverse Drain Current (A)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


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10000 10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>1000<br>1000<br>T = 175°C 100μsec<br>J  100<br>1msec<br>100<br>10<br>TJ = 25J = 25= 25 ° C DC 10msec<br>10<br>1 Tc = 25°C<br>Tj = 175°C<br>V GS  = 0V Single Pulse<br>1.0 0.1<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.1 1 10 100<br>VSD, Source-to-Drain Voltage (V) VDS, Drain-toSource Voltage (V)<br>Fig 7.   Typical Source-Drain Diode Fig 8.   Maximum Safe Operating Area<br>Forward Voltage<br>400 30<br>Id = 5mA<br>Limited By Package 29<br>300 pst LL<br>28<br>200 oneTN,TN, 27 RORRRREDZREREAD ZAREEAEE<br>26<br>100 PLT TEN ELE<br>25<br>0 TTT TN TN | 24 A LLLLE E ELLL E E<br>25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180<br> TC , Case Temperature (°C) TJ , Temperature ( °C )<br>Fig 9.   Maximum Drain Current vs. Fig 10.   Drain-to-Source Breakdown Voltage<br>Case Temperature<br>1.6 2500<br>ID<br>1.4<br>TOP         99A<br>eee 2000 LLL 100A<br>1.2 een A M BOTTOM 195A<br>1.0 en A NULL<br>1500<br>0.8<br>ay ae NEEL<br>1000<br>0.6<br>eee Ae EN<br>0.4<br>500<br>0.2 pf NUN EEE<br>> An a TSISSNIN BSS<br>0.0 0<br>-5 0 5 10 15 20 25 25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>ISD, Reverse Drain Current (A)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>Energy (μJ)<br>ID,  Drain-to-Source Current (A)<br>ID,  Drain Current (A)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

VDS, Drain-to-Source Voltage (V) 

**Fig 11.** Typical COSS Stored Energy 

**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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1<br>titty mm | TT tty ETT<br>D = 0.50 nT en a | ee td |<br>0.1 0.20<br>0.10<br>0.01 — 0.02 0.05 cae 2a | R1 R1 R2 R2 | R3R 3 Ri (°C/W)   i (sec) |<br>pTrat 0.01 PF pp J J 1  1  2 2 Th  3 3 C 0.0493    0.0001240.1910    0.003004 |)<br>ee eeEEEeee Ci=  T iRi T T 0.2586    0.021684 iat<br>0.001 Ci iRi<br>SINGLE PULSE<br>( THERMAL RESPONSE ) Notes:<br>PT TE 1. Duty Factor D = t1/t2 Hl<br>ee ell 2. Peak Tj = P dm x Zthjc + Tc ll<br>0.0001<br>1E-006 1E-005 0.0001 0.001 0.01 0.1 1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>Allowed avalanche Current vs avalanche<br>aa ee ee ee ee | pulsewidth, tav, assuming Tj = 150°C and  |]at<br>Duty Cycle = Single Pulse Tstart =25°C (Single Pulse)<br>eae<br>0.01<br>100 a SSS<br>TI aN | i | |<br>0.05<br>PEt<br>0.10<br>oTHE S S S S RSS SH<br>ATs 1 et<br>10 2729.82=== |<br>Ae 7 ee sO OO OOO OO OO<br>| Allowed avalanche Current vs avalanche  ee ee ee ee ee eee<br>pulsewidth, tav, assuming  j = 25°C and<br>Tstart = 150°C.<br>IE<br>1 EE<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Avalanche Current (A)<br>Thermal Response ( Z thJC ) °C/W<br>**----- End of picture text -----**<br>


**Fig 14.** Typical Avalanche Current vs. Pulsewidth 

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600<br>TOP          Single Pulse<br>BOTTOM   1.0% Duty Cycle<br>500 I D  = 195A<br>400<br>300<br>PNAE LEE EE<br>200<br>PNA<br>100<br>PSS<br>ELLE LESS<br>0<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>EAR , Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


**Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)** 

1. Avalanche failures assumption: 

- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figure 22a, 22b. 

4. PD (ave) = Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

6. Iav = Allowable avalanche current. 

7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). 

- tav = Average time in avalanche. 

- D = Duty cycle in avalanche =  tav ·f 

- ZthJC(D, tav) = Transient thermal resistance, see Figures 13) 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =** . **T/ ZthJC Iav = 2 T/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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4.0 Pty | ft | ft ft ft fe<br>3.5<br>3.0 PT TT [ORAL]<br>2.5 Pt tT htlyreIN<br>ma ID = 250μA AZALNNTSS<br>2.0 ID = 1.0mA<br>| | ID = 1.0A Ben<br>HAR| Poy<br>1.5<br>Pt ct cE KS<br>1.0 PoeTt tT te ET TIN<br>Pt TE<br>0.5 Pt tTtT || tt | dT cvdTlcdTge ttht LTeT<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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Driver Gate Drive<br>P.W.<br>D.U.T + { P.W. + Period ——— + D = —— Period<br>) [©)]  CircuitLow  LayoutStray ConsiderationsInduct | V t t GS=10<br><br>-  Low Leakage Inductance @ D.U.T. ISD Waveform<br>+<br>Reverse<br>Recovery Body Diode Forward<br>oi - [1] Current Transformer - ® + Current r Current di/dt AN<br>® D.U.T. VDS Waveform<br>Diode Recoverydv/dt ‘<br>00 > VDD<br>ma<br> Re-Applied<br> Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re (A  dv/dt controlled by Rg Vp p -<br><br>D.U.T. - Device Under Test SCO |<br>Ripple   5% ISD<br>Isp controlled by Duty Factor "D" @\ t<br>* Vg = 5V for Logic Level Devices<br>Fig 21.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V ~_— tp —><br>VDS L DRIVER<br>R G D.U.T +<br>- [V][DD]<br>IAS A<br>gp 20V dt<br>tp 0.01 Vv  IAS a<br> Unclamped Inductive Test Circuit Fig 22b.   Unclamped Inductive Waveforms<br>LDD<br>VDSDS VGS<br>ro 90% [<br>+<br>VDDDD -<br>D.U.T<br>10%<br>VGSGS VDS<br>Second Pulse Width < 1μs<br>Duty Factor < 0.1%<br>td(off) tf td(on) tr<br>  Switching Time Test Circuit Fig 23b.   Switching Time Waveforms<br>Id<br>Vds<br>Vgs<br>L<br>VCC<br>DUT<br>20K1K1K S Vgs(th)<br>Qgodr Qgd Qgs2 Qgs1<br>**----- End of picture text -----**<br>


**Fig 22b.** Unclamped Inductive Waveforms 

## **Fig 22a.** Unclamped Inductive Test Circuit 

**==> picture [206 x 244] intentionally omitted <==**

**----- Start of picture text -----**<br>
LDD<br>VDSDS<br>ro<br>+<br>VDDDD -<br>D.U.T<br>VGSGS<br>Second Pulse Width < 1μs<br>Duty Factor < 0.1%<br>Fig 23a.   Switching Time Test Circuit<br>L<br>VCC<br>DUT<br>0<br>20K1K1K S<br>**----- End of picture text -----**<br>


**Fig 24b.** Gate Charge Waveform 

**Fig 24a.** Gate Charge Test Circuit 

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8 

## TO-262 WideLead  Package Outline 

Dimensions are shown in millimeters (inches) 

## TO-262 WideLead Part Marking Information 

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9 

|**Ordering Information**<br>**Base part number**|**Ordering Information**<br>**Package Type**|**Standard Pack**|**Standard Pack**|**Complete Part Number**|
|---|---|---|---|---|
|||**Form**|**Quantity**||
|AUIRF1324WL|TO-262 WideLead|Tube|**Quantity**<br>50|AUIRF1324WL|



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10 

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---

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