AFS600-FGG256
FPGA, PLL, Fusion, 119 I/O's, 350 MHz, 1.425 V to 1.575 V, FBGA-256
- Manufacturer: MICROCHIP
- Product type: FPGAs
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (04-Feb-2026)
- FPGA Type: Flash based FPGA
- FPGA Family: Fusion
- IC Mounting: Surface Mount
- No. of Pins: 256Pins
- Speed Grade: -
- No. of I/O's: 119I/O's
- Product Range: AFS600 Series
- Qualification: -
- Total RAM Bits: 108Kbit
- No.of User I/Os: 119I/O's
- Clock Management: PLL
- Logic Case Style: FBGA
- IC Case / Package: FBGA
- I/O Supply Voltage: 3.3V
- No. of Logic Cells: -
- Process Technology: 130nm (CMOS)
- Core Supply Voltage Max: 1.575V
- Core Supply Voltage Min: 1.425V
- Operating Frequency Max: 350MHz
- Operating Temperature Max: 85°C
- Operating Temperature Min: 0°C
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 126.0 € |
| Current stock | 10+ |
| Lead time | 30 days |
**Revision 8 DS0092**
## **Fusion Family of Mixed Signal FPGAs**
## **Features and Benefits**
## **High-Performance Reprogrammable Flash Technology**
- Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
- Nonvolatile, Retains Program when Powered Off
- Instant On Single-Chip Solution
- 350 MHz System Performance
## **Embedded Flash Memory**
- User Flash Memory – 2 Mbits to 8 Mbits
- Configurable 8-, 16-, or 32-Bit Datapath
- 10 ns Access in Read-Ahead Mode
- 1 Kbit of Additional FlashROM
## **Integrated A/D Converter (ADC) and Analog I/O**
- Up to 12-Bit Resolution and up to 600 Ksps
- Internal 2.56 V or External Reference Voltage
- ADC: Up to 30 Scalable Analog Input Channels
- High-Voltage Input Tolerance: –10.5 V to +12 V
- Current Monitor and Temperature Monitor Blocks
- Up to 10 MOSFET Gate Driver Outputs
- P- and N-Channel Power MOSFET Support
- Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths
- ADC Accuracy is Better than 1%
## **On-Chip Clocking Support**
- Internal 100 MHz RC Oscillator (accurate to 1%)
- Crystal Oscillator Support (32 KHz to 20 MHz)
- Programmable Real-Time Counter (RTC)
- 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs – Phase Shift, Multiply/Divide, and Delay Capabilities
- – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
## **Low Power Consumption**
- Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
- • Sleep and Standby Low-Power Modes
## **In-System Programming (ISP) and Security**
- ISP with 128-Bit AES via JTAG
- FlashLock[®] Designed to Protect FPGA Contents
## **Advanced Digital I/O**
- 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
- Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
- Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input
- Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS – Built-In I/O Registers
- 700 Mbps DDR Operation
- Hot-Swappable I/Os
- Programmable Output Slew Rate, Drive Strength, and Weak Pull-Up/Down Resistor
- Pin-Compatible Packages across the Fusion[®] Family
## **SRAMs and FIFOs**
- Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
- True Dual-Port SRAM (except ×18)
- Programmable Embedded FIFO Control Logic
## **Soft ARM Cortex-M1 Fusion Devices (M1)**
- ARM[®] Cortex[®] -M1–Enabled
## **Pigeon Point ATCA IP Support (P1)**
- Targeted to Pigeon Point[®] Board Management Reference (BMR) Starter Kits
- Designed in Partnership with Pigeon Point Systems
- ARM Cortex-M1 Enabled
## **MicroBlade Advanced Mezzanine Card Support (U1)**
- Targeted to Advanced Mezzanine Card (AdvancedMC™ Designs)
- • Designed in Partnership with MicroBlade
- 8051-Based Module Management Controller (MMC)
**Table 1 • Fusion Family**
|**Fusion Devices**<br>~~a~~|**Fusion Devices**<br>~~a~~|**AFS090**<br>~~(~~<br>~~|~~|**AFS250**<br>~~|~~|**AFS600**<br>~~ee~~|**AFS1500**<br>~~ee~~|
|---|---|---|---|---|---|
|**ARM Cortex-M1* Devices**<br>~~a~~<br>~~RD~~||~~RD~~<br>~~(~~<br>~~|~~|**M1AFS250**<br>~~RD~~<br>~~|~~|**M1AFS600**<br>~~ee ~~<br>~~RD~~|**M1AFS1500**<br> ~~ee~~<br>~~RD~~|
|**Pigeon Point Devices**<br>~~ee~~||~~(~~<br>~~|~~<br>~~|~~|~~|~~<br>~~|~~<br>~~|~~|**P1AFS600**<br>~~|~~<br>~~|sCidzC~~|**P1AFS1500**<br>~~|sd~~|
|**MicroBlade Devices**<br>~~ee~~||~~|~~|**U1AFS250**<br>~~|~~<br>~~|~~|**U1AFS600**<br>~~|~~<br>~~|sCidzC~~|**U1AFS1500**<br>~~|sd~~|
|**General**<br>**Information**<br>~~ee~~|System Gates<br>~~ee~~|90,000<br>~~|~~|250,000<br>~~|~~<br>~~|~~|600,000<br>~~|~~<br>~~|sCidzC~~|1,500,000<br>~~|sd~~|
||Tiles (D-flip-flops)<br>~~ee~~|2,304<br>~~|~~|6,144<br>~~|~~<br>~~|~~|13,824<br>~~|~~<br>~~|CitisdC~~|38,400<br>~~|isd~~|
||Secure (AES) ISP<br>~~ee~~|Yes<br>~~|~~|Yes<br>~~|~~<br>~~|isd~~|Yes<br>~~|~~<br>~~|CitisdC~~|Yes<br>~~|isd~~|
||PLLs<br>~~ee~~|1<br>~~|~~<br>~~|~~|1<br>~~|~~<br>~~|~~<br>~~|~~|2<br>~~|~~<br>~~|CitisdC~~|2<br>~~|isd~~|
||Globals|18<br>~~|~~|18<br>~~|~~|18|18|
|**Memory**|Flash Memory Blocks (2 Mbits)<br>~~GO~~|1<br>~~GO~~<br>~~|~~|1<br>~~GO~~<br>~~|~~|2<br>~~GO~~|4<br>~~GO~~|
||Total Flash Memory Bits<br>~~ee~~|2M<br>~~ee~~|2M<br>~~|~~|4M<br>~~|~~<br>~~|~~|8M<br>~~|sd~~|
||FlashROM Bits<br>~~ee~~|1,024<br>~~ee~~|1,024<br>~~|~~|1,024<br>~~|~~<br>~~|Cid~~|1,024<br>~~|sd~~|
||RAM Blocks (4,608 bits)<br>~~ee ~~|6<br> ~~ee~~|8<br>~~|~~|24<br>~~|~~<br>~~|~~|60<br>~~|sd~~|
||RAM kbits<br>~~GO~~<br>~~ee~~|27<br>~~GO~~<br>~~|~~|36<br>~~GO~~<br>~~|~~<br>~~|~~|108<br>~~GO~~<br>~~|~~<br>~~|CitisdC~~|270<br>~~GO~~<br>~~|isd~~|
|**Analog and I/Os**<br>~~i~~|Analog Quads<br>~~ee~~<br>|5<br>~~|~~<br>~~isd~~|6<br>~~|~~<br>~~|isd~~|10<br>~~|~~<br>~~|CitisdC~~|10<br>~~|isd~~|
||Analog Input Channels<br>~~ee~~<br>|15<br>~~|~~<br>~~isd~~|18<br>~~|~~<br>~~|~~|30<br>~~|~~<br>~~|CitisdC~~|30<br>~~|isd~~|
||Gate Driver Outputs<br>~~|~~|5<br>~~|~~<br>~~|isd~~|6<br>~~|~~<br>~~|~~|10<br>~~|~~<br>~~|sd~~|10<br>~~|~~|
||I/O Banks (+ JTAG)<br>~~|~~<br>~~PO~~|4<br>~~|~~<br>~~|isd~~<br>~~——~~|4<br>~~|~~<br>~~|~~|5<br>~~|~~<br>~~|sd~~|5<br>~~|~~|
||Maximum Digital I/Os<br>~~|~~<br>~~PO~~<br>~~PO~~|75<br>~~|~~<br>~~|isd~~<br>~~——~~<br>~~es~~|114<br>~~|~~<br>~~|~~|172<br>~~|~~<br>~~|sd~~|252<br>~~|~~|
||Analog I/Os<br><br>~~PO~~<br>~~re~~|20<br>~~isd~~<br>~~——~~<br>~~re~~<br>~~es~~|24<br>~~re~~|40<br>~~re~~|40<br>~~re~~|
**May 2018** © 2018 Microsemi Corporation
**I**
_Fusion Family of Mixed Signal FPGAs_
## **Fusion Device Architecture Overview**
**==> picture [519 x 359] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bank 0 Bank 1<br>CCC<br>SRAM Block<br>4,608-Bit Dual-Port SRAM<br>or FIFO Block<br>OSC<br>a<br>I/Os<br>CCC/PL L<br>VersaTile<br>BRGGSHEHE<br>ee ee |e ee ee ee SRAM Block4,608-Bit Dual-Port SRAM<br>ISP AES User Nonvolatile<br>Charge Pumps or FIFO Block<br>Decryption FlashROM<br>Flash Memory Blocks ADC Flash Memory Blocks<br>Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog<br>Quad Quad Quad Quad Quad Quad Quad Quad Quad Quad<br>CCC Fit i} | )<br>Bank 3<br>Bank 4 Bank 2<br>**----- End of picture text -----**<br>
_**Figure 1 •**_ **Fusion Device Architecture Overview (AFS600) Package I/Os: Single-/Double-Ended (Analog) Fusion Devices AFS090 AFS250 AFS600 AFS1500 ARM Cortex-M1 Devices** ~~ee~~ **M1AFS250 M1AFS600** ~~es~~ **M1AFS1500 Pigeon Point Devices** ~~a~~ **P1AFS600** ~~ee~~ **[1] P1AFS1500[1] MicroBlade Devices** ~~ee~~ **U1AFS250[2]** ~~ee~~ **U1AFS600[2] U1AFS1500[2]** QN108[3] 37/9 (16) ~~ee~~ QN180[3] 60/16 (20) ~~es~~ 65/15 (24) ~~es~~ PQ208[4, 5] ~~es~~ 93/26 (24) ~~es~~ 95/46 (40) FG256 75/22 (20) ~~es~~ 114/37 (24) 119/58 (40) 119/58 (40) FG484 ~~a~~ 172/86 (40) 223/109 (40) FG676 ~~es es~~ 252/126 (40) _Notes: 1. Pigeon Point devices are only offered in FG484 and FG256. 2. MicroBlade devices are only offered in FG256. 3. Package not available. 4. Fusion devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600). 5. PQ208 package is discontinued._ ~~===~~ **II Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Product Ordering Codes**
M1AFS600 _ 1 FG G 256 Y I Application (junction temperature range) Blank = Commercial (0 to +85°C) I = Industrial (–40 to +100°C) PP = Pre-Production ES = Engineering Silicon (room temperature only) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Lead-Free Packaging Options Blank = Standard Packaging G = RoHS-Compliant (green) Packaging Package Type 1 QN[=] Quad Flat No Lead (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) 3 FG = Fine Pitch Ball Grid Array (1.0 mm pitch)2 Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number 2 = 25% Faster than Standard **Fusion Devices** AFS090 = 90,000 System Gates AFS250 = 250,000 System Gates AFS600 = 600,000 System Gates AFS1500 = 1,500,000 System Gates **ARM-Enabled Fusion Devices** M1AFS250[=] 250,000 System Gates M1AFS600[=] 600,000 System Gates M1AFS1500[=] 1,500,000 System Gates **Pigeon Point Devices** P1AFS600 = 600,000 System Gates P1AFS1500 = 1,500,000 System Gates **MicroBlade Devices** U1AFS250 = 250,000 System Gates U1AFS600 = 600,000 System Gates U1AFS1500 = 1,500,000 System Gates
_Notes:_
_1. For Fusion devices, Quad Flat No Lead packages are only offered as RoHS compliant, QNG packages._
_2. MicroBlade and Pigeon Point devices only support FG packages._
_3. Package is discontinued._
## **Fusion Device Status**
~~a~~ **Fusion** ~~|~~ **Status Cortex-M1 Status Pigeon Point Status MicroBlade Status** AFS090 Production ~~reeee|~~ AFS250 Production M1AFS250 Production U1AFS250 Production ~~a eee~~ AFS600 Production M1AFS600 Production P1AFS600 Production U1AFS600 Production ~~a|a ee ee a~~ AFS1500 Production M1AFS1500 Production P1AFS1500 Production U1AFS1500 Production
**Revision 8**
**III**
_Fusion Family of Mixed Signal FPGAs_
## **Temperature Grade Offerings**
|**Fusion Devices**<br>~~Oe~~|**AFS090**<br>~~Oe~~|**AFS250**<br>~~Oe~~|**AFS600**<br>~~Oe~~|**AFS1500**<br>~~Oe~~|
|---|---|---|---|---|
|**ARM Cortex-M1 Devices**<br>~~Oe~~<br>~~a~~|~~Oe~~<br>~~ai~~|**M1AFS250**<br>~~Oe~~<br>~~i~~|**M1AFS600**<br>~~Oe~~<br>~~i~~|**M1AFS1500**<br>~~Oe~~|
|**Pigeon Point Devices**<br>~~a~~|~~a~~||**P1AFS6003**|**P1AFS15003**|
|**MicroBlade Devices**<br>~~QR~~|~~QR~~|**U1AFS2504**<br>~~QR~~|**U1AFS6004**<br>~~QR~~|**U1AFS15004**<br>~~QR~~|
|QN108 5<br>~~QR~~<br>~~ee~~<br>~~a~~|C, I<br>~~QR~~<br>~~ee~~<br>|–<br>~~QR~~<br>~~ee~~<br>|–<br>~~QR~~<br>~~ee~~<br>|–<br>~~QR~~<br>~~ee~~<br>|
|QN180 5<br>~~a~~|C, I<br>|C, I<br>|–<br>|–<br>|
|PQ2086<br>~~aeG~~|–<br>~~eG~~|C, I<br>~~eG~~|C, I<br>~~eG~~|–<br>~~eG~~|
|FG256<br>~~eG~~<br>~~ee~~<br>~~a~~|C, I<br>~~eG~~<br>~~ee~~<br>|C, I<br>~~eG~~<br>~~ee~~<br>|C, I<br>~~eG~~<br>~~ee~~<br>|C, I<br>~~eG~~<br>~~ee~~<br>|
|FG484<br>~~a~~|–<br>|–<br>|C, I<br>|C, I<br>|
|FG676<br>~~aeG~~|–<br>~~eG~~|–<br>~~eG~~|–<br>~~eG~~|C, I<br>~~eG~~|
|_Notes:_<br>_1. C = Commercial Temperature Range: 0°C to 85°C Junction_<br>_2. I = Industrial Temperature Range: –40°C to 100°C Junction_<br>_3. Pigeon Point devices are only offered in FG484 and FG256._<br>_4. MicroBlade devices are only offered in FG256._<br>_5. Package not available._<br>_6. Package is discontinued._<br>~~eG~~|||||
_Notes:_
_1. C = Commercial Temperature Range: 0°C to 85°C Junction_
_2. I = Industrial Temperature Range: –40°C to 100°C Junction_
_3. Pigeon Point devices are only offered in FG484 and FG256._
_4. MicroBlade devices are only offered in FG256._
_5. Package not available._
_6. Package is discontinued._
## **Speed Grade and Temperature Grade Matrix**
||**Std.1**|**–1**|**–22**|
|---|---|---|---|
|C3||||
|I4||||
_Notes:_
_1. MicroBlade devices are only offered in standard speed grade._
_2. Pigeon Point devices are only offered in –2 speed grade._
_3. C = Commercial Temperature Range: 0°C to 85°C Junction_
_4. I = Industrial Temperature Range: –40°C to 100°C Junction_
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/index.php?option=com_content&id=137&lang=en&view=article.
## **Cortex-M1, Pigeon Point, and MicroBlade Fusion Device Information**
This datasheet provides information for all Fusion (AFS), Cortex-M1 (M1), Pigeon Point (P1), and MicroBlade (U1) devices. The remainder of the document will only list the Fusion (AFS) devices. Please apply relevant information to M1, P1, and U1 devices when appropriate. Please note the following:
- Cortex-M1 devices are offered in the same speed grades and packages as basic Fusion devices.
- Pigeon Point devices are only offered in –2 speed grade and FG484 and FG256 packages.
- MicroBlade devices are only offered in standard speed grade and the FG256 package.
**Revision 8**
**IV**
_Fusion Family of Mixed Signal FPGAs_
## **Table of Contents**
Fusion Device Family Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Unprecedented Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Device Architecture Fusion Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Real-Time Counter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76 Analog Configuration MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-126 User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-223 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-228 DC and Power Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Package Pin Assignments QN108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 QN180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
**Revision 8**
**V**
## **1 – Fusion Device Family Overview**
## **Introduction**
The Fusion mixed signal FPGA satisfies the demand from system architects for a device that simplifies design and unleashes their creativity. As the world’s first mixed signal programmable logic family, Fusion integrates mixed signal analog, flash memory, and FPGA fabric in a monolithic device. Fusion devices enable designers to quickly move from concept to completed design and then deliver feature-rich systems to market. This new technology takes advantage of the unique properties of Microsemi flash-based FPGAs, including a high-isolation, triple-well process and the ability to support high-voltage transistors to meet the demanding requirements of mixed signal system design.
Fusion mixed signal FPGAs bring the benefits of programmable logic to many application areas, including power management, smart battery charging, clock generation and management, and motor control. Until now, these applications have only been implemented with costly and space-consuming discrete analog components or mixed signal ASIC solutions. Fusion mixed signal FPGAs present new capabilities for system development by allowing designers to integrate a wide range of functionality into a single device, while at the same time offering the flexibility of upgrades late in the manufacturing process or after the device is in the field. Fusion devices provide an excellent alternative to costly and time-consuming mixed signal ASIC designs. In addition, when used in conjunction with the ARM Cortex-M1 processor, Fusion technology represents the definitive mixed signal FPGA platform.
Flash-based Fusion devices are Instant On. As soon as system power is applied and within normal operating specifications, Fusion devices are working. Fusion devices have a 128-bit flash-based lock and industry-leading AES decryption, used to secure programmed intellectual property (IP) and configuration data. Fusion devices are the most comprehensive single-chip analog and digital programmable logic solution available today.
To support this new ground-breaking technology, Microsemi has developed a series of major tool innovations to help maximize designer productivity. Implemented as extensions to the popular Microsemi Libero[®] System-on-Chip (SoC) software, these new tools allow designers to easily instantiate and configure peripherals within a design, establish links between peripherals, create or import building blocks or reference designs, and perform hardware verification. This tool suite will also add comprehensive hardware/software debug capability as well as a suite of utilities to simplify development of embedded soft-processor-based solutions.
## **General Description**
The Fusion family, based on the highly successful ProASIC[®] 3 and ProASIC3E flash FPGA architecture, has been designed as a high-performance, programmable, mixed signal platform. By combining an advanced flash FPGA core with flash memory blocks and analog peripherals, Fusion devices dramatically simplify system design and, as a result, dramatically reduce overall system cost and board space.
The state-of-the-art flash memory technology offers high-density integrated flash memory blocks, enabling savings in cost, power, and board area relative to external flash solutions, while providing increased flexibility and performance. The flash memory blocks and integrated analog peripherals enable true mixed-mode programmable logic designs. Two examples are using an on-chip soft processor to implement a fully functional flash MCU and using high-speed FPGA logic to offer system and power supervisory capabilities. Instant On, and capable of operating from a single 3.3 V supply, the Fusion family is ideally suited for system management and control applications.
The devices in the Fusion family are categorized by FPGA core density. Each family member contains many peripherals, including flash memory blocks, an analog-to-digital-converter (ADC), high-drive outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides the user with a high level of flexibility and integration to support a wide variety of mixed signal applications. The flash memory block capacity ranges from 2 Mbits to 8 Mbits. The integrated 12-bit ADC supports up to 30 independently configurable input channels.
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The on-chip crystal and RC oscillators work in conjunction with the integrated phase-locked loops (PLLs) to provide clocking support to the FPGA array and on-chip resources. In addition to supporting typical RTC uses such as watchdog timer, the Fusion RTC can control the on-chip voltage regulator to power down the device (FPGA fabric, flash memory block, and ADC), enabling a low power standby mode.
The Fusion family offers revolutionary features, never before available in an FPGA. The nonvolatile flash technology gives the Fusion solution the advantage of being a highly secure, low power, single-chip solution that is Instant On. Fusion is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
## **Flash Advantages**
## _**Reduced Cost of Ownership**_
Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flashbased Fusion devices are Instant On and do not need to be loaded from an external boot PROM. On-board security mechanisms prevent access to the programming information and enable remote updates of the FPGA logic that are protected with high level security. Designers can perform remote insystem reprogramming to support future design iterations and field upgrades, with confidence that valuable IP is highly unlikely to be compromised or copied. ISP can be performed using the industry-standard AES algorithm with MAC data authentication on the device. The Fusion family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the Fusion family a cost-effective ASIC replacement solution for applications in the consumer, networking and communications, computing, and avionics markets.
## _**Security**_
As the nonvolatile, flash-based Fusion family requires no boot PROM, there is no vulnerable external bitstream. Fusion devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
Fusion devices utilize a 128-bit flash-based key lock and a separate AES key to provide the highest level of protection in the FPGA industry for programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted prior to loading. Additionally, the flash memory blocks can be programmed during runtime using the industry-leading AES-128 block cipher encryption standard (FIPS Publication 192). The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the DES standard, which was adopted in 1977. Fusion devices have a built-in AES decryption engine and a flash-based AES key that make Fusion devices the most comprehensive programmable logic device security solution available today. Fusion devices with AES-based security provide a high level of protection for remote field updates over public networks, such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. As an additional security measure, the FPGA configuration data of a programmed Fusion device cannot be read back, although secure design verification is possible. During design, the user controls and defines both internal and external access to the flash memory blocks.
Security, built into the FPGA fabric, is an inherent component of the Fusion family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. Fusion with FlashLock and AES security is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. A Fusion device provides the best available security for programmable logic designs.
## _**Single Chip**_
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based Fusion FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability.
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## _**Instant On**_
Flash-based Fusion devices are Level 0 Instant On. Instant On Fusion devices greatly simplify total system design and reduce total system cost by eliminating the need for CPLDs. The Fusion Instant On clocking (PLLs) replaces off-chip clocking resources. The Fusion mix of Instant On clocking and analog resources makes these devices an excellent choice for both system supervisor and system management functions. Instant On from a single 3.3 V source enables Fusion devices to initiate, control, and monitor multiple voltage supplies while also providing system clocks. In addition, glitches and brownouts in system power will not corrupt the Fusion device flash configuration. Unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables reduction or complete removal of expensive voltage monitor and brownout detection devices from the PCB design. Flash-based Fusion devices simplify total system design and reduce cost and design risk, while increasing system reliability.
## _**Firm Errors**_
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. Another source of radiation-induced firm errors is alpha particles. For an alpha to cause a soft or firm error, its source must be in very close proximity to the affected circuit. The alpha source must be in the package molding compound or in the die itself. While low-alpha molding compounds are being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.
Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not occur in Fusion flash-based FPGAs. Once it is programmed, the flash cell configuration element of Fusion FPGAs cannot be altered by high-energy neutrons and is therefore immune to errors from them.
Recoverable (or soft) errors occur in the user data SRAMs of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
## _**Low Power**_
Flash-based Fusion devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. With Fusion devices, there is no power-on current surge and no high current transition, both of which occur on many FPGAs.
Fusion devices also have low dynamic power consumption and support both low power standby mode and very low power sleep mode, offering further power savings.
## **Advanced Flash Technology**
The Fusion family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows very high logic utilization (much higher than competing SRAM technologies) without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy.
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## **Advanced Architecture**
The proprietary Fusion architecture provides granularity comparable to standard-cell ASICs. The Fusion device consists of several distinct and programmable architectural features, including the following (Figure 1-1 on page 1-5):
- Embedded memories
- Flash memory blocks
- FlashROM
- SRAM and FIFO
- Clocking resources
- PLL and CCC
- RC oscillator
- Crystal oscillator
- No-Glitch MUX (NGMUX)
- Digital I/Os with advanced I/O standards
- FPGA VersaTiles
- Analog components
- ADC
- Analog I/Os supporting voltage, current, and temperature monitoring
- 1.5 V on-board voltage regulator
-
- Real-time counter
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic lookup table (LUT) equivalent or a D-flip-flop or latch (with or without enable) by programming the appropriate flash switch interconnections. This versatility allows efficient use of the FPGA fabric. The VersaTile capability is unique to the Microsemi families of flash-based FPGAs. VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid (3.3 V) single-voltage programming of Fusion devices via an IEEE 1532 JTAG interface.
## **Unprecedented Integration**
## **Integrated Analog Blocks and Analog I/Os**
Fusion devices offer robust and flexible analog mixed signal capability in addition to the highperformance flash FPGA fabric and flash memory block. The many built-in analog peripherals include a configurable 32:1 input analog MUX, up to 10 independent MOSFET gate driver outputs, and a configurable ADC. The ADC supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per second (Ksps), differential nonlinearity (DNL) < 1.0 LSB, and Total Unadjusted Error (TUE) of 0.72 LSB in 10-bit mode. The TUE is used for characterization of the conversion error and includes errors from all sources, such as offset and linearity. Internal bandgap circuitry offers 1% voltage reference accuracy with the flexibility of utilizing an external reference voltage. The ADC channel sampling sequence and sampling rate are programmable and implemented in the FPGA logic using Designer and Libero SoC software tool support.
Two channels of the 32-channel ADCMUX are dedicated. Channel 0 is connected internally to VCC and can be used to monitor core power supply. Channel 31 is connected to an internal temperature diode which can be used to monitor device temperature. The 30 remaining channels can be connected to external analog signals. The exact number of I/Os available for external connection signals is devicedependent (refer to the "Fusion Family" table on page I for details).
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With Fusion, Microsemi also introduces the Analog Quad I/O structure (Figure 1-1). Each quad consists of three analog inputs and one gate driver. Each quad can be configured in various built-in circuit combinations, such as three prescaler circuits, three digital input circuits, a current monitor circuit, or a temperature monitor circuit. Each prescaler has multiple scaling factors programmed by FPGA signals to support a large range of analog inputs with positive or negative polarity. When the current monitor circuit is selected, two adjacent analog inputs measure the voltage drop across a small external sense resistor. For more information, refer to the "Analog System Characteristics" section on page 2-117. Built-in operational amplifiers amplify small voltage signals for accurate current measurement. One analog input in each quad can be connected to an external temperature monitor diode. In addition to the external temperature monitor diode(s), a Fusion device can monitor an internal temperature diode using dedicated channel 31 of the ADCMUX.
Figure 1-1 on page 1-5 illustrates a typical use of the Analog Quad I/O structure. The Analog Quad shown is configured to monitor and control an external power supply. The AV pad measures the source of the power supply. The AC pad measures the voltage drop across an external sense resistor to calculate current. The AG MOSFET gate driver pad turns the external MOSFET on and off. The AT pad measures the load-side voltage level.
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Power Line Side Load Side<br>Off-Chip Rpullup<br>AV AC AG AT<br>Pads Voltage <4 Current Gate Temperature<br>Monitor Block Monitor Block Driver <¢ Monitor Block<br>On-Chip<br>Analog Quad<br>Pre- Pre- Pre-<br>scaler scaler scaler<br>ays Power =)<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor/Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 1-1 •**_ **Analog Quad**
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## **Embedded Memories**
## _**Flash Memory Blocks**_
The flash memory available in each Fusion device is composed of one to four flash blocks, each 2 Mbits in density. Each block operates independently with a dedicated flash controller and interface. Fusion flash memory blocks combine fast access times (60 ns random access and 10 ns access in Read-Ahead mode) with a configurable 8-, 16-, or 32-bit datapath, enabling high-speed flash operation without wait states. The memory block is organized in pages and sectors. Each page has 128 bytes, with 33 pages comprising one sector and 64 sectors per block. The flash block can support multiple partitions. The only constraint on size is that partition boundaries must coincide with page boundaries. The flexibility and granularity enable many use models and allow added granularity in programming updates.
Fusion devices support two methods of external access to the flash memory blocks. The first method is a serial interface that features a built-in JTAG-compliant port, which allows in-system programmability during user or monitor/test modes. This serial interface supports programming of an AES-encrypted stream. Data protected with security measures can be passed through the JTAG interface, decrypted, and then programmed in the flash block. The second method is a soft parallel interface.
FPGA logic or an on-chip soft microprocessor can access flash memory through the parallel interface. Since the flash parallel interface is implemented in the FPGA fabric, it can potentially be customized to meet special user requirements. For more information, refer to the _CoreCFI Handbook._ The flash memory parallel interface provides configurable byte-wide (×8), word-wide (×16), or dual-word-wide (×32) data-port options. Through the programmable flash parallel interface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations.
The flash memory has built-in security. The user can configure either the entire flash block or the small blocks to protect against unintentional or intrusive attempts to change or destroy the storage contents. Each on-chip flash memory block has a dedicated controller, enabling each block to operate independently.
The flash block logic consists of the following sub-blocks:
- Flash block – Contains all stored data. The flash block contains 64 sectors and each sector contains 33 pages of data.
- Page Buffer – Contains the contents of the current page being modified. A page contains 8 blocks of data.
- Block Buffer – Contains the contents of the last block accessed. A block contains 128 data bits.
- ECC Logic – The flash memory stores error correction information with each block to perform single-bit error correction and double-bit error detection on all data blocks.
## _**User Nonvolatile FlashROM**_
In addition to the flash blocks, Fusion devices have 1 Kbit of user-accessible, nonvolatile FlashROM on-chip. The FlashROM is organized as 8×128-bit pages. The FlashROM can be used in diverse system applications:
- Internet protocol addressing (wireless or fixed)
- System calibration settings
- Device serialization and/or inventory control
- Subscription-based business models (for example, set-top boxes)
- Secure key storage for communications algorithms protected by security
- Asset management/tracking
- Date stamping
- Version management
The FlashROM is written using the standard IEEE 1532 JTAG programming interface. Pages can be individually programmed (erased and written). On-chip AES decryption can be used selectively over public networks to load data such as security keys stored in the FlashROM for a user design.
The FlashROM can be programmed (erased and written) via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing.
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The FlashPoint tool in the Fusion development software solutions, Libero SoC and Designer, has extensive support for flash memory blocks and FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using the Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
## _**SRAM and FIFO**_
Fusion devices have embedded SRAM blocks along the north and south sides of the device. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be written through a 4-bit port and read as a single bitstream. The SRAM blocks can be initialized from the flash memory blocks or via the device JTAG port (ROM emulation mode), using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal EMPTY and FULL flags. The embedded FIFO control unit contains the counters necessary for the generation of the read and write address pointers. The SRAM/FIFO blocks can be cascaded to create larger configurations.
## **Clock Resources**
## _**PLLs and Clock Conditioning Circuits (CCCs)**_
Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of the Fusion family contains six CCCs. In the two larger family members, two of these CCCs also include a PLL; the smaller devices support one PLL.
The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs with dedicated CCC block connections.
The CCC block has the following key features:
- Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
- Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
- Clock phase adjustment via programmable and fixed delays from –6.275 ns to +8.75 ns
- Clock skew minimization (PLL)
- Clock frequency synthesis (PLL)
- On-chip analog clocking resources usable as inputs:
- 100 MHz on-chip RC oscillator
- Crystal oscillator
Additional CCC specifications:
- Internal phase shift = 0°, 90°, 180°, and 270°
- Output duty cycle = 50% ± 1.5%
- Low output jitter. Samples of peak-to-peak period jitter when a single global network is used:
- 70 ps at 350 MHz
- 90 ps at 100 MHz
- 180 ps at 24 MHz
- Worst case < 2.5% × clock period
- Maximum acquisition time = 150 µs
- Low power consumption of 5 mW
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## _**Global Clocking**_
Fusion devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there are on-chip oscillators as well as a comprehensive global clock distribution network.
The integrated RC oscillator generates a 100 MHz clock. It is used internally to provide a known clock source to the flash memory read and write control. It can also be used as a source for the PLLs.
The crystal oscillator supports the following operating modes:
- Crystal (32.768 KHz to 20 MHz)
- Ceramic (500 KHz to 8 MHz)
- RC (32.768 KHz to 4 MHz)
Each VersaTile input and output port has access to nine VersaNets: six main and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via MUXes. The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.
## _**Digital I/Os with Advanced I/O Standards**_
The Fusion family of FPGAs features a flexible digital I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). Fusion FPGAs support many different digital I/O standards, both single-ended and differential.
The I/Os are organized into banks, with four or five banks per device. The configuration of these banks determines the I/O standards supported. The banks along the east and west sides of the device support the full range of I/O standards (single-ended and differential). The south bank supports the Analog Quads (analog I/O). In the family's two smaller devices, the north bank supports multiple single-ended digital I/O standards. In the family’s larger devices, the north bank is divided into two banks of digital Pro I/Os, supporting a wide variety of single-ended, differential, and voltage-referenced I/O standards.
Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following applications:
- Single-Data-Rate (SDR) applications
- Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications
- Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points.
## _**VersaTiles**_
The Fusion core consists of VersaTiles, which are also used in the successful ProASIC3 family. The Fusion VersaTile supports the following:
- All 3-input logic functions—LUT-3 equivalent
- Latch with clear or set
- D-flip-flop with clear or set and optional enable
Refer to Figure 1-2 for the VersaTile configuration arrangement.
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LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set<br>**----- End of picture text -----**<br>
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X1 Data Y Data Y<br>X2 LUT-3 Y CLK D-FF CLK D-FFE<br>X3 CLR Enable<br>CLR<br>**----- End of picture text -----**<br>
_**Figure 1-2 •**_ **VersaTile Configurations**
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## **Specifying I/O States During Programming**
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the _FlashPro User Guide_ for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only.
The I/Os are controlled by the JTAG Boundary Scan register during programming, except for the analog pins (AC, AT and AV). The Boundary Scan register of the AG pin can be used to enable/disable the gate driver in Libero SoC.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming.
2. From the FlashPro GUI, click **PDB Configuration** . A FlashPoint – Programming File Generator window appears.
3. Click the **Specify I/O States During Programming** button to display the Specify I/O States During Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-3).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings:
- 1 – I/O is set to drive out logic High
- 0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
_**Figure 1-3 •**_ **I/O States During Programming Window**
6. Click **OK** to return to the FlashPoint – Programming File Generator window.
I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation.
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## **Related Documents**
## **Datasheet**
Core8051 www.microsemi.com/soc/ipdocs/Core8051_DS.pdf
## **Application Notes**
## _Fusion FlashROM_
http://www.microsemi.com/soc/documents/Fusion_FROM_AN.pdf _Fusion SRAM/FIFO Blocks_
http://www.microsemi.com/soc/documents/Fusion_RAM_FIFO_AN.pdf _Using DDR in Fusion Devices_ http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=129938 _Fusion Security_
http://www.microsemi.com/soc/documents/Fusion_Security_AN.pdf _Using Fusion RAM as Multipliers_
http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=129940
## **Handbook**
_Cortex-M1 Handbook_
www.microsemi.com/soc/documents/CortexM1_HB.pdf
## **User Guides**
## _Designer User Guide_
http://www.microsemi.com/soc/documents/designer_UG.pdf _Fusion FPGA Fabric User Guide_
http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=130817 _IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide_ http://www.microsemi.com/soc/documents/pa3_libguide_ug.pdf
_SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User Guide_ http://www.microsemi.com/soc/documents/genguide_ug.pdf
## **White Papers**
## _Fusion Technology_
http://www.microsemi.com/soc/documents/Fusion_Tech_WP.pdf
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## **2 – Device Architecture**
## **Fusion Stack Architecture**
To manage the unprecedented level of integration in Fusion devices, Microsemi developed the Fusion technology stack (Figure 2-1). This layered model offers a flexible design environment, enabling design at very high and very low levels of abstraction. Fusion peripherals include hard analog IP and hard and soft digital IP. Peripherals communicate across the FPGA fabric via a layer of soft gates—the Fusion backbone. Much more than a common bus interface, this Fusion backbone integrates a micro-sequencer within the FPGA fabric and configures the individual peripherals and supports low-level processing of peripheral data. Fusion applets are application building blocks that can control and respond to peripherals and other system signals. Applets can be rapidly combined to create large applications. The technology is scalable across devices, families, design types, and user expertise, and supports a well-defined interface for external IP and tool integration.
At the lowest level, Level 0, are Fusion peripherals. These are configurable functional blocks that can be hardwired structures such as a PLL or analog input channel, or soft (FPGA gate) blocks such as a UART or two-wire serial interface. The Fusion peripherals are configurable and support a standard interface to facilitate communication and implementation.
Connecting and controlling access to the peripherals is the Fusion backbone, Level 1. The backbone is a soft-gate structure, scalable to any number of peripherals. The backbone is a bus and much more; it manages peripheral configuration to ensure proper operation. Leveraging the common peripheral interface and a low-level state machine, the backbone efficiently offloads peripheral management from the system design. The backbone can set and clear flags based upon peripheral behavior and can define performance criteria. The flexibility of the stack enables a designer to configure the silicon, directly bypassing the backbone if that level of control is desired.
One step up from the backbone is the Fusion applet, Level 2. The applet is an application building block that implements a specific function in FPGA gates. It can react to stimuli and board-level events coming through the backbone or from other sources, and responds to these stimuli by accessing and manipulating peripherals via the backbone or initiating some other action. An applet controls or responds to the peripheral(s). Applets can be easily imported or exported from the design environment. The applet structure is open and well-defined, enabling users to import applets from Microsemi, system developers, third parties, and user groups.
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Optional ARM or 8051 Processor<br>User Applications Level 3<br>Fusion Applets Level 2<br>Flash<br>Memory Fusion Smart Backbone Level 1<br>Smart Peripherals<br>Analog Analog Analog in FPGA<br>Smart Smart Smart Level 0<br>Fabric<br>Peripheral 1 Peripheral 2 Peripheral n<br>(e.g., Logic, PLL, FIFO)<br>**----- End of picture text -----**<br>
_Note: Levels 1, 2, and 3 are implemented in FPGA logic gates._
_**Figure 2-1 •**_ **Fusion Architecture Stack**
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The system application, Level 3, is the larger user application that utilizes one or more applets. Designing at the highest level of abstraction supported by the Fusion technology stack, the application can be easily created in FPGA gates by importing and configuring multiple applets.
In fact, in some cases an entire FPGA system design can be created without any HDL coding.
An optional MCU enables a combination of software and HDL-based design methodologies. The MCU can be on-chip or off-chip as system requirements dictate. System portioning is very flexible, allowing the MCU to reside above the applets or to absorb applets, or applets and backbone, if desired.
The Fusion technology stack enables a very flexible design environment. Users can engage in design across a continuum of abstraction from very low to very high.
## **Core Architecture**
## **VersaTile**
Based upon successful ProASIC3/E logic architecture, Fusion devices provide granularity comparable to gate arrays. The Fusion device core consists of a sea-of-VersaTiles architecture.
As illustrated in Figure 2-2, there are four inputs in a logic VersaTile cell, and each VersaTile can be configured using the appropriate flash switch connections:
- Any 3-input logic function
- Latch with clear or set
- D-flip-flop with clear or set
- Enable D-flip-flop with clear or set (on a 4th input)
VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. VersaTiles and larger functions are connected with any of the four levels of routing hierarchy.
When the VersaTile is used as an enable D-flip-flop, the SET/CLR signal is supported by a fourth input, which can only be routed to the core cell over the VersaNet (global) network.
The output of the Versatile is F2 when the connection is to the ultra-fast local lines, or YL when the connection is to the efficient long-line or very-long-line resources (Figure 2-2).
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0<br>fu] 1 A . Y<br>Data<br>Pin 1<br> X3 0 0 F2<br>1 1<br>© L U CE<br>YL<br>0<br>CLK 1<br> X2 L<br> CLR/<br>Enable<br> X1 faa<br>CLR<br>XC* L<br>Legend: Via (hard connection) Switch (flash connection) Ground<br>**----- End of picture text -----**<br>
_Note: *This input can only be connected to the global clock distribution network._
_**Figure 2-2 •**_ **Fusion Core VersaTile**
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## _**VersaTile Characteristics**_
## _**Sample VersaTile Specifications—Combinatorial Module**_
The Fusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library (Figure 2-3). For more details, refer to the _IGLOO, ProASIC3, SmartFusion, and Fusion Macro Library Guide_ .
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A Y<br>INV<br>><br>A A<br>OR2 Y NOR2 Y<br>B B<br>><br>A<br>A<br>AND2 Y<br>NAND2 Y<br>B<br>| + B {><br>A<br>A<br>XOR2 Y B XOR 3 Y<br>B C<br>=) >- =} [>—]<br>A A<br>MAJ3 0<br>A MUX2 Y<br>B Y<br>B NAN D3 B<br>1<br>C<br>C<br>S<br>**----- End of picture text -----**<br>
_**Figure 2-3 •**_ **Sample of Combinatorial Cells**
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tPD<br>A<br>NAND2 or Y<br>Any Combinatorial<br>B Logic<br>tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR))<br>where edges are applicable for the<br>particular combinatorial cell<br>**----- End of picture text -----**<br>
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VCCA<br>50% 50%<br>A, B, C GND<br>VCCA<br>50%<br>50%<br>OUT<br>GND tPD tPD<br>(FF)<br>(RR)<br>VCCA<br>OUT tPD<br>50% (FR) 50%<br>tPD<br>GND<br>(RF)<br>**----- End of picture text -----**<br>
_**Figure 2-4 •**_ **Combinatorial Timing Model and Waveforms**
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## _**Timing Characteristics**_
_**Table 2-1 •**_ **Combinatorial Cell Propagation Delays**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Combinatorial Cell**<br>~~a~~<br>~~i~~|**Equation**<br>~~ee~~<br>~~ee~~|**Parameter**<br>~~ee~~|**–2**<br>~~ee~~|**–1**<br>~~ee~~|**Std.**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|
|INV<br>~~a~~<br>~~i~~<br>~~ee~~|Y = !A<br>~~ee~~<br>~~ee~~<br>~~ee~~|tPD<br>~~ee~~|0.40<br>~~ee~~|0.46<br>~~ee~~|0.54<br>~~ee~~|ns<br>~~ee~~|
|AND2<br>~~i ~~<br>~~ee~~|Y = A · B<br> ~~ee~~<br>~~ee~~|tPD|0.47|0.54|0.63|ns|
|NAND2<br>~~ee ~~<br>~~Rs~~|Y = !(A · B)<br> ~~ee~~<br>~~Rs~~|tPD<br>~~Rs~~|0.47<br>~~Rs~~|0.54<br>~~Rs~~|0.63<br>~~Rs~~|ns<br>~~Rs~~|
|OR2<br>~~se~~<br>~~es~~|Y = A + B<br>~~se~~|tPD<br>~~se~~|0.49<br>~~se~~|0.55<br>~~se~~|0.65<br>~~se~~|ns<br>~~se~~|
|NOR2<br>~~es~~<br>~~es~~|Y = !(A + B)<br>~~eG~~|tPD<br>~~eG~~|0.49|0.55|0.65|ns|
|XOR2<br>~~es~~<br>~~es~~|Y = AB<br>~~eG~~|tPD<br>~~eG~~|0.74|0.84|0.99|ns|
|MAJ3<br>~~es~~<br>~~a~~<br>~~ee~~|Y = MAJ(A, B, C)<br>~~eG~~<br>~~ee~~|tPD<br>~~eG~~|0.70|0.79|0.93|ns|
|XOR3<br>~~ee~~|Y = ABC<br>~~ee~~|tPD|0.87|1.00|1.17|ns|
|MUX2<br>~~ee ~~<br>~~Rs~~<br>~~rs~~|Y = A !S + B S<br> ~~ee~~<br>~~Rs~~|tPD<br>~~Rs~~|0.51<br>~~Rs~~|0.58<br>~~Rs~~|0.68<br>~~Rs~~|ns<br>~~Rs~~|
|AND3<br>~~rs~~|Y = A · B · C|tPD|0.56|0.64|0.75|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
## _**Sample VersaTile Specifications—Sequential Module**_
The Fusion library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library (Figure 2-5). For more details, refer to the _IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide_ .
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Data Out Data Out<br>D Q D Q<br>En<br>DFN1 DFN1E1<br>CLK CLK<br>PRE<br>Data Out Data Out<br>D Q D Q<br>En<br>DFN1C1 DFI1E1P1<br>CLK CLK<br>CLR<br>**----- End of picture text -----**<br>
_**Figure 2-5 •**_ **Sample of Sequential Cells**
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|tCKMPWHtCKMPWL|
|---|
|CLK<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%|
|tHD|
|tSUD|
|Data<br>EN<br>50%<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tWPRE<br>50%<br>50%<br>50%<br>~~|++~~+ —|
|PRE<br>tSUE|
|tRECCLR<br>tREMCLR<br>tWCLR|
|CLR<br>50%<br>50%<br>50%|
|tPRE2Q|
|tCLR2Q|
|50%<br>50%<br>50%|
|Out|
|tCLKQ|
||
|**_Figure 2-6 •_Sequential Timing Model and Waveforms**|
|**_Sequential Timing Characteristics_**|
|**_Table 2-2 •_Register Delays**|
|**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**|
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std.**<br>**Units**<br>tCLKQ<br>Clock-to-Q of the Core Register<br>0.55<br>0.63<br>0.74<br>ns<br>tSUD<br>Data Setup Time for the Core Register<br>0.43<br>0.49<br>0.57<br>ns<br>tHD<br>Data Hold Time for the Core Register<br>0.00<br>0.00<br>0.00<br>ns<br>tSUE<br>Enable Setup Time for the Core Register<br>0.45<br>0.52<br>0.61<br>ns<br>tHE<br>Enable Hold Time for the Core Register<br>0.00<br>0.00<br>0.00<br>ns<br>tCLR2Q<br>Asynchronous Clear-to-Q of the Core Register<br>0.40<br>0.45<br>0.53<br>ns<br>tPRE2Q<br>Asynchronous Preset-to-Q of the Core Register<br>0.40<br>0.45<br>0.53<br>ns<br>tREMCLR<br>Asynchronous Clear Removal Time for the Core Register<br>0.00<br>0.00<br>0.00<br>ns<br>tRECCLR<br>Asynchronous Clear Recovery Time for the Core Register<br>0.22<br>0.25<br>0.30<br>ns<br>tREMPRE<br>Asynchronous Preset Removal Time for the Core Register<br>0.00<br>0.00<br>0.00<br>ns<br>tRECPRE<br>Asynchronous Preset Recovery Time for the Core Register<br>0.22<br>0.25<br>0.30<br>ns<br>tWCLR<br>Asynchronous Clear Minimum Pulse Width for the Core Register<br>0.22<br>0.25<br>0.30<br>ns<br>tWPRE<br>Asynchronous Preset Minimum Pulse Width for the Core Register<br>0.22<br>0.25<br>0.30<br>ns<br>tCKMPWH<br>Clock Minimum Pulse Width High for the Core Register<br>0.32<br>0.37<br>0.43<br>ns<br>tCKMPWL<br>Clock Minimum Pulse Width Low for the Core Register<br>0.36<br>0.41<br>0.48<br>ns<br>~~esnn~~<br>~~I~~<br>~~lerns~~<br>~~I I~~<br>~~esns~~<br>~~lerns~~<br>~~I I~~<br>~~esns~~<br>~~lerns~~<br>~~I I~~<br>~~esns~~<br>~~lerns~~<br>~~I I~~<br>~~esns~~<br>~~lerns~~<br>~~I I~~<br>~~esns~~<br>~~lerns~~<br>~~I I~~<br>~~esns~~<br>~~lerns~~<br>~~I I~~<br>~~es~~~~**n**s~~<br>~~ee~~<br>~~S~~<br>~~I I~~|
|_Note:_<br>_For the derating values at specific junction temperature and voltage supply levels, refer toTable 3-7 on_|
|_page 3-9._|
_**Figure 2-6 •**_ **Sequential Timing Model and Waveforms**
_**Table 2-2 •**_ **Register Delays**
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## **Array Coordinates**
During many place-and-route operations in the Microsemi Designer software tool, it is possible to set constraints that require array coordinates. Table 2-3 is provided as a reference. The array coordinates are measured from the lower left (0, 0). They can be used in region constraints for specific logic groups/blocks, designated by a wild card, and can contain core cells, memories, and I/Os.
Table 2-3 provides array coordinates of core cells and memory blocks.
I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O cells and edge core cells. In addition, the I/O coordinate system changes depending on the die/package combination. It is not listed in Table 2-3. The Designer ChipPlanner tool provides array coordinates of all I/O locations. I/O and cell coordinates are used for placement constraints. However, I/O placement is easier by package pin assignment.
Figure 2-7 illustrates the array coordinates of an AFS600 device. For more information on how to use array coordinates for region/placement constraints, see the _Designer User's Guide_ or online help (available in the software) for Fusion software tools.
_**Table 2-3 •**_ **Array Coordinates**
|**Device**<br>~~sO~~<br>~~es~~<br>~~es~~<br>~~es~~|**VersaTiles**<br>~~sO~~|**VersaTiles**<br>~~sO~~|**VersaTiles**<br>~~sO~~|**VersaTiles**<br>~~sO~~|**Memory Rows**<br>~~sO~~|**Memory Rows**<br>~~sO~~|**All**<br>~~sO~~|**All**<br>~~sO~~|
|---|---|---|---|---|---|---|---|---|
||**Min.**<br>~~es~~<br>~~es~~<br>||**Max.**<br>~~eses~~<br>||**Bottom**<br>~~es~~|**Top**<br>~~es~~|**Min.**<br>~~es~~|**Max.**<br>~~es~~|
||**x**<br>~~es~~<br>~~**es**~~|**y**<br>~~es~~<br>~~es~~<br>~~**es**e~~~~**s**~~|**x**<br>~~es~~<br>~~e~~|**y**<br>~~es~~<br>~~e~~~~**G**~~|**(x, y)**<br>~~es~~<br>~~QS~~|**(x, y)**<br>~~es~~<br>~~QS~~|**(x, y)**<br>~~es~~<br>~~QS~~|**(x, y)**<br>~~es~~|
|AFS090<br>~~es~~<br>~~es~~<br>~~es~~|3<br>~~es~~<br>~~**es**~~|2<br>~~es~~<br>~~es~~<br>~~**es**e~~~~**s**~~|98<br>~~es~~<br>~~e~~<br>~~e~~|25<br>~~es~~<br>~~e~~~~**G**~~|None<br>~~es~~<br>~~QS~~|(3, 26)<br>~~es~~<br>~~QS~~<br>~~G~~|(0, 0)<br>~~es~~<br>~~QS~~<br>~~G~~|(101, 29)<br>~~es~~<br>~~G~~|
|AFS250<br>~~es~~<br>~~es ~~<br>~~es~~|3<br>~~es~~<br> ~~**es**~~|2<br>~~es~~<br>~~es~~<br>~~**es**e~~~~**s**~~|130<br>~~es~~<br>~~e~~<br>~~e~~|49<br>~~es~~<br>~~e~~~~**G**~~|None<br>~~es~~<br>~~QS~~|(3, 50)<br>~~es~~<br>~~QS~~<br>~~G~~|(0, 0)<br>~~es~~<br>~~QS~~<br>~~G~~|(133, 53)<br>~~es~~<br>~~G~~|
|AFS600<br> <br>~~es~~<br>~~PF~~<br>~~es~~|3<br> ~~**es**~~<br>~~PF~~<br>~~es~~|4<br>~~**es** e~~~~**s** ~~<br>~~es~~<br>~~es~~|194<br> ~~e~~<br>~~e~~<br>~~ee~~|75<br>~~e~~~~**G**~~<br>~~ee~~|(3, 2)<br>~~QS~~<br>~~ee~~|(3, 76)<br>~~QS~~<br>~~G~~<br>~~ee~~|(0, 0)<br>~~QS~~<br>~~G~~<br>~~ee~~|(197, 79)<br>~~G~~<br>~~ee~~|
|AFS1500<br>~~PF~~<br>~~es~~|3<br>~~PF~~<br>~~es~~|4<br>~~es~~<br>~~es~~|322<br>~~ee~~|123<br>~~ee~~|(3, 2)<br>~~ee~~|(3, 124)<br>~~ee~~|(0, 0)<br>~~ee~~|(325, 129)<br>~~ee~~|
## **I/O Tile**
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Top Row (7, 79) to (189, 79)<br>Bottom Row (5, 78) to (192, 78)<br>(0, 79) (197, 79)<br>Memory (3, 77) FEEL GREECE. FEEEEESEESEEEE FE (194, 77) Memory<br>Blocks (3, 76) (194, 76) Blocks<br>O08 f lee ee<br>VersaTile (Core)<br>po FLT TT TTT ettitt tt PE TTttti tt tt tit tt 4 _<br> (3, 75)<br>Sam pg (194, 75)<br>LILI TIT VersaTile (Core)<br>OTH yy ----eee ee LITT TTT ITT TIT tT tt) Ereee<br>tT ETTTTTTETTITEEA ITEP<br>VersaTile (Core) ==ae aOe ee SeeETEE EEE eo (194, 4)VersaTile(Core)<br> (3, 4)<br>(194, 3) Memory<br>(194, 2) Blocks<br>Memory (3, 3) foe ee =E=<br>Blocks (3, 2) FCCC CCE)? GEE<br>eo MUG HUHGHGHGHGEEnE ——Pt tpt tt | ry]<br>HH eeeFee aa<br>(197, 1)<br>ann FH LH EEE<br>See? Fone co EER<br>(0, 0) I/O Tile to Analog Block UJTAG FlashROM (197, 0)<br>Top Row (5, 1) to (168, 1) Top Row (169, 1) to (192, 1)<br>Bottom Row (7, 0) to (165, 0)<br>**----- End of picture text -----**<br>
_Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}._
_**Figure 2-7 •**_ **Array Coordinates for AFS600**
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## **Routing Architecture**
The routing structure of Fusion devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources; efficient long-line resources; highspeed very-long-line resources; and the high-performance VersaNet networks.
The ultra-fast local resources are dedicated lines that allow the output of each VersaTile to connect directly to every input of the eight surrounding VersaTiles (Figure 2-8). The exception to this is that the SET/CLR input of a VersaTile configured as a D-flip-flop is driven only by the VersaNet global network.
The efficient long-line resources provide routing for longer distances and higher-fanout connections. These resources vary in length (spanning one, two, or four VersaTiles), run both vertically and horizontally, and cover the entire Fusion device (Figure 2-9 on page 2-9). Each VersaTile can drive signals onto the efficient long-line resources, which can access every input of every VersaTile. Active buffers are inserted automatically by routing software to limit loading effects.
The high-speed very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length ±12 VersaTiles in the vertical direction and length ±16 in the horizontal direction from a given core VersaTile (Figure 2-10 on page 2-10). Very long lines in Fusion devices, like those in ProASIC3 devices, have been enhanced. This provides a significant performance boost for long-reach signals.
The high-performance VersaNet global networks are low-skew, high-fanout nets that are accessible from external pins or from internal logic (Figure 2-11 on page 2-11). These nets are typically used to distribute clocks, reset signals, and other high-fanout nets requiring minimum skew. The VersaNet networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all VersaTiles.
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Long Lines<br>A\<br>L L L<br>oe L Inputs So L L<br>Ultra-Fast Local Lines<br>(connects a VersaTile to the<br>N o n a 2 e adjacent VersaTile, I/O buffer,<br>or memory block)<br>i ttt it<br>L L L<br>Output<br>**----- End of picture text -----**<br>
_Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection._ _**Figure 2-8 •**_ **Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors**
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Spans Four VersaTiles Spans One VersaTile<br>Spans Two VersaTiles<br>VersaTile<br>L L L L L L<br>L L L L L L<br>Spans One VersaTile<br>L L L L L L<br>Spans Two VersaTiles<br>Spans Four VersaTiles<br>L L L L L L<br>L L L L L L<br>**----- End of picture text -----**<br>
_**Figure 2-9 •**_ **Efficient Long-Line Resources**
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High-Speed, Very-Long-Line Resources<br>[\<br>Pad Ring<br>SRAM<br>MAM<br>— SS<br>Lk ies<br>PF EP LILI LI EI LI LI LI<br>16×12 Block of VersaTiles<br>TIE LILI CLI EI LILI Ud is<br>we| | | |||<br>PF EI LILI LI LI LI LI LI oo<br>Be| | | | | |<br>——— eae<br>WMA<br>I/O Ring<br>I/O Ring<br>Pad Ring<br>**----- End of picture text -----**<br>
_**Figure 2-10 •**_ **Very-Long-Line Resources**
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## **Global Resources (VersaNets)**
Fusion devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has six CCCs. The west CCC also contains a PLL core. In the two larger devices (AFS600 and AFS1500), the west and the east CCCs each contain a PLL. The PLLs include delay lines, a phase shifter (0°, 90°, 180°, 270°), and clock multipliers/dividers. Each CCC has all the circuitry needed for the selection and interconnection of inputs to the VersaNet global network. The east and west CCCs each have access to three VersaNet global lines on each side of the chip (six lines total). The CCCs at the four corners each have access to three quadrant global lines on each quadrant of the chip.
## _**Advantages of the VersaNet Approach**_
One of the architectural benefits of Fusion is the set of powerful and low-delay VersaNet global networks. Fusion offers six chip (main) global networks that are distributed from the center of the FPGA array (Figure 2-11). In addition, Fusion devices have three regional globals (quadrant globals) in each of the four chip quadrants. Each core VersaTile has access to nine global network resources: three quadrant and six chip (main) global networks. There are a total of 18 global networks on the device. Each of these networks contains spines and ribs that reach all VersaTiles in all quadrants (Figure 2-12 on page 2-12). This flexible VersaNet global network architecture allows users to map up to 180 different internal/external clocks in a Fusion device. Details on the VersaNet networks are given in Table 2-4 on page 2-12. The flexibility of the Fusion VersaNet global network allows the designer to address several design requirements. User applications that are clock-resource-intensive can easily route external or gated internal clocks using VersaNet global routing networks. Designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the VersaNet global network.
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Quadrant Global Pads<br>High-Performance<br>VersaNet Global Network<br>Pad Ring<br>\E XX #<br>e e ee ee ee ee = Yr I<br>Top Spine<br>E E ] L e Ld t= | Main (chip)<br>PTE IL | C T Er L I T Global Network<br>NN Bx<br>Global<br>Chip (main) Pads<br>Global Pads<br>“ Za PIC EJ a s Global RibsGlobal Spine<br>Bottom Spine<br>z l 4 = = == | =<br>Spine-Selection<br>Tree MUX P L L e L d LY yikes<br>Pad Ring<br>I/O Ring<br>I/O Ring<br>**----- End of picture text -----**<br>
_**Figure 2-11 •**_ **Overview of Fusion VersaNet Global Network**
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Northwest Quadrant Global Network<br>CCC<br>CCC<br>3 3 3 3<br>Chip (main)<br>Global<br>Network<br>6 6 6 6<br>3<br>CCC<br>A ir Gee 2 ae 3 a<br>CCC<br>GE 6 6 6 6<br>3 3 3 3<br>CCC<br>CCC<br>a —— ‘<br>Southeast Quadrant Global Network<br>Quadrant Global Spine<br>Global Spine<br>**----- End of picture text -----**<br>
_**Figure 2-12 •**_ **Global Network Architecture**
_**Table 2-4 •**_ **Globals/Spines/Rows by Device**
|**_Table 2-4 •_Globals/Spines/Rows by Device**|||||
|---|---|---|---|---|
||**AFS090**|**AFS250**|**AFS600**|**AFS1500**|
|Global VersaNets (trees)*|9|9|9|9|
|VersaNet Spines/Tree|4|8|12|20|
|Total Spines|36|72|108|180|
|VersaTiles in Each Top or Bottom Spine|384|768|1,152|1,920|
|Total VersaTiles|2,304|6,144|13,824|38,400|
_Note: *There are six chip (main) globals and three globals per quadrant._
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## _**VersaNet Global Networks and Spine Access**_
The Fusion architecture contains a total of 18 segmented global networks that can access the VersaTiles, SRAM, and I/O tiles on the Fusion device. There are 6 chip (main) global networks that access the entire device and 12 quadrant networks (3 in each quadrant). Each device has a total of 18 globals. These VersaNet global networks offer fast, low-skew routing resources for high-fanout nets, including clock signals. In addition, these highly segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 180 internal/external clocks (in an AFS1500 device) or other high-fanout nets in Fusion devices. Optimal usage of these low-skew networks can result in significant improvement in design performance on Fusion devices.
The nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global network, which has six spines. Note that there are three quadrant spines in each quadrant of the device. There are four quadrant global network regions per device (Figure 2-12 on page 2-12).
The spines are the vertical branches of the global network tree, shown in Figure 2-11 on page 2-11. Each spine in a vertical column of a chip (main) global network is further divided into two equal-length spine segments: one in the top and one in the bottom half of the die.
Each spine and its associated ribs cover a certain area of the Fusion device (the “scope” of the spine; see Figure 2-11 on page 2-11). Each spine is accessed by the dedicated global network MUX tree architecture, which defines how a particular spine is driven—either by the signal on the global network from a CCC, for example, or another net defined by the user (Figure 2-13). Quadrant spines can be driven from user I/Os on the north and south sides of the die, via analog I/Os configured as direct digital inputs. The ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design.
Details of the chip (main) global network spine-selection MUX are presented in Figure 2-13. The spine drivers for each spine are located in the middle of the die.
Quadrant spines are driven from a north or south rib. Access to the top and bottom ribs is from the corner CCC or from the I/Os on the north and south sides of the device. For details on using spines in Fusion devices, see the application note _Using Global Resources in Actel Fusion Devices_ .
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Internal/External Internal/External<br>Signals Signals<br>f; f 4 4<br>Tree Node MUX Tree Node MUX<br>Internal/External<br>Signal<br>Tree Node MUX<br>Global Rib<br>Internal/External<br>Signal<br>Global Driver MUX<br>Spine<br>**----- End of picture text -----**<br>
_**Figure 2-13 •**_ **Spine-Selection MUX of Global Tree**
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## _**Clock Aggregation**_
Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also through local resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As Figure 2-14 indicates, this access system is contiguous.
There is no break in the middle of the chip for north and south I/O VersaNet access. This is different from the quadrant clocks, located in these ribs, which only reach the middle of the rib. Refer to the _Using Global Resources in Actel Fusion Devices_ application note.
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Global Spine I/O Access I/O Tiles<br>Global Rib Internal Signal Access<br>Global Driver and MUX — Global Signal Access ~~<br>Tree Node MUX<br>**----- End of picture text -----**<br>
_**Figure 2-14 •**_ **Clock Aggregation Tree Architecture**
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_Device Architecture_
## _**Global Resource Characteristics**_
## _**AFS600 VersaNet Topology**_
Clock delays are device-specific. Figure 2-15 is an example of a global tree used for clock routing. The global tree presented in Figure 2-15 is driven by a CCC located on the west side of the AFS600 device. It is used to drive all D-flip-flops in the device.
**==> picture [460 x 107] intentionally omitted <==**
**----- Start of picture text -----**<br>
Central<br>Global Rib<br>CCC<br>VersaTile<br>Rows<br>SERRE EERE REEY<br>can ae<br>Global Spine<br>**----- End of picture text -----**<br>
_**Figure 2-15 •**_ **Example of Global Tree Use in an AFS600 Device for Clock Routing**
**2-15**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**VersaNet Timing Characteristics**_
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are dependent upon I/O standard, and the clock may be driven and conditioned internally by the CCC module. Table 2-5, Table 2-6, Table 2-7, and Table 2-8 on page 2-17 present minimum and maximum global clock delays within the device Minimum and maximum delays are measured with minimum and maximum loading, respectively.
## _**Timing Characteristics**_
_**Table 2-5 •**_ **AFS1500 Global Resource Timing**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~eeee~~<br>~~Da~~|**Description**<br>~~ee~~<br>~~—~~<br>|**–2**<br>~~ee~~<br>~~—|~~<br>~~|~~<br>|**–2**<br>~~ee~~<br>~~—|~~<br>~~|~~<br>|**–1**<br>~~ee~~<br>~~|~~<br>~~|~~<br>|**–1**<br>~~ee~~<br>~~|~~<br>~~|~~<br>|**Std.**<br>~~ee~~<br>~~|~~<br>|**Std.**<br>~~ee~~<br>~~|~~<br>|**Units**<br>~~ee~~<br>~~|~~<br>|
|---|---|---|---|---|---|---|---|---|
|||**Min.1**<br>~~ee~~<br>~~—|~~<br>|**Max.2**<br>~~ee~~<br>~~|~~<br>|**Min.1**<br>~~ee~~<br>~~|~~<br>|**Max.2**<br>~~ee~~<br>~~|~~<br>|**Min.1**<br>~~ee~~<br>~~|~~<br>|**Max.2**<br>~~ee~~<br>~~|~~<br>||
|tRCKL<br>~~eeee~~<br>~~Da DR~~<br>~~LR~~|Input Low Delay for Global Clock<br>~~ee~~<br>~~—~~<br>~~DR~~<br>|1.53<br>~~ee~~<br>~~—|~~<br>~~DR~~<br>~~es~~<br>|1.75<br>~~ee~~<br>~~|~~<br>~~DR~~<br>~~es~~<br>|1.74<br>~~ee~~<br>~~|~~<br>~~DR~~<br>~~es~~<br>|1.99<br>~~ee~~<br>~~|~~<br>~~DR~~<br>|2.05<br>~~ee~~<br>~~|~~<br>~~DR~~<br>|2.34<br>~~ee~~<br>~~|~~<br>~~DR~~<br>|ns<br>~~ee~~<br>~~|~~<br>~~DR~~<br>|
|tRCKH<br>~~Da ~~<br>~~a De~~<br>~~LR~~|Input High Delay for Global Clock<br>~~—~~<br><br>~~De~~<br>|1.53<br>~~— |~~<br><br>~~De~~<br>~~es~~<br>|1.79<br>~~|~~<br><br>~~De~~<br>~~es~~<br>|1.75<br>~~|~~<br><br>~~De~~<br>~~es~~<br>|2.04<br>~~| ~~<br><br>~~De~~<br>|2.05<br> ~~|~~<br><br>~~De~~<br>|2.40<br>~~|~~<br><br>~~De~~<br>|ns<br>~~|~~<br><br>~~De~~<br>|
|tRCKMPWH<br>~~LR es~~|Minimum Pulse Width High for Global Clock<br>~~es~~|~~es~~<br>~~es~~|~~es~~<br>~~es~~|~~es~~<br>~~es~~|~~es~~|~~es~~|~~es~~|ns<br>~~es~~|
|tRCKMPWL<br>~~LR es~~<br>~~a~~|Minimum Pulse Width Low for Global Clock<br>~~es~~<br>|~~es~~<br>~~es~~<br>|~~es~~<br>~~es~~<br>|~~es~~<br>~~es~~<br>|~~es~~<br>|~~es~~<br>|~~es~~<br>|ns<br>~~es~~<br>|
|tRCKSW<br>~~De~~|Maximum Skew for Global Clock<br>~~De~~|~~De~~|0.26<br>~~De~~|~~De~~|0.29<br>~~De~~|~~De~~|0.34<br>~~De~~|ns<br>~~De~~|
_Notes:_
_1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net)._
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
_**Table 2-6 •**_ **AFS600 Global Resource Timing**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~ee~~<br>~~a~~|**Description**<br>~~ee~~<br>|**–2**<br>~~ee~~<br>~~i~~<br>~~ee~~<br>|**–2**<br>~~ee~~<br>~~i~~<br>~~ee~~<br>|**–1**<br>~~ee~~<br>~~eeee~~<br>|**–1**<br>~~ee~~<br>~~eeee~~<br>|**Std.**<br>~~ee~~<br>~~ee~~<br>|**Std.**<br>~~ee~~<br>~~ee~~<br>|**Units**<br>~~ee~~<br>|
|---|---|---|---|---|---|---|---|---|
|||**Min.1**<br>~~ee~~<br>~~i~~<br>|**Max.2**<br>~~ee~~<br>~~ee~~<br>|**Min.1**<br>~~ee~~<br>~~ee~~<br>|**Max.2**<br>~~ee~~<br>~~ee~~<br>|**Min.1**<br>~~ee~~<br>~~ee~~<br>|**Max.2**<br>~~ee~~<br>~~ee~~<br>||
|tRCKL<br>~~a~~<br>~~a~~|Input Low Delay for Global Clock<br><br>|1.27<br>~~i~~<br>|1.49<br>~~ee~~<br><br>~~ss~~|1.44<br>~~ee ~~<br><br>~~ss~~|1.70<br> ~~ee~~<br><br>~~ss~~|1.69<br>~~ee~~<br>|2.00<br>~~ee~~<br>|ns<br>|
|tRCKH<br>~~Os~~<br>~~a~~|Input High Delay for Global Clock<br>~~Os~~<br>|1.26<br>~~Os~~|1.54<br>~~Os~~<br>~~ss~~|1.44<br>~~Os~~<br>~~ss~~|1.75<br>~~Os~~<br>~~ss~~|1.69<br>~~Os~~|2.06<br>~~Os~~|ns<br>~~Os~~|
|tRCKMPWH<br>~~a ~~|Minimum Pulse Width High for Global Clock<br> ~~a~~||~~ss~~|~~ss~~|~~ss~~|||ns|
|tRCKMPWL<br>~~a~~|Minimum Pulse Width Low for Global Clock<br>~~a~~|~~a~~<br>~~ss~~|~~a~~<br>~~ss~~|~~a~~<br>~~ss~~|~~a~~<br>~~ss~~|~~a~~|~~a~~|ns<br>~~a~~|
|tRCKSW<br>~~i~~|Maximum Skew for Global Clock<br>~~i~~|~~i~~<br>~~ss~~|0.27<br>~~i~~<br>~~ss~~|~~i~~<br>~~ss~~|0.31<br>~~i~~<br>~~ss~~|~~i~~|0.36<br>~~i~~|ns<br>~~i~~|
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-16**
_Device Architecture_
_**Table 2-7 •**_ **AFS250 Global Resource Timing**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**–2**<br>~~a~~|**–2**<br>~~a~~|**–1**<br>~~a~~|**–1**<br>~~a~~|**Std.**<br>~~a~~|**Std.**<br>~~a~~|**Units**<br>~~a~~<br>~~tt~~|
|---|---|---|---|---|---|---|---|---|
|||**Min.1**<br>~~a~~<br>~~tt~~|**Max.2**<br>~~a~~<br>~~tt~~|**Min.1**<br>~~a~~<br>~~tt~~|**Max.2**<br>~~a~~<br>~~tt~~|**Min.1**<br>~~a~~<br>~~tt~~|**Max.2**<br>~~a~~<br>~~tt~~||
|tRCKL<br>~~a~~|Input Low Delay for Global Clock<br>~~es~~|0.89<br>~~es~~|1.12<br>~~es~~|1.02<br>~~es~~|1.27<br>~~es~~|1.20<br>~~es~~|1.50<br>~~es~~|ns<br>~~es~~|
|tRCKH<br>~~a~~|Input High Delay for Global Clock|0.88|1.14|1.00|1.30|1.17|1.53|ns|
|tRCKMPWH<br>~~a~~|Minimum Pulse Width High for Global Clock<br>~~Gs~~|~~Gs~~|~~Gs~~|~~Gs~~|~~Gs~~|~~Gs~~|~~Gs~~|ns<br>~~Gs~~|
|tRCKMPWL<br>~~a ss~~|Minimum Pulse Width Low for Global Clock<br>~~ss~~|~~ss~~|~~ss~~|~~ss~~|~~ss~~|~~ss~~|~~ss~~|ns<br>~~ss~~|
|tRCKSW<br>~~a ss~~<br>~~a ss~~|Maximum Skew for Global Clock<br>~~ss~~<br>~~ss~~|~~ss~~<br>~~ss~~|0.26<br>~~ss~~<br>~~ss~~|~~ss~~<br>~~ss~~|0.30<br>~~ss~~<br>~~ss~~|~~ss~~<br>~~ss~~|0.35<br>~~ss~~<br>~~ss~~|ns<br>~~ss~~<br>~~ss~~|
## _Notes:_
_1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net)._
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
## _**Table 2-8 •**_ **AFS090 Global Resource Timing**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~ee~~<br>~~a~~|**Description**<br>~~ee~~<br>~~i~~<br>|**–2**<br>~~ee~~<br>~~eee~~<br>~~i~~<br>~~ee~~<br>|**–2**<br>~~ee~~<br>~~eee~~<br>~~i~~<br>~~ee~~<br>|**–1**<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|**–1**<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|**Std.**<br>~~ee~~<br>~~el~~<br>|**Std.**<br>~~ee~~<br>~~el~~<br>|**Units**<br>~~ee~~<br>~~el~~<br>|
|---|---|---|---|---|---|---|---|---|
|||**Min.1**<br>~~ee~~<br>~~eee~~<br>~~i~~<br><br>~~es~~|**Max.2**<br>~~ee~~<br>~~eee~~<br>~~ee~~<br><br>~~ee~~|**Min.1**<br>**Max.2**<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>||**Min.1**<br>**Max.2**<br>~~ee~~<br>~~el~~<br>|||
|tRCKL<br>~~a Cs~~|Input Low Delay for Global Clock<br>~~i~~<br>~~Cs~~|0.84<br>~~eee~~<br>~~i~~<br>~~Cs~~<br>~~es~~|1.07<br>~~eee~~<br>~~ee~~<br>~~Cs~~<br>~~ee~~|0.96<br>1.21<br>~~eee ~~<br>~~ee~~<br>~~Cs~~||1.13<br>1.43<br> ~~el~~<br>~~Cs~~||ns<br>~~el~~<br>~~Cs~~|
|tRCKH<br>~~a Cs~~<br>~~ee~~|Input High Delay for Global Clock<br>~~Cs~~<br>~~ee~~|0.83<br>~~Cs~~<br>~~es ~~<br>~~ee~~|1.10<br>~~ee~~<br>~~Cs~~<br> ~~ee~~<br>~~ee~~|0.95<br>~~ee~~<br>~~Cs~~<br>~~ee~~|1.25<br>~~ee~~<br>~~Cs~~<br>~~ee~~|1.12<br>~~Cs~~<br>~~ee~~|1.47<br>~~Cs~~<br>~~ee~~|ns<br>~~Cs~~<br>~~ee~~|
|tRCKMPWH<br>~~Pe~~<br>~~VR~~|Minimum Pulse Width High for Global Clock<br>~~Pe~~|~~Pe~~|~~Pe~~|~~Pe~~|~~Pe~~|~~Pe~~|~~Pe~~|ns<br>~~Pe~~|
|tRCKMPWL<br>~~VR~~<br>~~PR~~|Minimum Pulse Width Low for Global Clock|||||||ns|
|tRCKSW<br>~~VR~~<br>~~PR~~|Maximum Skew for Global Clock||0.27||0.30||0.36|ns|
## _Notes:_
_1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net)._
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-17**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Clocking Resources**
The Fusion family has a robust collection of clocking peripherals, as shown in the block diagram in Figure 2-16. These on-chip resources enable the creation, manipulation, and distribution of many clock signals. The Fusion integrated RC oscillator produces a 100 MHz clock source with no external components. For systems requiring more precise clock signals, the Fusion family supports an on-chip crystal oscillator circuit. The integrated PLLs in each Fusion device can use the RC oscillator, crystal oscillator, or another on-chip clock signal as a source. These PLLs offer a variety of capabilities to modify the clock source (multiply, divide, synchronize, advance, or delay). Utilizing the CCC found in the popular ProASIC3 family, Fusion incorporates six CCC blocks. The CCCs allow access to Fusion global and local clock distribution nets, as described in the "Global Resources (VersaNets)" section on page 2-11.
**==> picture [458 x 215] intentionally omitted <==**
**----- Start of picture text -----**<br>
Off-Chip On-Chip<br>100 MHz<br>GNDOSC<br>RC Oscillator<br>VCCOSC<br>Clock Out to FPGA Core through CCC<br>XTAL1<br>GLINT<br>Crystal Oscillator<br>tT XTAL2 LL<br>To Core<br>Xtal Clock PLL/ GLA NGMUX<br>ExternalCrystal or ExternalRC Clock I/Os CCC GLC CLKOUT<br>From FPGA Core<br>**----- End of picture text -----**<br>
_**Figure 2-16 •**_ **Fusion Clocking Options**
**Revision 8**
**2-18**
_Device Architecture_
## **RC Oscillator**
The RC oscillator is an on-chip free-running clock source generating a 100 MHz clock. It can be used as a source clock for both on-chip and off-chip resources. When used in conjunction with the Fusion PLL and CCC circuits, the RC oscillator clock source can be used to generate clocks of varying frequency and phase.
The Fusion RC oscillator is very accurate at ±1% over commercial temperature ranges and ±3% over industrial temperature ranges. It is an automated clock, requiring no setup or configuration by the user. It requires only that the power and GNDOSC pins be connected; no external components are required. The RC oscillator can be used to drive either a PLL or another internal signal.
## _**RC Oscillator Characteristics**_
_**Table 2-9 •**_ **Electrical Characteristics of RC Oscillator**
|**Parameter**<br>~~se~~|**Description**<br>~~se~~|**Conditions**<br>~~se~~|**Min.**<br>~~se~~|**Typ.**<br>~~se~~|**Max.**<br>~~se~~|**Units**<br>~~se~~|
|---|---|---|---|---|---|---|
|FRC<br>~~se~~|Operating Frequency<br>~~se~~<br>~~a~~|~~se~~|~~se~~|100<br>~~se~~|~~se~~|MHz<br>~~se~~|
||Accuracy|Temperature: 0°C to 85°C<br>Voltage: 3.3 V ± 5%||1||%|
|||Temperature: –40°C to 125°C<br>Voltage: 3.3 V ± 5%||3||%|
||Output Jitter|Period Jitter (at 5 k cycles)<br>~~es~~|~~es~~|100<br>~~es~~|~~es~~|ps<br>~~es~~|
|||Cycle–Cycle Jitter (at 5 k cycles)<br>~~es~~<br>~~ee ee~~|~~es~~<br>~~ee~~|100<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|ps<br>~~es~~<br>~~ee~~|
|||Period Jitter (at 5 k cycles) with 1 KHz / 300 mV<br>peak-to-peak noise on power supply<br>~~ee ee~~|~~ee~~|150<br>~~ee~~|~~ee~~|ps<br>~~ee~~|
|||Cycle–Cycle Jitter (at 5 k cycles) with 1 KHz /<br>300 mV peak-to-peak noise on power supply<br>~~ee ee~~|~~ee~~|150<br>~~ee~~|~~ee~~|ps<br>~~ee~~|
||Output Duty Cycle<br>~~ee~~|~~ee~~|~~ee~~|50<br>~~ee~~|~~ee~~|%<br>~~ee~~|
|IDYNRC<br>~~ee~~|Operating Current<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
**2-19**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Crystal Oscillator**
The Crystal Oscillator (XTLOSC) is source that generates the clock from an external crystal. The output of XTLOSC CLKOUT signal can be selected as an input to the PLL. Refer to the "Clock Conditioning Circuits" section for more details. The XTLOSC can operate in normal operations and Standby mode (RTC is running and 1.5 V is not present).
In normal operation, the internal FPGA_EN signal is '1' as long as 1.5 V is present for VCC. As such, the internal enable signal, XTL_EN, for Crystal Oscillator is enabled since FPGA_EN is asserted. The XTL_MODE has the option of using MODE or RTC_MODE, depending on SELMODE.
During Standby, 1.5 V is not available, as such, and FPGA_EN is '0'. SELMODE must be asserted in order for XTL_EN to be enabled; hence XTL_MODE relies on RTC_MODE. SELMODE and RTC_MODE must be connected to RTCXTLSEL and RTCXTLMODE from the AB respectively for correct operation during Standby (refer to the "Real-Time Counter System" section on page 2-31 for a detailed description).
The Crystal Oscillator can be configured in one of four modes:
- RC network, 32 KHz to 4 MHz
- Low gain, 32 to 200 KHz
- Medium gain, 0.20 to 2.0 MHz
- High gain, 2.0 to 20.0 MHz
In RC network mode, the XTAL1 pin is connected to an RC circuit, as shown in Figure 2-16 on page 2-18. The XTAL2 pin should be left floating. The RC value can be chosen based on Figure 2-18 for any desired frequency between 32 KHz and 4 MHz. The RC network mode can also accommodate an external clock source on XTAL1 instead of an RC circuit.
In Low gain, Medium gain, and High gain, an external crystal component or ceramic resonator can be added onto XTAL1 and XTAL2, as shown in Figure 2-16 on page 2-18. In the case where the Crystal Oscillator block is not used, the XTAL1 pin should be connected to GND and the XTAL2 pin should be left floating.
**==> picture [259 x 130] intentionally omitted <==**
**----- Start of picture text -----**<br>
XTLOSC<br>FPGA_EN*<br>SELMODE XTL_EN*<br>CLKOU T<br>MODE[1:0] 0<br>XTL_MODE*<br>RTC_MODE[1:0 ] 1<br>XTL<br>**----- End of picture text -----**<br>
_Note: *Internal signal—does not exist in macro._
_**Figure 2-17 •**_ **XTLOSC Macro**
**Revision 8**
**2-20**
_Device Architecture_
**==> picture [343 x 230] intentionally omitted <==**
**----- Start of picture text -----**<br>
RC Time Constant Values vs. Frequency<br>1.00E-0.3<br>1.00E-0.4<br>1.00E-0.5<br>1.00E-0.6<br>1.00E-0.7<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5<br>Frequency (MHz)<br>RC Time Constant (sec)<br>**----- End of picture text -----**<br>
_**Figure 2-18 •**_ **Crystal Oscillator: RC Time Constant Values vs. Frequency (typical)**
_**Table 2-10 •**_ **XTLOSC Signals Descriptions**
|~~Re~~|~~Os~~|||||
|---|---|---|---|---|---|
|**Signal Name**<br>~~Re~~|**Width **<br>~~Os~~|**Direction**|**Function**|||
|XTL_EN*<br>~~Re ~~<br>~~ee~~|1<br> ~~Os~~<br>~~ee~~||Enables the crystal. Active high.|||
|XTL_MODE*<br>~~ee~~<br>~~se~~|2<br>~~ee~~<br>~~se~~|~~se~~|Settings for the crystal clock for different frequency.<br>~~se~~|||
|~~se~~|~~se~~||**Value**|**Modes**|**Frequency Range**|
|~~se~~<br>~~es~~|~~se~~<br>~~es~~|~~es~~|b'00<br>~~es~~|RC network<br>~~es~~|32 KHz to 4 MHz<br>~~es~~|
|~~se~~|~~se~~|~~se~~|b'01<br>~~se~~|Low gain<br>~~se~~|32 to 200 KHz<br>~~se~~|
|~~se~~<br>~~es~~|~~se~~<br>~~es~~|~~se~~<br>~~es~~|b'10<br>~~se~~<br>~~es~~|Medium gain<br>~~se~~<br>~~es~~|0.20 to 2.0 MHz<br>~~se~~<br>~~es~~|
|~~se~~<br>~~a~~|~~se~~<br>~~ee~~|~~se~~<br>~~ee~~|b'11<br>~~se~~<br>~~ee~~|High gain<br>~~se~~<br>~~ee~~|2.0 to 20.0 MHz<br>~~se~~<br>~~ee~~|
|SELMODE<br>~~se~~<br>~~a~~|1<br>~~se~~<br>~~ee~~|IN<br>~~se~~<br>~~ee~~|Selects the source of XTL_MODE and also enables the XTL_EN. Connect<br>from RTCXTLSEL from AB.<br>~~se~~<br>~~ee~~|||
|~~a~~<br>~~a~~|~~ee~~<br>|~~ee~~<br>|0<br>~~ee~~<br>|For normal operation or sleep mode, XTL_EN depends on<br>FPGA_EN, XTL_MODE depends on MODE<br>~~ee~~<br>||
|~~ee~~<br>~~a~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|1<br>~~ee~~|For Standby mode, XTL_EN is enabled, XTL_MODE depends on<br>RTC_MODE<br>~~ee~~||
|RTC_MODE[1:0]<br>~~ee~~<br>~~a~~|2<br>~~ee~~<br>~~ee~~|IN<br>~~ee~~<br>~~ee~~|Settings for the crystal clock for different frequency ranges. XTL_MODE uses<br>RTC_MODE when SELMODE is '1'.<br>~~ee~~|||
|MODE[1:0]<br>~~a~~<br>~~a~~|2<br>~~ee~~<br>~~a~~|IN<br>~~ee~~<br>~~a~~|Settings for the crystal clock for different frequency ranges. XTL_MODE uses<br>MODE when SELMODE is '0'. In Standby, MODE inputs will be 0's.|||
|FPGA_EN*<br>~~ee~~|1<br>~~ee~~|IN|0 when 1.5 V is not present for VCC 1 when 1.5 V is present for VCC|||
|XTL<br>~~ee~~<br>~~Gs~~|1<br>~~ee~~<br>~~Gs~~|IN<br>~~Gs~~|Crystal Clock source<br>~~Gs~~|||
|CLKOUT<br>~~ee~~|1<br>~~ee~~|OUT|Crystal Clock output|||
_Note: *Internal signal—does not exist in macro._
**2-21**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Clock Conditioning Circuits**
In Fusion devices, the CCCs are used to implement frequency division, frequency multiplication, phase shifting, and delay operations.
The CCCs are available in six chip locations—each of the four chip corners and the middle of the east and west chip sides.
Each CCC can implement up to three independent global buffers (with or without programmable delay), or a PLL function (programmable frequency division/multiplication, phase shift, and delays) with up to three global outputs. Unused global outputs of a PLL can be used to implement independent global buffers, up to a maximum of three global outputs for a given CCC.
A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, and CLKC-GLC) of a given CCC.
A PLL macro uses the CLKA CCC input to drive its reference clock. It uses the GLA and, optionally, the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC) output is used (Figure 2-19). Refer to the "PLL Macro" section on page 2-27 for more information.
Each global buffer, as well as the PLL reference clock, can be driven from one of the following:
- 3 dedicated single-ended I/Os using a hardwired connection
- 2 dedicated differential I/Os using a hardwired connection
- The FPGA core
The CCC block is fully configurable, either via flash configuration bits set in the programming bitstream or through an asynchronous interface. This asynchronous interface is dynamically accessible from inside the Fusion device to permit changes of parameters (such as divide ratios) during device operation. To increase the versatility and flexibility of the clock conditioning system, the CCC configuration is determined either by the user during the design process, with configuration data being stored in flash memory as part of the device programming procedure, or by writing data into a dedicated shift register during normal device operation. This latter mode allows the user to dynamically reconfigure the CCC without the need for core programming. The shift register is accessed through a simple serial interface. Refer to the “UJTAG Applications in Micro-semi's Low-Power Flash Devices” chapter of the _Fusion FPGA Fabric User Guide_ and the "CCC and PLL Characteristics" section on page 2-28 for more information.
**Revision 8**
**2-22**
_Device Architecture_
**==> picture [346 x 217] intentionally omitted <==**
**----- Start of picture text -----**<br>
Clock Source Clock Conditioning Output<br>CLKA GLA<br>Input LVDS/LVPECL Macro EXTFB LOCK<br>POWERDOWN<br>GLA<br>PADN Y GLB or<br>YB GLA and (GLB or YB)<br>PADP GLC or<br>YC GLA and (GLC or YC)<br>OADIVRST or<br>INBUF [2] Macro OADIVHALF GLA and (GLB or YB) and<br>PAD Y OADIV[4:0] (GLC or YC)<br>OAMUX[2:0]<br>DLYGLA[4:0]<br>OBDIV[4:0]<br>OBMUX[2:0]<br>DLYYB[4:0]<br>DLYGLB[4:0]<br>OCDIV[4:0]<br>OCMUX[2:0]<br>DLYYC[4:0]<br>DLYGLC[4:0]<br>FINDIV[6:0]<br>FBDIV[6:0]<br>FBDLY[4:0]<br>FBSEL[1:0]<br>XDLYSEL<br>VCOSEL[2:0]<br>**----- End of picture text -----**<br>
_Notes:_
_1. Visit the Microsemi SoC Products Group website for application notes concerning dynamic PLL reconfiguration. Refer to the "PLL Macro" section on page 2-27 for signal descriptions._
_2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family._
_3. Refer to the_ IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide _for more information._
## _**Figure 2-19 •**_ **Fusion CCC Options: Global Buffers with the PLL Macro**
_**Table 2-11 •**_ **Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros**
**==> picture [92 x 121] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||
|---|---|
|CLKBUF Macros|
|CLKBUF_LVCMOS5|
|CLKBUF_LVCMOS33|[1]|
|CLKBUF_LVCMOS18|
|CLKBUF_LVCMOS15|
|CLKBUF_PCI|
|CLKBUF_LVDS|[2]|
|CLKBUF_LVPECL|
**----- End of picture text -----**<br>
## _Notes:_
_1. This is the default macro. For more details, refer to the_ IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide _._
_2. The B-LVDS and M-LVDS standards are supported with CLKBUF_LVDS._
**2-23**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Global Buffers with No Programmable Delays**_
The CLKBUF and CLKBUF_LVPECL/LVDS macros are composite macros that include an I/O macro driving a global buffer, hardwired together (Figure 2-20).
The CLKINT macro provides a global buffer function driven by the FPGA core.
The CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are pass-through clock sources and do not use the PLL or provide any programmable delay functionality.
Many specific CLKBUF macros support the wide variety of single-ended and differential I/O standards supported by Fusion devices. The available CLKBUF macros are described in the _IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide_ .
**==> picture [445 x 85] intentionally omitted <==**
**----- Start of picture text -----**<br>
Clock Source Clock Conditioning Output<br>GLA<br>CLKBUF_LVDS/LVPECL Macro CLKBUF Macro CLKINT Macro or<br>PADN None<br>GLB<br>Y PAD Y A Y<br>PADP<br>or<br>GLC<br>**----- End of picture text -----**<br>
_**Figure 2-20 •**_ **Global Buffers with No Programmable Delay**
## _**Global Buffers with Programmable Delay**_
The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay (Figure 2-21 on page 2-25). The CLKDLY macro takes the selected clock input and adds a user-defined delay element. This macro generates an output clock phase shift from the input clock.
The CLKDLY macro can be driven by an INBUF macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations.
Many specific INBUF macros support the wide variety of single-ended and differential I/O standards supported by the Fusion family. The available INBUF macros are described in the _IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide._
The CLKDLY macro can be driven directly from the FPGA core.
The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier.
The visual CLKDLY configuration in the SmartGen part of the Libero SoC and Designer tools allows the user to select the desired amount of delay and configures the delay elements appropriately. SmartGen also allows the user to select the input clock source. SmartGen will automatically instantiate the special macro, PLLINT, when needed.
**Revision 8**
**2-24**
_Device Architecture_
**==> picture [371 x 128] intentionally omitted <==**
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Clock Source Clock Conditioning Output<br>GLA<br>Input LVDS/LVPECL Macro<br>CLK GL or<br>PADN Y GLB<br>PADP<br>or<br>= p<br>DLYGL[4:0] GLC<br>INBUF* Macro<br>PAD —xH>- Y<br>**----- End of picture text -----**<br>
_**Figure 2-21 •**_ **Fusion CCC Options: Global Buffers with Programmable Delay**
## **Global Input Selections**
Each global buffer, as well as the PLL reference clock, can be driven from one of the following (Figure 2- 22):
- 3 dedicated single-ended I/Os using a hardwired connection
- 2 dedicated differential I/Os using a hardwired connection
- The FPGA core
**==> picture [336 x 239] intentionally omitted <==**
**----- Start of picture text -----**<br>
Each shaded box represents an<br>input buffer called out by the<br>appropriate name: INBUF or<br>INBUF_LVDS/LVPECL. To Core<br>Sample Pin Names<br>GAA0 i [1] Ro o<br>GAA1 [1] ° — + at<br>Source for CCC<br>(CLKA or CLKB or CLKC)<br>=) H y<br>St S<br>_ f a }<br>ian<br>Routed Clock<br>GAA2 [1] a boss + (from FPGA core) [2]<br>GAA[0:2]: GA represents global in the northwest corner<br>of the device. A[0:2]: designates specific A clock source.<br>**----- End of picture text -----**<br>
_Notes:_
_1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric. Refer to the "User I/O Naming Convention" section on page 2-158 for more information._
_2. Instantiate the routed clock source input as follows: a) Connect the output of a logic element to the clock input of the PLL, CLKDLY, or CLKINT macro. b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location._
_3. LVDS-based clock sources are available in the east and west banks on all Fusion devices._
_**Figure 2-22 •**_ **Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT**
**2-25**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**CCC Physical Implementation**_
The CCC circuit is composed of the following (Figure 2-23):
- PLL core
- 3 phase selectors
- 6 programmable delays and 1 fixed delay
- 5 programmable frequency dividers that provide frequency multiplication/division (not shown in Figure 2-23 because they are automatically configured based on the user's required frequencies)
- 1 dynamic shift register that provides CCC dynamic reconfiguration capability (not shown)
## _**CCC Programming**_
**==> picture [469 x 395] intentionally omitted <==**
**----- Start of picture text -----**<br>
The CCC block is fully configurable. It is configured via static flash configuration bits in the array, set by<br>the user in the programming bitstream, or configured through an asynchronous dedicated shift register,<br>dynamically accessible from inside the Fusion device. The dedicated shift register permits changes of<br>parameters such as PLL divide ratios and delays during device operation. This latter mode allows the<br>user to dynamically reconfigure the PLL without the need for core programming. The register file is<br>accessed through a simple serial interface.<br>CLKA<br>Four-Phase Output Phase Programmable GLA<br>PLL Core<br>Select Delay Type 2<br>Programmable<br>Fixed Delay Delay Type 1<br>Le<br>Programmable GLB<br>—{}L_+ a Phase ee Delay Type 2<br>Select<br>Programmable YB<br> Delay Type 1<br>Programmable GLC<br> Delay Type 2<br>| a Phase —_<br>Select<br>Programmable YC<br> Delay Type 1<br>=) —<br>Note: Clock divider and multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured<br>based on the user's required frequencies.<br>**----- End of picture text -----**<br>
_**Figure 2-23 •**_ **PLL Block**
**Revision 8**
**2-26**
_Device Architecture_
## _**PLL Macro**_
The PLL functionality of the clock conditioning block is supported by the PLL macro. Note that the PLL macro reference clock uses the CLKA input of the CCC block, which is only accessible from the global A[2:0] package pins. Refer to Figure 2-22 on page 2-25 for more information.
The PLL macro provides five derived clocks (three independent) from a single reference clock. The PLL feedback loop can be driven either internally or externally. The PLL macro also provides power-down input and lock output signals. During power-up, POWERDOWN should be asserted Low until VCC is up. See Figure 2-19 on page 2-23 for more information.
Inputs:
- CLKA: selected clock input
- POWERDOWN (active low): disables PLLs. The default state is power-down on (active low).
Outputs:
- LOCK (active high): indicates that PLL output has locked on the input reference signal
- GLA, GLB, GLC: outputs to respective global networks
- YB, YC: allows output from the CCC to be routed back to the FPGA core
As previously described, the PLL allows up to five flexible and independently configurable clock outputs. Figure 2-23 on page 2-26 illustrates the various clock output options and delay elements.
As illustrated, the PLL supports three distinct output frequencies from a given input clock. Two of these (GLB and GLC) can be routed to the B and C global networks, respectively, and/or routed to the device core (YB and YC).
There are five delay elements to support phase control on all five outputs (GLA, GLB, GLC, YB, and YC). There is also a delay element in the feedback loop that can be used to advance the clock relative to the reference clock.
The PLL macro reference clock can be driven by an INBUF macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations.
The PLL macro reference clock can be driven directly from the FPGA core.
The PLL macro reference clock can also be driven from an I/O routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate it from the hardwired I/O connection described earlier.
The visual PLL configuration in SmartGen, available with the Libero SoC and Designer tools, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. SmartGen allows the user to select the various delays and phase shift values necessary to adjust the phases between the reference clock (CLKA) and the derived clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows the user to select where the input clock is coming from. SmartGen automatically instantiates the special macro, PLLINT, when needed.
**2-27**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**CCC and PLL Characteristics**_
## _**Timing Characteristics**_
_**Table 2-12 •**_ **Fusion CCC/PLL Specification**
|**_Table 2-12 •_Fusion CCC/PLL Specification**<br>~~a~~|||||
|---|---|---|---|---|
|**Parameter**<br>~~a~~|**Min.**<br>|**Typ.**<br>|**Max.**<br>|**Unit**<br>|
|Clock Conditioning Circuitry Input Frequency fIN_CCC<br>~~aGe~~|1.5<br>~~Ge~~|~~Ge~~|350<br>~~Ge~~|MHz<br>~~Ge~~|
|Clock Conditioning Circuitry Output Frequency fOUT_CCC<br>~~eG~~|0.75<br>~~eG~~|~~eG~~|350<br>~~eG~~|MHz<br>~~eG~~|
|Delay Increments in Programmable Delay Blocks1, 2|~~ee~~|1603||ps|
|Number of Programmable Values in Each Programmable<br>Delay Block<br>~~ee~~<br>~~a~~|~~ee~~<br>~~ee~~<br>~~G~~|~~ee~~<br>~~ee~~|32<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|
|Input Period Jitter<br>~~ee~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~ee~~<br>~~a~~<br>~~G~~|~~ee~~<br>~~a~~<br>~~ee~~|1.5<br>~~ee~~<br>~~a~~<br>~~ee~~|ns<br>~~ee~~<br>~~a~~<br>~~ee~~|
|CCC Output Peak-to-Peak Period Jitter FCCC_OUT<br>~~a~~<br>~~a~~|Max Peak-to-Peak Period Jitter<br>~~a~~<br>~~G~~<br>~~ee~~|||~~a~~<br>~~ee~~|
||1 Global<br>Network<br>Used<br>~~G~~|~~ee~~|3 Global<br>Networks<br>Used<br>~~ee~~|~~ee~~|
|0.75 MHz to 24 MHz<br>~~ss~~|1.00%<br>~~ss~~|~~ss~~|1.00%<br>~~ss~~|~~ss~~|
|24 MHz to 100 MHz<br>~~ss~~<br>~~es~~<br>~~a~~|1.50%<br>~~ss~~<br>~~es~~|~~ss~~<br>~~es~~|1.50%<br>~~ss~~<br>~~es~~|~~ss~~<br>~~es~~|
|100 MHz to 250 MHz<br>~~es~~<br>~~a~~|2.25%<br>~~es~~|~~es~~|2.25%<br>~~es~~|~~es~~|
|250 MHz to 350 MHz<br>~~a~~<br>~~eG~~<br>~~DR~~|3.50%<br>~~eG~~<br>|~~eG~~<br>|3.50%<br>~~eG~~<br>|~~eG~~<br>|
|Acquisition Time<br>LockControl = 0<br>~~DR~~|||300<br>|µs<br>|
|LockControl = 1<br>~~DRes~~|~~es~~|~~es~~|6.0<br>~~es~~|ms<br>~~es~~|
|Tracking Jitter4<br>LockControl = 0<br>~~ss~~|~~ss~~|~~ss~~|1.6<br>~~ss~~|ns<br>~~ss~~|
|LockControl = 1<br>~~ss~~<br>~~es~~<br>~~a~~|~~ss~~<br>~~es~~|~~ss~~<br>~~es~~|0.8<br>~~ss~~<br>~~es~~|ns<br>~~ss~~<br>~~es~~|
|Output Duty Cycle<br>~~es~~<br>~~a~~|48.5<br>~~es~~|~~es~~|51.5<br>~~es~~|%<br>~~es~~|
|Delay Range in Block: Programmable Delay 11, 2<br>~~a~~<br>~~eG~~<br>~~DR~~|0.6<br>~~eG~~<br>|~~eG~~<br>|5.56<br>~~eG~~<br>|ns<br>~~eG~~<br>|
|Delay Range in Block: Programmable Delay 21, 2<br>~~DR~~|0.025<br>||5.56<br>|ns<br>|
|Delay Range in Block: Fixed Delay1, 2<br>~~DRes~~|~~es~~|2.2<br>~~es~~|~~es~~|ns<br>~~es~~|
## _Notes:_
_1. This delay is a function of voltage and temperature. See Table 3-7 on page 3-9 for deratings._
_2. TJ = 25°C, VCC = 1.5 V_
_3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help associated with the core for more information._
_4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter._
**Revision 8**
**2-28**
_Device Architecture_
## _**No-Glitch MUX (NGMUX)**_
Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching sequence between two asynchronous clock domains that prevents generating any unwanted narrow clock pulses. The NGMUX is used to switch the source of a global between three different clock sources. Allowable inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular net, as shown in Figure 2-24. The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e., internal signal or GLC). These are set by SmartGen during design but can also be changed by dynamically reconfiguring the PLL. The GLMUXSEL[1:0] bits control which clock source is passed through the NGMUX to the global network (GL). See Table 2-13.
**==> picture [331 x 242] intentionally omitted <==**
**----- Start of picture text -----**<br>
Crystal Oscillator<br>RC Oscillator<br>W I/O Ring<br>CCC/PLL GLMUXCFG[1:0]<br>GLINT<br>PLL/ GLA To Clock Rib Driver<br>CCC NGM UX<br>GLC<br>Clock I/Os GL<br>From FPGA Core<br>{<br>PWR UP<br>GLMUXSEL[1:0]<br>**----- End of picture text -----**<br>
_**Figure 2-24 •**_ **NGMUX**
_**Table 2-13 •**_ **NGMUX Configuration and Selection Table**
|**GLMUXCFG[1:0]**|**GLMUXSEL[1:0]**|**GLMUXSEL[1:0]**|**Selected Input Signal**|**MUX Type**|
|---|---|---|---|---|
|00|X|0|GLA|2-to-1 GLMUX|
||X|1|GLC||
|01|X|0|GLA|2-to-1 GLMUX|
||X|1|GLINT||
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_Fusion Family of Mixed Signal FPGAs_
The NGMUX macro is simplified to show the two clock options that have been selected by the GLMUXCFG[1:0] bits. Figure 2-25 illustrates the NGMUX macro. During design, the two clock sources are connected to CLK0 and CLK1 and are controlled by GLMUXSEL[1:0] to determine which signal is to be passed through the MUX.
**==> picture [194 x 123] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK0<br>GL<br>CLK1<br>GLMUXSEL[1:0]<br>**----- End of picture text -----**<br>
_**Figure 2-25 •**_ **NGMUX Macro**
The sequence of switching between two clock sources (from CLK0 to CLK1) is as follows (Figure 2-26):
- GLMUXSEL[1:0] transitions to initiate a switch.
- GL drives one last complete CLK0 positive pulse (i.e., one rising edge followed by one falling edge).
- From that point, GL stays Low until the second rising edge of CLK1 occurs.
- At the second CLK1 rising edge, GL will begin to continuously deliver the CLK1 signal.
- Minimum tsw = 0.05 ns at 25°C (typical conditions)
For examples of NGMUX operation, refer to the _Fusion FPGA Fabric User Guide_ .
**==> picture [151 x 132] intentionally omitted <==**
**----- Start of picture text -----**<br>
t<br>SW<br>CLK0<br>CLK1<br>GLMUXSEL[1:0]<br>GL<br>**----- End of picture text -----**<br>
_**Figure 2-26 •**_ **NGMUX Waveform**
**Revision 8**
**2-30**
_Device Architecture_
## **Real-Time Counter System**
The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce power consumption in many applications.
- Sleep mode, typical 10 µA
- Standby mode (RTC running), typical 3 mA with 20 MHz
The RTC system is composed of five cores:
- RTC sub-block inside Analog Block (AB)
- Voltage Regulator and Power System Monitor (VRPSM)
- Crystal oscillator (XTLOSC); refer to the “Crystal Oscillator” section in the Fusion Clock Resources chapter of the _Fusion FPGA Fabric User Guide_ for more detail.
- Crystal clock; does not require instantiation in RTL
- 1.5 V voltage regulator; does not require instantiation in RTL
All cores are powered by 3.3 V supplies, so the RTC system is operational without a 1.5 V supply during standby mode. Figure 2-27 shows their connection.
**==> picture [446 x 293] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.3 V<br>AB<br>VRPSM 1.5 Voltage Regulator<br>Real-Time Counter<br>RTCMATCH VRPU FPGAGOOD PTBASE [1] ExternalPass<br>VRINITSTATE PUCORE Transistor<br>2N2222<br>RTCPSMMATCH RTCPSMMATCH PTEM [1]<br>VREN [1] VREN [1]<br>RTCCLK 1.5 V<br>PUB TRST [1]<br>RTCXTLSEL RTCXTLMODE[1:0]<br>XTLOSC<br>SELMODE RTC_MODE[1:0]<br>MODE[1:0] CLKOUT Can Be Route<br>FPGA_EN [1] to PLL<br>XTL<br>Crystal Clock<br>Power-Up/-Down External Pin<br>XTL [1] Toggle Control<br>Switch<br>Internal Pin<br>XTAL1 XTAL2<br>Cores do not require any<br>RTL instantiation<br>Cores require RTL instantiation [2]<br>Sub-block in cores does not<br>require additional RTL instantiation<br>**----- End of picture text -----**<br>
_Notes:_
_1. Signals are hardwired internally and do not exist in the macro core._
_2. User is only required to instantiate the VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator to be different from the default, or employ user logic to shut the voltage regulator off._
_**Figure 2-27 •**_ **Real-Time Counter System (not all the signals are shown for the AB macro)**
**2-31**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Modes of Operation**
## _**Standby Mode**_
Standby mode allows periodic power-up and power-down of the FPGA fabric. In standby mode, the realtime counter and crystal block are ON. The FPGA is not powered by disabling the 1.5 V voltage regulator. The 1.5 V voltage regulator can be enabled when the preset count is matched. Refer to the "Real-Time Counter (part of AB macro)" section for details. To enter standby mode, the RTC must be first configured and enabled. Then VRPSM is shut off by deasserting the VRPU signal. The 1.5 V voltage regulator is then disabled, and shuts off the 1.5 V output.
## _**Sleep Mode**_
In sleep mode, the real-time counter and crystal blocks are OFF. The 1.5 V voltage regulator inside the VRPSM can only be enabled by the PUB or TRST pin. Refer to the "Voltage Regulator and Power System Monitor (VRPSM)" section on page 2-36 for details on power-up and power-down of the 1.5 V voltage regulator.
## _**Standby and Sleep Mode Circuit Implementation**_
For extra power savings, VJTAG and VPUMP should be at the same voltage as VCC, floated or ground, during standby and sleep modes. Note that when VJTAG is not powered, the 1.5 V voltage regulator cannot be enabled through TRST.
VPUMP and VJTAG can be controlled through an external switch. Microsemi recommends ADG839, ADG849, or ADG841 as possible switches. Figure 2-28 shows the implementation for controlling VPUMP. The IN signal of the switch can be connected to PTBASE of the Fusion device. VJTAG can be controlled in same manner.
**==> picture [398 x 156] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.3 V VPUMP (or JTAG) Supply<br>Fusion ADG841<br>S VPUMP (or JTAG)<br>Pin of Fusion<br>IN<br>External i<br>PTBASE Pass<br>. Transistor<br>2N2222<br>PTEM<br>1.5 V<br>**----- End of picture text -----**<br>
_**Figure 2-28 •**_ **Implementation to Control VPUMP**
**Revision 8**
**2-32**
_Device Architecture_
## **Real-Time Counter (part of AB macro)**
The RTC is a 40-bit loadable counter and used as the primary timekeeping element (Figure 2-29). The clock source, RTCCLK, must come from the CLKOUT signal of the crystal oscillator. The RTC can be configured to reset itself when a count value reaches the match value set in the Match Register.
The RTC is part of the Analog Block (AB) macro. The RTC is configured by the analog configuration MUX (ACM). Each address contains one byte of data. The circuitry in the RTC is powered by VCC33A, so the RTC can be used in standby mode when the 1.5 V supply is not present.
**==> picture [452 x 273] intentionally omitted <==**
**----- Start of picture text -----**<br>
Real-Time Counter<br>xt_mode[1:0]<br>RTCXTLMODE[1:0]<br>Control Status xtal_en RTCXTLSEL<br>MatchBits Reg<br>1.5 V to — _ _|<br>ACM 3.3 V<br>Registers Level Match Reg<br>Shifter<br>Counter RTCMATCH<br>Read-Hold Reg<br>RTCPSMMATCH<br>Counter Reg<br>Crystal Prescaler<br>RTCCLK 40-Bit Counter<br>FRTCCLK Divide by 128<br>ee es =i<br>**----- End of picture text -----**<br>
_**Figure 2-29 •**_ **RTC Block Diagram**
_**Table 2-14 •**_ **RTC Signal Description**
|**Signal Name**|**Width **|**Direction**|**Function**|
|---|---|---|---|
|RTCCLK|1|In|Must come from CLKOUT of XTLOSC.|
|RTCXTLMODE[1:0]|2|Out|Controlled by xt_mode in CTRL_STAT. Signal must connect to the<br>RTC_MODE signal in XTLOSC, as shown in Figure 2-27.|
|RTCXTLSEL|1|Out|Controlled by xtal_en from CTRL_STAT register. Signal must connect to<br>RTC_MODE signal in XTLOSC inFigure 2-27.|
|RTCMATCH|1|Out|Match signal for FPGA<br>0 – Counter value does not equal the Match Register value.<br>1 – Counter value equals the Match Register value.|
|RTCPSMMATCH|1|Out|Same signal as RTCMATCH. Signal must connect to RTCPSMMATCH in<br>VRPSM, as shown in Figure 2-27.|
The 40-bit counter can be preloaded with an initial value as a starting point by the Counter Register. The count from the 40-bit counter can be read through the same set of address space. The count comes from a Read-Hold Register to avoid data changing during read. When the counter value equals the Match Register value, all Match Bits Register values will be 0xFFFFFFFFFF. The RTCMATCH and RTCPSMMATCH signals will assert. The 40-bit counter can be configured to automatically reset to 0x0000000000 when the counter value equals the Match Register value. The automatic reset does not apply if the Match Register value is 0x0000000000. The RTCCLK has a prescaler to divide the clock by 128 before it is used for the 40-bit counter. Below is an example of how to calculate the OFF time.
**2-33**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Example: Calculation for Match Count**_
To put the Fusion device on standby for one hour using an external crystal of 32.768 KHz:
The period of the crystal oscillator is Tcrystal:
Tcrystal = 1 / 32.768 KHz = 30.518 µs
The period of the counter is Tcounter:
Tcounter = 30.518 us X 128 = 3.90625 ms
The Match Count for 1 hour is tmatch:
tmatch / Tcounter = (1 hr X 60 min/hr X 60 sec/min) / 3.90625 ms = 921600 or 0xE1000
Using a 32.768 KHz crystal, the maximum standby time of the 40-bit counter is 4,294,967,296 seconds, which is 136 years.
_**Table 2-15 •**_ **Memory Map for RTC in ACM Register and Description**
|**ACMADDR **|**Register Name**|**Description**|**Use**|**Default**<br>**Value**|
|---|---|---|---|---|
|0x40|COUNTER0|Counter bits 7:0|Used to preload the counter to a specified start<br>point.|0x00|
|0x41<br>~~a~~<br><br>~~a~~|COUNTER1<br>~~ae~~|Counter bits 15:8<br>~~ee~~|~~ee~~|0x00<br>~~ee~~|
|0x42<br>~~a ~~<br>~~a~~|COUNTER2<br> ~~ae~~|Counter bits 23:16<br>~~ee~~|~~ee~~|0x00<br>~~ee~~|
|0x43<br> <br>~~a~~|COUNTER3<br> ~~ae~~<br>~~ee~~|Counter bits 31:24<br>~~ee~~<br>~~ee~~|~~ee~~|0x00<br>~~ee~~|
|0x44<br>~~a~~<br>~~a~~|COUNTER4<br>~~se~~<br>~~ee~~|Counter bits 39:32<br>~~se~~||0x00|
|0x48<br>~~a~~|MATCHREG0<br>~~ee~~|Match register bits 7:0|The RTC comparison bits|0x00|
|0x49<br>~~a~~<br>~~a ee~~|MATCHREG1<br>~~ee~~<br>~~ee~~|Match register bits 15:8<br>~~ee~~|~~ee~~|0x00<br>~~ee~~|
|0x4A<br>~~a ee~~<br>~~a~~|MATCHREG2<br>~~ee~~<br>~~ae~~|Match register bits 23:16<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~ee~~|
|0x4B<br>~~a~~|MATCHREG3<br>~~ae~~|Match register bits 31:24<br>~~ee~~|~~ee~~|0x00<br>~~ee~~|
|0x4C<br>~~pf~~|MATCHREG4<br>~~ae~~<br>~~pf~~|Match register bits 39:32<br>~~ee~~<br>|~~ee~~<br>|0x00<br>~~ee~~<br>|
|0x50<br>~~pf~~|MATCHBIT0<br>~~pf|~~|Individual match bits 7:0<br>~~|~~|The output of the XNOR gates<br>0 – Not matched<br>1 – Matched<br>~~|~~|0x00<br>~~|~~|
|0x51<br>~~pf~~<br>~~a~~<br><br>~~a~~|MATCHBIT1<br>~~pf|~~<br>~~ae~~|Individual match bits 15:8<br>~~|~~<br>~~ee~~|~~|~~<br>~~ee~~|0x00<br>~~|~~<br>~~ee~~|
|0x52<br>~~a ~~<br>~~a~~|MATCHBIT2<br> ~~ae~~|Individual match bits 23:16<br>~~ee~~|~~ee~~|0x00<br>~~ee~~|
|0x53<br> <br>~~a~~|MATCHBIT3<br> ~~ae~~<br>~~ee~~|Individual match bits 31:24<br>~~ee~~<br>~~ee~~|~~ee~~|0x00<br>~~ee~~|
|0x54<br>~~a~~|MATCHBIT4<br>~~a~~|Individual match bits 29:32<br>~~ee~~||0x00|
|0x58<br>~~a~~|CTRL_STAT<br>~~a~~|Control (write/read) / Status<br>(read only) register bits<br>~~ee~~|Refer toTable 2-16 on page 2-35 for details.|0x00|
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_**Table 2-16 •**_ **RTC Control/Status Register**
|**Bit**|**Name**|**Description**|**Default**<br>**Value**|
|---|---|---|---|
|7|rtc_rst|RTC Reset<br>1 – Resets the RTC<br>0 – Deassert reset on after two ACM_CLK cycle.||
|6|cntr_en|Counter Enable<br>1 – Enables the counter; rtc_rst must be deasserted as well. First counter increments<br>after 64 RTCCLK positive edges.<br>0 – Disables the crystal prescaler but does not reset the counter value. Counter value<br>can only be updated when the counter is disabled.|0|
|5|vr_en_mat|Voltage Regulator Enable on Match<br>1 – Enables RTCMATCH and RTCPSMMATCH to output 1 when the counter value<br>equals the Match Register value. This enables the 1.5 V voltage regulator when<br>RTCPSMMATCH connects to the RTCPSMMATCH signal in VRPSM.<br>0 – RTCMATCH and RTCPSMMATCH output 0 at all times.|0|
|4:3|xt_mode[1:0]|Crystal Mode<br>Controls RTCXTLMODE[1:0]. Connects to RTC_MODE signal in XTLOSC.<br>XTL_MODE uses this value when xtal_en is 1. See the"Crystal Oscillator" section on<br>page 2-20for mode configuration.|00|
|2|rst_cnt_omat|Reset Counter on Match<br>1 – Enables the sync clear of the counter when the counter value equals the Match<br>Register value. The counter clears on the rising edge of the clock. If all the Match<br>Registers are set to 0, the clear is disabled.<br>0 – Counter increments indefinitely|0|
|1|rstb_cnt|Counter Reset, active Low<br>0 - Resets the 40-bit counter value|0|
|0|xtal_en|Crystal Enable<br>Controls RTCXTLSEL. Connects to SELMODE signal in XTLOSC.<br>0 – XTLOSC enables control by FPGA_EN; xt_mode is not used. Sleep mode requires<br>this bit to equal 0.<br>1 – Enables XTLOSC, XTL_MODE control by xt_mode<br>Standby mode requires this bit to be set to 1.<br>See the"Crystal Oscillator" section on page 2-20for further details on SELMODE<br>configuration.|0|
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## **Voltage Regulator and Power System Monitor (VRPSM)**
The VRPSM macro controls the power-up state of the FPGA. The power-up bar (PUB) pin can turn on the voltage regulator when set to 0. TRST can enable the voltage regulator when deasserted, allowing the FPGA to power-up when user want access to JTAG ports. The inputs VRINITSTATE and RTCPSMMATCH come from the flash bits and RTC, and can also power up the FPGA.
**==> picture [127 x 92] intentionally omitted <==**
**----- Start of picture text -----**<br>
VRPSM<br>VRPU FPGAGOOD<br>VRINITSTATE PUCORE<br>RTCPSMMATCH<br>VREN*<br>PUB<br>TRST*<br>**----- End of picture text -----**<br>
_Note: *Signals are hardwired internally and do not exist in the macro core._
_**Figure 2-30 •**_ **VRPSM Macro**
_**Table 2-17 •**_ **VRPSM Signal Descriptions**
|**Signal Name**|**Width **|**Direction**|**Function**|
|---|---|---|---|
|VRPU|1|In|Voltage Regulator Power-Up<br>0 – Voltage regulator disabled. PUB must be floated or pulled up, and the TRST<br>pin must be grounded to disable the voltage regulator.<br>1 – Voltage regulator enabled|
|VRINITSTATE|1|In|Voltage Regulator Initial State<br>Defines the voltage Regulator status upon power-up of the 3.3 V. The signal is<br>configured by Libero SoC when the VRPSM macro is generated.<br>Tie off to 1 – Voltage regulator enables when 3.3 V is powered.<br>Tie off to 0 – Voltage regulator disables when 3.3 V is powered.|
|RTCPSMMATCH|1|In|RTC Power System Management Match<br>Connect from RTCPSMATCH signal from RTC in AB<br>0 transition to 1 turns on the voltage regulator|
|PUB|1|In|External pin, built-in weak pull-up<br>Power-Up Bar<br>0 – Enables voltage regulator at all times|
|TRST*|1|In|External pin, JTAG Test Reset<br>1 – Enables voltage regulator at all times|
|FPGAGOOD|1|Out|Indicator that the FPGA is powered and functional<br>No need to connect if it is not used.<br>1 – Indicates that the FPGA is powered up and functional.<br>0 – Not possible to read by FPGA since it has already powered off.|
|PUCORE|1|Out|Power-Up Core<br>Inverted signal of PUB. No need to connect if it is not used.|
|VREN*|1|Out|Voltage Regulator Enable<br>Connected to 1.5 V voltage regulator in Fusion device internally.<br>0 – Voltage regulator disables<br>1 – Voltage regulator enables|
|_Note:_<br>_*Signals are hardwired internally and do not exist in the macro core._||||
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**==> picture [397 x 287] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.3 V Power Supply ON/OFF<br>3.3 V OFF 3.3 V ON<br>VINITSTATE = 0<br>And PUB = 1<br>And TRST = 0 Sleep Mode Standby Mode<br>3.3 V On, 3.3 V On,<br>VREN Disabled RTC Enabled<br>VREN Disabled<br>*RTCPSMMATCH = 1<br>Or PUB = 0<br>OFF State PUB = 0 Or TRST = 1<br>3.3 V Off, or TRST = 1<br>PUB Pull-Up,<br>TRST Pull-Down,<br>VRPU = 0<br>VREN Disabled<br>And PUB = 1<br>And TRST = 0<br>Normal Operation<br>3.3 V on,<br>VRINITSTATE = 1 VREN Enable<br>or PUB = 0 VRPU = 0<br>or TRST = 1 And PUB = 1<br>And TRST = 0<br>And *RTC: CTRL_STAT:<br>xtal_en = 1<br>3.3 V ON, 1.5 V ON (VR on)<br>**----- End of picture text -----**<br>
_Note: * To enter and exit standby mode without any external stimulus on PUB or TRST, the vr_en_mat in the CTRL_STAT register must also be set to 1, so that RTCPSMMATCH will assert when a match occurs; hence the device exits standby mode._
## _**Figure 2-31 •**_ **State Diagram for All Different Power Modes**
When TRST is 1 or PUB is 0, the 1.5 V voltage regulator is always ON, putting the Fusion device in normal operation at all times. Therefore, when the JTAG port is not in reset, the Fusion device cannot enter sleep mode or standby mode.
To enter standby mode, the Fusion device must first power-up into normal operation. The RTC is enabled through the RTC Control/Status Register described in the "Real-Time Counter (part of AB macro)" section on page 2-33. A match value corresponding to the wake-up time is loaded into the Match Register. The 1.5 V voltage regulator is disabled by setting VRPU to 0 to allow the Fusion device to enter standby mode, when the 1.5 V supply is off but the RTC remains on.
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## **1.5 V Voltage Regulator**
The 1.5 V voltage regulator uses an external pass transistor to generate 1.5 V from a 3.3 V supply. The base of the pass transistor is tied to PTBASE, the collector is tied to 3.3 V, and an emitter is tied to PTBASE and the 1.5 V supplies of the Fusion device. Figure 2-27 on page 2-31 shows the hook-up of the 1.5 V voltage regulator to an external pass transistor.
Microsemi recommends using a PN2222A or 2N2222A transistor. The gain of such a transistor is approximately 25, with a maximum base current of 20 mA. The maximum current that can be supported is 0.5 A. Transistors with different gain can also be used for different current requirements.
_**Table 2-18 •**_ **Electrical Characteristics**
**VCC33A = 3.3 V**
|~~a~~|**VCC33A = 3.3 V**<br>~~ee~~|||||||
|---|---|---|---|---|---|---|---|
|**Symbol**<br>~~a~~|**Parameter**<br>~~ee~~|**Condition**||**Min**|**Typical**|**Max**|**Units**|
|VOUT<br>~~a ~~|Output Voltage<br> ~~ee~~|Tj = 25ºC||1.425|1.5|1.575|V|
|ICC33A<br>~~a~~|Operation Current<br>~~ee~~|Tj = 25ºC<br>~~ee~~|ILOAD = 1 mA<br>ILOAD = 100 mA<br>ILOAD = 0.5 A||11<br>11<br>30||mA<br>mA<br>mA|
|VOUT<br>~~a~~|Load Regulation<br>~~ee~~|Tj = 25ºC<br>~~ee~~|ILOAD = 1 mA to 0.5 A||90||mV|
|VOUT<br>~~a~~|Line Regulation<br>~~ee~~|Tj = 25ºC<br>~~ee~~|VCC33A = 2.97 V to 3.63 V<br>ILOAD = 1 mA<br>VCC33A = 2.97 V to 3.63 V<br>ILOAD = 100 mA<br>VCC33A = 2.97 V to 3.63 V<br>ILOAD = 500 mA||10.6<br>12.1<br>10.6||mV/V<br>mV/V<br>mV/V|
||Dropout Voltage*|Tj = 25ºC|ILOAD = 1 mA<br>ILOAD = 100 mA<br>ILOAD = 0.5 A||0.63<br>0.84<br>1.35||V<br>V<br>V|
|IPTBASE|PTBase Current|Tj = 25ºC|ILOAD = 1 mA<br>ILOAD = 100 mA<br>ILOAD = 0.5 A||48<br>736<br>12|20|µA<br>µA<br>mA|
_Note: *Data collected with 2N2222A._
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## **Embedded Memories**
Fusion devices include four types of embedded memory: flash block, FlashROM, SRAM, and FIFO.
## **Flash Memory Block**
Fusion is the first FPGA that offers a flash memory block (FB). Each FB block stores 2 Mbits of data. The flash memory block macro is illustrated in Figure 2-32. The port pin name and descriptions are detailed on Table 2-19 on page 2-40. All flash memory block signals are active high, except for CLK and active low RESET. All flash memory operations are synchronous to the rising edge of CLK.
||ADDR[17:0]<br>WD[31:0]<br>PROGRAM<br>CLK<br>RESET<br>RD[31:0]<br>BUSY<br>STATUS[1:0]<br>UNPROTECTPAGE<br>DISCARDPAGE<br>OVERWRITEPROTECT<br>PAGELOSSPROTECT<br>DATAWIDTH[1:0]<br>REN<br>WEN<br>ERASEPAGE<br>SPAREPAGE<br>AUXBLOCK<br>READNEXT<br>OVERWRITEPAGE<br>PAGESTATUS<br>PIPE<br>LOCKREQUEST||
|---|---|---|
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_**Figure 2-32 •**_ **Flash Memory Block**
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## _**Flash Memory Block Pin Names**_
_**Table 2-19 •**_ **Flash Memory Block Pin Names**
|**Interface Name**<br>~~ss~~|**Width **<br>~~ss~~|**Direction**<br>~~ss~~|**Description**<br>~~ss~~|
|---|---|---|---|
|ADDR[17:0]|18|In|Byte offset into the FB. Byte-based address.|
|AUXBLOCK<br>~~a~~|1|In|When asserted, the page addressed is used to access the auxiliary<br>block within that page.|
|BUSY<br>~~a~~|1<br>~~ee~~|Out<br>~~ee~~|When asserted, indicates that the FB is performing an operation.<br>~~ee~~|
|CLK<br>~~a~~|1<br>~~ee~~|In<br>~~ee~~|User interface clock. All operations and status are synchronous to the<br>rising edge of this clock.<br>~~ee~~|
|DATAWIDTH[1:0]|2<br>~~ee~~|In<br>~~ee~~|Data width<br>00 = 1 byte in RD/WD[7:0]<br>01 = 2 bytes in RD/WD[15:0]<br>1x = 4 bytes in RD/WD[31:0]<br>~~ee~~|
|DISCARDPAGE|1|In|When asserted, the contents of the Page Buffer are discarded so that<br>a new page write can be started.|
|ERASEPAGE|1|In|When asserted, the address page is to be programmed with all zeros.<br>ERASEPAGE must transition synchronously with the rising edge of<br>CLK.|
|LOCKREQUEST|1|In|When asserted, indicates to the JTAG controller that the FPGA<br>interface is accessing the FB.|
|OVERWRITEPAGE|1|In|When asserted, the page addressed is overwritten with the contents of<br>the Page Buffer if the page is writable.|
|OVERWRITEPROTECT|1|In|When asserted, all program operations will set the overwrite protect bit<br>of the page being programmed.|
|PAGESTATUS|1|In|When asserted with REN, initiates a read page status operation.|
|PAGELOSSPROTECT<br>~~a ee~~|1<br>~~ee~~|In<br>~~ee~~|When asserted, a modified Page Buffer must be programmed or<br>discarded before accessing a new page.<br>~~ee~~|
|PIPE<br>~~a ee~~<br>~~a~~|1<br>~~ee~~<br>~~ee~~|In<br>~~ee~~<br>~~ee~~|Adds a pipeline stage to the output for operation above 50 MHz.<br>~~ee~~<br>~~ee~~|
|PROGRAM<br>~~a~~|1<br>~~ee~~|In<br>~~ee~~|When asserted, writes the contents of the Page Buffer into the FB<br>page addressed.<br>~~ee~~|
|RD[31:0]<br>~~a~~<br>~~re~~|32<br>~~ee~~<br>~~ee~~|Out<br>~~ee~~<br>~~Ge~~|Read data; data will be valid from the first non-busy cycle (BUSY = 0)<br>after REN has been asserted.<br>~~ee~~<br>~~Ge~~|
|READNEXT<br>~~re~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|In<br>~~Ge~~|When asserted with REN, initiates a read-next operation.<br>~~Ge~~|
|REN<br>~~re ~~<br>~~ee~~|1<br> ~~ee~~<br>~~ee~~|In<br>~~Ge~~|When asserted, initiates a read operation.<br>~~Ge~~|
|RESET<br>~~ee ~~<br>~~a~~|1<br> ~~ee~~<br>~~ee~~|In<br>~~ee~~|When asserted, resets the state of the FB (active low).<br>~~ee~~|
|SPAREPAGE<br>~~a~~|1<br>~~ee~~|In<br>~~ee~~|When asserted, the sector addressed is used to access the spare<br>page within that sector.<br>~~ee~~|
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_**Table 2-19 •**_ **Flash Memory Block Pin Names (continued)**
|**Interface Name**|**Width **|**Direction**|**Description**|
|---|---|---|---|
|STATUS[1:0]|2|Out|Status of the last operation completed:<br>00: Successful completion<br>01: Read-/Unprotect-Page: single error detected and corrected<br>Write: operation addressed a write-protected page<br>Erase-Page: protection violation<br>Program: Page Buffer is unmodified<br>Protection violation<br>10: Read-/Unprotect-Page: two or more errors detected<br>11: Write: attempt to write to another page before programming<br>current page<br>Erase-Page/Program: page write count has exceeded the 10-year<br>retention threshold|
|UNPROTECTPAGE|1|In|When asserted, the page addressed is copied into the Page Buffer<br>and the Page Buffer is made writable.|
|WD[31:0]|32|In|Write data|
|WEN|1|In|When asserted, stores WD in the page buffer.|
All flash memory block input signals are active high, except for RESET.
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## _**Flash Memory Block Diagram**_
A simplified diagram of the flash memory block is shown in Figure 2-33.
**==> picture [457 x 277] intentionally omitted <==**
**----- Start of picture text -----**<br>
RD[31:0] OutputMUX LogicECC Page Buffer = 8 Blocks Flash Array = 64 Sectors<br> Plus AUX Block<br>Block Buffer<br>(128 bits)<br>WD[31 :0]<br>ADDDR[17:0]<br>DATAWIDTH[1:0]<br>REN<br>READNEXT<br>PAGESTATUS<br>WEN<br>ERASEPAGE<br>PROGRAM<br>SPAREPAGE<br>Control<br>AUXBLOCK Logic<br>UNPROTECTPAGE<br>OVERWRITEPAGE<br>DISCARDPAGE<br>OVERWRITEPROTECT<br>PAGELOSSPROTECT<br>PIPE<br>LOCKREQUEST<br>CLK<br>RESET<br>STATUS[1:0]<br>BUSY<br>**----- End of picture text -----**<br>
## _**Figure 2-33 •**_ **Flash Memory Block Diagram**
The logic consists of the following sub-blocks:
- Flash Array
- Contains all stored data. The flash array contains 64 sectors, and each sector contains 33 pages of data.
- Page Buffer
A page-wide volatile register. A page contains 8 blocks of data and an AUX block.
- Block Buffer
- Contains the contents of the last block accessed. A block contains 128 data bits.
- ECC Logic
The FB stores error correction information with each block to perform single-bit error correction and double-bit error detection on all data blocks.
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## _**Flash Memory Block Addressing**_
Figure 2-34 shows a graphical representation of the flash memory block.
**==> picture [443 x 378] intentionally omitted <==**
**----- Start of picture text -----**<br>
S pare Page<br>Page 31<br>Page 3<br>K ika<br>Page 2<br>Page 1<br>Page 0<br>LLL<br>a 7<br>og<br>||<br>a LYe<br>| 4<br>1190<br>140<br>Block<br>0 1 2 3 4 5 6 7<br>FEE EEEUP”<br>Notes:<br>1 block = 128 bits<br>Block Organization 1 page = 8 blocks plus the AUX block<br>1 sector = 33 pages<br>1 Flash array = 64 sectors<br>. . . .<br>Sector n<br>33 Pages<br>Sector 1<br>Sector 0<br>. . . .<br>. . . .<br>Aux Block<br>Byte 0 Byte 1 Byte 2 Byte 3 Byte 14 Byte 15 User Data (32 bits)<br>**----- End of picture text -----**<br>
_**Figure 2-34 •**_ **Flash Memory Block Organization**
Each FB is partitioned into sectors, pages, blocks, and bytes. There are 64 sectors in an FB, and each sector contains 32 pages and 1 spare page. Each page contains 8 data blocks and 1 auxiliary block. Each data block contains 16 bytes of user data, and the auxiliary block contains 4 bytes of user data. Addressing for the FB is shown in Table 2-20.
_**Table 2-20 •**_ **FB Address Bit Allocation ADDR[17:0]**
|**_Table 2-20 •_FB Address Bit Allocation ADDR[17:0]**|**_Table 2-20 •_FB Address Bit Allocation ADDR[17:0]**||
|---|---|---|
|When the spare page of a sector is addressed (SPAREPAGE active), ADDR[11:7] are ignored.<br>17<br>12<br>11<br>7<br>6<br>4<br>3<br>Sector<br>Page<br>Block<br>Byte<br>~~ee~~||0|
|When the Auxiliary block is addressed (AUXBLOCK active), ADDR[6:2] are ignored.|||
Note: The spare page of sector 0 is unavailable for any user data. Writes to this page will return an error, and reads will return all zeroes.
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Data operations are performed in widths of 1 to 4 bytes. A write to a location in a page that is not already in the Page Buffer will cause the page to be read from the FB Array and stored in the Page Buffer. The block that was addressed during the write will be put into the Block Buffer, and the data written by WD will overwrite the data in the Block Buffer. After the data is written to the Block Buffer, the Block Buffer is then written to the Page Buffer to keep both buffers in sync. Subsequent writes to the same block will overwrite the Block Buffer and the Page Buffer. A write to another block in the page will cause the addressed block to be loaded from the Page Buffer, and the write will be performed as described previously.
The data width can be selected dynamically via the DATAWIDTH input bus. The truth table for the data width settings is detailed in Table 2-21. The minimum resolvable address is one 8-bit byte. For data widths greater than 8 bits, the corresponding address bits are ignored—when DATAWIDTH = 0 (2 bytes), ADDR[0] is ignored, and when DATAWIDTH = '10' or '11' (4 bytes), ADDR[1:0] are ignored. Data pins are LSB-oriented and unused WD data pins must be grounded.
_**Table 2-21 •**_ **Data Width Settings**
|**DATAWIDTH[1:0]**|**Data Width**|
|---|---|
|00|1 byte [7:0]|
|01|2 byte [15:0]|
|10, 11|4 bytes [31:0]|
## _**Flash Memory Block Protection**_
## _**Page Loss Protection**_
When the PAGELOSSPROTECT pin is set to logic 1, it prevents writes to any page other than the current page in the Page Buffer until the page is either discarded or programmed.
A write to another page while the current page is Page Loss Protected will return a STATUS of '11'.
## _**Overwrite Protection**_
Any page that is Overwrite Protected will result in the STATUS being set to '01' when an attempt is made to either write, program, or erase it. To set the Overwrite Protection state for a page, set the OVERWRITEPROTECT pin when a Program operation is undertaken. To clear the Overwrite Protect state for a given page, an Unprotect Page operation must be performed on the page, and then the page must be programmed with the OVERWRITEPROTECT pin cleared to save the new page.
## _**LOCKREQUEST**_
LOCKREQUEST indicates to the JTAG controller that the FPGA interface is accessing the Flash memory Block. For the JTAG master LOCKREQUEST check is optional and can be ignored.
## _**Flash Memory Block Operations**_
## _**FB Operation Priority**_
The FB provides for priority of operations when multiple actions are requested simultaneously. Table 2-22 shows the priority order (priority 0 is the highest).
_**Table 2-22 •**_ **FB Operation Priority**
|**Operation**|**Priority**|
|---|---|
|System Initialization|0|
|FB Reset|1|
|Read|2|
|Write|3|
|Erase Page|4|
|Program|5|
|Unprotect Page|6|
|Discard Page|7|
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Access to the FB is controlled by the BUSY signal. The BUSY output is synchronous to the CLK signal. FB operations are only accepted in cycles where BUSY is logic 0.
## _**Write Operation**_
Write operations are initiated with the assertion of the WEN signal. Figure 2-35 on page 2-45 illustrates the multiple Write operations.
**==> picture [463 x 179] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>WEN<br>ADDR[17:0] rete A0 A1 rt A2 A3 tee A4 A5 A6<br>WD[31:0] D0 D1 D2 D3 D4 D5 D6<br>DATAWIDTH[1:0] SoS<br>PAGELOSSPROTECT po Sonora<br>BUSY<br>e ee eee ee ee<br>STATUS[1:0] S0 S1 S2 S3 ae S4 S5 S6<br>aaannan [Sto]<br>**----- End of picture text -----**<br>
## _**Figure 2-35 •**_ **FB Write Waveform**
When a Write operation is initiated to a page that is currently not in the Page Buffer, the FB control logic will issue a BUSY signal to the user interface while the page is loaded from the FB Array into the Page Buffer. A Copy Page operation takes no less than 55 cycles and could take more if a Write or Unprotect Page operation is started while the NVM is busy pre-fetching a block. The basic operation is to read a block from the array into the block register (5 cycles) and then write the block register to the page buffer (1 cycle) and if necessary, when the copy is complete, reading the block being written from the page buffer into the block buffer (1 cycle). A page contains 9 blocks, so 9 blocks multiplied by 6 cycles to read/write each block, plus 1 is 55 cycles total. Subsequent writes to the same block of the page will incur no busy cycles. A write to another block in the page will assert BUSY for four cycles (five cycles when PIPE is asserted), to allow the data to be written to the Page Buffer and have the current block loaded into the Block Buffer.
Write operations are considered successful as long as the STATUS output is '00'. A non-zero STATUS indicates that an error was detected during the operation and the write was not performed. Note that the STATUS output is "sticky"; it is unchanged until another operation is started.
Only one word can be written at a time. Write word width is controlled by the DATAWIDTH bus. Users are responsible for keeping track of the contents of the Page Buffer and when to program it to the array. Just like a regular RAM, writing to random addresses is possible. Users can write into the Page Buffer in any order but will incur additional BUSY cycles. It is not necessary to modify the entire Page Buffer before saving it to nonvolatile memory.
Write errors include the following:
1. Attempting to write a page that is Overwrite Protected (STATUS = '01'). The write is not performed.
2. Attempting to write to a page that is not in the Page Buffer when Page Loss Protection is enabled (STATUS = '11'). The write is not performed.
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## _**Program Operation**_
A Program operation is initiated by asserting the PROGRAM signal on the interface. Program operations save the contents of the Page Buffer to the FB Array. Due to the technologies inherent in the FB, the total programming (including erase) time per page of the eNVM is 6.8 ms. While the FB is writing the data to the array, the BUSY signal will be asserted.
During a Program operation, the sector and page addresses on ADDR are compared with the stored address for the page (and sector) in the Page Buffer. If there is a mismatch between the two addresses, the Program operation will be aborted and an error will be reported on the STATUS output.
It is possible to write the Page Buffer to a different page in memory. When asserting the PROGRAM pin, if OVERWRITEPAGE is asserted as well, the FB will write the contents of the Page Buffer to the sector and page designated on the ADDR inputs if the destination page is not Overwrite Protected.
A Program operation can be utilized to either modify the contents of the page in the flash memory block or change the protections for the page. Setting the OVERWRITEPROTECT bit on the interface while asserting the PROGRAM pin will put the page addressed into Overwrite Protect Mode. Overwrite Protect Mode safeguards a page from being inadvertently overwritten during subsequent Program or Erase operations.
Program operations that result in a STATUS value of '01' do not modify the addressed page. For all other values of STATUS, the addressed page is modified. Program errors include the following:
1. Attempting to program a page that is Overwrite Protected (STATUS = '01')
2. Attempting to program a page that is not in the Page Buffer when the Page Buffer has entered Page Loss Protection Mode (STATUS = '01')
3. Attempting to perform a program with OVERWRITEPAGE set when the page addressed has been Overwrite Protected (STATUS = '01')
4. The Write Count of the page programmed exceeding the Write Threshold defined in the part specification (STATUS = '11')
5. The ECC Logic determining that there is an uncorrectable error within the programmed page (STATUS = '10')
6. Attempting to program a page that is **not** in the Page Buffer when OVERWRITEPAGE is not set and the page in the Page Buffer is modified (STATUS = '01')
7. Attempting to program the page in the Page Buffer when the Page Buffer is **not** modified
The waveform for a Program operation is shown in Figure 2-36.
**==> picture [442 x 155] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>PROGRAM<br>Rf<br>ADDR[17:0] Page<br>SD a ff| ft<br>OVERWRITEPAGE HAT.<br>OVERWRITEPROTECT<br>mn [sl lL 1_!<br>PAGELOSSPROTECT<br>men oe<br>BUSY a a oe——>— |<br>STATUS[1:0] 0 Valid<br>**----- End of picture text -----**<br>
## _**Figure 2-36 •**_ **FB Program Waveform**
Note: OVERWRITEPAGE is only sampled when the PROGRAM or ERASEPAGE pins are asserted. OVERWRITEPAGE is ignored in all other operations.
**Revision 8**
**2-46**
_Device Architecture_
## _**Erase Page Operation**_
The Erase Page operation is initiated when the ERASEPAGE pin is asserted. The Erase Page operation allows the user to erase (set user data to zero) any page within the FB.
The use of the OVERWRITEPAGE and PAGELOSSPROTECT pins is the same for erase as for a Program Page operation.
As with the Program Page operation, a STATUS of '01' indicates that the addressed page is not erased.
A waveform for an Erase Page operation is shown in Figure 2-37.
Erase errors include the following:
1. Attempting to erase a page that is Overwrite Protected (STATUS = '01')
2. Attempting to erase a page that is not in the Page Buffer when the Page Buffer has entered Page Loss Protection mode (STATUS = '01')
3. The Write Count of the erased page exceeding the Write Threshold defined in the part specification (STATUS = '11')
4. The ECC Logic determining that there is an uncorrectable error within the erased page (STATUS = '10')
**==> picture [449 x 145] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>ERASE<br>pS<br>ADDR[17:0] Page<br>ip GD |<br>OVERWRITEPROTECT Ta<br>PAGELOSSPROTECT<br>BUSY rt te ft tt<br>STATUS[1:0] a Valid<br>**----- End of picture text -----**<br>
_**Figure 2-37 •**_ **FB Erase Page Waveform**
**2-47**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Read Operation**_
Read operations are designed to read data from the FB Array, Page Buffer, Block Buffer, or status registers. Read operations support a normal read and a read-ahead mode (done by asserting READNEXT). Also, the timing for Read operations is dependent on the setting of PIPE.
The following diagrams illustrate representative timing for Non-Pipe Mode (Figure 2-38) and Pipe Mode (Figure 2-39) reads of the flash memory block interface.
**==> picture [464 x 356] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>REN PPP RAP PP<br>ADDR[17:0] —T A0 TTP A1 A2 A3 rrr A4<br>So —O00O 00 ET [0D_IlI0I00Oo®@®®$o]<br>DATAWIDTH[1:0]<br>BUSY<br>RDAT<br>STATUS[1:0] 0 S0 S1 S2 S3 0 S4<br>RD[31:0] lr 0 D0 D1 D2 D3 0 D4 0<br>Figure 2-38 • Read Waveform (Non-Pipe Mode, 32-bit access)<br>CLK<br>REN PPP PPP<br>ADDR[17:0] —T A0 TTT A1 tr A2 A3 A4<br>DATAWIDTH[1:0]<br>PD Owéeo*7<br>BUSY<br> e e e<br>STATUS[1:0] 0 S0 S1 S2 S3 0 S4<br>RD[31:0] 0 D0 D1 D2 D3 0 X D4 0<br>**----- End of picture text -----**<br>
_**Figure 2-39 •**_ **Read Waveform (Pipe Mode, 32-bit access)**
**Revision 8**
**2-48**
_Device Architecture_
The following error indications are possible for Read operations:
1. STATUS = '01' when a single-bit data error was detected and corrected within the block addressed.
2. STATUS = '10' when a double-bit error was detected in the block addressed (note that the error is uncorrected).
In addition to data reads, users can read the status of any page in the FB by asserting PAGESTATUS along with REN. The format of the data returned by a page status read is shown in Table 2-23, and the definition of the page status bits is shown in Table 2-24.
_**Table 2-23 •**_ **Page Status Read Data Format**
|31|8|7|4|3|2|1|0|
|---|---|---|---|---|---|---|---|
|Write Count||Reserved||Over Threshold|Read Protected|Write Protected|Overwrite Protected|
_**Table 2-24 •**_ **Page Status Bit Definition**
|**Page Status Bit(s)**|**Definition**|
|---|---|
|31–8|The number of times the page addressed has been programmed/erased|
|7–4|Reserved; read as 0|
|3|Over Threshold indicator (see the"Program Operation" section on page 2-46)|
|2|Read Protected; read protect bit for page, which is set via the JTAG interface and only affects<br>JTAG operations. This bit can be overridden by using the correct user key value.|
|1|Write Protected; write protect bit for page, which is set via the JTAG interface and only affects<br>JTAG operations. This bit can be overridden by using the correct user key value.|
|0|Overwrite Protected; designates that the user has set the OVERWRITEPROTECT bit on the<br>interface while doing a Program operation. The page cannot be written without first performing<br>an Unprotect Page operation.|
**2-49**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Read Next Operation**_
The Read Next operation is a feature by which the next block relative to the block in the Block Buffer is read from the FB Array while performing reads from the Block Buffer. The goal is to minimize wait states during consecutive sequential Read operations.
The Read Next operation is performed in a predetermined manner because it does look-ahead reads. The general look-ahead function is as follows:
- Within a page, the next block fetched will be the next in linear address.
- When reading the last data block of a page, it will fetch the first block of the next page.
- When reading spare pages, it will read the first block of the next sector's spare page.
- Reads of the last sector will wrap around to sector 0.
- Reads of Auxiliary blocks will read the next linear page's Auxiliary block.
When an address on the ADDR input does not agree with the predetermined look-ahead address, there is a time penalty for this access. The FB will be busy finishing the current look-ahead read before it can start the next read. The worst case is a total of nine BUSY cycles before data is delivered.
The Non-Pipe Mode and Pipe Mode waveforms for Read Next operations are illustrated in Figure 2-40 and Figure 2-41.
**==> picture [449 x 356] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>REN EEE<br>TFT<br>READNEXT<br>ADDR[17:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9<br>S035ELE LL<br>DATAWIDTH[1:0]<br>RD 300<br>BUSY<br> Qe eee<br>STATUS[1:0] 0 S0 S1 S2 S3 0 S4 S5 S6 S7 0 S8 S9<br>RD[31:0] es 0 D0 D1 D2 D3 0 lh D4 D5 D6 D7 0 D8 D9<br>Figure 2-40 • Read Next Waveform (Non-Pipe Mode, 32-bit access)<br>CLK<br>REN PIPPI<br>READNEXT ATE<br>ADDR[17:0] A0 A1 A2 A3 A4 A5 A6 A7 A8<br>BUSY SS<br>STATUS[1:0] eS, S0 S1 S2 S3 0 S4 S5 S6 S7 0<br>RD[31:0] 5 0 D0 D1 D2 55666558 D3 0 D4 D5 D6 D7 0<br>**----- End of picture text -----**<br>
_**Figure 2-40 •**_ **Read Next Waveform (Non-Pipe Mode, 32-bit access)**
_**Figure 2-41 •**_ **Read Next WaveForm (Pipe Mode, 32-bit access)**
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_Device Architecture_
## _**Unprotect Page Operation**_
An Unprotect Page operation will clear the protection for a page addressed on the ADDR input. It is initiated by setting the UNPROTECTPAGE signal on the interface along with the page address on ADDR.
**==> picture [442 x 291] intentionally omitted <==**
**----- Start of picture text -----**<br>
If the page is not in the Page Buffer, the Unprotect Page operation will copy the page into the Page<br>Buffer. The Copy Page operation occurs only if the current page in the Page Buffer is not Page Loss<br>Protected.<br>The waveform for an Unprotect Page operation is shown in Figure 2-42.<br>CLK<br>UNPROTECTPAGE<br>ADDR[17:0] | X__) Page eee<br>BUSY<br>STATUS[1:0] PT Valid<br>= ({<br>FB Unprotected Page Waveform<br>The Unprotect Page operation can incur the following error conditions:<br>1. If the copy of the page to the Page Buffer determines that the page has a single-bit correctable<br>error in the data, it will report a STATUS = '01'.<br>**----- End of picture text -----**<br>
## _**Figure 2-42 •**_ **FB Unprotected Page Waveform**
2. If the address on ADDR does not match the address of the Page Buffer, PAGELOSSPROTECT is asserted, and the Page Buffer has been modified, then STATUS = '11' and the addressed page is not loaded into the Page Buffer.
3. If the copy of the page to the Page Buffer determines that at least one block in the page has a double-bit uncorrectable error, STATUS = '10' and the Page Buffer will contain the corrupted data.
## _**Discard Page Operation**_
If the contents of the modified Page Buffer have to be discarded, the DISCARDPAGE signal should be asserted. This command results in the Page Buffer being marked as unmodified.
The timing for the operation is shown in Figure 2-43. The BUSY signal will remain asserted until the operation has completed.
**==> picture [63 x 62] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>DISCARDPAGE<br>BUSY<br>**----- End of picture text -----**<br>
_**Figure 2-43 •**_ **FB Discard Page Waveform**
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**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Flash Memory Block Characteristics**_
CLK RESET Active Low, Asynchronous BUSY
_**Figure 2-44 •**_ **Reset Timing Diagram**
_**Table 2-25 •**_ **Flash Memory Block Timing Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
**==> picture [469 x 493] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|Clock-to-Q in 5-cycle read mode of the Read Data|7.99|9.10|10.70|ns|
|tCLK2RD|
|a|ee|Clock-to-Q in 6-cycle read mode of the Read Data|ee|5.03|eee|5.73|6.74|ns|
|Clock-to-Q in 5-cycle read mode of BUSY|4.95|5.63|6.62|ns|
|tCLK2BUSY|
|Clock-to-Q in 6-cycle read mode of BUSY|4.45|5.07|5.96|ns|
|eeee|
|Clock-to-Status in 5-cycle read mode|11.24|12.81|15.06|ns|
|tCLK2STATUS|
|Clock-to-Status in 6-cycle read mode|4.48|5.10|6.00|ns|
|pea|
|tDSUNVM|Data Input Setup time for the Control Logic|1.92|2.19|2.57|—|ns|
|Oe|
|tDHNVM|Data Input Hold time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tASUNVM|Address Input Setup time for the Control Logic|2.76|3.14|3.69|ns|
|Oe|
|tAHNVM|Address Input Hold time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUDWNVM|Data Width Setup time for the Control Logic|1.85|2.11|2.48|ns|
|Oe|
|tHDDWNVM|Data Width Hold time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSURENNVM|Read Enable Setup time for the Control Logic|3.85|4.39|5.16|ns|
|Oe|
|tHDRENNVM|Read Enable Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUWENNVM|Write Enable Setup time for the Control Logic|2.37|2.69|3.17|ns|
|Oe|
|tHDWENNVM|Write Enable Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUPROGNVM|Program Setup time for the Control Logic|2.16|2.46|2.89|ns|
|Oe|
|tHDPROGNVM|Program Hold time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUSPAREPAGE|SparePage Setup time for the Control Logic|3.74|4.26|5.01|ns|
|Oe|
|tHDSPAREPAGE|SparePage Hold time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUAUXBLK|Auxiliary Block Setup Time for the Control Logic|3.74|4.26|5.00|ns|
|Oe|
|tHDAUXBLK|Auxiliary Block Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSURDNEXT|ReadNext Setup Time for the Control Logic|2.17|2.47|2.90|ns|
|Oe|
|tHDRDNEXT|ReadNext Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUERASEPG|Erase Page Setup Time for the Control Logic|3.76|4.28|5.03|ns|
|Oe|
|tHDERASEPG|Erase Page Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUUNPROTECTPG|Unprotect Page Setup Time for the Control Logic|2.01|2.29|2.69|ns|
|Oe|
|tHDUNPROTECTPG|Unprotect Page Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUDISCARDPG|Discard Page Setup Time for the Control Logic|1.88|2.14|2.52|ns|
|Oe|
|tHDDISCARDPG|Discard Page Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|GeO|
|tSUOVERWRPRO|Overwrite Protect Setup Time for the Control Logic|1.64|1.86|2.19|ns|
|Oe|
|tHDOVERWRPRO|Overwrite Protect Hold Time for the Control Logic|0.00|0.00|0.00|ns|
|ee|
**----- End of picture text -----**<br>
**Revision 8**
**2-52**
_Device Architecture_
_**Table 2-25 •**_ **Flash Memory Block Timing (continued)**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~a~~|**Description**<br>~~ee~~|**–2**<br>~~ee~~<br>~~ee ee~~|**–1**<br>~~ee~~<br>~~ee~~|**Std.**<br>~~ee~~<br>~~ee~~|**Units**<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|
|tSUPGLOSSPRO<br>~~se~~|Page Loss Protect Setup Time for the Control Logic<br>~~se~~|1.69<br>~~ee ee~~<br>~~se~~|1.93<br>~~ee~~<br>~~se~~|2.27<br>~~ee~~<br>~~se~~|ns<br>~~ee~~<br>~~se~~|
|tHDPGLOSSPRO<br>~~Ge~~|Page Loss Protect Hold Time for the Control Logic<br>~~Ge~~|0.00<br>~~Ge~~|0.00<br>~~Ge~~|0.00<br>~~Ge~~|ns<br>~~Ge~~|
|tSUPGSTAT<br>~~Oe~~|Page Status Setup Time for the Control Logic<br>~~Oe~~|2.49<br>~~Oe~~|2.83<br>~~Oe~~|3.33<br>~~Oe~~|ns<br>~~Oe~~|
|tHDPGSTAT<br>~~Oe~~<br>~~GeO~~|Page Status Hold Time for the Control Logic<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|ns<br>~~Oe~~<br>~~GeO~~|
|tSUOVERWRPG<br>~~Oe~~|Over Write Page Setup Time for the Control Logic<br>~~Oe~~|1.88<br>~~Oe~~|2.14<br>~~Oe~~|2.52<br>~~Oe~~|ns<br>~~Oe~~|
|tHDOVERWRPG<br>~~Oe~~<br>~~GeO~~|Over Write Page Hold Time for the Control Logic<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|ns<br>~~Oe~~<br>~~GeO~~|
|tSULOCKREQUEST<br>~~Oe~~|Lock Request Setup Time for the Control Logic<br>~~Oe~~|0.87<br>~~Oe~~|0.99<br>~~Oe~~|1.16<br>~~Oe~~|ns<br>~~Oe~~|
|tHDLOCKREQUEST<br>~~Oe~~<br>~~GeO~~|Lock Request Hold Time for the Control Logic<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|ns<br>~~Oe~~<br>~~GeO~~|
|tRECARNVM<br>~~Oe~~|Reset Recovery Time<br>~~Oe~~|0.94<br>~~Oe~~|1.07<br>~~Oe~~|1.25<br>~~Oe~~|ns<br>~~Oe~~|
|tREMARNVM<br>~~Oe~~<br>~~GeO~~|Reset Removal Time<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~<br>~~ee~~|0.00<br>~~Oe~~<br>~~GeO~~|0.00<br>~~Oe~~<br>~~GeO~~|ns<br>~~Oe~~<br>~~GeO~~|
|tMPWARNVM<br>~~a~~|Asynchronous Reset Minimum Pulse Width for the<br>Control Logic<br>~~ee~~|10.00<br>~~ee~~<br>~~ee~~|12.50<br>~~ee~~|12.50<br>~~ee~~|ns<br>~~ee~~|
|tMPWCLKNVM<br>~~eG~~|Clock Minimum Pulse Width for the Control Logic<br>~~eG~~|4.00<br>~~ee~~<br>~~eG~~|5.00<br>~~eG~~|5.00<br>~~eG~~|ns<br>~~eG~~|
|tFMAXCLKNVM<br>~~pp~~|Maximum Frequency for Clock for the Control Logic – for<br>AFS1500/AFS600<br>~~pp~~|80.00<br>~~pp~~<br>~~ee ee~~|80.00<br>~~pp~~<br>~~ee~~|80.00<br>~~pp~~<br>~~ee~~|MHz<br>~~pp~~<br>~~ee~~|
||Maximum Frequency for Clock for the Control Logic – for<br>AFS250/AFS090<br>~~pp~~<br>~~ee~~|100.00<br>~~pp~~<br>~~ee~~<br>~~ee ee~~|80.00<br>~~pp~~<br>~~ee~~<br>~~ee~~|80.00<br>~~pp~~<br>~~ee~~<br>~~ee~~|MHz<br>~~pp~~<br>~~ee~~<br>~~ee~~|
## **FlashROM**
Fusion devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the FPGA core fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits in each bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core (Figure 2- 45).
The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed directly from the FPGA core. When programming, each of the eight 128-bit banks can be selectively reprogrammed. The FlashROM can only be reprogrammed on a bank boundary. Programming involves an automatic, on-chip bank erase prior to reprogramming the bank. The FlashROM supports a synchronous read and can be read on byte boundaries. The upper three bits of the FlashROM address from the FPGA core define the bank that is being accessed. The lower four bits of the FlashROM address from the FPGA core define which of the 16 bytes in the bank is being accessed.
The maximum FlashROM access clock is given in Table 2-26 on page 2-54. Figure 2-46 shows the timing behavior of the FlashROM access cycle—the address has to be set up on the rising edge of the clock for DOUT to be valid on the next falling edge of the clock.
If the address is unchanged for two cycles:
- D0 becomes invalid tCK2Q ns after the second rising edge of the clock.
- D0 becomes valid again tCK2Q ns after the second falling edge.
If the address unchanged for three cycles:
- D0 becomes invalid tCK2Q ns after the second rising edge of the clock.
- D0 becomes valid again tCK2Q ns after the second falling edge.
- D0 becomes invalid tCK2Q ns after the third rising edge of the clock.
- D0 becomes valid again tCK2Q ns after the third falling edge.
**2-53**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|~~bee~~<br>~~FEE~~|~~bee~~<br>~~FEE~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|**Byte Number in Bank**<br>**4 LSB of ADDR (READ)**<br>~~bee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||15<br>~~bee~~<br>~~FEE~~|14<br>~~bee~~<br>~~FEE~~|13<br>~~bee~~<br>|12<br>~~bee~~<br>|11<br>~~bee~~<br>|10<br>~~bee~~<br>|9<br>~~bee~~<br>|8<br>~~bee~~<br>|7<br>~~bee~~<br>|6<br>~~bee~~<br>|5<br>~~bee~~<br>|4<br>~~bee~~<br>~~**E**~~<br>|3<br>~~bee~~<br>~~**E**ER~~<br>|2<br>~~bee~~<br>~~ER~~<br>|1<br>~~bee~~<br>~~ER~~~~**E**~~<br>|0<br>~~bee~~<br>~~**E**~~|
|**Bank Number**<br>**3 MSB of ADDR (READ)**|7<br>~~PERE~~<br>~~FEE~~|~~PERE~~<br>~~FEE~~|~~PERE~~<br>~~FEE~~|~~PERE~~<br>|~~EEE~~<br>|~~EEE~~<br>|~~EEE~~<br>|~~EEEEEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>~~**E**~~<br>|~~EEEEE~~<br>~~**E**ER~~<br>|~~EEEEE~~<br>~~ER~~<br>|~~EEEEE~~<br>~~ER~~~~**E**~~<br>|~~EEEEE~~<br>~~**E**~~|
||6<br>~~PERE~~<br>~~FEE~~|~~PERE~~<br>~~FEE~~|~~PERE~~<br>~~FEE~~|~~PERE ~~<br>|~~EEE~~<br>|~~EEE~~<br>|~~EEE~~<br>|~~EEEEEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>|~~EEEEE~~<br>~~**E**~~<br>|~~EEEEE~~<br>~~**E**ER~~<br>|~~EEEEE~~<br>~~ER~~<br>|~~EEEEE~~<br>~~ER~~~~**E**~~<br>|~~EEEEE~~<br>~~**E**~~|
||5<br>~~FEE~~|~~FEE~~|~~FEE~~||~~EE~~|~~EE EEE~~|~~EEE~~|~~EEE~~|~~EEE EEE~~|~~EEE~~|~~EEE~~|~~EEE E~~|~~**E**~~<br>~~E~~|~~**E**ER~~<br>~~E~~|~~ER~~<br>~~E E~~|~~ER~~~~**E**~~<br>~~E~~|~~**E**~~|
||4<br>~~FEE~~|~~FEE~~|~~FEE ~~||~~EE~~|~~EE EEE~~|~~EEE~~|~~EEE~~|~~EEE EEE~~|~~EEE~~|~~EEE~~|~~EEE E~~|~~**E**~~<br>~~E ~~|~~**E**ER~~<br> ~~E~~|~~ER~~<br>~~E E~~|~~ER~~~~**E**~~<br>~~E~~|~~**E**~~|
||3<br>~~PEE~~|~~PEE~~|~~PEE EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~||~~EE~~|~~EE EEE~~|~~EEE~~|~~EEE~~|~~EEE EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|
||2<br>~~PEE~~|~~PEE~~|~~PEE EEE~~|~~EEE~~|~~EEE~~|~~EEE~~<br>~~EE~~|~~EEE~~<br>~~EE EEE EEE~~|~~EEE EEE~~|~~EE~~<br>~~EEE EEE~~|~~EE EEE~~<br>~~EEE EEE~~|~~EEE~~<br>~~EEE EEE~~|~~EEE~~<br>~~EEE EEE~~|~~EEE EEE~~<br>~~EEE EEEEEE~~|~~EEE~~<br>~~EEE~~|~~EEE~~<br>~~EEE~~|~~EEE~~<br>~~EEE~~|~~EEE~~<br>~~EEE~~|
||1<br>~~FERRE~~|~~FERRE~~|~~FERRE~~|~~FERRE~~|~~FERRE~~|~~FERRE~~<br>~~EE~~|~~FERRE~~<br>~~EE EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEEEEE~~|~~FERRE~~<br>~~EEE~~|~~FERRE~~<br>~~EEE~~|~~FERRE~~<br>~~EEE~~|~~FERRE~~<br>~~EEE~~|
||0<br>~~FERRE~~|~~FERRE~~|~~FERRE~~|~~FERRE~~|~~FERRE~~|~~FERRE~~<br>~~EE~~|~~FERRE~~<br>~~EE EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEE~~|~~FERRE~~<br>~~EEE EEEEEE~~|~~FERRE~~<br>~~EEE~~|~~FERRE~~<br>~~EEE~~|~~FERRE~~<br>~~EEE~~|~~FERRE~~<br>~~EEE~~|
_**Figure 2-45 •**_ **FlashROM Architecture**
## _**FlashROM Characteristics**_
**==> picture [410 x 190] intentionally omitted <==**
**----- Start of picture text -----**<br>
tSU tSU tSU<br>tHOLD tHOLD tHOLD<br>Address<br>A0 A1<br>1 en YD 1000000<br>tCK2Q tCK2Q tCK2Q<br>D0 D0 D1<br>OOOO Y O O X<br>Figure 2-46 • FlashROM Timing Diagram<br>FlashROM Access Time<br>Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V<br>**----- End of picture text -----**<br>
_**Table 2-26 •**_ **FlashROM Access Time**
|**Parameter**|**Description**|**–2**|**–1**|**Std.**|**Units**|
|---|---|---|---|---|---|
|tSU|Address Setup Time|0.53|0.61|0.71|ns|
|tHOLD|Address Hold Time|0.00|0.00|0.00|ns|
|tCK2Q|Clock to Out|21.42|24.40|28.68|ns|
|FMAX|Maximum Clock frequency|15.00|15.00|15.00|MHz|
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## **SRAM and FIFO**
All Fusion devices have SRAM blocks along the north side of the device. Additionally, AFS600 and AFS1500 devices have an SRAM block on the south side of the device. To meet the needs of highperformance designs, the memory blocks operate strictly in synchronous mode for both read and write operations. The read and write clocks are completely independent, and each may operate at any desired frequency less than or equal to 350 MHz. The following configurations are available:
- 4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—two read, two write or one read, one write)
- 512×9, 256×18 (two-port RAM—one read and one write)
- Sync write, sync pipelined/nonpipelined read
The Fusion SRAM memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY).
During RAM operation, addresses are sourced by the user logic, and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Refer to Figure 2-47 for more information about the implementation of the embedded FIFO controller.
The Fusion architecture enables the read and write sizes of RAMs to be organized independently, allowing for bus conversion. This is done with the WW (write width) and RW (read width) pins. The different D×W configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1. For example, the write size can be set to 256×18 and the read size to 512×9.
Both the write and read widths for the RAM blocks can be specified independently with the WW (write width) and RW (read width) pins. The different D×W configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1.
Refer to the allowable RW and WW values supported for each of the RAM macro types in Table 2-27 on page 2-58.
When a width of one, two, or four is selected, the ninth bit is unused. For example, when writing 9-bit values and reading 4-bit values, only the first four bits and the second four bits of each 9-bit value are addressable for read operations. The ninth bit is not accessible.
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Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation will be undefined. The RAM blocks employ little-endian byte order for read and write operations.
**==> picture [377 x 258] intentionally omitted <==**
**----- Start of picture text -----**<br>
RD[17:0] RD<br>WD WD[17:0]<br>RCLK RCLK<br>WCLK WCLK<br>RAM<br>RADD[J:0]<br>WADD[J:0]<br>REN<br>FREN WEN<br>FWEN<br>RBLK CNT 12<br>REN E [-]<br>= FULL<br>ESTOP B tga AFVAL<br>AFULL<br>AEVAL<br>WBLK [id] CNT 12 SUB 12 AEMPTY<br>WEN<br>E<br>LH =<br>Pat EMPTY<br>FSTOP<br>Reset<br>RPIPE RW[2:0] WW[2:0]<br>**----- End of picture text -----**<br>
_**Figure 2-47 •**_ **Fusion RAM Block with Embedded FIFO Controller**
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## **RAM4K9 Description**
RAM4K9 ADDRA11 DOUTA8 ADDRA10 DOUTA7 ADDRA0 DOUTA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA - ADDRB11 DOUTB8 ADDRB10 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB - RESET
_**Figure 2-48 •**_ **RAM4K9**
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The following signals are used to configure the RAM4K9 memory element.
## _**WIDTHA and WIDTHB**_
These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 2-27).
_**Table 2-27 •**_ **Allowable Aspect Ratio Settings for WIDTHA[1:0]**
|**_Table 2-27 •_Allowable Aspect Ratio Settings for WIDTHA[1:0]**|**Allowable Aspect Ratio Settings for WIDTHA[1:0]**||
|---|---|---|
|**WIDTHA1, WIDTHA0**|**WIDTHB1, WIDTHB0**|**D×W**|
|00|00|4k×1|
|01|01|2k×2|
|10|10|1k×4|
|11|11|512×9|
|_Note:_<br>_The aspect ratio settings are constant and cannot be changed on the fly._|||
_Note: The aspect ratio settings are constant and cannot be changed on the fly._
## _**BLKA and BLKB**_
These signals are active low and will enable the respective ports when asserted. When a BLKx signal is deasserted, the corresponding port’s outputs hold the previous value.
## _**WENA and WENB**_
These signals switch the RAM between read and write mode for the respective ports. A Low on these signals indicates a write operation, and a High indicates a read.
## _**CLKA and CLKB**_
These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver.
## _**PIPEA and PIPEB**_
These signals are used to specify pipelined read on the output. A Low on PIPEA or PIPEB indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A High indicates a pipelined, read and data appears on the corresponding output in the next clock cycle.
## _**WMODEA and WMODEB**_
These signals are used to configure the behavior of the output when the RAM is in write mode. A Low on these signals makes the output retain data from the previous read. A High indicates pass-through behavior, wherein the data being written will appear immediately on the output. This signal is overridden when the RAM is being read.
## _**RESET**_
This active low signal resets the output to zero, disables reads and writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory.
## _**ADDRA and ADDRB**_
These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k is specified, the unused high-order bits must be grounded (Table 2-28).
_**Table 2-28 •**_ **Address Pins Unused/Used for Various Supported Bus Widths**
|**D×W**|**ADDRx**|**ADDRx**|
|---|---|---|
||**Unused**|**Used**|
|4k×1|None|[11:0]|
|2k×2|[11]|[10:0]|
|1k×4|[11:10]|[9:0]|
|512×9|[11:9]|[8:0]|
_Note: The "x" in ADDRx implies A or B._
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## _**DINA and DINB**_
These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused high-order signals must be grounded (Table 2-29).
## _**DOUTA and DOUTB**_
These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA and DINB, high-order bits may not be used (Table 2-29). The output data on unused pins is undefined.
_**Table 2-29 •**_ **Unused/Used Input and Output Data Pins for Various Supported Bus Widths**
|**D×W**|**DINx/DOUTx**|**DINx/DOUTx**|
|---|---|---|
||**Unused**|**Used**|
|4k×1|[8:1]|[0]|
|2k×2|[8:2]|[1:0]|
|1k×4|[8:4]|[3:0]|
|512×9|None|[8:0]|
_Note: The "x" in DINx and DOUTx implies A or B._
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## _**RAM512X18 Description**_
RAM512X18
RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 RW1 RW0 PIPE REN RCLK ~~7~~ WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 WW1 WW0 WEN WCLK - RESET
_**Figure 2-49 •**_ **RAM512X18**
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RAM512X18 exhibits slightly different behavior from RAM4K9, as it has dedicated read and write ports.
## _**WW and RW**_
These signals enable the RAM to be configured in one of the two allowable aspect ratios (Table 2-30).
## _**Table 2-30 •**_ **Aspect Ratio Settings for WW[1:0]**
|**_Table 2-30 •_Aspect Ratio Settings for WW[1:0]**|**Aspect Ratio Settings for WW[1:0]**||
|---|---|---|
|**WW[1:0]**|**RW[1:0]**|**D×W**|
|01|01|512×9|
|10|10|256×18|
|00, 11|00, 11|Reserved|
## _**WD and RD**_
These are the input and output data signals, and they are 18 bits wide. When a 512×9 aspect ratio is used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, then RD[17:9] are undefined.
## _**WADDR and RADDR**_
These are read and write addresses, and they are nine bits wide. When the 256×18 aspect ratio is used for write or read, WADDR[8] or RADDR[8] are unused and must be grounded.
## _**WCLK and RCLK**_
These signals are the write and read clocks, respectively. They are both active high.
## _**WEN and REN**_
These signals are the write and read enables, respectively. They are both active low by default. These signals can be configured as active high.
## _**RESET**_
This active low signal resets the output to zero, disables reads and/or writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory.
## _**PIPE**_
This signal is used to specify pipelined read on the output. A Low on PIPE indicates a nonpipelined read, and the data appears on the output in the same clock cycle. A High indicates a pipelined read, and data appears on the output in the next clock cycle.
## _**Clocking**_
The dual-port SRAM blocks are only clocked on the rising edge. SmartGen allows falling-edge-triggered clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge or by separate clocks, by port.
Fusion devices support inversion (bubble pushing) throughout the FPGA architecture, including the clock input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the HDL code will be automatically accounted for during design compile without incurring additional delay in the clock path.
The two-port SRAM can be clocked on the rising edge or falling edge of WCLK and RCLK.
If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automatically used within the Fusion development tools, without performance penalty.
Note: Data in the SRAM block can be corrupted during a read operation, when the read address does not meet setup and hold requirements with respect to the clock for that port. The data corruption occurs when the read address (RADDR) changes almost simultaneously with read clock (RCLK) edge (that is, RADDR violates the timing requirement of the memory). Users must always meet the setup and hold time requirements on the RAM inputs; to have reliable and predictable results for reads and writes.To avoid data corruption due to asynchronous clocking for read address and read clock of the RAM, users must implement a proper synchronizer circuit. For more information, see, _Fusion and Extended Temperature Fusion FPGA Fabric User's Guide_
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## _**Modes of Operation**_
There are two read modes and one write mode:
- Read Nonpipelined (synchronous—1 clock edge): In the standard read mode, new data is driven onto the RD bus in the same clock cycle following RA and REN valid. The read address is registered on the read port clock active edge, and data appears at RD after the RAM access time. Setting PIPE to OFF enables this mode.
- Read Pipelined (synchronous—2 clock edges): The pipelined mode incurs an additional clock delay from the address to the data but enables operation at a much higher frequency. The read address is registered on the read port active clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode.
- Write (synchronous—1 clock edge): On the write clock active edge, the write data is written into the SRAM at the write address when WEN is High. The setup times of the write address, write enables, and write data are minimal with respect to the write clock. Write and read transfers are described with timing requirements in the "SRAM Characteristics" section on page 2-63 and the "FIFO Characteristics" section on page 2-72.
## _**RAM Initialization**_
Each SRAM block can be individually initialized on power-up by means of the JTAG port using the UJTAG mechanism (refer to the "JTAG IEEE 1532" section on page 2-229 and the _Fusion SRAM/FIFO Blocks_ application note). The shift register for a target block can be selected and loaded with the proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation.
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## _**SRAM Characteristics**_
## _**Timing Waveforms**_
**==> picture [406 x 497] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>[R|W]ADDR A0 A1 A2<br>tBKS<br>tBKH<br>BLK<br>D oeCOO<br>tENS tENH<br>WEN<br>t<br>CKQ1<br>DOUT|RD Dn A ae D0 D | 1 XD D2<br>tDOH1<br>Figure 2-50 • RAM Read for Flow-Through Output. Applicable to both RAM4K9 and RAM512x18.<br>tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>[R|W]ADDR A0 A1 A2<br>tBKS<br>tBKH<br>BLK<br>oe<br>tENS tENH<br>| | Ci<br>WEN<br>t<br>CKQ2<br>DOUT|RD Dn D0 D1<br>Lal<br>tDOH2<br>**----- End of picture text -----**<br>
_**Figure 2-50 •**_ **RAM Read for Flow-Through Output. Applicable to both RAM4K9 and RAM512x18.**
_**Figure 2-51 •**_ **RAM Read for Pipelined Output. Applicable to both RAM4K9 and RAM512x18.**
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**==> picture [415 x 567] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>[R|W]ADDR A0 A1 A2<br>tBKS<br>2 S asa a m c tBKH<br>BLK<br>tENS tENH<br>WEN<br>tDS tDH<br>DIN|WD DI0 DI1<br>DOUT|RD Dn D2<br>ae<br>Figure 2-52 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18.<br>tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>ADDR A0 A1 A2<br>tBKS<br>x6 Hs c = XXX<br>tBKH<br>BLK<br>tENS<br>WEN<br>el tDS tDH<br>DIN D0 DI1 DI2<br>oc em t S hem Sone<br>DOUT<br>Dn DI0 DI1<br>KKK<br>(flow-through)<br>DOUT<br>(pipelined) Dn DI0 DI1<br>**----- End of picture text -----**<br>
_**Figure 2-53 •**_ **RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.**
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**==> picture [409 x 406] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK1<br>tAS tAH<br>ADDR1 A0 A2 A3<br>DOK DO OOOK DOOOCDK DOOOO<br>tDS tDH<br>DIN1 D0 D2 D3<br>XK DOOOKDK DOOOCODK DOOOO<br>tWRO<br>CLK2<br>tAS tAH<br>ADDR2 A0 A1 A4<br>t<br>CKQ1<br>DOUT2 YOOO =e Dn D0 DOOOK D1 DOOKODK<br>(flow-through) DOOO™? OXOCODKK KOO<br>t<br>CKQ2<br>DOUT2<br>Dn OK D0 DOO<br>(Pipelined)<br>Figure 2-54 • One Port Write / Other Port Read Same<br>tCYC<br>t CKH tCKL<br>CLK<br>RESET<br>t<br>RSTBQ<br>DOUT|RD Dm Dn<br>**----- End of picture text -----**<br>
_**Figure 2-54 •**_ **One Port Write / Other Port Read Same**
_**Figure 2-55 •**_ **RAM Reset. Applicable to both RAM4K9 and RAM512x18.**
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## _**Timing Characteristics**_
## _**Table 2-31 •**_ **RAM4K9**
## **Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~a~~|**Description**|**–2**|**–1**|**Std. Units**|**Std. Units**|
|---|---|---|---|---|---|
|tAS<br>~~a~~<br>~~a~~|Address setup time|0.25|0.28|0.33|ns|
|tAH<br>~~a~~|Address hold time|0.00|0.00|0.00|ns|
|tENS<br>~~a~~|REN, WEN setup time|0.14|0.16|0.19|ns|
|tENH<br>~~a~~|REN, WEN hold time|0.10|0.11|0.13|ns|
|tBKS<br>~~a~~|BLK setup time|0.23|0.27|0.31|ns|
|tBKH<br>~~a~~|BL hold time|0.02|0.02|0.02|ns|
|tDS<br>~~a~~<br>~~a~~|Input data (DIN) setup time|0.18|0.21|0.25|ns|
|tDH<br>~~a~~<br>~~a~~<br>~~_———————SSE~~|Input data (DIN) hold time<br>~~_———————SSE~~|0.00<br>~~_———————SSE~~|0.00<br>~~_———————SSE~~|0.00<br>~~_———————SSE~~|ns<br>~~_———————SSE~~|
|tCKQ1<br>~~_———————SSE~~|Clock High to new data valid on DOUT (output retained, WMODE = 0)<br>~~_———————SSE~~|1.79<br>~~_———————SSE~~|2.03<br>~~_———————SSE~~|2.39<br>~~_———————SSE~~|ns<br>~~_———————SSE~~|
||Clock High to new data valid on DOUT (flow-through, WMODE = 1)<br>~~_———————SSE~~<br>~~tt~~|2.36<br>~~_———————SSE~~<br>~~tt~~|2.68<br>~~_———————SSE~~<br>~~tt~~|3.15<br>~~_———————SSE~~<br>~~tt~~|ns<br>~~_———————SSE~~<br>~~tt~~|
|tCKQ2<br>~~_———————SSE~~|Clock High to new data valid on DOUT (pipelined)<br>~~_———————SSE~~|0.89<br>~~_———————SSE~~|1.02<br>~~_———————SSE~~|1.20<br>~~_———————SSE~~|ns<br>~~_———————SSE~~|
|tC2CWWH<br>1|Address collision clk-to-clk delay for reliable write after write on same<br>address—Applicable to Rising Edge|0.30|0.26|0.23|ns|
|tC2CRWH<br>1|Address collision clk-to-clk delay for reliable read access after write on<br>same address—Applicable to Opening Edge|0.45|0.38|0.34|ns|
|tC2CWRH<br>1|Address collision clk-to-clk delay for reliable write access after read on<br>same address— Applicable to Opening Edge|0.49|0.42|0.37|ns|
|tRSTBQ<br>~~Se~~|RESET Low to data out Low on DOUT (flow-through)<br>~~Se~~|0.92<br>~~Se~~|1.05<br>~~Se~~|1.23<br>~~Se~~|ns<br>~~Se~~|
||RESET Low to Data Out Low on DOUT (pipelined)<br>~~Se~~<br>~~a~~|0.92<br>~~Se~~<br>~~a~~|1.05<br>~~Se~~<br>~~a~~|1.23<br>~~Se~~<br>~~a~~|ns<br>~~Se~~<br>~~a~~|
|tREMRSTB<br>~~Se~~<br>~~a~~|RESET removal<br>~~Se~~<br>~~a~~|0.29<br>~~Se~~<br>~~a~~|0.33<br>~~Se~~<br>~~a~~|0.38<br>~~Se~~<br>~~a~~|ns<br>~~Se~~<br>~~a~~|
|tRECRSTB<br>~~a~~|RESET recovery|1.50|1.71|2.01|ns|
|tMPWRSTB<br>~~a~~|RESET minimum pulse width|0.21|0.24|0.29|ns|
|tCYC<br>~~a~~|Clock cycle time|3.23|3.68|4.32|ns|
|FMAX<br>~~a~~<br>~~a~~|Maximum frequency<br>~~ee~~|310<br>~~ee~~|272<br>~~ee~~|231<br>~~ee~~|MHz<br>~~ee~~|
_Notes:_
_1. For more information, refer to the application note_ Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs _._
_2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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## _**Table 2-32 •**_ **RAM512X18**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~a~~|**Description**|**–2**|**–1**|**Std.**|**Units**|
|---|---|---|---|---|---|
|tAS<br>~~a~~|Address setup time|0.25|0.28|0.33|ns|
|tAH<br>~~a~~|Address hold time<br>~~i~~|0.00<br>~~i~~|0.00<br>~~i~~|0.00<br>~~i~~|ns<br>~~i~~|
|tENS<br>~~a~~|REN, WEN setup time|0.09|0.10|0.12|ns|
|tENH<br>~~a~~|REN, WEN hold time|0.06|0.07|0.08|ns|
|tDS<br>~~a~~|Input data (WD) setup time<br>~~a~~|0.18<br>~~a~~|0.21<br>~~a~~|0.25<br>~~a~~|ns<br>~~a~~|
|tDH<br>~~a~~<br>~~a~~|Input data (WD) hold time<br>~~a~~<br>~~a~~<br>~~a~~|0.00<br>~~a~~<br>~~a~~<br>~~a~~|0.00<br>~~a~~<br>~~a~~<br>~~a~~|0.00<br>~~a~~<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~<br>~~a~~|
|tCKQ1<br>~~a~~<br>~~a~~|Clock High to new data valid on RD (output retained)<br>~~a~~<br>~~a~~<br>~~a~~|2.16<br>~~a~~<br>~~a~~<br>~~a~~|2.46<br>~~a~~<br>~~a~~<br>~~a~~|2.89<br>~~a~~<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~<br>~~a~~|
|tCKQ2|Clock High to new data valid on RD (pipelined)|0.90|1.02|1.20|ns|
|tC2CRWH<br>1|Address collision clk-to-clk delay for reliable read access after write on<br>same address—Applicable to Opening Edge|0.50|0.43|0.38|ns|
|tC2CWRH<br>1|Address collision clk-to-clk delay for reliable write access after read on<br>same address—Applicable to Opening Edge|0.59|0.50|0.44|ns|
|tRSTBQ<br>1<br>~~eee~~<br>~~a~~|RESET Low to data out Low on RD (flow-through)<br>~~eee~~<br>~~a~~|0.92<br>~~eee~~|1.05<br>~~eee~~|1.23<br>~~eee~~|ns<br>~~eee~~|
||RESET Low to data out Low on RD (pipelined)<br>~~eee~~<br>~~a~~|0.92<br>~~eee~~|1.05<br>~~eee~~|1.23<br>~~eee~~|ns<br>~~eee~~|
|tREMRSTB<br>~~a~~<br>~~a~~|RESET removal<br>~~a~~<br>~~a~~|0.29|0.33|0.38|ns|
|tRECRSTB<br>~~a~~|RESET recovery<br>~~a~~|1.50|1.71|2.01|ns|
|tMPWRSTB<br>~~a~~|RESET minimum pulse width<br>~~aa~~|0.21<br>~~a~~|0.24<br>~~a~~|0.29<br>~~a~~|ns<br>~~a~~|
|tCYC<br>~~a~~<br>~~a~~|Clock cycle time<br>~~aa~~<br>~~a~~<br>~~a~~|3.23<br>~~a~~<br>~~a~~<br>~~a~~|3.68<br>~~a~~<br>~~a~~<br>~~a~~|4.32<br>~~a~~<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~<br>~~a~~|
|FMAX<br>~~a~~<br>~~a~~|Maximum frequency<br>~~a~~<br>~~a~~<br>~~a~~|310<br>~~a~~<br>~~a~~<br>~~a~~|272<br>~~a~~<br>~~a~~<br>~~a~~|231<br>~~a~~<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~<br>~~a~~|
_Notes:_
_1. For more information, refer to the application note_ Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs _._
_2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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## **FIFO4K18 Description**
**==> picture [127 x 438] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIFO4K18<br>RW2 RD17<br>RW1 RD16<br>RW0<br>WW2<br>WW1<br>WW0 RD0<br>ESTOP<br>FSTOP FULL<br>AFULL<br>EMPTY<br>AEVAL11 AEMPTY<br>AEVAL10<br>AEVAL0<br>AFVAL11<br>AFVAL10<br>AFVAL0<br>REN<br>- RBLK<br>RCLK<br>/<br>WD17<br>WD16<br>WD0<br>WEN<br>) WBLK<br>WCLK<br>RPIPE<br>- RESET<br>**----- End of picture text -----**<br>
_**Figure 2-56 •**_ **FIFO4KX18**
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The following signals are used to configure the FIFO4K18 memory element.
## _**WW and RW**_
These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 2-33).
_**Table 2-33 •**_ **Aspect Ratio Settings for WW[2:0]**
|**WW2, WW1, WW0**|**RW2, RW1, RW0**|**D×W**|
|---|---|---|
|000|000|4k×1|
|001|001|2k×2|
|010|010|1k×4|
|011|011|512×9|
|100|100|256×18|
|101, 110, 111|101, 110, 111|Reserved|
## _**WBLK and RBLK**_
These signals are active low and will enable the respective ports when Low. When the RBLK signal is High, the corresponding port’s outputs hold the previous value.
## _**WEN and REN**_
Read and write enables. WEN is active low and REN is active high by default. These signals can be configured as active high or low.
## _**WCLK and RCLK**_
These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver.
## _**RPIPE**_
This signal is used to specify pipelined read on the output. A Low on RPIPE indicates a nonpipelined read, and the data appears on the output in the same clock cycle. A High indicates a pipelined read, and data appears on the output in the next clock cycle.
## _**RESET**_
This active low signal resets the output to zero when asserted. It resets the FIFO counters. It also sets all the RD pins Low, the FULL and AFULL pins Low, and the EMPTY and AEMPTY pins High (Table 2-34).
_**Table 2-34 •**_ **Input Data Signal Usage for Different Aspect Ratios**
|**D×W**|**WD/RD Unused**|
|---|---|
|4k×1|WD[17:1], RD[17:1]|
|2k×2|WD[17:2], RD[17:2]|
|1k×4|WD[17:4], RD[17:4]|
|512×9|WD[17:9], RD[17:9]|
|256×18|–|
## _**WD**_
This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data width less than 18 is specified, unused higher-order signals must be grounded (Table 2-34).
## _**RD**_
This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD bus, high-order bits become unusable if the data width is less than 18. The output data on unused pins is undefined (Table 2-34).
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## _**ESTOP, FSTOP**_
ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the EMPTY flag goes High). A High on this signal inhibits the counting.
FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the FULL flag goes High). A High on this signal inhibits the counting.
For more information on these signals, refer to the "ESTOP and FSTOP Usage" section on page 2-70.
## _**FULL, EMPTY**_
When the FIFO is full and no more data can be written, the FULL flag asserts High. The FULL flag is synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to prevent overflows. Since the write address is compared to a resynchronized (and thus time-delayed) version of the read address, the FULL flag will remain asserted until two WCLK active edges after a read operation eliminates the full condition.
When the FIFO is empty and no more data can be read, the EMPTY flag asserts High. The EMPTY flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition and to prevent underflows. Since the read address is compared to a resynchronized (and thus time-delayed) version of the write address, the EMPTY flag will remain asserted until two RCLK active edges after a write operation removes the empty condition.
For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on page 2-70.
## _**AFULL, AEMPTY**_
These are programmable flags and will be asserted on the threshold specified by AFVAL and AEVAL, respectively.
When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output will go High. Likewise, when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go High.
## _**AFVAL, AEVAL**_
The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values, respectively. They are 12-bit signals. For more information on these signals, refer to "FIFO Flag Usage Considerations" section.
## _**ESTOP and FSTOP Usage**_
The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e., the EMPTY flag goes High). Likewise, the FSTOP pin is used to stop the write counter from counting any further once the FIFO is full (i.e., the FULL flag goes High).
The FIFO counters in the Fusion device start the count at 0, reach the maximum depth for the configuration (e.g., 511 for a 512×9 configuration), and then restart at 0. An example application for the ESTOP, where the read counter keeps counting, would be writing to the FIFO once and reading the same content over and over without doing another write.
## _**FIFO Flag Usage Considerations**_
The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values, respectively. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR) counters. WADDR is incremented every time a write operation is performed, and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms of total data bits instead of total data words. When users specify AFVAL and AEVAL in terms of read or write words, the SmartGen tool translates them into bit addresses and configures these signals automatically. SmartGen configures the AFULL flag to assert when the write address exceeds the read address by at least a predefined value. In a 2k×8 FIFO, for example, a value of 1,500 for AFVAL means that the AFULL flag will be asserted after a write when the difference between the write address and the read address reaches 1,500 (there have been at least 1500 more writes than reads). It will stay asserted until the difference between the write and read addresses drops below 1,500.
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The AEMPTY flag is asserted when the difference between the write address and the read address is less than a predefined value. In the example above, a value of 200 for AEVAL means that the AEMPTY flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. It will stay asserted until that difference rises above 200. Note that the FIFO can be configured with different read and write widths; in this case, the AFVAL setting is based on the number of write data entries and the AEVAL setting is based on the number of read data entries. For aspect ratios of 512×9 and 256×18, only 4,096 bits can be addressed by the 12 bits of AFVAL and AEVAL. The number of words must be multiplied by 8 and 16, instead of 9 and 18. The SmartGen tool automatically uses the proper values. To avoid halfwords being written or read, which could happen if different read and write aspect ratios are specified, the FIFO will assert FULL or EMPTY as soon as at least a minimum of one word cannot be written or read. For example, if a two-bit word is written and a four-bit word is being read, the FIFO will remain in the empty state when the first word is written. This occurs even if the FIFO is not completely empty, because in this case, a complete word cannot be read. The same is applicable in the full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one word is read. The FULL flag will remain asserted because a complete word cannot be written at this point.
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## _**FIFO Characteristics**_
## _**Timing Waveforms**_
**==> picture [449 x 254] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCYC<br>RCLK<br>tENS tENH<br>REN<br>tBKS tBKH<br>RBLK<br>t<br>CKQ1<br>(flow-through)RD Dn D0 D1 D2<br>t<br>CKQ2<br>(pipelined)RD Dn XKKKOO D0 D1<br>**----- End of picture text -----**<br>
_**Figure 2-57 •**_ **FIFO Read**
**==> picture [452 x 195] intentionally omitted <==**
**----- Start of picture text -----**<br>
t<br>CYC<br>WCLK<br>tENS tENH<br>WEN<br>tBKS tBKH<br>WBLK<br>t t<br>DS DH<br>WD OoGe, DI0 0.6.6.6GEE DI1 O:0-OOOOOOCCCOOx<br>**----- End of picture text -----**<br>
_**Figure 2-58 •**_ **FIFO Write**
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**==> picture [464 x 462] intentionally omitted <==**
**----- Start of picture text -----**<br>
RCLK/<br>WCLK<br>tMPWRSTB tRSTCK<br>RESET<br>tRSTFG<br>EF POOKY<br>tRSTAF<br>AEF POOQOOOOOKOKY<br>tRSTFG<br>FF POQODOOOOW<br>tRSTAF<br>AFF POOOOOKOOOKO'N<br>WA/RA<br>(Address Counter) XXX MATCH (A0)<br>Figure 2-59 • FIFO Reset<br>tCYC<br>RCLK<br>tRCKEF<br>EF<br>tCKAF<br>AEF<br>WA/RA<br>NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)<br>(Address Counter) KKK<br>**----- End of picture text -----**<br>
_**Figure 2-59 •**_ **FIFO Reset**
_**Figure 2-60 •**_ **FIFO EMPTY Flag and AEMPTY Flag Assertion**
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**==> picture [463 x 350] intentionally omitted <==**
**----- Start of picture text -----**<br>
t<br>CYC<br>WCLK<br>t<br> WCKFF<br>FF<br>t<br> CKAF<br>AFF<br>WA/RA<br>(Address Counter) GD NO MATCH NO MATCH Ge Dist = AFF_TH MATCH (FULL)<br>Figure 2-61 • FIFO FULL and AFULL Flag Assertion<br>WCLK<br>WA/RA MATCH NO MATCH NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1<br>(Address Counter) (EMPTY)<br>er Sa Ge Ge,<br>1st rising 2nd rising<br>edge edge<br>after 1st after 1st<br>RCLK write oe write<br>tRCKEF<br>EF<br>tCKAF<br>AEF<br>**----- End of picture text -----**<br>
_**Figure 2-61 •**_ **FIFO FULL and AFULL Flag Assertion**
_**Figure 2-62 •**_ **FIFO EMPTY Flag and AEMPTY Flag Deassertion**
**==> picture [458 x 134] intentionally omitted <==**
**----- Start of picture text -----**<br>
RCLK<br>WA/RA<br>(Address Counter) MATCH (FULL) SD NO MATCH Ge NO MATCH Gn NO MATCH Ge NO MATCH Dist = AFF_TH – 1<br>1st Rising 1st Rising<br>Edge Edge<br>After 1st After 2nd<br>Read Read<br>WCLK<br>tWCKF<br>FF e e<br>tCKAF<br>AFF<br>**----- End of picture text -----**<br>
_**Figure 2-63 •**_ **FIFO FULL Flag and AFULL Flag Deassertion**
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## _**Timing Characteristics**_
_**Table 2-35 •**_ **FIFO**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~a~~|**Description**|**–2**|**–1**|**Std.**|**Units**|
|---|---|---|---|---|---|
|tENS<br>~~a~~<br>~~a~~|REN, WEN Setup time|1.34|1.52|1.79|ns|
|tENH<br>~~a~~|REN, WEN Hold time|0.00|0.00|0.00|ns|
|tBKS<br>~~a~~|BLK Setup time|0.19|0.22|0.26|ns|
|tBKH<br>~~a a~~|BLK Hold time<br>~~a~~|0.00|0.00|0.00|ns|
|tDS<br>~~a~~|Input data (WD) Setup time<br>~~a~~<br>~~a~~|0.18|0.21|0.25|ns|
|tDH<br>~~a~~|Input data (WD) Hold time<br>~~a~~<br>~~i~~|0.00<br>~~i~~|0.00<br>~~i~~|0.00<br>~~i~~|ns<br>~~i~~|
|tCKQ1<br>~~a~~<br>~~a~~|Clock High to New Data Valid on RD (flow-through)<br>~~a~~<br>~~i~~|2.17<br>~~i~~|2.47<br>~~i~~|2.90<br>~~i~~|ns<br>~~i~~|
|tCKQ2<br>~~a~~<br>~~a~~|Clock High to New Data Valid on RD (pipelined)|0.94|1.07|1.26|ns|
|tRCKEF<br>~~a~~|RCLK High to Empty Flag Valid|1.72|1.96|2.30|ns|
|tWCKFF<br>~~a a~~|WCLK High to Full Flag Valid<br>~~a~~|1.63|1.86|2.18|ns|
|tCKAF<br>~~a~~|Clock High to Almost Empty/Full Flag Valid<br>~~a~~<br>~~a~~|6.19<br>~~a~~<br>~~a~~|7.05<br>~~a~~<br>~~a~~|8.29<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tRSTFG<br>~~a~~|RESET Low to Empty/Full Flag Valid<br>~~a~~<br>~~es~~|1.69<br>~~a~~<br>~~es~~|1.93<br>~~a~~<br>~~es~~|2.27<br>~~a~~<br>~~es~~|ns<br>~~a~~<br>~~es~~|
|tRSTAF<br>~~a~~<br>~~a~~|RESET Low to Almost-Empty/Full Flag Valid<br>~~a~~<br>~~es~~|6.13<br>~~a~~<br>~~es~~|6.98<br>~~a~~<br>~~es~~|8.20<br>~~a~~<br>~~es~~|ns<br>~~a~~<br>~~es~~|
|tRSTBQ<br>~~a~~<br>~~a~~|RESET Low to Data out Low on RD (flow-through)<br>~~ee~~|0.92<br>~~ee~~|1.05<br>~~ee~~|1.23<br>~~ee~~|ns<br>~~ee~~|
||RESET Low to Data out Low on RD (pipelined)<br>~~a~~|0.92<br>~~a~~|1.05<br>~~a~~|1.23<br>~~a~~|ns<br>~~a~~|
|tREMRSTB<br>~~a~~|RESET Removal<br>~~a~~<br>~~a~~|0.29|0.33|0.38|ns|
|tRECRSTB<br>~~a~~|RESET Recovery<br>~~a~~<br>~~a~~|1.50<br>~~a~~|1.71<br>~~a~~|2.01<br>~~a~~|ns<br>~~a~~|
|tMPWRSTB<br>~~a es~~|RESET Minimum Pulse Width<br>~~es~~|0.21<br>~~es~~|0.24<br>~~es~~|0.29<br>~~es~~|ns<br>~~es~~|
|tCYC<br>~~a es~~<br>~~a~~|Clock Cycle time<br>~~es~~|3.23<br>~~es~~|3.68<br>~~es~~|4.32<br>~~es~~|ns<br>~~es~~|
|FMAX<br>~~a~~<br>~~a~~|Maximum Frequency for FIFO|310|272|231|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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## **Analog Block**
With the Fusion family, Microsemi has introduced the world's first mixed-mode FPGA solution. Supporting a robust analog peripheral mix, Fusion devices will support a wide variety of applications. It is this Analog Block that separates Fusion from all other FPGA solutions on the market today.
By combining both flash and high-speed CMOS processes in a single chip, these devices offer the best of both worlds. The high-performance CMOS is used for building RAM resources. These highperformance structures support device operation up to 350 MHz. Additionally, the advanced Microsemi 0.13 µm flash process incorporates high-voltage transistors and a high-isolation, triple-well process. Both of these are suited for the flash-based programmable logic and nonvolatile memory structures.
High-voltage transistors support the integration of analog technology in several ways. They aid in noise immunity so that the analog portions of the chip can be better isolated from the digital portions, increasing analog accuracy. Because they support high voltages, Microsemi flash FPGAs can be connected directly to high-voltage input signals, eliminating the need for external resistor divider networks, reducing component count, and increasing accuracy. By supporting higher internal voltages, the Microsemi advanced flash process enables high dynamic range on analog circuitry, increasing precision and signal–noise ratio. Microsemi flash FPGAs also drive high-voltage outputs, eliminating the need for external level shifters and drivers.
The unique triple-well process enables the integration of high-performance analog features with increased noise immunity and better isolation. By increasing the efficiency of analog design, the triplewell process also enables a smaller overall design size, reducing die size and cost.
The Analog Block consists of the Analog Quad I/O structure, RTC (for details refer to the "Real-Time Counter System" section on page 2-31), ADC, and ACM. All of these elements are combined in the single Analog Block macro, with which the user implements this functionality (Figure 2-64).
The Analog Block needs to be reset/reinitialized after the core powers up or the device is programmed. An external reset/initialize signal, which can come from the internal voltage regulator when it powers up, must be applied.
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**==> picture [153 x 505] intentionally omitted <==**
**----- Start of picture text -----**<br>
VAREF<br>ADCGNDREF<br>AV0 DAVOUT0<br>AC0 DACOUT0<br>AT0 DATOUT0<br>AV9 DAVOUT9<br>AC9 DACOUT9<br>AT9 DATOUT9<br>ATRETURN01<br>AG0<br>ATRETURN9 AG1<br>DENAV0<br>DENAC0 AG9<br>DENAT0<br>DENAV0<br>DENAC0<br>DENAT0<br>CMSTB0<br>CSMTB9<br>GDON0<br>GDON9<br>TMSTB0<br>TMSTB9<br>MODE[3:0] BUSY<br>TVC[7:0] CALIBRATE<br>STC[7:0] DATAVALID<br>CHNUMBER[4:0] SAMPLE<br>TMSTINT RESULT[11:0]<br>ADCSTART RTCMATCH<br>VAREFSEL RTCXTLMODE<br>PWRDWN RTCXTLSEL<br>ADCRESET RTCPSMMATCH<br>RTCCLK<br>» _ SYSCLK<br>ACMWEN ACMRDATA[7:0]<br>ACMRESET<br>ACMWDATA<br>ACMADDR<br>ACMCLK<br>S o<br>AB<br>**----- End of picture text -----**<br>
_**Figure 2-64 •**_ **Analog Block Macro**
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||~~ee~~|~~ee~~|~~ee~~|~~ee~~|
|---|---|---|---|---|
|**Signal Name**<br>~~a~~|**Number**<br>**of Bits**<br>~~a~~<br>~~ee~~|**Number**<br>**Direction**<br>~~a~~<br>~~ee~~|**Function**<br>~~a~~<br>~~ee~~|**Location of**<br>**Details**<br>~~a~~<br>~~ee~~|
|VAREF<br>~~eG~~<br>~~ee~~|1<br>~~ee ~~<br>~~eG~~<br>~~sO~~|Input/Output<br> ~~ee ~~<br>~~eG~~<br>~~sO~~|Voltage reference for ADC<br> ~~ee~~<br>~~eG~~|ADC<br>~~ee~~<br>~~eG~~|
|ADCGNDREF<br>~~ee~~|1<br>~~sO~~|Input<br>~~sO~~|External ground reference|ADC|
|MODE[3:0]<br>~~ee ~~<br>~~ee~~|4<br> ~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|ADC operating mode<br>~~ee~~|ADC<br>~~ee~~|
|SYSCLK<br>~~eG~~<br>~~ee~~|1<br>~~eG~~<br>~~sO~~|Input<br>~~eG~~<br>~~sO~~|External system clock<br>~~eG~~|~~eG~~|
|TVC[7:0]<br>~~ee~~|8<br>~~sO~~|Input<br>~~sO~~|Clock divide control|ADC|
|STC[7:0]<br>~~ee ~~<br>~~ee~~|8<br> ~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|Sample time control<br>~~ee~~|ADC<br>~~ee~~|
|ADCSTART|1|Input|Start of conversion|ADC|
|PWRDWN<br>~~a~~|1<br>~~ee~~|Input<br>~~ee~~|ADC comparator power-down if 1.<br>When asserted, the ADC will stop<br>functioning, and the digital portion of<br>the<br>analog<br>block<br>will<br>continue<br>operating. This may result in invalid<br>status flags from the analog block.<br>Therefore,<br>Microsemi<br>does<br>not<br>recommend asserting the PWRDWN<br>pin.<br>~~ee~~|ADC<br>~~ee~~|
|ADCRESET<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ee~~|Input<br>~~ee~~<br>~~ee~~|ADC resets and disables Analog Quad<br>– active high<br>~~ee~~<br>~~ee~~|ADC<br>~~ee~~<br>~~ee~~|
|BUSY<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ee ~~|Output<br>~~ee~~<br> ~~ee~~|1 – Running conversion<br>~~ee~~<br>~~ee~~|ADC<br>~~ee~~<br>~~ee~~|
|CALIBRATE<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|1 – Power-up calibration<br>~~ee~~|ADC<br>~~ee~~|
|DATAVALID<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|1 – Valid conversion result<br>~~ee~~|ADC<br>~~ee~~|
|RESULT[11:0]<br>~~ee~~<br>~~a~~|12<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|Conversion result<br>~~ee~~|ADC<br>~~ee~~|
|TMSTBINT<br>~~ee~~|1<br>~~ee~~|Input<br>~~ee~~|Internal temp. monitor strobe<br>~~ee~~|ADC<br>~~ee~~|
|SAMPLE|1|Output|1 – An analog signal is actively being<br>sampled (stays high during signal<br>acquisition only)<br>0 – No analog signal is being sampled|ADC|
|VAREFSEL|1<br>~~ee~~|Input<br>~~ee~~|0 = Output internal voltage reference<br>(2.56 V) to VAREF<br>1 = Input external voltage reference<br>from VAREF and ADCGNDREF<br>~~ee~~|ADC|
|CHNUMBER[4:0]<br>~~a~~|5<br>~~a~~<br>~~ee~~|Input<br>~~a~~<br>~~ee~~|Analog input channel select<br>~~a~~<br>~~ee~~|Input<br>multiplexer<br>~~a~~|
|ACMCLK<br>~~sO~~|1<br>~~ee ~~<br>~~sO~~|Input<br> ~~ee ~~<br>~~sO~~|ACM clock<br> ~~ee~~<br>~~sO~~|ACM<br>~~sO~~|
|ACMWEN<br>~~sO~~<br>~~ee~~|1<br>~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|ACM write enable – active high<br>~~sO~~<br>~~ee~~|ACM<br>~~sO~~<br>~~ee~~|
|ACMRESET<br>~~sO~~|1<br>~~sO~~|Input<br>~~sO~~|ACM reset – active low<br>~~sO~~|ACM<br>~~sO~~|
|ACMWDATA[7:0]<br>~~sO~~|8<br>~~sO~~|Input<br>~~sO~~|ACM write data<br>~~sO~~|ACM<br>~~sO~~|
|ACMRDATA[7:0]<br>~~sO~~<br>~~a~~|8<br>~~sO~~<br>~~a~~|Output<br>~~sO~~<br>~~a~~|ACM read data<br>~~sO~~<br>~~a~~|ACM<br>~~sO~~<br>~~a~~|
|ACMADDR[7:0]<br>~~i~~|8<br>~~i~~<br>~~ee~~|Input<br>~~i~~<br>~~ee~~|ACM address<br>~~i~~<br>~~ee~~|ACM<br>~~i~~<br>~~ee~~|
|CMSTB0 to CMSTB9<br>~~a~~|10<br>~~a~~<br>~~ee~~|Input<br>~~a~~<br>~~ee~~|Current monitor strobe – 1 per quad,<br>active high<br>~~a~~<br>~~ee~~|Analog Quad<br>~~a~~<br>~~ee~~|
_**Table 2-36 •**_ **Analog Block Pin Description**
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_**Table 2-36 •**_ **Analog Block Pin Description (continued)**
|~~a~~|~~ee~~|~~ee~~|~~ee~~||
|---|---|---|---|---|
|**Signal Name**<br>~~a~~<br>~~a~~|**Number**<br>**of Bits**<br>~~ee~~|**Number**<br>**Direction**<br>~~ee~~|**Function**<br>~~ee~~|**Location of**<br>**Details**|
|GDON0 to GDON9<br>~~a~~<br>~~a~~|10<br>~~ee ~~|Input<br> ~~ee~~|Control to power MOS – 1 per quad<br>~~ee~~|Analog Quad|
|TMSTB0 to TMSTB9<br>~~a~~|10|Input|Temperature monitor strobe – 1 per<br>quad; active high|Analog Quad|
|DAVOUT0, DACOUT0, DATOUT0<br>to<br>DAVOUT9, DACOUT9, DATOUT9<br>~~a~~<br>~~a~~|30<br>~~ee~~|Output<br>~~eee~~<br>~~ee~~|Digital outputs – 3 per quad<br>~~eee~~<br>~~ee~~|Analog Quad<br>~~eee~~|
|DENAV0, DENAC0, DENAT0 to<br>DENAV9, DENAC9, DENAT9<br>~~a~~|30<br>~~ee~~|Input<br>~~ee~~|Digital input enables – 3 per quad<br>~~ee~~|Analog Quad|
|AV0<br>~~a~~<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ee~~<br>~~ss~~|Analog Quad 0<br>~~ee~~<br>~~ee~~|Analog Quad<br>~~ee~~|
|AC0<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AG0<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AT0<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ee~~|Input<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|Analog Quad<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|ATRETURN01<br>~~a~~|1<br>~~ee~~|Input<br>~~ee~~|Temperature monitor return shared by<br>Analog Quads 0 and 1<br>~~ee~~|Analog Quad<br>~~ee~~<br>~~ee~~|
|AV1<br>~~a~~<br>~~ee~~|1<br>~~ee ~~<br>~~ee~~|Input<br> ~~ee~~<br>~~ee~~|Analog Quad 1<br>~~ee~~<br>~~ee~~|Analog Quad<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|AC1<br>~~sO~~|1<br>~~sO~~|Input<br>~~sO~~|~~sO~~|Analog Quad<br>~~sO~~|
|AG1<br>~~sO~~|1<br>~~sO~~|Output<br>~~sO~~|~~sO~~|Analog Quad<br>~~sO~~|
|AT1<br>~~sO~~<br>~~ee~~|1<br>~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|~~sO~~<br>~~ee~~|Analog Quad<br>~~sO~~<br>~~ee~~|
|AV2<br>~~sO~~|1<br>~~sO~~|Input<br>~~sO~~|Analog Quad 2<br>~~sO~~|Analog Quad<br>~~sO~~|
|AC2<br>~~sO~~|1<br>~~sO~~|Input<br>~~sO~~|~~sO~~|Analog Quad<br>~~sO~~|
|AG2<br>~~sO~~<br>~~ee~~|1<br>~~sO~~<br>~~ee~~|Output<br>~~sO~~<br>~~ee~~|~~sO~~<br>~~ee~~|Analog Quad<br>~~sO~~<br>~~ee~~|
|AT2<br>~~sO~~<br>~~a~~|1<br>~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|~~sO~~<br>~~ee~~|Analog Quad<br>~~sO~~|
|ATRETURN23<br>~~a~~|1<br>~~ee~~|Input<br>~~ee~~|Temperature monitor return shared by<br>Analog Quads 2 and 3<br>~~ee~~|Analog Quad|
|AV3<br>~~a~~<br>~~ee~~<br>~~a~~|1<br>~~ee ~~<br>~~ee~~<br>~~ss~~|Input<br> ~~ee~~<br>~~ee~~<br>~~ss~~|Analog Quad 3<br>~~ee~~<br>~~ee~~|Analog Quad<br>~~ee~~|
|AC3<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AG3<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AT3<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AV4<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ss~~|Analog Quad 4<br>~~ee~~|Analog Quad<br>~~ee~~|
|AC4<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AG4<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AT4<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~<br>~~ee~~|Input<br>~~ee~~<br>~~ss~~<br>~~ee~~|~~ee~~<br>~~ee~~|Analog Quad<br>~~ee~~|
|ATRETURN45<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~<br>~~ee~~|Input<br>~~ee~~<br>~~ss~~<br>~~ee~~|Temperature monitor return shared by<br>Analog Quads 4 and 5<br>~~ee~~<br>~~ee~~|Analog Quad<br>~~ee~~|
|AV5<br>~~sO~~|1<br>~~ee ~~<br>~~sO~~|Input<br> ~~ee~~<br>~~sO~~|Analog Quad 5<br>~~ee~~<br>~~sO~~|Analog Quad<br>~~sO~~|
|AC5<br>~~sO~~|1<br>~~sO~~|Input<br>~~sO~~|~~sO~~|Analog Quad<br>~~sO~~|
|AG5<br>~~sO~~<br>~~a~~|1<br>~~sO~~<br>~~a~~|Output<br>~~sO~~<br>~~a~~|~~sO~~<br>~~a~~|Analog Quad<br>~~sO~~<br>~~a~~|
|AT5<br>~~i~~|1<br>~~i~~|Input<br>~~i~~|~~i~~|Analog Quad<br>~~i~~|
|AV6<br>~~sO~~|1<br>~~sO~~|Input<br>~~sO~~|Analog Quad 6<br>~~sO~~|Analog Quad<br>~~sO~~|
|AC6<br>~~sO~~<br>~~ee~~|1<br>~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|~~sO~~<br>~~ee~~|Analog Quad<br>~~sO~~<br>~~ee~~|
**2-79**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-36 •**_ **Analog Block Pin Description (continued)**
|~~a~~|~~ee~~|~~ee~~|~~ee~~||
|---|---|---|---|---|
|**Signal Name**<br>~~a~~<br>~~a~~|**Number**<br>**of Bits**<br>~~ee~~<br>|**Number**<br>**Direction**<br>~~ee~~<br>|**Function**<br>~~ee~~|**Location of**<br>**Details**|
|AG6<br>~~a~~<br>~~aee~~|1<br>~~ee ~~<br>~~es~~|Output<br> ~~ee~~<br>~~es~~|~~ee~~|Analog Quad|
|AT6<br>~~aee~~|1<br>~~es~~<br>~~ee~~|Input<br>~~es~~<br>~~ee~~|~~ee~~|Analog Quad<br>~~ee~~|
|ATRETURN67<br>~~ee~~<br>~~a~~|1<br>~~es~~<br>~~a~~<br>~~ee~~|Input<br>~~es~~<br>~~a~~<br>~~ee~~|Temperature monitor return shared by<br>Analog Quads 6 and 7<br>~~a~~<br>~~ee~~|Analog Quad<br>~~a~~<br>~~ee~~|
|AV7<br>~~eG~~<br>~~ee~~|1<br>~~ee ~~<br>~~eG~~<br>~~sO~~|Input<br> ~~ee ~~<br>~~eG~~<br>~~sO~~|Analog Quad 7<br> ~~ee ~~<br>~~eG~~|Analog Quad<br> ~~ee~~<br>~~eG~~|
|AC7<br>~~ee~~|1<br>~~sO~~|Input<br>~~sO~~||Analog Quad|
|AG7<br>~~ee ~~<br>~~ee~~|1<br> ~~sO~~<br>~~ee~~|Output<br>~~sO~~<br>~~ee~~|~~ee~~|Analog Quad<br>~~ee~~|
|AT7<br>~~eG~~<br>~~ee~~|1<br>~~eG~~<br>~~sO~~|Input<br>~~eG~~<br>~~sO~~|~~eG~~|Analog Quad<br>~~eG~~|
|AV8<br>~~ee~~|1<br>~~sO~~|Input<br>~~sO~~|Analog Quad 8|Analog Quad|
|AC8<br>~~ee ~~<br>~~ee~~|1<br> ~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|~~ee~~|Analog Quad<br>~~ee~~|
|AG8<br>~~sO~~|1<br>~~sO~~|Output<br>~~sO~~|~~sO~~|Analog Quad<br>~~sO~~|
|AT8<br>~~sO~~|1<br>~~sO~~<br>~~ee~~|Input<br>~~sO~~<br>~~ee~~|~~sO~~<br>~~ee~~|Analog Quad<br>~~sO~~<br>~~ee~~|
|ATRETURN89<br>~~sO~~<br>~~a~~<br>~~a~~|1<br>~~sO~~<br>~~a~~<br>~~ee~~<br>~~ss~~|Input<br>~~sO~~<br>~~a~~<br>~~ee~~<br>~~ss~~|Temperature monitor return shared by<br>Analog Quads 8 and 9<br>~~sO~~<br>~~a~~<br>~~ee~~|Analog Quad<br>~~sO~~<br>~~a~~<br>~~ee~~|
|AV9<br>~~ee~~<br>~~a~~|1<br>~~ee ~~<br>~~ee~~<br>~~ss~~|Input<br> ~~ee ~~<br>~~ee~~<br>~~ss~~|Analog Quad 9<br> ~~ee ~~<br>~~ee~~|Analog Quad<br> ~~ee~~<br>~~ee~~|
|AC9<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AG9<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|AT9<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Input<br>~~ee~~<br>~~ss~~|~~ee~~|Analog Quad<br>~~ee~~|
|RTCMATCH<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|MATCH<br>~~ee~~|RTC<br>~~ee~~|
|RTCPSMMATCH<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|MATCH connected to VRPSM<br>~~ee~~|RTC<br>~~ee~~|
|RTCXTLMODE[1:0]<br>~~ee~~<br>~~a~~|2<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|Drives XTLOSC RTCMODE[1:0] pins<br>~~ee~~|RTC<br>~~ee~~|
|RTCXTLSEL<br>~~ee~~<br>~~a~~<br>~~I~~|1<br>~~ee~~<br>~~ss~~|Output<br>~~ee~~<br>~~ss~~|Drives XTLOSC MODESEL pin<br>~~ee~~|RTC<br>~~ee~~|
|RTCCLK<br>~~I~~|1|Input|RTC clock input|RTC|
## **Analog Quad**
With the Fusion family, Microsemi introduces the Analog Quad, shown in Figure 2-65 on page 2-81, as the basic analog I/O structure. The Analog Quad is a four-channel system used to precondition a set of analog signals before sending it to the ADC for conversion into a digital signal. To maximize the usefulness of the Analog Quad, the analog input signals can also be configured as LVTTL digital input signals. The Analog Quad is divided into four sections.
The first section is called the Voltage Monitor Block, and its input pin is named AV. It contains a twochannel analog multiplexer that allows an incoming analog signal to be routed directly to the ADC or allows the signal to be routed to a prescaler circuit before being sent to the ADC. The prescaler can be configured to accept analog signals between –12 V and 0 or between 0 and +12 V. The prescaler circuit scales the voltage applied to the ADC input pad such that it is compatible with the ADC input voltage range. The AV pin can also be used as a digital input pin.
The second section of the Analog Quad is called the Current Monitor Block. Its input pin is named AC. The Current Monitor Block contains all the same functions as the Voltage Monitor Block with one addition, which is a current monitoring function. A small external current sensing resistor (typically less than 1 ) is connected between the AV and AC pins and is in series with a power source. The Current Monitor Block contains a current monitor circuit that converts the current through the external resistor to a voltage that can then be read using the ADC.
**Revision 8**
**2-80**
_Device Architecture_
The third part of the Analog Quad is called the Gate Driver Block, and its output pin is named AG. This section is used to drive an external FET. There are two modes available: a High Current Drive mode and a Current Source Control mode. Both negative and positive voltage polarities are available, and in the current source control mode, four different current levels are available.
The fourth section of the Analog Quad is called the Temperature Monitor Block, and its input pin name is AT. This block is similar to the Voltage Monitor Block, except that it has an additional function: it can be used to monitor the temperature of an external diode-connected transistor. It has a modified prescaler and is limited to positive voltages only.
The Analog Quad can be configured during design time by Libero SoC; however, the ACM can be used to change the parameters of any of these I/Os during runtime. This type of change is referred to as a context switch. The Analog Quad is a modular structure that is replicated to generate the analog I/O resources. Each Fusion device supports between 5 and 10 Analog Quads.
The analog pads are numbered to clearly identify both the type of pad (voltage, current, gate driver, or temperature pad) and its corresponding Analog Quad (AV0, AC0, AG0, AT0, AV1, …, AC9, AG9, and AT9). There are three types of input pads (AVx, ACx, and ATx) and one type of analog output pad (AGx). Since there can be up to 10 Analog Quads on a device, there can be a maximum of 30 analog input pads and 10 analog output pads.
**==> picture [447 x 279] intentionally omitted <==**
**----- Start of picture text -----**<br>
Off-Chip<br>AV AC AG AT<br>Pads Voltage Current Gate Temperature<br>Monitor Block Monitor Block Driver Monitor Block<br>On-Chip<br>Analog Quad<br>Prescaler Prescaler Prescaler<br>Power<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor/Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 2-65 •**_ **Analog Quad**
**2-81**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Voltage Monitor**_
The Fusion Analog Quad offers a robust set of voltage-monitoring capabilities unique in the FPGA industry. The Analog Quad comprises three analog input pads— Analog Voltage (AV), Analog Current (AC), and Analog Temperature (AT)—and a single gate driver output pad, Analog Gate (AG). There are many common characteristics among the analog input pads. Each analog input can be configured to connect directly to the input MUX of the ADC. When configured in this manner (Figure 2-66), there will be no prescaling of the input signal. Care must be taken in this mode not to drive the ADC into saturation by applying an input voltage greater than the reference voltage. The internal reference voltage of the ADC is 2.56 V. Optionally, an external reference can be supplied by the user. The external reference can be a maximum of 3.3 V DC.
**==> picture [447 x 279] intentionally omitted <==**
**----- Start of picture text -----**<br>
Off-Chip<br>AV AC AG AT<br>Pads Voltage Current Gate Temperature<br>Monitor Block Monitor Block Driver Monitor Block<br>On-Chip<br>Analog Quad<br>Prescaler Prescaler Prescaler<br>Power<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor / Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 2-66 •**_ **Analog Quad Direct Connect**
The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input signals. Figure 2-67 shows the path through the Analog Quad for a signal that is to be prescaled prior to conversion. The ADC internal reference voltage and the prescaler factors were selected to make both prescaling and postscaling of the signals easy binary calculations (refer to Table 2-57 on page 2-130 for details). When an analog input pad is configured with a prescaler, there will be a 1 M resistor to ground. This occurs even when the device is in power-down mode. In low power standby or sleep mode (VCC is OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, analog inputs are pulled down to ground through a 1 M resistor. The gate driver output is floating (or tristated), and there is no extra current on VCC33A.
These scaling factors hold true whether the particular pad is configured to accept a positive or negative voltage. Note that whereas the AV and AC pads support the same prescaling factors, the AT pad supports a reduced set of prescaling factors and supports positive voltages only.
**Revision 8**
**2-82**
_Device Architecture_
Typical scaling factors are given in Table 2-57 on page 2-130, and the gain error (which contributes to the minimum and maximum) is in Table 2-49 on page 2-117.
**==> picture [450 x 281] intentionally omitted <==**
**----- Start of picture text -----**<br>
Off-Chip<br>AV AC AG AT<br>Pads Voltage Current Gate Temperature<br>Monitor Block Monitor Block Driver Monitor Block<br>On-Chip<br>Analog Quad<br>Prescaler Prescaler Prescaler<br>Power<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor / Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 2-67 •**_ **Analog Quad Prescaler Input Configuration**
## _**Terminology**_
## _**BW – Bandwidth**_
BW is a range of frequencies that a Channel can handle.
## _**Channel**_
A channel is define as an analog input configured as one of the Prescaler range shown in Table 2-57 on page 2-130. The channel includes the Prescaler circuit and the ADC.
## _**Channel Gain**_
Channel Gain is a measured of the deviation of the actual slope from the ideal slope. The slope is measured from the 20% and 80% point.
**==> picture [73 x 24] intentionally omitted <==**
**==> picture [23 x 8] intentionally omitted <==**
## _**Channel Gain Error**_
Channel Gain Error is a deviation from the ideal slope of the transfer function. The Prescaler Gain Error is expressed as the percent difference between the actual and ideal, as shown in EQ 2.
**==> picture [115 x 11] intentionally omitted <==**
**==> picture [23 x 8] intentionally omitted <==**
**2-83**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Channel Input Offset Error**_
Channel Offset error is measured as the input voltage that causes the transition from zero to a count of one. An Ideal Prescaler will have offset equal to ½ of LSB voltage. Offset error is a positive or negative when the first transition point is higher or lower than ideal. Offset error is expressed in LSB or input voltage.
## _**Total Channel Error**_
Total Channel Error is defined as the total error measured compared to the ideal value. Total Channel Error is the sum of gain error and offset error combined. Figure 2-68 shows how Total Channel Error is measured.
Total Channel Error is defined as the difference between the actual ADC output and ideal ADC output. In the example shown in Figure 2-68, the Total Channel Error would be a negative number.
**==> picture [183 x 155] intentionally omitted <==**
**----- Start of picture text -----**<br>
C hannel Gain<br>Actual Output<br>Total C hannel Error<br>Channel Input<br>Offset Error<br>Input Voltage to Prescaler<br>Ideal Output<br>ADC Output Code<br>}<br>**----- End of picture text -----**<br>
_**Figure 2-68 •**_ **Total Channel Error Example**
**Revision 8**
**2-84**
_Device Architecture_
## _**Direct Digital Input**_
The AV, AC, and AT pads can also be configured as high-voltage digital inputs (Figure 2-69). As these pads are 12 V–tolerant, the digital input can also be up to 12 V. However, the frequency at which these pads can operate is limited to 10 MHz.
To enable one of these analog input pads to operate as a digital input, its corresponding Digital Input Enable (DENA _xy_ ) pin on the Analog Block must be pulled High, where _x_ is either V, C, or T (for AV, AC, or AT pads, respectively) and _y_ is in the range 0 to 9, corresponding to the appropriate Analog Quad.
When the pad is configured as a digital input, the signal will come out of the Analog Block macro on the appropriate DA _x_ OUT _y_ pin, where _x_ represents the pad type (V for AV pad, C for AC pad, or T for AT pad) and _y_ represents the appropriate Analog Quad number. Example: If the AT pad in Analog Quad 5 is configured as a digital input, it will come out on the DATOUT5 pin of the Analog Block macro.
**==> picture [447 x 273] intentionally omitted <==**
**----- Start of picture text -----**<br>
Off-Chip<br>AV AC AG AT<br>Pads Voltage Current Gate Temperature<br>Monitor Block Monitor Block Driver Monitor Block<br>On-Chip<br>Analog Quad<br>Prescaler Prescaler Prescaler<br>Power<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor / Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 2-69 •**_ **Analog Quad Direct Digital Input Configuration**
**2-85**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Current Monitor**_
The Fusion Analog Quad is an excellent element for voltage- and current-monitoring applications. In addition to supporting the same functionality offered by the AV pad, the AC pad can be configured to monitor current across an external sense resistor (Figure 2-70). To support this current monitor function, a differential amplifier with 10x gain passes the amplified voltage drop between the AV and AC pads to the ADC. The amplifier enables the user to use very small resistor values, thereby limiting any impact on the circuit. This function of the AC pad does not limit AV pad operation. The AV pad can still be configured for use as a direct voltage input or scaled through the AV prescaler independently of it’s use as an input to the AC pad’s differential amplifier.
**==> picture [450 x 315] intentionally omitted <==**
**----- Start of picture text -----**<br>
Power<br>Off-Chip<br>AV AC AG AT<br>Pads Voltage Current Gate Temperature<br>Monitor Block Monitor Block Driver Monitor Block<br>On-Chip<br>Analog Quad<br>Prescaler Prescaler Prescaler<br>Power<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor / Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 2-70 •**_ **Analog Quad Current Monitor Configuration**
**Revision 8**
**2-86**
_Device Architecture_
To initiate a current measurement, the appropriate Current Monitor Strobe (CMSTB) signal on the AB macro must be asserted low for at least tCMSLO in order to discharge the previous measurement. Then CMSTB must be asserted high for at least tCMSET prior to asserting the ADCSTART signal. The CMSTB must remain high until after the SAMPLE signal is de-asserted by the AB macro. Note that the minimum sample time cannot be less than tCMSHI. Figure 2-71 shows the timing diagram of CMSTB in relationship with the ADC control signals.
**==> picture [24 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
tC MSHI<br>**----- End of picture text -----**<br>
**==> picture [357 x 126] intentionally omitted <==**
**----- Start of picture text -----**<br>
CMSTBx<br>tCM SLO tCMSET<br>VADC ADCSTART can be asserted<br>after this point to start ADC<br>sampling.<br>ADCSTART<br>e t<br>**----- End of picture text -----**<br>
## _**Figure 2-71 •**_ **Timing Diagram for Current Monitor Strobe**
Figure 2-72 illustrates positive current monitor operation. The differential voltage between AV and AC goes into the 10× amplifier and is then converted by the ADC. For example, a current of 1.5 A is drawn from a 10 V supply and is measured by the voltage drop across a 0.050 sense resistor, The voltage drop is amplified by ten times by the amplifier and then measured by the ADC. The 1.5 A current creates a differential voltage across the sense resistor of 75 mV. This becomes 750 mV after amplification. Thus, the ADC measures a current of 1.5 A as 750 mV. Using an ADC with 8-bit resolution and VAREF of 2.56 V, the ADC result is decimal 75. EQ 3 shows how to compute the current from the ADC result.
~~||~~ I = _ADC_ _VAREF_ 10 2 _[N]_ _Rsense_
_EQ 3_
where
I is the current flowing through the sense resistor ADC is the result from the ADC VAREF is the Reference voltage N is the number of bits
Rsense is the resistance of the sense resistor
**2-87**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
**==> picture [327 x 175] intentionally omitted <==**
**----- Start of picture text -----**<br>
0-12 V RSENSE I<br>AVx ACx<br>CMSTBx<br>VADC to Analog MUX<br>10 X (refer Table 2-36<br>for MUX channel<br>number)<br>Current Monitor<br>**----- End of picture text -----**<br>
_**Figure 2-72 •**_ **Positive Current Monitor**
Care must be taken when choosing the right resistor for current measurement application. Note that because of the 10× amplification, the maximum measurable difference between the AV and AC pads is VAREF / 10. A larger AV-to-AC voltage drop will result in ADC saturation; that is, the digital code put out by the ADC will stay fixed at the full scale value. Therefore, the user must select the external sense resistor appropriately. Table 2-38 shows recommended resistor values for different current measurement ranges. When choosing resistor values for a system, there is a trade-off between measurement accuracy and power consumption. Choosing a large resistor will increase the voltage drop and hence increase accuracy of the measurement; however the larger voltage drop dissipates more power (P = I[2] × R).
The Current Monitor is a unipolar system, meaning that the differential voltage swing must be from 0 V to VAREF/10. Therefore, the Current Monitor only supports differential voltage where |VAV-VAC| is greater than 0 V. This results in the requirement that the potential of the AV pad must be larger than the potential of the AC pad. This is straightforward for positive voltage systems. For a negative voltage system, it means that the AV pad must be “more negative” than the AC pad. This is shown in Figure 2-73.
In this case, both the AV pad and the AC pad are configured for negative operations and the output of the differential amplifier still falls between 0 V and VAREF as required .
_**Table 2-37 •**_ **Recommended Resistor for Different Current Range Measurement**
|**Current Range**|**Recommended Minimum Resistor Value (Ohms)**|
|---|---|
|> 5 mA – 10 mA|10 – 20|
|> 10 mA – 20 mA|5 – 10|
|> 20 mA – 50 mA|2.5 – 5|
|> 50 mA – 100 mA|1 – 2|
|> 100 mA – 200 mA|0.5 – 1|
|> 200 mA – 500 mA|0.3 – 0.5|
|> 500 mA – 1 A|0.1 – 0.2|
|> 1 A – 2 A|0.05 – 0.1|
|> 2 A – 4 A|0.025 – 0.05|
|> 4 A – 8 A|0.0125 – 0.025|
|> 8 A – 12 A|0.00625 – 0.02|
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0 to RSENSE I<br>–10.5 V<br>AVx ACx<br>CMSTBx<br>VADC to Analog MUX<br>10 X (see Table 2-36<br>for MUXchannel<br>number)<br>Current Monitor<br>**----- End of picture text -----**<br>
_**Figure 2-73 •**_ **Negative Current Monitor**
## _**Terminology**_
## _**Accuracy**_
The accuracy of Fusion Current Monitor is ±2 mV minimum plus 5% of the differential voltage at the input. The input accuracy can be translated to error at the ADC output by using EQ 4. The 10 V/V gain is the gain of the Current Monitor Circuit, as described in the "Current Monitor" section on page 2-86. For 8- bit mode, _N_ = 8, _VAREF_ = 2.56 V, zero differential voltage between AV and AC, the Error ( _EADC_ ) is equal to 2 LSBs.
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where
_N_ is the number of bits
_VAREF_ is the Reference voltage
_VAV_ is the voltage at AV pad
_VAC_ is the voltage at AC pad
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## _**Gate Driver**_
The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin (Figure 2-74). Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current sink or source and requires an external pull-up or pull-down resistor. The AG supports 4 selectable gate drive levels: 1 µA, 3 µA, 10 µA, and 30 µA (Figure 2-75 on page 2-91). The AG also supports a High Current Drive mode in which it can sink 20 mA; in this mode the switching rate is approximately 1.3 MHz with 100 ns turn-on time and 600 ns turn-off time. Modeled on an open-drain-style output, it does not output a voltage level without an appropriate pull-up or pull-down resistor. If 1 V is forced on the drain, the current sinking/sourcing will exceed the ability of the transistor, and the device could be damaged.
The AG pad is turned on via the corresponding GDON _x_ pin in the Analog Block macro, where _x_ is the number of the corresponding Analog Quad for the AG pad to be enabled (GDON0 to GDON9).
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Power Line Side Load Side<br>Off-Chip Rpullup<br>AV AC AG AT<br>Pads Voltage <n) Current Gate Temperature<br>Monitor Block Monitor Block << (0 Driver =< Monitor Block<br>On-Chip<br>Analog Quad<br>Prescaler Prescaler Prescaler<br>Power<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor / Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 2-74 •**_ **Gate Driver**
The gate-to-source voltage (Vgs) of the external MOSFET is limited to the programmable drive current times the external pull-up or pull-down resistor value (EQ 5).
Vgs Ig × (Rpullup or Rpulldown)
_EQ 5_
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The rate at which the gate voltage of the external MOSFET slews is determined by the current, Ig, sourced or sunk by the AG pin and the gate-to-source capacitance, CGS, of the external MOSFET. As an approximation, the slew rate is given by EQ 6.
dv/dt = Ig / CGS
_EQ 6_
CGS is not a fixed capacitance but, depending on the circuitry connected to its drain terminal, can vary significantly during the course of a turn-on or turn-off transient. Thus, EQ 6 on page 2-91 can only be used for a first-order estimate of the switching speed of the external MOSFET.
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High<br>Current<br>1 μA 3 μA 10 μA 30 μA<br>AG<br>High<br>Current<br>1 μA 3 μA 10 μA 30 μA<br>**----- End of picture text -----**<br>
_**Figure 2-75 •**_ **Gate Driver Example**
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## **Temperature Monitor**
The final pin in the Analog Quad is the Analog Temperature (AT) pin. The AT pin is used to implement an accurate temperature monitor in conjunction with an external diode-connected bipolar transistor (Figure 2-76). For improved temperature measurement accuracy, it is important to use the ATRTN pin for the return path of the current sourced by the AT pin. Each ATRTN pin is shared between two adjacent Analog Quads. Additionally, if not used for temperature monitoring, the AT pin can provide functionality similar to that of the AV pad. However, in this mode only positive voltages can be applied to the AT pin, and only two prescaler factors are available (16 V and 4 V ranges—refer to Table 2-57 on page 2-130).
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Discrete<br>Bipolar<br>Transistor<br>Off-Chip<br>AV AC AG AT ATRTN<br>Pads Voltage Current Gate Temperature<br>Monitor Block Monitor Block Driver Monitor Block<br>On-Chip<br>Analog Quad<br>Prescaler Prescaler Prescaler<br>Power<br>MOSFET<br>Digital Digital Gate Driver Digital<br>Input Input Input<br>Current Temperature<br>Monitor / Instr Monitor<br>Amplifier<br>To FPGA To FPGA From FPGA To FPGA<br>(DAVOUTx) (DACOUTx) (GDONx) (DATOUTx)<br>To Analog MUX To Analog MUX To Analog MUX<br>**----- End of picture text -----**<br>
_**Figure 2-76 •**_ **Temperature Monitor Quad**
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Fusion uses a remote diode as a temperature sensor. The Fusion Temperature Monitor uses a differential input; the AT pin and ATRTN (AT Return) pin are the differential inputs to the Temperature Monitor. There is one Temperature Monitor in each Quad. A simplified block diagram is shown in Figure 2-77.
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VDD33A<br>10 μA 100 μA<br>TMSTBx<br>+<br>ATx + VADC to Analog MUX<br>∆V 12.5 X (refer Table 2-36<br>– for MUX ChannelNumber)<br>–<br>ATRTNxy<br>**----- End of picture text -----**<br>
_**Figure 2-77 •**_ **Block Diagram for Temperature Monitor Circuit**
The Fusion approach to measuring temperature is forcing two different currents through the diode with a ratio of 10:1. The switch that controls the different currents is controlled by the Temperature Monitor Strobe signal, TMSTB. Setting TMSTB to '1' will initiate a Temperature reading. The TMSTB should remain '1' until the ADC finishes sampling the voltage from the Temperature Monitor. The minimum sample time for the Temperature Monitor cannot be less than the minimum strobe high time minus the setup time. Figure 2-78 shows the timing diagram.
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tT MSHI<br>TMSTBx<br>tTMSLO tTMSSET<br>VADC ADC should start<br>sampling at this point<br>ADCSTART<br>ei t<br>**----- End of picture text -----**<br>
_**Figure 2-78 •**_ **Timing Diagram for the Temperature Monitor Strobe Signal**
Note: When the IEEE 1149.1 Boundary Scan EXTEST instruction is executed, the AG pad drive strength ceases and becomes a 1 µA sink into the Fusion device.
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The diode’s voltage is measured at each current level and the temperature is calculated based on EQ 7.
_V_ TMSLO – _V_ TMSHI = _n_ ----- _[kT] q_ **-** ln _I_ ----------------- _I_ TMSLOTMSHI
_EQ 7_
where
_ITMSLO_ is the current when the Temperature Strobe is Low, typically 100 µA
_ITMSHI_ is the current when the Temperature Strobe is High, typically 10 µA
_VTMSLO_ is diode voltage while Temperature Strobe is Low
_VTMSHI_ is diode voltage while Temperature Strobe is High
_n_ is the non-ideality factor of the diode-connected transistor. It is typically 1.004 for the Microsemirecommended transistor type 2N3904.
_K_ = 1.3806 x 10[-23] J/K is the Boltzman constant
_Q_ = 1.602 x 10[-19] C is the charge of a proton
When _ITMSLO_ / _ITMSHI_ = 10, the equation can be simplified as shown in EQ 8.
– _V_ = _V_ TMSLO – _V_ TMSHI = 1.986 10[4] _nT_
_EQ 8_
In the Fusion TMB, the ideality factor _n_ for 2N3904 is 1.004 and _V_ is amplified 12.5 times by an internal amplifier; hence the voltage before entering the ADC is as given in EQ 9.
_VADC_ = _V_ 12.5 = 2.5 mV _K_ _T_
_EQ 9_
This means the temperature to voltage relationship is 2.5 mV per degree Kelvin. The unique design of Fusion has made the Temperature Monitor System simple for the user. When the 10-bit mode ADC is used, each LSB represents 1 degree Kelvin, as shown in EQ 10. That is, e. 25°C is equal to 293°K and is represented by decimal 293 counts from the ADC.
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_EQ 10_
If 8-bit mode is used for the ADC resolution, each LSB represents 4 degrees Kelvin; however, the resolution remains as 1 degree Kelvin per LSB, even for 12-bit mode, due to the Temperature Monitor design. An example of the temperature data format for 10-bit mode is shown in Table 2-38.
_**Table 2-38 •**_ **Temperature Data Format**
|**_Table 2-38 •_Temperature Data Format**|**Temperature Data Format**||
|---|---|---|
|**Temperature**|**Temperature (K)**|**Digital Output (ADC 10-bit mode)**|
|–40°C|233|00 1110 1001|
|–20°C|253|00 1111 1101|
|0°C|273|01 0001 0001|
|1°C|274|01 0001 0010|
|10 °C|283|01 0001 1011|
|25°C|298|01 0010 1010|
|50 °C|323|01 0100 0011|
|85 °C|358|01 0110 0110|
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## _**Terminology**_
## _**Resolution**_
Resolution defines the smallest temperature change Fusion Temperature Monitor can resolve. For ADC configured as 8-bit mode, each LSB represents 4°C, and 1°C per LSB for 10-bit mode. With 12-bit mode, the Temperature Monitor can still only resolve 1°C due to Temperature Monitor design.
## _**Offset**_
The Fusion Temperature Monitor has a systematic offset (Table 2-49 on page 2-117), excluding error due to board resistance and ideality factor of the external diode. Microsemi provides an IP block (CalibIP) that is required in order to mitigate the systematic temperature offset. For further details on CalibIP, refer to the “ _Temperature_ , _Voltage, and Current Calibration in Fusion FPGAs_ ” _chapter of the Fusion FPGA Fabric User Guide._
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## **Analog-to-Digital Converter Block**
At the heart of the Fusion analog system is a programmable Successive Approximation Register (SAR) ADC. The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can resolve 500 ksps. All results are MSB-justified in the ADC. The input to the ADC is a large 32:1 analog input multiplexer. A simplified block diagram of the Analog Quads, analog input multiplexer, and ADC is shown in Figure 2-79. The ADC offers multiple self-calibrating modes to ensure consistent high performance both at power-up and during runtime.
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VCC (1.5 V)<br>Pads 0<br>AV0<br>AC0 1<br>AG0 Analog<br>AT0 Quad 0<br>t-$— C= These are hardwired<br>ATRETURN01<br>connections within<br>AV1AC1 — Analog SCS Analog Quad.<br>AG1 Quad 1<br>AT1 — ee y<br>AV2 - SCS<br>AC2 Analog<br>AG2<br>AT2 — Quad 2 CSCS<br>ATRETURN23<br>AV3AC3 +-— Analog<br>AG3 — Quad 3 ,<br>AT3<br>AV4<br>AG4AC4 — Analog aa<br>AT4 Quad 4 12<br>— PT Analog MUX<br>ATRETURN45<br>AV5 (32 to 1) ADC<br>AC5 — Analog PT<br>AG5AT5 — Quad 5 Digital Output to FPGA<br>AV6 -<br>AC6<br>AG6 — Analog fT<br>AT6 — Quad 6 TC<br>ATRETURN67<br>AV7AC7 — Analog SC~S=S<br>AG7 — Quad 7 SCS~SCS<br>AT7<br>AV8 - SCS<br>AG8AC8AT8 — — Quad 8Analog CSCSSCS<br>ATRETURN89<br>AV9AC9 — Analog SCS<br>AG9 Quad 9<br>AT9<br>31<br>Temperature<br>Monitor<br>CHNUMBER[4:0]<br>Internal Diode<br>**----- End of picture text -----**<br>
_**Figure 2-79 •**_ **ADC Block Diagram**
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## _**ADC Description**_
The Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of features for different use models. Figure 2-80 shows a block diagram of the Fusion ADC.
- Configurable resolution: 8-bit, 10-bit, and 12-bit mode
- DNL: 0.6 LSB for 10-bit mode
- INL: 0.4 LSB for 10-bit mode
- No missing code
- Internal VAREF = 2.56 V
- Maximum Sample Rate = 600 Ksps
- Power-up calibration and dynamic calibration after every sample to compensate for temperature drift over time
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CALIBRATE<br>SAMPLE<br>BUSY<br>DATAVALID<br>VAREF<br>Analog<br>STATUS<br>MUX<br>32 12<br>Signals from<br>SAR ADC RESULT<br>Analog Quads<br>CHNUMBER STC MODE<br>SYSCLK TVC ADCCLK<br>**----- End of picture text -----**<br>
_**Figure 2-80 •**_ **ADC Simplified Block Diagram**
## _**ADC Theory of Operation**_
An analog-to-digital converter is used to capture discrete samples of a continuous analog voltage and provide a discrete binary representation of the signal. Analog-to-digital converters are generally characterized in three ways:
- Input voltage range
- Resolution
- Bandwidth or conversion rate
The input voltage range of an ADC is determined by its reference voltage (VREF). Fusion devices include an internal 2.56 V reference, or the user can supply an external reference of up to 3.3 V. The following examples use the internal 2.56 V reference, so the full-scale input range of the ADC is 0 to 2.56 V.
The resolution (LSB) of the ADC is a function of the number of binary bits in the converter. The ADC approximates the value of the input voltage using 2n steps, where n is the number of bits in the converter. Each step therefore represents VREF÷ 2n volts. In the case of the Fusion ADC configured for 12-bit operation, the LSB is 2.56 V / 4096 = 0.625 mV.
Finally, bandwidth is an indication of the maximum number of conversions the ADC can perform each second. The bandwidth of an ADC is constrained by its architecture and several key performance characteristics.
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There are several popular ADC architectures, each with advantages and limitations.
The analog-to-digital converter in Fusion devices is a switched-capacitor Successive Approximation Register (SAR) ADC. It supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per second (ksps). Built-in bandgap circuitry offers 1% internal voltage reference accuracy or an external reference voltage can be used.
As shown in Figure 2-81, a SAR ADC contains N capacitors with binary-weighted values.
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Comparator<br>C C / 2 C / 4 C / 2 [N–2] C / 2 [N–1]<br>VIN VREF<br>**----- End of picture text -----**<br>
_**Figure 2-81 •**_ **Example SAR ADC Architecture**
To begin a conversion, all of the capacitors are quickly discharged. Then VIN is applied to all the capacitors for a period of time (acquisition time) during which the capacitors are charged to a value very close to VIN. Then all of the capacitors are switched to ground, and thus –VIN is applied across the comparator. Now the conversion process begins. First, C is switched to VREF. Because of the binary weighting of the capacitors, the voltage at the input of the comparator is then shown by EQ 11.
Voltage at input of comparator = –VIN + VREF / 2
_EQ 11_
If VIN is greater than VREF / 2, the output of the comparator is 1; otherwise, the comparator output is 0. A register is clocked to retain this value as the MSB of the result. Next, if the MSB is 0, C is switched back to ground; otherwise, it remains connected to VREF, and C / 2 is connected to VREF. The result at the comparator input is now either –VIN + VREF / 4 or –VIN + 3 VREF / 4 (depending on the state of the MSB), and the comparator output now indicates the value of the next most significant bit. This bit is likewise registered, and the process continues for each subsequent bit until a conversion is completed. The conversion process requires some acquisition time plus N + 1 ADC clock cycles to complete.
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This process results in a binary approximation of VIN. Generally, there is a fixed interval T, the sampling period, between the samples. The inverse of the sampling period is often referred to as the sampling frequency fS = 1 / T. The combined effect is illustrated in Figure 2-82.
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LSB<br>T<br>**----- End of picture text -----**<br>
_**Figure 2-82 •**_ **Conversion Example**
Figure 2-82 demonstrates that if the signal changes faster than the sampling rate can accommodate, or if the actual value of VIN falls between counts in the result, this information is lost during the conversion. There are several techniques that can be used to address these issues.
First, the sampling rate must be chosen to provide enough samples to adequately represent the input signal. Based on the Nyquist-Shannon Sampling Theorem, the minimum sampling rate must be at least twice the frequency of the highest frequency component in the target signal (Nyquist Frequency). For example, to recreate the frequency content of an audio signal with up to 22 KHz bandwidth, the user must sample it at a minimum of 44 ksps. However, as shown in Figure 2-82, significant post-processing of the data is required to interpolate the value of the waveform during the time between each sample.
Similarly, to re-create the amplitude variation of a signal, the signal must be sampled with adequate resolution. Continuing with the audio example, the dynamic range of the human ear (the ratio of the amplitude of the threshold of hearing to the threshold of pain) is generally accepted to be 135 dB, and the dynamic range of a typical symphony orchestra performance is around 85 dB. Most commercial recording media provide about 96 dB of dynamic range using 16-bit sample resolution. But 16-bit fidelity does not necessarily mean that you need a 16-bit ADC. As long as the input is sampled at or above the Nyquist Frequency, post-processing techniques can be used to interpolate intermediate values and reconstruct the original input signal to within desired tolerances.
If sophisticated digital signal processing (DSP) capabilities are available, the best results are obtained by implementing a reconstruction filter, which is used to interpolate many intermediate values with higher resolution than the original data. Interpolating many intermediate values increases the effective number of samples, and higher resolution increases the effective number of bits in the sample. In many cases, however, it is not cost-effective or necessary to implement such a sophisticated reconstruction algorithm. For applications that do not require extremely fine reproduction of the input signal, alternative methods can enhance digital sampling results with relatively simple post-processing. The details of such techniques are out of the scope of this chapter; refer to the _Improving ADC Results through Oversampling and Post-Processing of Data_ white paper for more information.
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## _**ADC Terminology**_
## _**Conversion Time**_
Conversion time is the interval between the release of the hold state (imposed by the input circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one LSB of a new input value.
## _**DNL – Differential Non-Linearity**_
For an ideal ADC, the analog-input levels that trigger any two successive output codes should differ by one LSB (DNL = 0). Any deviation from one LSB in defined as DNL (Figure 2-83).
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Ideal Output<br>Error = –0.5 LSB Actual Output<br>Error = +1 LSB<br>Input Voltage to Prescaler<br>ADC Output Code<br>**----- End of picture text -----**<br>
_**Figure 2-83 •**_ **Differential Non-Linearity (DNL)**
## _**ENOB – Effective Number of Bits**_
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists only of quantization of noise. As the input frequency increases, the overall noise (particularly in the distortion components) also increases, thereby reducing the ENOB and SINAD (also see “Signal-to-Noise and Distortion Ratio (SINAD)”.) ENOB for a full-scale, sinusoidal input waveform is computed using EQ 12.
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## _**FS Error – Full-Scale Error**_
Full-scale error is the difference between the actual value that triggers that transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error.
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## _**Gain Error**_
The gain error of an ADC indicates how well the slope of an actual transfer function matches the slope of the ideal transfer function. Gain error is usually expressed in LSB or as a percent of full-scale (%FSR). Gain error is the full-scale error minus the offset error (Figure 2-84).
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Gain = 2 LSB<br>1...11<br>Ideal Output<br>Actual Output<br>0...00<br>Input Voltage to Prescaler<br>ADC Output Code<br>FS<br>Voltage<br>**----- End of picture text -----**<br>
_**Figure 2-84 •**_ **Gain Error**
## _**Gain Error Drift**_
Gain-error drift is the variation in gain error due to a change in ambient temperature, typically expressed in ppm/°C.
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## _**INL – Integral Non-Linearity**_
INL is the deviation of an actual transfer function from a straight line. After nullifying offset and gain errors, the straight line is either a best-fit straight line or a line drawn between the end points of the transfer function (Figure 2-85).
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INL = +0.5 LSB<br>Ideal Output<br>Actual Output<br>INL = +1 LSB<br>Input Voltage to Prescaler<br>ADC Output Code<br>**----- End of picture text -----**<br>
_**Figure 2-85 •**_ **Integral Non-Linearity (INL)**
## _**LSB – Least Significant Bit**_
In a binary number, the LSB is the least weighted bit in the group. Typically, the LSB is the furthest right bit. For an ADC, the weight of an LSB equals the full-scale voltage range of the converter divided by 2[N] , where N is the converter’s resolution.
EQ 13 shows the calculation for a 10-bit ADC with a unipolar full-scale voltage of 2.56 V:
1 LSB = (2.56 V / 2[10] ) = 2.5 mV
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## _**No Missing Codes**_
An ADC has no missing codes if it produces all possible digital codes in response to a ramp signal applied to the analog input.
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## _**Offset Error**_
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. For an ideal ADC, the first transition occurs at 0.5 LSB above zero. The offset voltage is measured by applying an analog input such that the ADC outputs all zeroes and increases until the first transition occurs (Figure 2-86).
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Ideal Output<br>Actual Output<br>0...01<br>Offset Error = 1.5 LSB<br>0...00<br>Input Voltage to Prescaler<br>ADC Output Code<br>**----- End of picture text -----**<br>
_**Figure 2-86 •**_ **Offset Error**
## _**Resolution**_
ADC resolution is the number of bits used to represent an analog input signal. To more accurately replicate the analog signal, resolution needs to be increased.
## _**Sampling Rate**_
Sampling rate or sample frequency, specified in samples per second (sps), is the rate at which an ADC acquires (samples) the analog input.
## _**SNR – Signal-to-Noise Ratio**_
SNR is the ratio of the amplitude of the desired signal to the amplitude of the noise signals at a given point in time. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR (EQ 14) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum ADC noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
_SNR_ dB[MAX] = 6.02dB _N_ + 1.76dB
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## _**SINAD – Signal-to-Noise and Distortion**_
SINAD is the ratio of the rms amplitude to the mean value of the root-sum-square of the all other spectral components, including harmonics, but excluding DC. SINAD is a good indication of the overall dynamic performance of an ADC because it includes all components which make up noise and distortion.
## _**Total Harmonic Distortion**_
THD measures the distortion content of a signal, and is specified in decibels relative to the carrier (dBc). THD is the ratio of the RMS sum of the selected harmonics of the input signal to the fundamental itself. Only harmonics within the Nyquist limit are included in the measurement.
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## _**TUE – Total Unadjusted Error**_
TUE is a comprehensive specification that includes linearity errors, gain error, and offset error. It is the worst-case deviation from the ideal device performance. TUE is a static specification (Figure 2-87).
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TUE = ±0.5 LSB<br>IDEAL OUTPUT<br>Input Voltage to Prescaler<br>ADC Output Code<br>**----- End of picture text -----**<br>
_**Figure 2-87 •**_ **Total Unadjusted Error (TUE)**
## _**ADC Operation**_
Once the ADC has powered up and been released from reset, ADCRESET, the ADC will initiate a calibration routine designed to provide optimal ADC performance. The Fusion ADC offers a robust calibration scheme to reduce integrated offset and linearity errors. The offset and linearity errors of the main capacitor array are compensated for with an 8-bit calibration capacitor array. The offset/linearity error calibration is carried out in two ways. First, a power-up calibration is carried out when the ADC comes out of reset. This is initiated by the CALIBRATE output of the Analog Block macro and is a fixed number of ADC_CLK cycles (3,840 cycles), as shown in Figure 2-89 on page 2-111. In this mode, the linearity and offset errors of the capacitors are calibrated.
To further compensate for drift and temperature-dependent effects, every conversion is followed by postcalibration of either the offset or a bit of the main capacitor array. The post-calibration ensures that, over time and with temperature, the ADC remains consistent.
After both calibration and the setting of the appropriate configurations, as explained above, the ADC is ready for operation. Setting the ADCSTART signal high for one clock period will initiate the sample and conversion of the analog signal on the channel as configured by CHNUMBER[4:0]. The status signals SAMPLE and BUSY will show when the ADC is sampling and converting (Figure 2-91 on page 2-112). Both SAMPLE and BUSY will initially go high. After the ADC has sampled and held the analog signal, SAMPLE will go low. After the entire operation has completed and the analog signal is converted, BUSY will go low and DATAVALID will go high. This indicates that the digital result is available on the RESULT[11:0] pins.
DATAVALID will remain high until a subsequent ADCSTART is issued. The DATAVALID goes low on the rising edge of SYSCLK as shown in Figure 2-90 on page 2-112. The RESULT signals will be kept constant until the ADC finishes the subsequent sample. The next sampled RESULT will be available when DATAVALID goes high again. It is ideal to read the RESULT when DATAVALID is '1'. The RESULT is latched and remains unchanged until the next DATAVLAID rising edge.
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## _**ADC Input Multiplexer**_
At the input to the Fusion ADC is a 32:1 multiplexer. Of the 32 input channels, up to 30 are user definable. Two of these channels are hardwired internally. Channel 31 connects to an internal temperature diode so the temperature of the Fusion device itself can be monitored. Channel 0 is wired to the FPGA’s 1.5 V VCC supply, enabling the Fusion device to monitor its own power supply. Doing this internally makes it unnecessary to use an analog I/O to support these functions. The balance of the MUX inputs are connected to Analog Quads (see the "Analog Quad" section on page 2-80). Table 2-40 defines which Analog Quad inputs are associated with which specific analog MUX channels. The number of Analog Quads present is device-dependent; refer to the family list in the "Fusion Family" table on page I of this datasheet for the number of quads per device. Regardless of the number of quads populated in a device, the internal connections to both VCC and the internal temperature diode remain on Channels 0 and 31, respectively. To sample the internal temperature monitor, it must be strobed (similar to the AT pads). The TMSTBINT pin on the Analog Block macro is the control for strobing the internal temperature measurement diode.
To determine which channel is selected for conversion, there is a five-pin interface on the Analog Block, CHNUMBER[4:0], defined in Table 2-39.
_**Table 2-39 •**_ **Channel Selection**
|**_Table 2-39 •_Channel Selection**||
|---|---|
|**Channel Number**|**CHNUMBER[4:0]**|
|0|00000|
|1|00001|
|2|00010|
|3|00011|
|.<br>.<br>.|.<br>.<br>.|
|30|11110|
|31|11111|
Table 2-40 shows the correlation between the analog MUX input channels and the analog input pins.
_**Table 2-40 •**_ **Analog MUX Channels**
|**_Table 2-40 •_Analog MUX Channels**|||
|---|---|---|
|**Analog MUX Channel**|**Signal**|**Analog Quad Number**|
|0|Vcc_analog||
|1|AV0|Analog Quad 0|
|2|AC0||
|3|AT0||
|4|AV1|Analog Quad 1|
|5|AC1||
|6|AT1||
|7|AV2|Analog Quad 2|
|8|AC2||
|9|AT2||
|10|AV3|Analog Quad 3|
|11|AC3||
|12|AT3||
|13|AV4|Analog Quad 4|
|14|AC4||
|15|AT4||
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_**Table 2-40 •**_ **Analog MUX Channels (continued)**
|**Analog MUX Channel**|**Signal**|**Analog Quad Number**|
|---|---|---|
|16|AV5|Analog Quad 5|
|17|AC5||
|18|AT5||
|19|AV6|Analog Quad 6|
|20|AC6||
|21|AT6||
|22|AV7|Analog Quad 7|
|23|AC7||
|24|AT7||
|25|AV8|Analog Quad 8|
|26|AC8||
|27|AT8||
|28|AV9|Analog Quad 9|
|29|AC9||
|30|AT9||
|31|Internal temperature monitor||
The ADC can be powered down independently of the FPGA core, as an additional control or for powersaving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls only the comparators in the ADC.
## _**ADC Modes**_
The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion, and dynamic calibration. This is controlled by MODE[3:0], as defined in Table 2-41 on page 2-106.
The output of the ADC is the RESULT[11:0] signal. In 8-bit mode, the Most Significant 8 Bits RESULT[11:4] are used as the ADC value and the Least Significant 4 Bits RESULT[3:0] are logical '0's. In 10-bit mode, RESULT[11:2] are used the ADC value and RESULT[1:0] are logical 0s.
_**Table 2-41 •**_ **Mode Bits Function**
|**Name**|**Bits**|**Function**|
|---|---|---|
|MODE|3|0 – Internal calibration after every conversion; two ADCCLK cycles are used after the conversion.<br>1 – No calibration after every conversion|
|MODE|2|0 – Power-down after conversion<br>1 – No Power-down after conversion|
|MODE|1:0|00 – 10-bit<br>01 – 12-bit<br>10 – 8-bit<br>11 – Unused|
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## _**Integrated Voltage Reference**_
The Fusion device has an integrated on-chip 2.56 V reference voltage for the ADC. The value of this reference voltage was chosen to make the prescaling and postscaling factors for the prescaler blocks change in a binary fashion. However, if desired, an external reference voltage of up to 3.3 V can be connected between the VAREF and ADCGNDREF pins. The VAREFSEL control pin is used to select the reference voltage.
## _**Table 2-42 •**_ **VAREF Bit Function**
|**Name**|**Bit**|**Function**|
|---|---|---|
|VAREF|0|Reference voltage selection<br>0 – Internal voltage reference selected. VAREF pin outputs 2.56 V.<br>1 – Input external voltage reference from VAREF and ADCGNDREF|
## _**ADC Clock**_
The speed of the ADC depends on its internal clock, ADCCLK, which is not accessible to users. The ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed of the ADCCLK in relationship to SYSCLK, based on EQ 15.
tADCCLK = 4 1 + TVC tSYSCLK
_EQ 15_
TVC: Time Divider Control (0–255)
tADCCLK is the period of ADCCLK, and must be between 0.5 MHz and 10 MHz tSYSCLK is the period of SYSCLK
## _**Table 2-43 •**_ **TVC Bits Function**
|**_Table 2-43 •_TVC Bits Function**|||
|---|---|---|
|**Name**|**Bits**|**Function**|
|TVC|[7:0]|SYSCLK divider control|
The frequency of ADCCLK, fADCCLK, must be within 0.5 Hz to 10 MHz.
The inputs to the ADC are synchronized to SYSCLK. A conversion is initiated by asserting the ADCSTART signal on a rising edge of SYSCLK. Figure 2-90 on page 2-112 and Figure 2-91 on page 2-112 show the timing diagram for the ADC.
## _**Acquisition Time or Sample Time Control**_
Acquisition time (tSAMPLE) specifies how long an analog input signal has to charge the internal capacitor array. Figure 2-88 shows a simplified internal input sampling mechanism of a SAR ADC.
**==> picture [164 x 78] intentionally omitted <==**
**----- Start of picture text -----**<br>
Sample and Hold<br>Rsource ZINAD<br>CINAD<br>**----- End of picture text -----**<br>
## _**Figure 2-88 •**_ **Simplified Sample and Hold Circuitry**
The internal impedance (ZINAD), external source resistance (RSOURCE), and sample capacitor (CINAD) form a simple RC network. As a result, the accuracy of the ADC can be affected if the ADC is given insufficient time to charge the capacitor. To resolve this problem, you can either reduce the source resistance or increase the sampling time by changing the acquisition time using the STC signal.
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EQ 16 through EQ 18 can be used to calculate the acquisition time required for a given input. The STC signal gives the number of sample periods in ADCCLK for the acquisition time of the desired signal. If the actual acquisition time is higher than the STC value, the settling time error can affect the accuracy of the ADC, because the sampling capacitor is only partially charged within the given sampling cycle. Example acquisition times are given in Table 2-44 and Table 2-45. When controlling the sample time for the ADC along with the use of the active bipolar prescaler, current monitor, or temperature monitor, the minimum sample time(s) for each must be obeyed. EQ 19 can be used to determine the appropriate value of STC. You can calculate the minimum actual acquisition time by using EQ 16:
VOUT = VIN(1 – e–[t/RC] )
**==> picture [29 x 8] intentionally omitted <==**
For 0.5 LSB gain error, VOUT should be replaced with (VIN –(0.5 × LSB Value)): (VIN – 0.5 × LSB Value) = VIN(1 – e–[t/RC] )
**==> picture [29 x 8] intentionally omitted <==**
where VIN is the ADC reference voltage (VREF) Solving EQ 17:
t = RC x ln (VIN / (0.5 x LSB Value))
**==> picture [29 x 8] intentionally omitted <==**
where R = ZINAD + RSOURCE and C = CINAD. Calculate the value of STC by using EQ 19.
tSAMPLE = (2 + STC) x (1 / ADCCLK) or tSAMPLE = (2 + STC) x (ADC Clock Period)
_EQ 19_
where ADCCLK = ADC clock frequency in MHz.
tSAMPLE = 0.449 µs from bit resolution in Table 2-44. ADC Clock frequency = 10 MHz or a 100 ns period. STC = (tSAMPLE / (1 / 10 MHz)) – 2 = 4.49 – 2 = 2.49.
You must round up to 3 to accommodate the minimum sample time.
_**Table 2-44 •**_ **Acquisition Time Example with VAREF = 2.56 V**
||**VIN = 2.56V, R = 4K (RSOURCE ~ 0), C = 18 pF**|**VIN = 2.56V, R = 4K (RSOURCE ~ 0), C = 18 pF**|
|---|---|---|
|**Resolution**|**LSB Value (mV)**|**Min. Sample/Hold Time for 0.5 LSB (µs)**|
|8|10|0.449|
|10|2.5|0.549|
|12|0.625|0.649|
|**_Table 2-45 •_Acquisition Time Example with VAREF = 3.3 V**|||
||**VIN = 3.3V, R = 4K (RSOURCE ~ 0), C = 18 pF**||
|**Resolution**|**LSB Value (mV)**|**Min. Sample/Hold time for 0.5 LSB (µs)**|
|8|12.891|0.449|
|10|3.223|0.549|
|12|0.806|0.649|
_**Table 2-45 •**_ **Acquisition Time Example with VAREF = 3.3 V**
## _**Sample Phase**_
A conversion is performed in three phases. In the first phase, the analog input voltage is sampled on the input capacitor. This phase is called sample phase. During the sample phase, the output signals BUSY and SAMPLE change from '0' to '1', indicating the ADC is busy and sampling the analog signal. The sample time can be controlled by input signals STC[7:0]. The sample time can be calculated by EQ 20. When controlling the sample time for the ADC along with the use of Prescaler or Current Monitor or Temperature Monitor, the minimum sample time for each must be obeyed.
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Refer to Table 2-46 on page 2-109 and the "Acquisition Time or Sample Time Control" section on page 2-107
tsample = 2 + STC tADCCLK
_EQ 20_
STC: Sample Time Control value (0–255)
tSAMPLE is the sample time
## _**Table 2-46 •**_ **STC Bits Function**
**==> picture [344 x 23] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||
|---|---|---|
|Name|Bits|Function|
|STC|[7:0]|Sample time control|
**----- End of picture text -----**<br>
Sample time is computed based on the period of ADCCLK.
## _**Distribution Phase**_
The second phase is called the distribution phase. During distribution phase, the ADC computes the equivalent digital value from the value stored in the input capacitor. In this phase, the output signal SAMPLE goes back to '0', indicating the sample is completed; but the BUSY signal remains '1', indicating the ADC is still busy for distribution. The distribution time depends strictly on the number of bits. If the ADC is configured as a 10-bit ADC, then 10 ADCCLK cycles are needed. EQ 8 describes the distribution time.
tdistrib = N tADCCLK
_EQ 21_
## N: Number of bits
## _**Post-Calibration Phase**_
The last phase is the post-calibration phase. This is an optional phase. The post-calibration phase takes two ADCCLK cycles. The output BUSY signal will remain '1' until the post-calibration phase is completed. If the post-calibration phase is skipped, then the BUSY signal goes to '0' after distribution phase. As soon as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating the digital result is available on the RESULT output signals. DATAVAILD will remain '1' until the next ADCSTART is asserted. Microsemi recommends enabling post-calibration to compensate for drift and temperature-dependent effects. This ensures that the ADC remains consistent over time and with temperature. The post-calibration phase is enabled by bit 3 of the Mode register. EQ 9 describes the post-calibration time.
tpost-cal = MODE3 2 tADCCLK _EQ 22_
MODE[3]: Bit 3 of the Mode register, described in Table 2-41 on page 2-106.
The calculation for the conversion time for the ADC is summarized in EQ 23.
tconv = tsync_read + tsample + tdistrib + tpost-cal + tsync_write
_EQ 23_
## tconv: conversion time
tsync_read: maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the worst case is a period of SYSCLK, tSYSCLK.
tsample: Sample time
tdistrib: Distribution time
t : Post-calibration time post-cal
tsync_write: Maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the worst case is a period of SYSCLK, tSYSCLK.
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## _**Intra-Conversion**_
Performing a conversion during power-up calibration is possible but should be avoided, since the performance is not guaranteed, as shown in Table 2-49 on page 2-117. This is described as intra-conversion. Figure 2-92 on page 2-113 shows intra-conversion, (conversion that starts during power-up calibration).
## _**Injected Conversion**_
A conversion can be interrupted by another conversion. Before the current conversion is finished, a second conversion can be started by issuing a pulse on signal ADCSTART. When a second conversion is issued before the current conversion is completed, the current conversion would be dropped and the ADC would start the second conversion on the rising edge of the SYSCLK. This is known as injected conversion. Since the ADC is synchronous, the minimum time to issue a second conversion is two clock cycles of SYSCLK after the previous one. Figure 2-93 on page 2-113 shows injected conversion, (conversion that starts before a previously started conversion is finished). The total time for calibration still remains 3,840 ADCCLK cycles.
## _**ADC Example**_
This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit mode for a system that runs at 66 MHz. Assume the acquisition times defined in Table 2-44 on page 2-108 for 10-bit mode, which gives 0.549 µs as a minimum hold time.
The period of SYSCLK: tSYSCLK = 1/66 MHz = 0.015 µs
Choosing TVC between 1 and 33 will meet the maximum and minimum period for the ADCCLK requirement. A higher TVC leads to a higher ADCCLK period.
The minimum TVC is chosen so that tdistrib and tpost-cal can be run faster. The period of ADCCLK with a TVC of 1 can be computed by EQ 24.
tADCCLK = 4 1 + TVC tSYSCLK = 4 1 + 1 0.015 µs = 0.12 µs
_EQ 24_
The STC value can now be computed by using the minimum sample/hold time from Table 2-44 on page 2-108, as shown in EQ 25.
**==> picture [229 x 24] intentionally omitted <==**
_EQ 25_
You must round up to 3 to accommodate the minimum sample time requirement. The actual sample time, tsample, with an STC of 3, is now equal to 0.6 µs, as shown in EQ 26
**==> picture [299 x 12] intentionally omitted <==**
_EQ 26_
Microsemi recommends post-calibration for temperature drift over time, so post-calibration is enabled. The post-calibration time, tpost-cal, can be computed by EQ 27. The post-calibration time is 0.24 µs.
**==> picture [131 x 11] intentionally omitted <==**
**==> picture [29 x 9] intentionally omitted <==**
The distribution time, tdistrib, is equal to 1.2 µs and can be computed as shown in EQ 28 (N is number of bits, referring back to EQ 8 on page 2-94).
**==> picture [173 x 11] intentionally omitted <==**
_EQ 28_
The total conversion time can now be summated, as shown in EQ 29 (referring to EQ 23 on page 2-109).
tsync_read + tsample + tdistrib + tpost-cal + tsync_write = (0.015 + 0.60 + 1.2 + 0.24 + 0.015) µs = 2.07 µs
_EQ 29_
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The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is shown in Table 2-47:
_**Table 2-47 •**_ **Optimal Setting at 66 MHz in 10-Bit Mode**
|TVC[7:0]|= 1|= 1|= 0x01|= 0x01|
|---|---|---|---|---|
|STC[7:0]|= 3|= 3|= 0x03|= 0x03|
|MODE[3:0]|= b'0100|= b'0100|= 0x4*|= 0x4*|
_Note:_ No power-down after every conversion is chosen in this case; however, if the application is power-sensitive, the MODE[2] can be set to '0', as described above, and it will not affect any performance.
## _**Timing Diagrams**_
**==> picture [360 x 147] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCAL = 3,840 tADCCLK*<br>SYSCLK<br>tRECCLR tREMCLR<br>ADCRESET<br>tSUTVC tHDTVC<br>TVC[7:0]<br>t t<br>CK2QCAL CK2QCAL<br>CALIBRATE<br>**----- End of picture text -----**<br>
_Note: *Refer to EQ 15 on page 2-107 for the calculation on the period of ADCCLK, tADCCLK._
_**Figure 2-89 •**_ **Power-Up Calibration Status Signal Timing Diagram**
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**==> picture [334 x 273] intentionally omitted <==**
**----- Start of picture text -----**<br>
tMINSYSCLK tMPWSYSCLK<br>SYSCLK<br>tSUADCSTART tHDADCSTART<br>ADCSTART<br>tSUMODE tHDMODE<br>MODE[3:0]<br>eS Se ee,<br>tSUTVC tHDTVC<br>TVC[7:0] a a a<br>tSUSTC tHDSTC<br>STC[7:0] D<br>tSUVAREFSEL tHDVAREFSEL<br>VAREF<br>tSUCHNUM tHDCHNUM<br>CHNUMBER[7:0]<br>**----- End of picture text -----**<br>
_**Figure 2-90 •**_ **Input Setup Time**
_**Standard Conversion**_
**==> picture [411 x 198] intentionally omitted <==**
**----- Start of picture text -----**<br>
t SAMPLE1 t DATA2START [3]<br>SYSCLK p l<br>t SUADCSTART t HDADCSTART<br>ADCSTART<br>t CK2QBUSY<br>BUSY<br>t CK2QSAMPLE<br>SAMPLE<br>t CONV [2] t CK2QVAL t CK2QVAL<br>DATAVALID<br>x t CLK2RESULT<br>ADC_RESULT[11:0] 1 [st] Sample Result<br>2 [nd] Sample Result<br>**----- End of picture text -----**<br>
_Notes:_
_1. Refer to EQ 20 on page 2-109 for the calculation on the sample time, tSAMPLE. 2. See EQ 23 on page 2-109 for calculation of the conversion time, tCONV._
_3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period_
_**Figure 2-91 •**_ **Standard Conversion Status Signal Timing Diagram**
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## _**Intra-Conversion**_
**==> picture [451 x 227] intentionally omitted <==**
**----- Start of picture text -----**<br>
SYSCLK<br>ADCRESET<br>ADCSTART<br>ee<br>t<br>CK2QBUSY<br>BUSY<br>a<br>t t<br>CK2QSAMPLE CK2QSAMPLE<br>SAMPLE<br>ee tCLR2QVAL tCONV* tCK2QVAL<br>DATAVALID<br>S e a<br>tCK2QCAL tCK2QCAL<br>CALIBRATE<br>~ ~<br>Interrupts Power-Up Calibration Resumes Power-Up Calibration<br>**----- End of picture text -----**<br>
_Note: *tCONV represents the conversion time of the second conversion. See EQ 23 on page 2-109 for calculation of the conversion time, tCONV._
_**Figure 2-92 •**_ **Intra-Conversion Timing Diagram**
## _**Injected Conversion**_
**==> picture [416 x 149] intentionally omitted <==**
**----- Start of picture text -----**<br>
SYSCLK<br>1st Start 2nd Start<br>ADCSTART<br>t<br>1st Conversion CK2QBUSY<br>BUSY<br>1st Conversion Cancelled,<br>t t<br>CK2QSAMPLE 2nd Conversion CK2QSAMPLE<br>SAMPLE —<br>i<br>tCK2QVAL tCONV* tCK2QVAL<br>DATAVALID<br>**----- End of picture text -----**<br>
_Note: *See EQ 23 on page 2-109 for calculation on the conversion time, tCONV._ _**Figure 2-93 •**_ **Injected Conversion Timing Diagram**
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## _**ADC Interface Timing**_
_**Table 2-48 •**_ **ADC Interface Timing**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~Rs~~<br>~~es~~|**Description**<br>~~Rs~~|**–2**<br>~~Rs~~|**–1**<br>~~Rs~~|**Std.**<br>~~Rs~~|**Units**<br>~~Rs~~|
|---|---|---|---|---|---|
|tSUMODE<br>~~es~~|Mode Pin Setup Time|0.56|0.64|0.75|ns|
|tHDMODE<br>~~es~~<br>~~Rs~~|Mode Pin Hold Time<br>~~Rs~~|0.26<br>~~Rs~~|0.29<br>~~Rs~~|0.34<br>~~Rs~~|ns<br>~~Rs~~|
|tSUTVC<br>~~a~~|Clock Divide Control (TVC) Setup Time<br>|0.68<br>|0.77<br>|0.90<br>|ns<br>|
|tHDTVC<br>~~Rs~~<br>~~es~~|Clock Divide Control (TVC) Hold Time<br>~~Rs~~|0.32<br>~~Rs~~|0.36<br>~~Rs~~|0.43<br>~~Rs~~|ns<br>~~Rs~~|
|tSUSTC<br>~~es~~|Sample Time Control (STC) Setup Time|1.58|1.79|2.11|ns|
|tHDSTC<br>~~es~~<br>~~Rs~~<br>~~es~~|Sample Time Control (STC) Hold Time<br>~~Rs~~|1.27<br>~~Rs~~|1.45<br>~~Rs~~|1.71<br>~~Rs~~|ns<br>~~Rs~~|
|tSUVAREFSEL<br>~~es~~|Voltage Reference Select (VAREFSEL) Setup Time|0.00|0.00|0.00|ns|
|tHDVAREFSEL<br>~~es~~<br>~~Rs~~|Voltage Reference Select (VAREFSEL) Hold Time<br>~~Rs~~|0.67<br>~~Rs~~|0.76<br>~~Rs~~|0.89<br>~~Rs~~|ns<br>~~Rs~~|
|tSUCHNUM<br>~~a~~|Channel Select (CHNUMBER) Setup Time<br>|0.90<br>|1.03<br>|1.21<br>|ns<br>|
|tHDCHNUM<br>~~Rs~~|Channel Select (CHNUMBER) Hold Time<br>~~Rs~~|0.00<br>~~Rs~~|0.00<br>~~Rs~~|0.00<br>~~Rs~~|ns<br>~~Rs~~|
|tSUADCSTART<br>~~a~~|Start of Conversion (ADCSTART) Setup Time<br>|0.75<br>|0.85<br>|1.00<br>|ns<br>|
|tHDADCSTART<br>~~se~~|Start of Conversion (ADCSTART) Hold Time<br>~~se~~|0.43<br>~~se~~|0.49<br>~~se~~|0.57<br>~~se~~|ns<br>~~se~~|
|tCK2QBUSY<br>~~a~~|Busy Clock-to-Q<br>|1.33<br>|1.51<br>|1.78<br>|ns<br>|
|tCK2QCAL<br>~~se~~|Power-Up Calibration Clock-to-Q<br>~~se~~|0.63<br>~~se~~|0.71<br>~~se~~|0.84<br>~~se~~|ns<br>~~se~~|
|tCK2QVAL<br>~~a~~|Valid Conversion Result Clock-to-Q<br>|3.12<br>|3.55<br>|4.17<br>|ns<br>|
|tCK2QSAMPLE<br>~~se~~|Sample Clock-to-Q<br>~~se~~|0.22<br>~~se~~|0.25<br>~~se~~|0.30<br>~~se~~|ns<br>~~se~~|
|tCK2QRESULT<br>~~a~~|Conversion Result Clock-to-Q<br>|2.53<br>|2.89<br>|3.39<br>|ns<br>|
|tCLR2QBUSY<br>~~Rs~~|Busy Clear-to-Q<br>~~Rs~~|2.06<br>~~Rs~~|2.35<br>~~Rs~~|2.76<br>~~Rs~~|ns<br>~~Rs~~|
|tCLR2QCAL<br>~~a~~|Power-Up Calibration Clear-to-Q<br>~~a~~|2.15<br>~~a~~|2.45<br>~~a~~|2.88<br>~~a~~|ns<br>~~a~~|
|tCLR2QVAL<br>~~Rs~~|Valid Conversion Result Clear-to-Q<br>~~Rs~~|2.41<br>~~Rs~~|2.74<br>~~Rs~~|3.22<br>~~Rs~~|ns<br>~~Rs~~|
|tCLR2QSAMPLE<br>~~a~~|Sample Clear-to-Q<br>~~a~~|2.17<br>~~a~~|2.48<br>~~a~~|2.91<br>~~a~~|ns<br>~~a~~|
|tCLR2QRESULT<br>~~Rs~~|Conversion result Clear-to-Q<br>~~Rs~~|2.25<br>~~Rs~~|2.56<br>~~Rs~~|3.01<br>~~Rs~~|ns<br>~~Rs~~|
|tRECCLR<br>~~a~~|Recovery Time of Clear<br>~~a~~|0.00<br>~~a~~|0.00<br>~~a~~|0.00<br>~~a~~|ns<br>~~a~~|
|tREMCLR<br>~~Rs~~|Removal Time of Clear<br>~~Rs~~|0.63<br>~~Rs~~|0.72<br>~~Rs~~|0.84<br>~~Rs~~|ns<br>~~Rs~~|
|tMPWSYSCLK<br>~~a~~|Clock Minimum Pulse Width for the ADC<br>~~a~~|4.00<br>~~a~~|4.00<br>~~a~~|4.00<br>~~a~~|ns<br>~~a~~|
|tFMAXSYSCLK<br>~~se~~|Clock Maximum Frequency for the ADC<br>~~se~~|100.00<br>~~se~~|100.00<br>~~se~~|100.00<br>~~se~~|MHz<br>~~se~~|
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## **Typical Performance Characteristics**
**==> picture [245 x 168] intentionally omitted <==**
**----- Start of picture text -----**<br>
Temperature Errror vs. Die Temperature<br>3.5<br>3<br>2.5<br>2<br>1.5<br>1<br>0.5<br>0<br>–40 10 60 110<br>Temperature (°C)<br>Temperature Error (°C)<br>**----- End of picture text -----**<br>
_**Figure 2-94 •**_ **Temperature Error**
**==> picture [306 x 197] intentionally omitted <==**
**----- Start of picture text -----**<br>
Temperature Error vs. Interconnect Capacitance<br>1<br>0<br>-1<br>-2<br>-3<br>-4<br>-5<br>-6<br>-7<br>0 500 1000 1500 2000<br>Capacitance (pF)<br>Temperature Error (°C)<br>**----- End of picture text -----**<br>
_**Figure 2-95 •**_ **Effect of External Sensor Capacitance**
**2-115**
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**==> picture [294 x 195] intentionally omitted <==**
**----- Start of picture text -----**<br>
Temperature Reading Noise RMS vs. Averaging<br>1 2<br>1 0<br>8<br>6<br>4<br>2<br>0<br>1 10 100 1000 10000<br>Number of Averages<br>Noise RMS (°C)<br>**----- End of picture text -----**<br>
_**Figure 2-96 •**_ **Temperature Reading Noise When Averaging is Used**
**Revision 8**
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_Device Architecture_
## **Analog System Characteristics**
## _**Table 2-49 •**_ **Analog Channel Specifications**
**Commercial Temperature Range Conditions, TJ = 85°C (unless noted otherwise), Typical: VCC33A = 3.3 V, VCC = 1.5 V**
|**Parameter**<br>~~es~~|**Description**<br>~~rs~~|**Condition**<br>~~Pe~~|**Min.**<br>~~tn~~|**Typ.**<br>~~ts~~|**Max.**|**Units**|
|---|---|---|---|---|---|---|
|**Voltage Monitor Using Analog Pads AV, AC and AT (using prescaler)**<br>~~es~~<br>~~rsPe~~<br>~~tn ts~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|||||||
|~~ee~~<br>~~ee~~|Input Voltage<br>(Prescaler)<br>~~ee~~<br>~~ee~~|Refer toTable 3-2 on page 3-3<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|||
|VINAP<br>~~ee~~<br>~~ee~~<br>~~a~~|Uncalibrated Gain and<br>Offset Errors<br>~~ee~~<br>~~ee~~<br>~~ee~~|Refer toTable 2-51 on<br>page 2-122<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~|~~ee~~|
|~~ee~~<br>~~a~~<br>~~es~~|Calibrated Gain and<br>Offset Errors<br>~~ee~~<br>~~ee~~<br>~~rs te~~|Refer toTable 2-52 on<br>page 2-123<br>~~ee~~<br>~~ee~~<br>~~te~~|~~ee~~<br>~~ee~~<br>~~ts~~|~~ee~~<br>~~ee~~<br>~~ts~~|~~ee~~|~~ee~~|
|~~a~~<br>~~es~~<br>~~es~~|Bandwidth1<br>~~ee~~<br>~~rs te~~<br>~~rs te~~|~~ee~~<br>~~te~~<br>~~te~~|~~ee~~<br>~~ts~~<br>~~ts~~|~~ee~~<br>~~ts~~<br>~~ts~~|100<br>~~ee~~|KHz<br>~~ee~~|
|~~es~~<br>~~es~~<br>~~a~~|Input Resistance<br>~~rs te~~<br>~~rs te~~<br>~~ee~~|Refer toTable 3-3 on page 3-4<br>~~te~~<br>~~te~~<br>~~ee~~|~~ts ~~<br>~~ts~~<br>~~eee~~|~~ts~~<br>~~ts~~<br>~~eee~~|~~eee~~|~~eee~~|
|~~es~~<br>~~a~~<br>~~es~~|Scaling Factor<br>~~rs te~~<br>~~ee~~<br>~~rs~~|Prescaler modes (Table 2-57 on<br>page 2-130)<br>~~te~~<br>~~ee~~<br>~~Pn~~|~~ts ~~<br>~~eee~~<br>~~ts~~|~~ts~~<br>~~eee~~<br>~~ts~~|~~eee~~|~~eee~~|
|~~a~~<br>~~es~~|Sample Time<br>~~ee~~<br>~~rs~~|~~ee ~~<br>~~Pn~~|10<br> ~~eee~~<br>~~ts~~|~~eee~~<br>~~ts~~|~~eee~~|µs<br>~~eee~~|
|**Current Monitor Using Analog Pads AV and AC**<br>~~es~~<br>~~rsPn~~<br>~~ts ts~~<br>~~eee~~<br>~~ee~~|||||||
|VRSM1<br>~~eee~~<br>~~ee~~<br>~~es~~|Maximum Differential<br>Input Voltage<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|VAREF / 10<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|mV<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|~~ee~~<br>~~es~~<br>~~ee~~|Resolution<br>~~ee~~<br>~~rs~~|Refer to"Current Monitor"<br>section<br>~~ee~~<br>~~ee~~<br>~~Pe~~|~~ee~~<br>~~eee~~<br>~~ts~~|~~ee~~<br>~~eee~~<br>~~ts~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|
|~~es~~<br>~~ee~~<br>~~es~~|Common Mode Range<br>~~rs~~<br>~~ee~~|~~ee~~<br>~~Pe~~<br>~~ee~~|~~eee~~<br>~~ts~~<br>~~ee~~|~~eee~~<br>~~ts~~<br>~~ee~~|– 10.5 to +12<br>~~eee~~|V<br>~~eee~~|
|CMRR<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|Common Mode<br>Rejection Ratio<br>~~rs~~<br>~~ee~~<br>~~rs~~<br>|DC – 1 KHz<br>~~ee ~~<br>~~Pe~~<br>~~ee~~<br>~~Pe~~|~~eee~~<br>~~ts~~<br>~~ee~~<br>~~ts~~|60<br>~~eee~~<br>~~ts~~<br>~~ee~~<br>~~ts~~|~~eee~~|dB<br>~~eee~~|
|~~ee~~<br>~~es~~<br>~~es~~<br>~~es~~|~~rs~~<br>~~ee~~<br>~~rs~~<br>~~ee~~|1 KHz - 10 KHz<br>~~Pe~~<br>~~ee~~<br>~~Pe~~|~~ts~~<br>~~ee~~<br>~~ts~~|50<br>~~ts~~<br>~~ee~~<br>~~ts~~||dB|
|~~es~~<br>~~es~~<br>~~es~~|~~ee~~<br>~~rs~~<br>~~ee~~|> 10 KHz<br>~~ee ~~<br>~~Pe~~|~~ee~~<br>~~ts~~|30<br>~~ee~~<br>~~ts~~||dB|
|tCMSHI<br>~~es~~<br>~~es~~<br>~~fe~~|Strobe High time<br>~~rs~~<br>~~ee~~<br>~~rs~~<br>|~~Pe~~<br>~~te~~|ADC<br>conv.<br>time<br>~~ts~~<br>~~ts~~|~~ts~~<br>~~ts~~|200|µs|
|tCMSHI<br>~~es ~~<br>~~es~~<br>~~fe~~|Strobe Low time<br>~~rs~~<br> ~~ee~~<br>~~rs~~<br>~~ee~~|~~Pe~~<br>~~te~~|5<br>~~ts~~<br>~~ts~~|~~ts~~<br>~~ts~~||µs|
|tCMSHI<br> <br>~~es~~<br>~~fe~~|Settling time<br> ~~ee~~<br>~~rs~~<br>~~ee~~|~~te~~|0.02<br>~~ts~~|~~ts~~||µs|
|~~fe~~|Accuracy<br>~~rs~~<br>~~ee~~|Input differential voltage > 50 mV<br>~~te~~|~~ts~~|~~ts~~|–2 –(0.05 x<br>VRSM) to +2 +<br>(0.05 x VRSM)|mV|
_1. VRSM is the maximum voltage drop across the current sense resistor._
_2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no reliability concern on digital inputs as long as VIND does not exceed these limits._
_3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency._
_4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance allowed across the AT pins is 500 pF._
_5. The temperature offset is a fixed positive value._
_6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad._
_7. When using SmartGen Analog System Builder, CalibIP is required to obtain specified offset. For further details on CalibIP, refer to the “Temperature, Voltage, and Current Calibration in Fusion FPGAs” chapter of the_ Fusion FPGA Fabric User Guide.
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## _**Table 2-49 •**_ **Analog Channel Specifications (continued)**
**Commercial Temperature Range Conditions, TJ = 85°C (unless noted otherwise), Typical: VCC33A = 3.3 V, VCC = 1.5 V**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Condition**<br>~~Ge~~|**Min.**|**Typ.**|**Max.**|**Units**|
|---|---|---|---|---|---|---|
|**Temperature Monitor Using Analog Pad AT**<br>~~eeeeGe~~<br>~~Ce~~<br>~~———S~~|||||||
|External<br>Temperature<br>Monitor<br>(external diode<br>2N3904,<br>TJ= 25°C)4|Resolution<br>~~———S~~|8-bit ADC<br>~~a~~<br>~~———S~~|4|||°C|
|||10-bit ADC<br>~~a~~<br>~~———S~~|1|||°C|
|||12-bit ADC<br>~~———S~~<br>~~ee~~|0.25<br>~~ee~~|||°C<br>~~ee~~|
||Systematic Offset5<br>~~———S~~|AFS090, AFS250, AFS600,<br>AFS1500, uncalibrated7<br>~~———S~~<br>~~ee~~|5<br>~~ee~~|||°C<br>~~ee~~|
|||AFS090, AFS250, AFS600,<br>AFS1500, calibrated7|±5|||°C|
||Accuracy<br>~~rs~~|~~rs~~|~~rs~~|±3<br>~~rs~~|±5<br>~~rs~~|°C<br>~~rs~~|
||External Sensor Source<br>Current<br>~~eee~~|High level, TMSTBx = 0<br>~~eee~~<br>~~ee ee~~|~~eee~~<br>~~ee~~|10<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|µA<br>~~eee~~|
|||Low level, TMSTBx = 1<br>~~eee~~<br>~~ee ee~~|~~eee~~<br>~~ee~~|100<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|µA<br>~~eee~~|
||Max Capacitance on AT<br>pad|~~ee ee~~|~~ee~~|~~ee~~|1.3<br>~~ee~~|nF|
|Internal<br>Temperature<br>Monitor<br>~~eo~~<br>~~De~~|Resolution<br>~~eee~~|8-bit ADC<br>~~ee ee~~<br>~~es~~|4<br>~~ee~~<br>~~es~~|~~ee~~<br>~~es~~|~~ee~~<br>~~es~~|°C<br>~~es~~|
|||10-bit ADC<br>~~ee~~|1<br>~~ee~~|~~ee~~|~~ee~~|°C<br>~~ee~~|
|||12-bit ADC<br>~~es~~<br>~~eee~~|0.25<br>~~es~~<br>~~eee~~|~~es~~<br>~~eee~~|~~es~~<br>~~eee~~|°C<br>~~es~~<br>~~eee~~|
||Systematic Offset5<br>~~eee~~<br>~~eo~~|AFS0907<br>~~eee~~|5<br>~~eee~~|||°C<br>~~eee~~|
|||AFS250, AFS600, AFS15007<br>~~eee~~<br>~~ee~~|11<br>~~eee~~<br>~~ee~~|||°C<br>~~eee~~<br>~~ee~~|
||Accuracy<br>~~eee~~<br>~~eo~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|±3<br>~~eee~~<br>~~ee~~|±5<br>~~eee~~<br>~~ee~~|°C<br>~~eee~~<br>~~ee~~|
|tTMSHI<br>~~eo~~<br>~~De~~<br>~~De~~|Strobe High time<br>~~eo~~|~~ee~~|10<br>~~ee~~|~~ee~~|105<br>~~ee~~|µs<br>~~ee~~|
|tTMSLO<br>~~eo~~<br>~~De~~<br>~~De~~<br>~~De~~|Strobe Low time<br>~~eo~~|~~ee~~|5<br>~~ee~~|~~ee~~|~~ee~~|µs<br>~~ee~~|
|tTMSSET<br>~~De~~<br>~~De~~|Settling time||5|||µs|
_1. VRSM is the maximum voltage drop across the current sense resistor._
_2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no reliability concern on digital inputs as long as VIND does not exceed these limits._
_3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency._
_4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance allowed across the AT pins is 500 pF._
_5. The temperature offset is a fixed positive value._
_6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad._
_7. When using SmartGen Analog System Builder, CalibIP is required to obtain specified offset. For further details on CalibIP, refer to the “Temperature, Voltage, and Current Calibration in Fusion FPGAs” chapter of the_ Fusion FPGA Fabric User Guide.
**Revision 8**
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_**Table 2-49 •**_ **Analog Channel Specifications (continued)**
**Commercial Temperature Range Conditions, TJ = 85°C (unless noted otherwise), Typical: VCC33A = 3.3 V, VCC = 1.5 V**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Condition**<br>~~ee~~|**Min.**<br>~~ee~~|**Typ.**<br>~~ee~~|**Max.**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|
|**Digital Input using Analog Pads AV, AC and AT**<br>~~Ce~~<br>~~es~~|||||||
|VIND2,3<br>~~es~~<br>~~Rs~~|Input Voltage|Refer toTable 3-2 on page 3-3|||||
|VHYSDIN<br>~~es~~<br>~~Rs~~<br>~~Rs~~|Hysteresis|||0.3||V|
|VIHDIN<br>~~Rs~~<br>~~Rs~~<br>~~Rs~~|Input High|||1.2||V|
|VILDIN<br>~~Rs~~<br>~~Rs~~<br>~~Rs~~|Input Low|||0.9||V|
|VMPWDIN<br>~~Rs~~<br>~~Rs~~<br>~~Rs~~|Minimum Pulse With||50|||ns|
|FDIN<br>~~Rs~~<br>~~Rs~~<br>~~Rs~~|Maximum Frequency||||10|MHz|
|ISTBDIN<br>~~Rs~~<br>~~Rs~~<br>~~Rs~~|Input Leakage Current|||2||µA|
|IDYNDIN<br>~~Rs~~<br>~~Rs~~|Dynamic Current|||20||µA|
|tINDIN<br>~~Rs~~<br>~~se~~|Input Delay<br>~~se~~|~~se~~|~~se~~|10<br>~~se~~|~~se~~|ns<br>~~se~~|
|**Gate Driver Output Using Analog Pad AG**<br>~~se~~<br>~~Ce~~|||||||
|VG<br>~~Ce~~<br>~~se~~<br>~~Rs~~|Voltage Range<br>~~Ce~~<br>~~se~~|Refer toTable 3-2 on page 3-3<br>~~Ce~~<br>~~se~~|~~Ce~~<br>~~se~~|~~Ce~~<br>~~se~~|~~Ce~~<br>~~se~~|~~Ce~~<br>~~se~~|
|IG<br>~~se~~<br>~~Rs~~<br>~~Rs~~|Output Current Drive<br>~~se~~|High Current Mode6at 1.0 V<br>~~se~~|~~se~~|~~se~~|±20<br>~~se~~|mA<br>~~se~~|
|~~Rs~~<br>~~Rs~~<br>~~Rs~~||Low Current Mode: ±1 µA|0.8|1.0|1.3|µA|
|~~Rs~~<br>~~Rs~~<br>~~Rs~~||Low Current Mode: ±3 µA|2.0|2.7|3.3|µA|
|~~Rs~~<br>~~Rs~~<br>~~Rs~~||Low Current Mode: ± 10 µA|7.4|9.0|11.5|µA|
|~~Rs~~<br>~~Rs~~<br>~~Rs~~||Low Current Mode: ± 30 µA|21.0|27.0|32.0|µA|
|IOFFG<br>~~Rs~~<br>~~Rs~~<br>~~a~~|Maximum Off Current<br>~~ee~~|~~ee~~|~~ee~~||100|nA|
|FG<br>~~Rs~~<br>~~a~~<br>~~a~~|Maximum switching rate <br>~~ee~~<br>~~ee~~|High Current Mode6at 1.0 V, 1<br>kresistive load<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|1.3||MHz|
|~~a~~<br>~~a~~|~~ee~~<br>~~ee~~|Low Current Mode:<br>±1 µA, 3 Mresistive load<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|3||KHz|
|~~a~~<br>~~a ~~|~~ee~~<br> ~~a ~~|Low Current Mode:<br>±3 µA, 1 Mresistive load<br>~~ee~~<br> ~~ee~~|~~ee~~<br>~~ee~~|7<br>~~ee~~|~~ee~~|KHz<br>~~ee~~|
|~~a~~<br>~~a~~|~~ee~~|Low Current Mode:<br>±10 µA, 300 kresistive load<br>~~ee~~<br>~~ee ee~~|~~ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|KHz<br>~~ee~~<br>~~ee~~|
|~~a~~||Low Current Mode:<br>±30 µA, 105 kresistive load<br>~~ee ee~~|~~ee~~|78<br>~~ee~~|~~ee~~|KHz<br>~~ee~~|
_1. VRSM is the maximum voltage drop across the current sense resistor._
_2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no reliability concern on digital inputs as long as VIND does not exceed these limits._
_3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency._
_4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance allowed across the AT pins is 500 pF._
_5. The temperature offset is a fixed positive value._
_6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad._
_7. When using SmartGen Analog System Builder, CalibIP is required to obtain specified offset. For further details on CalibIP, refer to the “Temperature, Voltage, and Current Calibration in Fusion FPGAs” chapter of the_ Fusion FPGA Fabric User Guide.
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_**Table 2-50 •**_ **ADC Characteristics in Direct Input Mode**
**Commercial Temperature Range Conditions, TJ = 85°C (unless noted otherwise), Typical: VCC33A = 3.3 V, VCC = 1.5 V**
|~~ee~~|||||||
|---|---|---|---|---|---|---|
|**Parameter**<br>~~ee~~|**Description**<br>|**Condition**<br>|**Min.**<br>|**Typ.**<br>|**Max.**<br>|**Units**<br>|
|**Direct Input using Analog Pad AV, AC, AT**<br>~~eepn~~|||||||
|VINADC<br>~~i~~<br>||Input Voltage (Direct Input)<br>|Refer toTable 3-2 on<br>page 3-3<br>|~~ee~~<br>|~~ee~~<br>|||
|CINADC<br>||Input Capacitance<br>~~FARE~~|Channel not selected<br>~~ee~~<br>~~FARE~~|~~ee~~<br>~~ee~~<br>~~FARE~~|7<br>~~ee~~<br>~~ee~~<br>~~FARE~~|~~ee~~<br>~~FARE~~|pF<br>~~ee~~<br>~~FARE~~|
|||Channel selected but not<br>sampling<br>~~FARE~~<br>~~ee se~~|~~ee~~<br>~~FARE~~<br>~~se~~|8<br>~~ee~~<br>~~FARE~~<br>~~se~~|~~FARE~~<br>~~se~~|pF<br>~~FARE~~|
|||Channel selected and<br>sampling<br>~~FARE~~<br>~~ee se~~|~~ee ~~<br>~~FARE~~<br>~~se~~|18<br> ~~ee~~<br>~~FARE~~<br>~~se~~|~~FARE~~<br>~~se~~|pF<br>~~FARE~~|
|ZINADC<br>~~Bf~~|Input Impedance<br>~~Bf~~|8-bit mode<br>~~ee se~~<br>~~**ee**~~|~~se~~<br>~~**ee**~~|2<br>~~se~~<br>~~**ee**~~|~~se~~<br>~~**ee**~~|k<br>~~**ee**~~|
|||10-bit mode<br>~~ee se~~<br>~~**ee**~~<br>~~eee~~|~~se~~<br>~~**ee**~~<br>~~eee~~|2<br>~~se~~<br>~~**ee**~~<br>~~eee~~|~~se~~<br>~~**ee**~~<br>~~eee~~|k<br>~~**ee**~~<br>~~eee~~|
|||12-bit mode<br>~~**ee**~~|~~**ee**~~|2<br>~~**ee**~~|~~**ee**~~|k<br>~~**ee**~~|
|**Analog Reference Voltage VAREF**<br>~~pT~~<br>~~ee~~<br>~~a~~|||||||
|VAREF<br>~~eee~~|Accuracy<br>~~es~~<br>~~eee~~<br>~~a~~|TJ= 25°C<br>~~es~~<br>~~eee~~<br>~~ee~~|2.537<br>~~es~~<br>~~eee~~<br>~~ee~~|2.56<br>~~es~~<br>~~eee~~<br>~~ee~~|2.583<br>~~es~~<br>~~eee~~|V<br>~~es~~<br>~~eee~~|
||Temperature Drift of<br>Internal Reference<br>~~eee~~<br>~~a~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|65<br>~~eee~~<br>~~ee~~|~~eee~~|ppm / °C<br>~~eee~~|
||External Reference<br>~~eee~~<br>~~a~~|~~eee~~<br>~~ee~~|2.527<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|VCC33A + 0.05<br>~~eee~~|V<br>~~eee~~|
|**ADC Accuracy (using external reference)1,2**<br>~~ee~~<br>~~a~~<br>~~pT~~|||||||
|**DC Accuracy**<br>~~a~~|||~~a~~|~~a~~|~~a~~|~~a~~|
|TUE<br>~~Se~~|Total Unadjusted Error<br>~~ee~~<br>~~Se~~|8-bit mode<br>~~ee~~<br>~~Se~~|0.29<br>~~ee~~<br>~~Se~~|||LSB<br>~~ee~~<br>~~Se~~|
||~~ee~~<br>~~Se~~|10-bit mode<br>~~ee~~<br>~~Se~~|0.72<br>~~ee~~<br>~~Se~~|||LSB<br>~~ee~~<br>~~Se~~|
||~~Se~~<br>~~ee~~|12-bit mode<br>~~Se~~<br>~~ee~~|1.8<br>~~Se~~<br>~~ee~~|||LSB<br>~~Se~~<br>~~ee~~|
|INL<br>~~SS~~|Integral Non-Linearity<br>~~ee~~<br>~~SS~~|8-bit mode<br>~~ee~~<br>~~SS~~|~~ee~~<br>~~SS~~|0.20<br>~~ee~~<br>~~SS~~|0.25<br>~~ee~~<br>~~SS~~|LSB<br>~~ee~~<br>~~SS~~|
||~~SS~~|10-bit mode<br>~~SS~~|~~SS~~|0.32<br>~~SS~~|0.43<br>~~SS~~|LSB<br>~~SS~~|
||~~SS~~<br>~~ee~~|12-bit mode<br>~~SS~~<br>~~ee~~|~~SS~~<br>~~ee~~|1.71<br>~~SS~~<br>~~ee~~|1.80<br>~~SS~~<br>~~ee~~|LSB<br>~~SS~~<br>~~ee~~|
|DNL<br>~~SS~~<br>~~eee~~<br>~~|~~|Differential Non-Linearity<br>(no missing code)<br>~~SS~~<br>~~ee~~<br>~~eee~~|8-bit mode<br>~~SS~~<br>~~ee~~<br>~~eee~~|~~SS~~<br>~~ee~~<br>~~eee~~|0.20<br>~~SS~~<br>~~ee~~<br>~~eee~~|0.24<br>~~SS~~<br>~~ee~~<br>~~eee~~|LSB<br>~~SS~~<br>~~ee~~<br>~~eee~~|
||~~eee~~<br>~~ee~~|10-bit mode<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|0.60<br>~~eee~~<br>~~ee~~|0.65<br>~~eee~~<br>~~ee~~|LSB<br>~~eee~~<br>~~ee~~|
||~~eee~~<br>~~ee~~<br>~~ee~~|12-bit mode<br>~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~ee~~|2.40<br>~~eee~~<br>~~ee~~<br>~~ee~~|2.48<br>~~eee~~<br>~~ee~~<br>~~ee~~|LSB<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|~~eee~~<br>~~|~~<br>~~=~~|Offset Error<br>~~eee~~<br>~~ee~~<br>~~=~~|8-bit mode<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~=~~|~~eee~~<br>~~ee~~<br>~~ee~~<br>~~=~~|0.01<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~=~~|0.17<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~=~~|LSB<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~=~~|
|~~|~~<br>~~=~~<br>~~|~~||10-bit mode<br>~~ee~~<br>~~ee~~<br>~~=~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~=~~<br>~~ee~~|0.05<br>~~ee~~<br>~~ee~~<br>~~=~~<br>~~ee~~|0.20<br>~~ee~~<br>~~ee~~<br>~~=~~<br>~~ee~~|LSB<br>~~ee~~<br>~~ee~~<br>~~=~~<br>~~ee~~|
|~~=~~<br>~~|~~<br>~~|~~||12-bit mode<br>~~=~~<br>~~ee~~<br>~~ee~~|~~=~~<br>~~ee~~<br>~~ee~~|0.20<br>~~=~~<br>~~ee~~<br>~~ee~~|0.40<br>~~=~~<br>~~ee~~<br>~~ee~~|LSB<br>~~=~~<br>~~ee~~<br>~~ee~~|
|~~=~~<br>~~|~~<br>~~|~~<br>~~=~~|Gain Error<br>~~=~~<br>~~=~~|8-bit mode<br>~~=~~<br>~~ee~~<br>~~ee~~<br>~~=~~|~~=~~<br>~~ee~~<br>~~ee~~<br>~~=~~|0.0004<br>~~=~~<br>~~ee~~<br>~~ee~~<br>~~=~~|0.003<br>~~=~~<br>~~ee~~<br>~~ee~~<br>~~=~~|LSB<br>~~=~~<br>~~ee~~<br>~~ee~~<br>~~=~~|
|~~|~~<br>~~=~~<br>~~|~~||10-bit mode<br>~~ee~~<br>~~=~~<br>~~ee~~|~~ee~~<br>~~=~~<br>~~ee~~|0.002<br>~~ee~~<br>~~=~~<br>~~ee~~|0.011<br>~~ee~~<br>~~=~~<br>~~ee~~|LSB<br>~~ee~~<br>~~=~~<br>~~ee~~|
|~~=~~<br>~~|~~||12-bit mode<br>~~=~~<br>~~ee~~|~~=~~<br>~~ee~~|0.007<br>~~=~~<br>~~ee~~|0.044<br>~~=~~<br>~~ee~~|LSB<br>~~=~~<br>~~ee~~|
|~~=~~<br>~~|~~<br>~~ee~~|Gain Error (with internal<br>reference)<br>~~=~~<br>~~ee~~|All modes<br>~~=~~<br>~~ee~~<br>~~ee~~|~~=~~<br>~~ee~~<br>~~ee~~|2<br>~~=~~<br>~~ee~~<br>~~ee~~|~~=~~<br>~~ee~~<br>~~ee~~|% FSR<br>~~=~~<br>~~ee~~<br>~~ee~~|
_1. Accuracy of the external reference is 2.56 V ± 4.6 mV._
_2. Data is based on characterization._
_3. The sample rate is time-shared among active analog inputs._
**Revision 8**
**2-120**
_Device Architecture_
_**Table 2-50 •**_ **ADC Characteristics in Direct Input Mode (continued) Commercial Temperature Range Conditions, TJ = 85°C (unless noted otherwise), Typical: VCC33A = 3.3 V, VCC = 1.5 V**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Condition**<br>~~ee~~<br>~~G~~|**Min.**<br>~~ee~~|**Typ.**<br>~~ee~~|**Max.**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|
|**Dynamic Performance**<br>~~G~~<br>~~Ge~~|||~~Ge~~|~~Ge~~|~~Ge~~|~~Ge~~|
|SNR<br>~~Ce~~<br>~~se~~|Signal-to-Noise Ratio<br>~~Ce~~<br>~~se~~|8-bit mode<br>~~GGG~~<br>~~GG~~|48.0<br>~~GGG~~<br>~~GG~~|49.5<br>~~GGG~~<br>~~Gs~~||dB|
|~~Ce~~<br>~~se~~<br>~~se~~|~~Ce~~<br>~~se~~<br>~~se~~|10-bit mode<br>~~GGG~~<br>~~GG~~<br>~~GG~~|58.0<br>~~GGG~~<br>~~GG~~<br>~~GG~~|60.0<br>~~GGG~~<br>~~Gs~~<br>~~Gs~~||dB|
|~~se~~<br>~~se~~<br>~~se~~|~~se~~<br>~~se~~<br>~~se~~|12-bit mode<br>~~GG~~<br>~~GG~~<br>~~GG~~|62.9<br>~~GG ~~<br>~~GG~~<br>~~GG~~|64.5<br> ~~Gs~~<br>~~Gs~~<br>~~Gs~~||dB|
|SINAD<br>~~se~~<br>~~se~~<br>~~se~~|Signal-to-Noise Distortion<br>~~se~~<br>~~se~~<br>~~se~~|8-bit mode<br>~~GG~~<br>~~GG~~<br>~~GG~~|47.6<br>~~GG ~~<br>~~GG~~<br>~~GG~~|49.5<br> ~~Gs~~<br>~~Gs~~<br>~~Gs~~||dB|
|~~se~~<br>~~se~~|~~se~~<br>~~se~~|10-bit mode<br>~~GG~~<br>~~GG~~|57.4<br>~~GG ~~<br>~~GG~~|59.8<br> ~~Gs~~<br>~~Gs~~||dB|
|~~se~~<br>~~a~~|~~se~~<br>~~ee~~|12-bit mode<br>~~GG~~<br>~~ee~~|62.0<br>~~GG ~~<br>~~ee~~|64.2<br> ~~Gs~~<br>~~ee~~|~~ee~~|dB<br>~~ee~~|
|THD<br>~~a~~|Total Harmonic<br>Distortion<br>~~ee~~|8-bit mode<br>~~ee~~|~~ee~~|–74.4<br>~~ee~~|–63.0<br>~~ee~~|dBc<br>~~ee~~|
|~~a~~<br>~~i~~|~~ee~~|10-bit mode<br>~~ee~~|~~ee~~|–78.3<br>~~ee ~~|–63.0<br> ~~ee~~|dBc<br>~~ee~~|
|~~i~~||12-bit mode||–77.9|–64.4|dBc|
|ENOB<br>~~i~~|Effective Number of Bits|8-bit mode|7.6|7.9||bits|
|~~i~~||10-bit mode<br>|9.5<br>|9.6<br>||bits<br>|
|~~ee~~|~~ee~~|12-bit mode<br>~~ee~~|10.0<br>~~ee~~|10.4<br>~~ee~~|~~ee~~|bits<br>~~ee~~|
|**Conversion Rate**<br>~~Oe~~|||~~Oe~~|~~Oe~~|~~Oe~~|~~Oe~~|
|~~GO~~|Conversion Time<br>~~GO~~|8-bit mode<br>~~GO~~|1.7<br>~~GO~~|~~GO~~|~~GO~~|µs<br>~~GO~~|
|~~i~~||10-bit mode|1.8|||µs|
|~~i~~||12-bit mode|2|||µs|
|~~i~~|Sample Rate|8-bit mode|||600|Ksps|
|~~i~~||10-bit mode<br>|||550<br>|Ksps<br>|
|~~ee~~|~~ee~~|12-bit mode<br>~~ee~~|~~ee~~|~~ee~~|500<br>~~ee~~|Ksps<br>~~ee~~|
## _Notes:_
_1. Accuracy of the external reference is 2.56 V ± 4.6 mV._
_2. Data is based on characterization._
_3. The sample rate is time-shared among active analog inputs._
**2-121**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-51 •**_ **Uncalibrated Analog Channel Accuracy* Worst-Case Industrial Conditions, TJ = 85°C**
|||**Total Channel**<br>**Error (LSB)**|**Total Channel**<br>**Error (LSB)**|**Total Channel**<br>**Error (LSB)**|**Channel Input Offset**<br>**Error (LSB)**|**Channel Input Offset**<br>**Error (LSB)**|**Channel Input Offset**<br>**Error (LSB)**|**Channel Input Offset**<br>**Error (mV)**|**Channel Input Offset**<br>**Error (mV)**|**Channel Input Offset**<br>**Error (mV)**|**Channel Gain Error**<br>**(%FSR)**|**Channel Gain Error**<br>**(%FSR)**|**Channel Gain Error**<br>**(%FSR)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Analog**<br>**Pad**|**Prescaler**<br>**Range (V)**|**Neg.**<br>**Max.**|**Med.**|**Pos.**<br>**Max.**|**Neg**<br>**Max**|**Med.**|**Pos.**<br>**Max.**|**Neg.**<br>**Max.**|**Med.**|**Pos.**<br>**Max.**|**Min.**|**Typ.**|**Max.**|
|**Positive Range**<br>~~Re~~<br>~~a~~||**ADC in 10-Bit Mode**<br>~~Re~~<br>~~eeeeee~~<br>~~eeee~~||||||||||||
|AV, AC|16<br>~~a~~<br>~~es~~|–22<br>~~ee~~<br>~~ee~~|–2<br>~~ee~~<br>~~ee~~|12<br>~~ee~~<br>~~ee~~|–11<br>~~ee~~<br>~~ee~~|–2<br>~~ee~~<br>~~ee~~|14<br>~~ee~~<br>~~ee~~|–169<br>~~ee~~<br>~~ee~~|–32<br>~~ee~~<br>~~ee~~|224<br>~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|–3<br>~~ee~~<br>~~ee~~|
||8<br>~~a ~~<br>~~es~~|–40<br> ~~ee~~<br>~~ee~~|–5<br>~~ee ~~<br>~~ee~~|17<br> ~~ee~~<br>~~ee~~|–11<br>~~ee~~<br>~~ee~~|–5<br>~~ee ~~<br>~~ee~~|21<br> ~~ee~~<br>~~ee~~|–87<br>~~ee~~<br>~~ee~~|–40<br>~~ee~~<br>~~ee~~|166<br>~~ee ~~<br>~~ee~~|2<br> ~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|–4<br>~~ee~~<br>~~ee~~|
||4<br>~~es~~<br>~~a~~<br>~~es~~|–45<br>~~ee~~<br>~~ee~~|–9<br>~~ee~~<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~<br>~~ee~~|–16<br>~~ee~~<br>~~ee~~<br>~~ee~~|–11<br>~~ee~~<br>~~ee~~|36<br>~~ee~~<br>~~ee~~|–63<br>~~ee~~|–43<br>~~ee~~|144<br>~~ee~~|2<br>~~ee~~|0<br>~~ee~~|–4<br>~~ee~~|
||2<br>~~es~~|–70<br>~~ee~~|–19<br>~~ee~~|33<br>~~ee~~|–33<br>~~ee~~|–20<br>~~ee~~|66<br>~~ee~~|–66|–39|131|2|0|–4|
||1<br>~~es~~<br>~~a~~|–25<br>~~ee~~<br>~~ee~~|–7<br>~~ee~~<br>~~ee~~|5<br>~~ee ~~<br>~~ee~~|–11<br> ~~ee~~<br>~~ee~~|–3<br>~~ee ~~<br>~~ee~~|26<br> ~~ee~~<br>~~ee~~|–11<br>~~ee~~|–3<br>~~ee~~|26<br>~~ee~~|3<br>~~ee~~|–1<br>~~ee~~|–3<br>~~ee~~|
||0.5<br>~~a~~|–41<br>~~se~~|–12<br>~~se~~|8|–12<br>~~ee~~|–7<br>~~ee~~|38<br>~~ee~~|–6<br>~~ee~~|–4<br>~~ee~~|19<br>~~ee~~|3<br>~~ee~~|–1<br>~~ee~~|–3<br>~~ee~~|
||0.25<br>~~a~~<br>~~i~~|–53<br>~~i~~<br>~~i~~|–14<br>~~ee~~<br>~~ee~~|19<br>~~ee~~<br>~~ee~~|–20<br>~~ee~~<br>~~ee~~|–14<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br>~~ee~~|–5<br>~~ee~~|–3<br>~~ee~~|10<br>~~ee~~|5<br>~~ee~~|0<br>~~ee~~|–4<br>~~ee~~|
||0.125<br>~~a ~~<br>~~i~~|–89<br> ~~i~~<br>~~i~~|–29<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|–40<br>~~ee~~<br>~~ee~~|–28<br>~~ee~~<br>~~ee~~|88<br>~~ee ~~<br>~~ee~~|–5<br> ~~ee~~|–4<br>~~ee~~|11<br>~~ee ~~|7<br> ~~ee~~|0<br>~~ee~~|–5<br>~~ee~~|
|AT<br>~~eee~~|16<br>~~i~~<br>~~eee~~<br>~~Rs~~|–3<br>~~i~~<br>~~eee~~<br>~~ee~~|9<br>~~ee~~<br>~~eee~~<br>~~ee~~|15<br>~~ee~~<br>~~eee~~<br>~~ee~~|–4<br>~~ee~~<br>~~eee~~<br>~~ee~~|0<br>~~ee ~~<br>~~eee~~<br>~~ee~~|4<br> ~~ee~~<br>~~eee~~<br>~~ee~~|–64<br>~~eee~~<br>~~se~~|5<br>~~eee~~<br>~~se~~|64<br>~~eee~~|1<br>~~eee~~|0<br>~~eee~~|–1<br>~~eee~~|
||4<br>~~eee~~<br>~~Rs~~|–10<br>~~eee~~<br>~~ee~~|2<br>~~eee~~<br>~~ee~~|15<br>~~eee~~<br>~~ee~~|–11<br>~~eee~~<br>~~ee~~|–2<br>~~eee~~<br>~~ee~~|11<br>~~eee~~<br>~~ee~~|–44<br>~~eee~~<br>~~se~~|–8<br>~~eee~~<br>~~se~~|44<br>~~eee~~|1<br>~~eee~~|0<br>~~eee~~|–1<br>~~eee~~|
|**Negative Range**<br>~~Rs~~<br>~~i~~||**ADC in 10-Bit Mode**<br>~~ee ee ee se~~||||||||||||
|AV, AC|16<br>~~a~~|–35<br>~~a~~<br>a~~eee~~|–10<br>~~a~~<br>~~eee~~|9<br>~~eee~~|–24<br>~~eee~~|–6<br>~~eee~~|9<br>~~eee~~|–383<br>~~eee~~|–96<br>~~eee~~|148<br>~~eee~~|5<br>~~eee~~|–1<br>~~eee~~|–6<br>~~eee~~|
||8<br>~~a~~<br>~~es~~|–65<br>~~ee~~<br>~~ee~~|–19<br>~~ee~~<br>~~ee~~|12<br>~~ee~~|–34<br>~~ee~~<br>~~ee~~|–12<br>~~ee~~<br>~~ee~~|9<br>~~ee~~<br>~~ee~~|–268<br>~~ee~~<br>~~ee~~|–99<br>~~ee~~<br>~~ee~~|75<br>~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~|–1<br>~~ee~~<br>~~ee~~|–5<br>~~ee~~<br>~~ee~~|
||4<br>~~a~~<br>~~es~~|–86<br>~~ee~~<br>~~ee~~|–28<br>~~ee~~<br>~~ee~~|21<br>~~ee~~|–64<br>~~ee~~<br>~~ee~~|–24<br>~~ee~~<br>~~ee~~|19<br>~~ee ~~<br>~~ee~~|–254<br> ~~ee~~<br>~~ee~~|–96<br>~~ee~~<br>~~ee~~|76<br>~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~|–1<br>~~ee~~<br>~~ee~~|–6<br>~~ee~~<br>~~ee~~|
||2<br>~~es~~<br>~~a~~<br>~~es~~|–136<br>~~ee~~<br>~~ee~~|–53<br>~~ee~~<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~<br>~~ee~~|–115<br>~~ee~~<br>~~ee~~<br>~~ee~~|–42<br>~~ee~~<br>~~ee~~|39<br>~~ee~~<br>~~ee~~|–230<br>~~ee~~|–83<br>~~ee~~|78<br>~~ee~~|6<br>~~ee~~|–2<br>~~ee~~|–7<br>~~ee~~|
||1<br>~~es~~|–98<br>~~ee~~|–35<br>~~ee~~|8<br>~~ee~~|–39<br>~~ee~~|–8<br>~~ee~~|15<br>~~ee~~|–39|–8|15|10|–3|–10|
||0.5<br>~~es~~<br>~~a~~|–121<br>~~ee~~<br>~~ee~~|–46<br>~~ee~~<br>~~ee~~|7<br>~~ee ~~<br>~~ee~~|–54<br> ~~ee~~<br>~~ee~~|–14<br>~~ee ~~<br>~~ee~~|18<br> ~~ee~~<br>~~ee~~|–27<br>~~ee~~|–7<br>~~ee~~|9<br>~~ee~~|10<br>~~ee~~|–4<br>~~ee~~|–11<br>~~ee~~|
||0.25<br>~~a~~|–149<br>~~ee~~|–49<br>~~ee~~|19<br>~~ee~~|–72<br>~~ee~~|–16<br>~~ee~~|40<br>~~ee~~|–18<br>~~ee~~<br>~~ee~~|–4<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|14<br>~~ee~~<br>~~ee~~|–4<br>~~ee~~<br>~~ee~~|–12<br>~~ee~~<br>~~ee~~|
||0.125<br>~~a ee~~|–188<br>~~ee~~|–67<br>~~ee~~|38<br>~~ee~~|–112<br>~~ee~~|–27<br>~~ee~~|56<br>~~ee~~|–14<br>~~ee~~<br>~~ee~~|–3<br>~~ee~~<br>~~ee~~|7<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|–5<br>~~ee~~<br>~~ee~~|–14<br>~~ee~~<br>~~ee~~|
_Note: *Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For 8-bit mode, divide the LSB count by 4. Gain remains the same._
**Revision 8**
**2-122**
_Device Architecture_
_**Table 2-52 •**_ **Calibrated Analog Channel Accuracy[1,2,3]**
## **Worst-Case Industrial Conditions, TJ = 85°C**
|||~~Q~~||||
|---|---|---|---|---|---|
|~~es~~||**Condition**<br>~~es~~<br>~~Q~~|**Total Channel Error (LSB)**<br>~~es~~|||
|**Analog**<br>**Pad**<br>~~es~~|**Prescaler Range (V)**<br>~~es~~|**Input Voltage4 (V)**<br>~~es~~<br>~~Q~~|**Negative Max.**<br>~~es~~|**Median**<br>~~es~~|**Positive Max.**<br>~~es~~|
|**Positive Range**<br>~~Ge~~||~~Ge~~|**ADC in 10-Bit Mode**<br>~~Ge~~|||
|AV, AC<br>~~Ge~~<br>~~pF~~|16<br>~~Ge~~<br>~~a~~|0.300 to 12.0<br>~~Ge~~|–6<br>~~Ge~~|1<br>~~Ge~~|6<br>~~Ge~~|
||8<br>~~a~~|0.250 to 8.00|–6|0|6|
||4<br>~~a~~<br>~~ee es~~|0.200 to 4.00<br>~~es ee~~|–7<br>~~ee~~|–1|7|
||2<br>~~ee es~~<br>~~es~~|0.150 to 2.00<br>~~es ee~~<br>~~ss~~|–7<br>~~ee~~<br>~~ss~~|0<br>~~ss~~|7<br>~~ss~~|
||1<br>~~ee es~~<br>~~es~~<br>~~pF~~|0.050 to 1.00<br>~~es ee~~<br>~~ss~~<br>|–6<br>~~ee~~<br>~~ss~~<br>|–1<br>~~ss~~<br>|6<br>~~ss~~<br>|
|AT<br>~~pF~~|16<br>~~es~~<br>~~pF~~|0.300 to 16.0<br>~~ss~~<br>|–5<br>~~ss~~<br>|0<br>~~ss~~<br>|5<br>~~ss~~<br>|
||4<br>~~pFss~~|0.100 to 4.00<br>~~ss~~|–7<br>~~ss~~|–1<br>~~ss~~|7<br>~~ss~~|
|**Negative Range**<br>~~pFss~~<br>~~Ge~~<br>~~es~~||~~ss~~<br>~~Ge~~<br>~~ss~~|**ADC in 10-Bit Mode**<br>~~ss~~<br>~~Ge~~<br>~~ss~~|||
|AV, AC<br>~~Ge~~|16<br>~~Ge~~<br>~~es~~<br>~~es~~|–0.400 to –10.5<br>~~Ge~~<br>~~ss~~<br>~~es~~|–7<br>~~Ge~~<br>~~ss~~|1<br>~~Ge~~<br>~~ss~~|9<br>~~Ge~~<br>~~ss~~|
||8<br>~~es~~<br>~~es~~<br>~~es~~|–0.350 to –8.00<br>~~ss~~<br>~~es~~<br>~~es~~|–7<br>~~ss~~|–1<br>~~ss~~|7<br>~~ss~~|
||4<br>~~es ~~<br>~~es~~<br>~~es~~|–0.300 to –4.00<br> ~~es~~<br>~~es~~<br>~~es~~|–7|–2|9|
||2<br>~~es ~~<br>~~es~~|–0.250 to –2.00<br> ~~es~~<br>~~es~~|–7<br>~~es~~|–2|7|
||1<br>~~es ~~<br>~~ss~~|–0.050 to –1.00<br> ~~es~~<br>~~ss~~|–16<br>~~ss~~<br>~~es~~|–1<br>~~ss~~|20<br>~~ss~~|
_Notes:_
_1. Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For 8-bit mode, divide the LSB count by 4. Overall accuracy remains the same._
_2. Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the “Temperature, Voltage, and Current Calibration in Fusion FPGAs” chapter of the_ Fusion FPGA Fabric User Guide _._
_3. Calibrated with two-point calibration methodology, using 20% and 80% full-scale points._
_4. The lower limit of the input voltage is determined by the prescaler input offset._
**2-123**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**Typical Conditions, T**|**Typical Conditions, TA = 25°C**<br>|**Typical Conditions, TA = 25°C**<br>|**Typical Conditions, TA = 25°C**<br>|**Typical Conditions, TA = 25°C**<br>|**Typical Conditions, TA = 25°C**<br>|**Typical Conditions, TA = 25°C**<br>|**Typical Conditions, TA = 25°C**<br>||
|---|---|---|---|---|---|---|---|---|
|**Input Voltage**<br>**(V)**|**Calibrated Typical Error per Positive Prescaler Setting 1 (%FSR)**<br>~~ef~~<br>~~Ffff~~|||||||**Direct ADC 2,3**<br>**(%FSR)**<br>~~ef~~|
||**16 V (AT)**<br>~~Ff~~|**16 V (12 V)**<br>**(AV/AC)**<br>~~Ffff~~|**8 V**<br>**(AV/AC)**<br>~~ff~~|**4 V (AT)**<br>~~ff~~|**4 V**<br>**(AV/AC)**|**2 V**<br>**(AV/AC)**|**1 V**<br>**(AV/AC)**|**VAREF = 2.56 V**|
|15<br>~~a~~|1<br>~~Ff~~<br>~~a~~|~~Ff ff~~|~~ff~~|~~ff~~|||||
|14<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|~~eee~~|||||||
|12<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|~~ee~~<br>|~~ee~~|||||
|5<br>~~ee~~<br>~~ee~~<br>~~ee~~|2<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~es~~|2<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~|||||
|3.3<br>~~ee~~<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~es~~<br>~~es~~<br>|2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>|1||~~F~~|~~F~~|
|2.5<br>~~ee ~~<br>~~ee~~<br>~~ee es~~<br>~~ee~~|3<br>~~ee ~~<br> ~~es~~<br>~~es~~<br>~~es~~<br>|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>~~ee~~<br>|1<br>~~es~~||~~F~~|1<br>~~F~~<br>~~PY~~|
|1.8<br> <br>~~ee~~<br>~~ee es~~<br>~~ee~~<br>~~ee~~|4<br> ~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|4<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>~~ee~~<br>|1<br>~~es~~<br>~~es~~|1|~~F~~|1<br>~~F~~<br>~~PY~~<br>~~PY~~|
|1.5<br>~~ee es~~<br>~~ee~~<br>~~ee~~<br>~~a~~|5<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|2<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|2<br>~~ee~~<br>~~ee~~<br>~~ee~~|2<br>~~es~~<br>~~es~~<br>~~es~~|1|~~F~~|1<br>~~F~~<br>~~PY~~<br>~~PY~~<br>~~Pe~~|
|1.2<br>~~es~~<br>~~ee ~~<br>~~ee~~<br>~~a~~|7<br>~~es ~~<br> ~~es~~<br>~~es~~<br>~~es~~|6<br> ~~ee ~~<br>~~ee~~<br>~~ee ee~~<br>~~es~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|2<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|2<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|1<br>~~es~~||1<br>~~PY~~<br>~~PY~~<br>~~Pe~~|
|0.9<br> <br>~~ee ~~<br>~~a~~|9<br> ~~es ~~<br> ~~es ~~<br>~~es~~|9<br> ~~ee ~~<br> ~~ee ee~~<br>~~es~~|4<br> ~~ee ~~<br>~~ee ee~~<br>~~ee~~|3<br> ~~ee~~<br>~~ee~~<br>~~es~~|3<br>~~es~~<br>~~es~~<br>~~es~~|1<br>~~es~~|1|1<br>~~PY~~<br>~~Pe~~|
_1. Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the “Temperature, Voltage, and Current Calibration in Fusion FPGAs” chapter of the_ Fusion FPGA Fabric User Guide _._
_2. Direct ADC mode using an external VAREF of 2.56V±4.6mV, without Analog Calibration macro._
_3. For input greater than 2.56 V, the ADC output will saturate. A higher VAREF or prescaler usage is recommended._
## _**Examples**_
## _**Calculating Accuracy for an Uncalibrated Analog Channel**_
## _**Formula**_
For a given prescaler range, EQ 30 gives the output voltage.
_Output Voltage = (Channel Output Offset in V) + (Input Voltage x Channel Gain)_
_EQ 30_
## where
_Channel Output offset in V = Channel Input offset in LSBs x Equivalent voltage per LSB Channel Gain Factor = 1+ (% Channel Gain / 100)_
## _**Example**_
Input Voltage = 5 V Chosen Prescaler range = 8 V range Refer to Table 2-51 on page 2-122.
Max. Output Voltage = (Max Positive input offset) + (Input Voltage x Max Positive Channel Gain)
Max. Positive input offset = (21 LSB) x (8 mV per LSB in 10-bit mode) Max. Positive input offset = 166 mV Max. Positive Gain Error = +3% Max. Positive Channel Gain = 1 + (+3% / 100) Max. Positive Channel Gain = 1.03 Max. Output Voltage = (166 mV) + (5 V x 1.03) Max. Output Voltage = **5.316 V**
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## Similarly,
Min. Output Voltage = (Max. Negative input offset) + (Input Voltage x Max. Negative Channel Gain) = (–88 mV) + (5 V x 0.96) = **4.712 V**
## _**Calculating Accuracy for a Calibrated Analog Channel**_
## _**Formula**_
For a given prescaler range, EQ 31 gives the output voltage.
_Output Voltage = Channel Error in V + Input Voltage_
_EQ 31_
## where
_Channel Error in V = Total Channel Error in LSBs x Equivalent voltage per LSB_
## _**Example**_
Input Voltage = 5 V Chosen Prescaler range = 8 V range Refer to Table 2-52 on page 2-123.
Max. Output Voltage = Max. Positive Channel Error in V + Input Voltage Max. Positive Channel Error in V = (6 LSB) × (8 mV per LSB in 10-bit mode) = 48 mV Max. Output Voltage = 48 mV + 5 V = **5.048 V**
## Similarly,
Min. Output Voltage = Max. Negative Channel Error in V + Input Voltage = (–48 mV) + 5 V = **4.952 V**
## _**Calculating LSBs from a Given Error Budget**_
## _**Formula**_
For a given prescaler range,
_LSB count = ± (Input Voltage × Required% error) / (Equivalent voltage per LSB)_
## _**Example**_
Input Voltage = 3.3 V Required error margin= 1% Refer to Table 2-52 on page 2-123. Equivalent voltage per LSB = 16 mV for a 16V prescaler, with ADC in 10-bit mode LSB Count = ± (5.0 V × 1%) / (0.016) LSB Count = **± 3.125** Equivalent voltage per LSB = **8 mV** for an 8 V prescaler, with ADC in 10-bit mode LSB Count = ± (5.0 V × 1%) / (0.008) LSB Count = **± 6.25**
The 8 V prescaler satisfies the calculated LSB count accuracy requirement (see Table 2-52 on page 2-123).
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## **Analog Configuration MUX**
The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time counter. Microsemi Libero SoC will generate IP that will load and configure the Analog Block via the ACM. However, users are not limited to using the Libero SoC IP. This section provides a detailed description of the ACM's register map, truth tables for proper configuration of the Analog Block and RTC, as well as timing waveforms so users can access and control the ACM directly from their designs.
The Analog Block contains four 8-bit latches per Analog Quad that are initialized through the ACM. These latches act as configuration bits for Analog Quads. The ACM block runs from the core voltage supply (1.5 V).
Access to the ACM is achieved via 8-bit address and data busses with enables. The pin list is provided in Table 2-36 on page 2-78. The ACM clock speed is limited to a maximum of 10 MHz, more than sufficient to handle the low-bandwidth requirements of configuring the Analog Block and the RTC (sub-block of the Analog Block).
Table 2-54 decodes the ACM address space and maps it to the corresponding Analog Quad and configuration byte for that quad.
_**Table 2-54 •**_ **ACM Address Decode Table for Analog Quad**
|**ACMADDR [7:0] in**<br>**Decimal**|**Name**|**Description**|**Associated**<br>**Peripheral**|
|---|---|---|---|
|0<br>~~eG~~<br>~~es~~|–<br>~~eG~~|–<br>~~eG~~|Analog Quad<br>~~eG~~|
|1<br>~~es~~|AQ0|Byte 0|Analog Quad|
|2<br>~~es~~<br>~~GG~~|AQ0<br>~~GG~~|Byte 1<br>~~GG~~|Analog Quad<br>~~GG~~|
|3<br>~~eG~~|AQ0<br>~~eG~~|Byte 2<br>~~eG~~|Analog Quad<br>~~eG~~|
|4<br>~~see~~|AQ0<br>~~see~~|Byte 3<br>~~see~~|Analog Quad<br>~~see~~|
|5<br>~~see~~<br>~~**e**e~~|AQ1<br>~~see~~<br>~~e~~|Byte 0<br>~~see~~<br>~~ee~~|Analog Quad<br>~~see~~<br>~~ee~~|
|.<br>.<br>.<br>~~**e**e~~|.<br>.<br>.<br>~~e~~|.<br>.<br>.<br>~~ee~~|Analog Quad<br>~~ee~~|
|36<br>~~**e**e~~|AQ8<br>~~e ~~|Byte 3<br> ~~ee ~~<br>~~G~~|Analog Quad<br> ~~ee~~<br>~~G~~|
|37<br>~~see~~<br>~~es~~|AQ9<br>~~see~~|Byte 0<br>~~see~~|Analog Quad<br>~~see~~|
|38<br>~~see~~<br>~~es~~|AQ9<br>~~see~~|Byte 1<br>~~see~~|Analog Quad<br>~~see~~|
|39<br>~~es~~<br>~~eG~~<br>~~es~~|AQ9<br>~~eG~~|Byte 2<br>~~eG~~|Analog Quad<br>~~eG~~|
|40<br>~~es~~|AQ9|Byte 3|Analog Quad|
|41<br>~~es~~||Undefined<br>~~ee~~|Analog Quad<br>~~ee~~|
|.<br>.<br>.<br>~~ee~~|.<br>.<br>.<br>~~ee~~|Undefined<br>~~ee~~<br>~~ee~~|Analog Quad<br>~~ee~~<br>~~ee~~|
|63<br>~~ee~~<br>~~eG~~<br>~~es~~|~~ee~~<br>~~eG~~|Undefined<br>~~ee~~<br>~~ee~~<br>~~eG~~|RTC<br>~~ee~~<br>~~ee~~<br>~~eG~~|
|64<br>~~es~~|COUNTER0|Counter bits 7:0|RTC|
|65<br>~~es~~<br>~~GG~~|COUNTER1<br>~~GG~~|Counter bits 15:8<br>~~GG~~|RTC<br>~~GG~~|
|66<br>~~eG~~|COUNTER2<br>~~eG~~|Counter bits 23:16<br>~~eG~~|RTC<br>~~eG~~|
|67<br>~~eG~~|COUNTER3<br>~~eG~~|Counter bits 31:24<br>~~eG~~|RTC<br>~~eG~~|
|68<br>~~see~~<br>~~es~~|COUNTER4<br>~~see~~<br>~~eG~~|Counter bits 39:32<br>~~see~~<br>~~eG~~|RTC<br>~~see~~<br>~~eG~~|
|72<br>~~see~~<br>~~es~~|MATCHREG0<br>~~see~~<br>~~eG~~|Match register bits 7:0<br>~~see~~<br>~~eG~~|RTC<br>~~see~~<br>~~eG~~|
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_**Table 2-54 •**_ **ACM Address Decode Table for Analog Quad (continued)**
|**ACMADDR [7:0] in**<br>**Decimal**|**Name**|**Description**|**Associated**<br>**Peripheral**|
|---|---|---|---|
|73|MATCHREG1|Match register bits 15:8|RTC|
|74|MATCHREG2|Match register bits 23:16|RTC|
|75|MATCHREG3|Match register bits 31:24|RTC|
|76|MATCHREG4|Match register bits 39:32|RTC|
|80|MATCHBITS0|Individual match bits 7:0|RTC|
|81|MATCHBITS1|Individual match bits 15:8|RTC|
|82|MATCHBITS2|Individual match bits 23:16|RTC|
|83|MATCHBITS3|Individual match bits 31:24|RTC|
|84|MATCHBITS4|Individual match bits 39:32|RTC|
|88|CTRL_STAT|Control (write) / Status (read) register bits<br>7:0|RTC|
|_Note:_<br>_ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC._||||
_Note: ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC._
## **ACM Characteristics[1]**
**==> picture [452 x 107] intentionally omitted <==**
**----- Start of picture text -----**<br>
ACMCLK<br>tSUEACM tHEACM<br>ACMWEN<br>XXXX /— R OKK KOKI KKK KKK KXXXXXKXXAXARXARAKA<br>tSUDACM tHDACM<br>ACMWDATA D0 D1<br>KKK. KKK KKK KIRK KK KKK KKKIRKKKKX__ X KOIKKKKKKKKKKKIKII<br>tSUAACM tHAACM<br>ACMADDRESS A0 A1<br>KEKE K KK KKK KKK KKK KIKI KROKIKKKRKKKKKIKIKICK<br>**----- End of picture text -----**<br>
_**Figure 2-97 •**_ **ACM Write Waveform**
**==> picture [397 x 82] intentionally omitted <==**
**----- Start of picture text -----**<br>
tMPWCLKACM<br>ACMCLK<br>ACMADDRESS A0 A1<br>KR tCLKQACM XK KKK KK KKK IKK RIROKKKK<br>ACMRDATA RD0 RD1<br>**----- End of picture text -----**<br>
_**Figure 2-98 •**_ **ACM Read Waveform**
> _1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the rc_osc, byte_en, and aq_wen signals have no impact._
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## _**Timing Characteristics**_
_**Table 2-55 •**_ **Analog Configuration Multiplexer (ACM) Timing**
|**Parameter**<br>~~Re~~<br>~~es~~|**Description**<br>~~a~~<br>|**–2**<br>~~a~~<br>|**–1**<br>~~a~~<br>|**Std.**<br>~~a~~<br>|**Units**<br>~~a~~<br>|
|---|---|---|---|---|---|
|tCLKQACM<br>~~Re~~<br>~~es~~|Clock-to-Q of the ACM<br>~~a~~<br>|19.73<br>~~a~~<br>|22.48<br>~~a~~<br>|26.42<br>~~a~~<br>|ns<br>~~a~~<br>|
|tSUDACM<br>~~esa~~<br>~~es~~|Data Setup time for the ACM<br>~~a~~<br>|4.39<br>~~a~~<br>|5.00<br>~~a~~<br>|5.88<br>~~a~~<br>|ns<br>~~a~~<br>|
|tHDACM<br>~~a~~<br>~~es~~|Data Hold time for the ACM<br>~~a~~<br>|0.00<br>~~a~~<br>|0.00<br>~~a~~<br>|0.00<br>~~a~~<br>|ns<br>~~a~~<br>|
|tSUAACM<br>~~esa~~<br>~~es~~|Address Setup time for the ACM<br>~~a~~<br>|4.73<br>~~a~~<br>|5.38<br>~~a~~<br>|6.33<br>~~a~~<br>|ns<br>~~a~~<br>|
|tHAACM<br>~~a~~<br>~~es~~|Address Hold time for the ACM<br>~~a~~<br>|0.00<br>~~a~~<br>|0.00<br>~~a~~<br>|0.00<br>~~a~~<br>|ns<br>~~a~~<br>|
|tSUEACM<br>~~esa~~<br>~~es~~|Enable Setup time for the ACM<br>~~a~~<br>|3.93<br>~~a~~<br>|4.48<br>~~a~~<br>|5.27<br>~~a~~<br>|ns<br>~~a~~<br>|
|tHEACM<br>~~a~~<br>~~es~~|Enable Hold time for the ACM<br>~~a~~<br>|0.00<br>~~a~~<br>|0.00<br>~~a~~<br>|0.00<br>~~a~~<br>|ns<br>~~a~~<br>|
|tMPWARACM<br>~~esa~~<br>~~es~~|Asynchronous Reset Minimum Pulse Width for the ACM<br>~~a~~<br>|10.00<br>~~a~~<br>|10.00<br>~~a~~<br>|10.00<br>~~a~~<br>|ns<br>~~a~~<br>|
|tREMARACM<br>~~a~~<br>~~es~~|Asynchronous Reset Removal time for the ACM<br>~~a~~<br>|12.98<br>~~a~~<br>|14.79<br>~~a~~<br>|17.38<br>~~a~~<br>|ns<br>~~a~~<br>|
|tRECARACM<br>~~esa~~<br>~~es~~|Asynchronous Reset Recovery time for the ACM<br>~~a~~<br>|12.98<br>~~a~~<br>|14.79<br>~~a~~<br>|17.38<br>~~a~~<br>|ns<br>~~a~~<br>|
|tMPWCLKACM<br>~~a~~<br>~~es~~|Clock Minimum Pulse Width for the ACM<br>~~a~~<br>|45.00<br>~~a~~<br>|45.00<br>~~a~~<br>|45.00<br>~~a~~<br>|ns<br>~~a~~<br>|
|tFMAXCLKACM<br>~~esa~~|lock Maximum Frequency for the ACM<br>~~a~~|10.00<br>~~a~~|10.00<br>~~a~~|10.00<br>~~a~~|MHz<br>~~a~~|
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## _**Analog Quad ACM Description**_
Table 2-56 maps out the ACM space associated with configuration of the Analog Quads within the Analog Block. Table 2-56 shows the byte assignment within each quad and the function of each bit within each byte. Subsequent tables will explain each bit setting and how it corresponds to a particular configuration. After 3.3 V and 1.5 V are applied to Fusion, Analog Quad configuration registers are loaded with default settings until the initialization and configuration state machine changes them to userdefined settings.
_**Table 2-56 •**_ **Analog Quad ACM Byte Assignment**
|**Byte**<br>~~a~~|**Bit**<br>~~es~~|**Signal (Bx)**<br>~~es~~|**Function**<br>~~es~~|**Default Setting**<br>~~es~~|
|---|---|---|---|---|
|Byte 0<br>(AV)<br>~~ee~~<br>~~eo~~|0<br>~~a~~|B0[0]<br>~~a~~|Scaling factor control – prescaler<br>|Highest voltage range<br>|
||1<br>~~a~~|B0[1]<br>~~a~~|||
||2<br>~~a~~<br>~~a~~<br>~~ee~~|B0[2]<br>~~a~~<br>~~a~~<br>|||
||3<br>~~ee~~|B0[3]<br>|Analog MUX select<br>|Prescaler<br>|
||4<br>~~eees~~<br>~~a~~|B0[4]<br>~~es~~<br>~~es~~|Current monitor switch<br>~~es~~|Off<br>~~es~~|
||5<br>~~es~~<br>~~a~~|B0[5]<br>~~es~~<br>~~es~~|Direct analog input switch<br>~~es~~|Off<br>~~es~~|
||6<br>~~a~~<br>~~ss~~<br>~~eo~~|B0[6]<br>~~es~~<br>~~ss~~<br>|Selects V-pad polarity<br>~~ss~~<br>|Positive<br>~~ss~~<br>|
||7<br>~~eo~~|B0[7]<br>|Prescaler op amp mode<br>|Power-down<br>|
|Byte 1<br>(AC)<br>~~eo~~|0<br>~~eoa~~|B1[0]<br>~~a~~|Scaling factor control – prescaler<br>~~a~~<br>~~a~~<br>~~a~~|Highest voltage range<br>~~a~~<br>~~a~~<br>~~a~~|
||1<br>~~a~~|B1[1]<br>~~a~~|||
||2<br>~~a~~|B1[2]<br>~~a~~|||
||3<br>~~a~~<br>~~**a**~~|B1[3]<br>~~a~~<br>~~**a**~~|Analog MUX select<br>~~a~~<br>~~**a**~~|Prescaler<br>~~a~~<br>~~**a**~~|
||4<br>~~**a**~~|B1[4]<br>~~**a**~~|||
||5<br>~~ss~~<br>~~a~~|B1[5]<br>~~ss~~<br>~~es~~|Direct analog input switch<br>~~ss~~|Off<br>~~ss~~|
||6<br>~~ss~~<br>~~a~~|B1[6]<br>~~ss~~<br>~~es~~|Selects C-pad polarity<br>~~ss~~|Positive<br>~~ss~~|
||7<br>~~a~~<br>~~ee~~|B1[7]<br>~~es~~<br>~~ee~~|Prescaler op amp mode<br>~~ee~~|Power-down<br>~~ee~~|
|Byte 2<br>(AG)|0<br>~~es~~<br>~~a~~|B2[0]<br>~~es~~<br>~~es~~|Internal chip temperature monitor *<br>~~es~~|Off<br>~~es~~|
||1<br>~~es~~<br>~~a~~<br>~~ee~~|B2[1]<br>~~es~~<br>~~es~~<br>~~a~~|Spare<br>~~es~~<br>~~a~~|–<br>~~es~~<br>~~a~~|
||2<br>~~a~~<br>~~ee~~|B2[2]<br>~~es~~<br>~~a~~|Current drive control<br>~~a~~|Lowest current<br>~~a~~|
||3<br>~~ee~~<br>~~a~~|B2[3]<br>~~a~~<br>~~a~~<br>~~es~~|||
||4<br>~~ee~~<br>~~a~~<br>~~a~~|B2[4]<br>~~a~~<br>~~a~~<br>~~a~~<br>~~es~~|Spare<br>~~a~~|–<br>~~a~~|
||5<br>~~ee~~|B2[5]<br>~~es~~<br>~~ee~~|Spare<br>~~ee~~|–<br>~~ee~~|
||6<br>~~a~~<br>~~es~~|B2[6]|Selects G-pad polarity|Positive|
||7<br>~~a~~<br>~~es~~|B2[7]|Selects low/high drive|Low drive|
|Byte 3<br>(AT)|0<br>~~es~~<br>~~a~~|B3[0]<br>~~a~~|Scaling factor control – prescaler<br>~~a~~|Highest voltage range<br>~~a~~|
||1<br>~~a~~|B3[1]<br>~~a~~|||
||2<br>~~a~~<br>~~a~~<br>~~ee~~|B3[2]<br>~~a~~<br>~~a~~<br>~~a~~|||
||3<br>~~ee~~|B3[3]<br>~~a~~|Analog MUX select<br>~~a~~|Prescaler<br>~~a~~|
||4<br>~~ee~~<br>~~a~~<br>~~es~~|B3[4]<br>~~a~~<br>~~a~~|||
||5<br>~~ee~~<br>~~a~~<br>~~es~~<br>~~es~~|B3[5]<br>~~a~~<br>~~a~~|Direct analog input switch<br>~~a~~|Off<br>~~a~~|
||6<br>~~es~~<br>~~es~~|B3[6]|–|–|
||7<br>~~es~~<br>~~a~~|B3[7]|Prescaler op amp mode|Power-down|
_Note: *For the internal temperature monitor to function, Bit 0 of Byte 2 for all 10 Quads must be set._
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Table 2-57 details the settings available to control the prescaler values of the AV, AC, and AT pins. Note that the AT pin has a reduced number of available prescaler values.
_**Table 2-57 •**_ **Prescaler Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)**
|**Control Lines**<br>**Bx[2:0]**<br>~~i~~|**Scaling**<br>**Factor, Pad to**<br>**ADC Input**|**LSB for an**<br>**8-Bit**<br>**Conversion1**<br>**(mV)**<br>~~ee~~|**LSB for a**<br>**10-Bit**<br>**Conversion1**<br>**(mV)**|**LSB for a**<br>**12-Bit**<br>**Conversion1**<br>**(mV)**|**Full-Scale**<br>**Voltage in**<br>**10-Bit**<br>**Mode2**|**Range Name**|
|---|---|---|---|---|---|---|
|0003<br>~~ss~~<br>~~i~~|0.15625<br>~~ss~~<br>~~es~~|64<br>~~ss~~<br>~~ee~~<br>~~eG~~|16<br>~~ss~~<br>~~eG~~|4<br>~~ss~~|16.368 V<br>~~ss~~|16 V<br>~~ss~~|
|001<br>~~ss~~<br>~~i~~|0.3125<br>~~ss~~<br>~~es~~|32<br>~~ss~~<br>~~ee~~<br>~~eG~~|8<br>~~ss~~<br>~~eG~~|2<br>~~ss~~|8.184 V<br>~~ss~~|8 V<br>~~ss~~|
|0103<br>~~ss~~<br>~~i~~|0.625<br>~~es~~<br>~~ss~~|16<br>~~eG~~<br>~~eG~~<br>~~ee~~|4<br>~~eG~~<br>~~eG~~|1<br>~~eG~~|4.092 V|4 V|
|011<br>~~ss~~<br>~~i~~|1.25<br>~~ss~~<br>~~es~~|8<br>~~ss~~<br>~~ee~~<br>~~eG~~|2<br>~~ss~~<br>~~eG~~|0.5<br>~~ss~~|2.046 V<br>~~ss~~|2 V<br>~~ss~~|
|100<br>~~ss~~<br>~~i~~|2.5<br>~~ss~~<br>~~es~~|4<br>~~ss~~<br>~~ee~~<br>~~eG~~|1<br>~~ss~~<br>~~eG~~|0.25<br>~~ss~~|1.023 V<br>~~ss~~|1 V<br>~~ss~~|
|101<br>~~ss~~<br>~~a~~|5.0<br>~~es~~<br>~~ss~~<br>~~a~~|2<br>~~eG~~<br>~~eG~~<br>~~**e**e~~|0.5<br>~~eG~~<br>~~eG~~|0.125<br>~~eG~~|0.5115 V|0.5 V|
|110<br>~~ss~~<br>~~a~~|10.0<br>~~ss~~<br>~~a~~|1<br>~~ss~~<br>~~**e**e~~|0.25<br>~~ss~~|0.0625<br>~~ss~~|0.25575 V<br>~~ss~~|0.25 V<br>~~ss~~|
|111<br>~~ss~~<br>~~a~~|20.0<br>~~ss~~<br>~~a~~|0.5<br>~~ss~~<br>~~**e**e~~|0.125<br>~~ss~~|0.03125<br>~~ss~~<br>~~G~~|0.127875 V<br>~~ss~~<br>~~G~~|0.125 V<br>~~ss~~<br>~~G~~|
_Notes:_
_1. LSB voltage equivalences assume VAREF = 2.56 V._
_2. Full Scale voltage for n-bit mode: ((2^n) - 1) x (LSB for a n-bit Conversion)_
_3. These are the only valid ranges for the Temperature Monitor Block Prescaler._
Table 2-58 details the settings available to control the MUX within each of the AV, AC, and AT circuits. This MUX determines whether the signal routed to the ADC is the direct analog input, prescaled signal, or output of either the Current Monitor Block or the Temperature Monitor Block.
_**Table 2-58 •**_ **Analog Multiplexer Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)**
|**Control Lines Bx[4]**|**Control Lines Bx[3]**|**ADC Connected To**|
|---|---|---|
|0|0|Prescaler|
|0|1|Direct input|
|1|0|Current amplifier temperature monitor|
|1|1|Not valid|
Table 2-59 details the settings available to control the Direct Analog Input switch for the AV, AC, and AT pins.
_**Table 2-59 •**_ **Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)**
|**_Table 2-59 •_Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)**|**Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)**|
|---|---|
|**Control Lines Bx[5]**|**Direct Input Switch**|
|0|Off|
|1|On|
Table 2-60 details the settings available to control the polarity of the signals coming to the AV, AC, and AT pins. Note that the only valid setting for the AT pin is logic 0 to support positive voltages.
_**Table 2-60 •**_ **Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)***
|**Control Lines Bx[6]**|**Input Signal Polarity**|
|---|---|
|0|Positive|
|1|Negative|
_Note: *The B3[6] signal for the AT pad should be kept at logic 0 to accept only positive voltages._
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Table 2-61 details the settings available to either power down or enable the prescaler associated with the analog inputs AV, AC, and AT.
_**Table 2-61 •**_ **Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)**
|**Control Lines Bx[7]**|**Prescaler Op Amp**|
|---|---|
|0|Power-down|
|1|Operational|
Table 2-62 details the settings available to enable the Current Monitor Block associated with the AC pin.
_**Table 2-62 •**_ **Current Monitor Input Switch Control Truth Table—AV (x = 0)**
|**Control Lines B0[4]**|**Current Monitor Input Switch**|
|---|---|
|0|Off|
|1|On|
Table 2-63 details the settings available to configure the drive strength of the gate drive when not in highdrive mode.
_**Table 2-63 •**_ **Low-Drive Gate Driver Current Truth Table (AG)**
|**Control Lines B2[3]**|**Control Lines B2[2]**|**Current (µA)**|
|---|---|---|
|0|0|1|
|0|1|3|
|1|0|10|
|1|1|30|
Table 2-64 details the settings available to set the polarity of the gate driver (either p-channel- or n-channel-type devices).
_**Table 2-64 •**_ **Gate Driver Polarity Truth Table (AG)**
|**Control Lines B2[6]**|**Gate Driver Polarity**|
|---|---|
|0|Positive|
|1|Negative|
Table 2-65 details the settings available to turn on the Gate Driver and set whether high-drive mode is on or off.
_**Table 2-65 •**_ **Gate Driver Control Truth Table (AG)**
|**Control Lines B2[7]**|**GDON**|**Gate Driver**|
|---|---|---|
|0|0|Off|
|0|1|Low drive on|
|1|0|Off|
|1|1|High drive on|
Table 2-66 details the settings available to turn on and off the chip internal temperature monitor. Note: For the internal temperature monitor to function, Bit 0 of Byte 2 for all 10 Quads must be set.
_**Table 2-66 •**_ **Internal Temperature Monitor Control Truth Table**
|**_Table 2-66 •_Internal Temperature Monitor Control Truth Table**|**Internal Temperature Monitor Control Truth Table**||
|---|---|---|
|**Control Lines B2[0]**|**PDTMB**|**Chip Internal Temperature Monitor**|
|0|0|Off|
|1|1|On|
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## **User I/Os**
## **Introduction**
Fusion devices feature a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) through a bank-selectable voltage. Table 2-68, Table 2-69, Table 2-70, and Table 2-71 on page 2-135 show the voltages and the compatible I/O standards. I/Os provide programmable slew rates, drive strengths, weak pull-up, and weak pull-down circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V–tolerant. See the "5 V Input Tolerance" section on page 2-144 for possible implementations of 5 V tolerance.
All I/Os are in a known state during power-up, and any power-up sequence is allowed without current impact. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)" section on page 3-5 for more information. In low power standby or sleep mode (VCC is OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, digital inputs are tristated, digital outputs are tristated, and digital bibufs (input/output) are tristated. I/O Tile
The Fusion I/O tile provides a flexible, programmable structure for implementing a large number of I/O standards. In addition, the registers available in the I/O tile in selected I/O banks can be used to support high-performance register inputs and outputs, with register enable if desired (Figure 2-99 on page 2-133). The registers can also be used to support the JESD-79C DDR standard within the I/O structure (see the "Double Data Rate (DDR) Support" section on page 2-139 for more information).
As depicted in Figure 2-100 on page 2-138, all I/O registers share one CLR port. The output register and output enable register share one CLK port. Refer to the "I/O Registers" section on page 2-138 for more information.
## **I/O Banks and I/O Standards Compatibility**
The digital I/Os are grouped into I/O voltage banks. There are three digital I/O banks on the AFS090 and AFS250 devices and four digital I/O banks on the AFS600 and AFS1500 devices. Figure 2-113 on page 2-158 and Figure 2-114 on page 2-159 show the bank configuration by device. The north side of the I/O in the AFS600 and AFS1500 devices comprises two banks of Pro I/Os. The Pro I/Os support a wide number of voltage-referenced I/O standards in addition to the multitude of single-ended and differential I/O standards common throughout all Microsemi digital I/Os. Each I/O voltage bank has dedicated I/O supply and ground voltages (VCCI/GNDQ for input buffers and VCCI/GND for output buffers). Because of these dedicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Table 2-69 and Table 2-70 on page 2-134 show the required voltage compatibility values for each of these voltages.
For more information about I/O and global assignments to I/O banks, refer to the specific pin table of the device in the "Package Pin Assignments" on page 4-1 and the "User I/O Naming Convention" section on page 2-158.
Each Pro I/O bank is divided into minibanks. Any user I/O in a VREF minibank (a minibank is the region of scope of a VREF pin) can be configured as a VREF pin (Figure 2-99 on page 2-133). Only one VREF pin is needed to control the entire VREF minibank. The location and scope of the VREF minibanks can be determined by the I/O name. For details, see the "User I/O Naming Convention" section on page 2-158.
Table 2-70 on page 2-134 shows the I/O standards supported by Fusion devices and the corresponding voltage levels.
I/O standards are compatible if the following are true:
- Their VCCI values are identical.
- If both of the standards need a VREF, their VREF values must be identical (Pro I/O only).
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||**Bank 0**<br>CCC|**Bank 0**<br>CCC|**Bank 0**<br>CCC|**Bank 0**|**Bank 0**|CCC|CCC||||||**Bank 1**<br>CCC|||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||||||||||||||
||I/O<br>I/O<br>GND<br>I/O<br>I/O<br>I/O<br>I/O<br>GND<br>I/O<br>I/O<br>If needed, the VREF for a given<br>Up to five VREF<br>minibanks within<br>an I/O bank<br>VREF signal scope is<br>between 8 and 18 I/Os.<br>Common VREF<br>signal for all I/Os<br>in VREF minibanks<br>VCCI<br>VCC<br>VCCI<br>VCC<br>[—_<br>/\<br>HOO A|||||||||||||||
||I/O Pad||I/O Pad|||minibank can be provided by<br>any I/O within the minibank.||||||||||
|**_Figure 2-99 •_Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500)**||||||||||||||||
|**_Table 2-67 •_I/O Standards Supported by Bank Type**||||||||||||||||
|||||||**Differential I/O**|||||||||**Hot-**|
|**I/O Bank**|**Single-Ended I/O Standards**|||||**Standards**|||||||**Voltage-Referenced**||**Swap**|
|Standard I/O|LVTTL/LVCMOS 3.3 V, LVCMOS|||||–|||||||–||Yes|
||2.5 V / 1.8 V / 1.5 V, LVCMOS|||||||||||||||
||2.5/5.0 V|||||||||||||||
|Advanced I/O|LVTTL/LVCMOS 3.3 V, LVCMOS|||||LVPECL and|||||||–||–|
||2.5 V / 1.8 V / 1.5 V, LVCMOS|||||LVDS||||||||||
||2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X|||||||||||||||
|Pro I/O|LVTTL/LVCMOS 3.3 V, LVCMOS|||||LVPECL and|||||||GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V,||Yes|
||2.5 V / 1.8 V / 1.5 V, LVCMOS|||||LVDS|||||||HSTL Class I and II, SSTL2 Class I|||
||2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X|2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X|||||||||||and II, SSTL3 Class I and II|||
_**Figure 2-99 •**_ **Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500)**
_**Table 2-67 •**_ **I/O Standards Supported by Bank Type**
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_**Table 2-68 •**_ **I/O Bank Support by Device**
|**I/O Bank**|**AFS090**|**AFS250**|**AFS600**|**AFS1500**|
|---|---|---|---|---|
|Standard I/O|N|N|–|–|
|Advanced I/O|E, W|E, W|E, W|E, W|
|Pro I/O|–|–|N|N|
|Analog Quad|S|S|S|S|
_Note: E = East side of the device W = West side of the device N = North side of the device S = South side of the device_
_**Table 2-69 •**_ **Fusion VCCI Voltages and Compatible Standards**
|**VCCI (typical)**|**Compatible Standards**|
|---|---|
|3.3 V|LVTTL/LVCMOS 3.3, PCI 3.3, SSTL3 (Class I and II),* GTL+ 3.3, GTL 3.3,* LVPECL|
|2.5 V|LVCMOS 2.5, LVCMOS 2.5/5.0, SSTL2 (Class I and II),* GTL+ 2.5,* GTL 2.5,* LVDS, BLVDS, M-<br>LVDS|
|1.8 V|LVCMOS 1.8|
|1.5 V|LVCMOS 1.5, HSTL (Class I),* HSTL (Class II)*|
_Note: *I/O standard supported by Pro I/O banks._
_**Table 2-70 •**_ **Fusion VREF Voltages and Compatible Standards***
|**VREF (typical)**|**Compatible Standards**|
|---|---|
|1.5 V|SSTL3 (Class I and II)|
|1.25 V|SSTL2 (Class I and II)|
|1.0 V|GTL+ 2.5, GTL+ 3.3|
|0.8 V|GTL 2.5, GTL 3.3|
|0.75 V|HSTL (Class I), HSTL (Class II)|
_Note: *I/O standards supported by Pro I/O banks._
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_**Table 2-71 •**_ **Fusion Standard and Advanced I/O Features**
|**I/O Bank Voltage (typical)**|**Minibank Voltage (typical)**|**LVTTL/LVCMOS 3.3 V**|**LVCMOS 2.5 V**|**LVCMOS 1.8 V**|**LVCMOS 1.5 V**|**3.3 V PCI / PCI-X**|**GTL + (3.3 V)**|**GTL + (2.5 V)**|**GTL (3.3 V)**|**GTL (2.5 V)**|**HSTL Class I and II (1.5 V)**|**SSTL2 Class I and II (2.5 V)**|**SSTL3 Class I and II (3.3 V)**|**LVDS (2.5 V ± 5%)**|**LVPECL (3.3 V)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|3.3 V<br>~~|~~|–<br>~~Ff~~<br>~~Tf~~|~~Ff~~<br>~~Tf~~||||||~~Pe~~|~~Pe~~|||||||
||0.80 V<br>~~Tf~~<br>~~|~~|~~Tf~~<br>~~|~~|||~~|~~|~~|~~<br>~~|~~||~~Pe~~|~~Pe~~|||||||
||1.00 V<br>~~Tf~~<br>~~|~~<br>~~|~~|~~Tf~~<br>~~|~~|||~~|~~<br>~~Se~~|~~|~~<br>~~|~~<br>~~Se~~||~~Pe~~|~~Pe~~||||~~Ff]~~|~~Ff]~~|~~Ff]~~|
||1.50 V<br>~~|~~<br>~~|~~<br>~~|Ly~~|~~|~~<br>~~Ly~~|~~Ly~~||~~|~~<br>~~Se~~|~~|~~<br>~~|~~<br>~~Se~~|||||||~~Ff]~~|~~Ff]~~|~~Ff]~~|
|2.5 V<br>~~|~~<br>~~Ff~~|–<br>~~|~~<br>~~|Ly~~|~~Ly~~|~~Ly~~||~~Se~~|~~Se~~|||||||~~Ff]~~|~~Ff]~~|~~Ff]~~|
||0.80 V<br>~~| Ly~~<br>~~Ff~~|~~Ly~~|~~Ly~~|||||||~~|~~||||||
||1.00 V<br>~~Ff~~<br>~~Ff~~|||||||~~|~~||||~~Ff~~|~~|~~|~~|~~||
||1.25 V<br>~~Ff~~<br>~~Ff~~|||~~||~~||||||||~~Ff~~|~~|~~|~~|~~||
|1.8 V<br>~~Ff~~<br>~~|~~|–<br>~~Ff~~<br>~~Ff~~<br>~~-—~~|||~~||~~<br>~~**|**~~|~~**|**|~~|||||||~~Ff~~|~~|~~|~~|~~||
|1.5 V<br>~~Ff~~<br>~~|~~<br>~~||~~|–<br>~~Ff~~<br>~~-—~~<br>~~||~~|||~~||~~<br>~~**|**~~|~~**|**|~~||||||~~|~~|||||
||0.75 V<br>~~-—~~<br>~~||~~|||~~**|**~~|~~**|**|~~||||||~~|~~|||||
_Note: White box: Allowable I/O standard combinations Gray box: Illegal I/O standard combinations_
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## **Features Supported on Pro I/Os**
Table 2-72 lists all features supported by transmitter/receiver for single-ended and differential I/Os.
## _**Table 2-72 •**_ **Fusion Pro I/O Features**
|**Feature**|**Description**|
|---|---|
|Single-ended<br>and<br>voltage-<br>referenced transmitter<br>features|•<br>Hot insertion in every mode except PCI or 5 V input tolerant (these modes use<br>clamp diodes and do not allow hot insertion)|
||•<br>Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.|
||•<br>Weak pull-up and pull-down|
||•<br>Two slew rates|
||•<br>Skew between output buffer enable/disable time: 2 ns delay (rising edge) and<br>0 ns delay (falling edge); see"Selectable Skew between Output Buffer<br>Enable/Disable Time" on page 2-149for more information|
||•<br>Five drive strengths|
||•<br>5 V–tolerant receiver ("5 V Input Tolerance" section on page 2-144)|
||•<br>LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs ("5 V Output<br>Tolerance" section on page 2-148)|
||•<br>High performance (Table 2-76 on page 2-143)|
|Single-ended receiver features|•<br>Schmitt trigger option|
||•<br>ESD protection|
||•<br>Programmable delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns<br>with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)|
||•<br>High performance (Table 2-76 on page 2-143)|
||•<br>Separate ground planes, GND/GNDQ, for input buffers only to avoid output-<br>induced noise in the input circuitry|
|Voltage-referenced<br>differential<br>receiver features|•<br>Programmable Delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns<br>with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)|
||•<br>High performance (Table 2-76 on page 2-143)|
||•<br>Separate ground planes, GND/GNDQ, for input buffers only to avoid output-<br>induced noise in the input circuitry|
|CMOS-style<br>LVDS,<br>BLVDS,<br>M-LVDS, or LVPECL<br>transmitter|•<br>Two I/Os and external resistors are used to provide a CMOS-style LVDS,<br>BLVDS, M-LVDS, or LVPECL transmitter solution.|
||•<br>Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.|
||•<br>Weak pull-up and pull-down|
||•<br>Fast slew rate|
|LVDS/LVPECL differential<br>receiver features|•<br>ESD protection|
||•<br>High performance (Table 2-76 on page 2-143)|
||•<br>Programmable delay: 0.625 ns with '000' setting, 6.575 ns with '111' setting,<br>0.85-ns intermediate delay increments (at 25°C, 1.5 V)|
||•<br>Separate input buffer ground and power planes to avoid output-induced noise<br>in the input circuitry|
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_**Table 2-73 •**_ **Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os; All I/O Bank Types (maximum drive strength and high slew selected)**
|**Specification**|**Performance Up To**|
|---|---|
|LVTTL/LVCMOS 3.3 V|200 MHz|
|LVCMOS 2.5 V|250 MHz|
|LVCMOS 1.8 V|200 MHz|
|LVCMOS 1.5 V|130 MHz|
|PCI|200 MHz|
|PCI-X|200 MHz|
|HSTL-I|300 MHz|
|HSTL-II|300 MHz|
|SSTL2-I|300 MHz|
|SSTL2-II|300 MHz|
|SSTL3-I|300 MHz|
|SSTL3-II|300 MHz|
|GTL+ 3.3 V|300 MHz|
|GTL+ 2.5 V|300 MHz|
|GTL 3.3 V|300 MHz|
|GTL 2.5 V|300 MHz|
|LVDS|350 MHz|
|LVPECL|300 MHz|
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## **I/O Registers**
Each I/O module contains several input, output, and enable registers. Refer to Figure 2-100 for a simplified representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in Figure 2-100) between registers to implement single or differential data transmission to and from the FPGA core. The Designer software sets these switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy some rules.
**==> picture [459 x 394] intentionally omitted <==**
**----- Start of picture text -----**<br>
I/O / Q0 1 2<br>Input Input<br>Reg Reg<br>Y<br>R a e Pull-Up/Down<br>Resistor Control<br>CLR/PRE<br>To FPGA Core<br>| I/O / Q1 3 th| | | =<br>Input PAD<br>ICE Reg<br>Ir Le.<br>CLR/PRE<br>I/O / ICLK Signal Drive Strength<br>and Slew-Rate Control<br>A E = Enable Pin<br>P i$<br>a<br>I/O / D0 4<br>OCE Output<br>Reg<br>From FPGA Core CLR/PRE<br>. I/O / D1 / ICE ieres 5<br>ICE Output<br>Reg<br>I/O / OCLK a e CLR/PRE<br>I/O / OE i m e 6<br>OCE Output<br>Enable<br>Reg<br>a a<br>I/O / CLR or I/O / PRE / OCE Tey CLR/PRE<br>**----- End of picture text -----**<br>
_Note: Fusion I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-139 for more information)._
_**Figure 2-100 •**_ **I/O Block Logical Representation**
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## **Double Data Rate (DDR) Support**
Fusion Pro I/Os support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity requirements, making it very efficient for implementing very high-speed systems.
DDR interfaces can be implemented using HSTL, SSTL, LVDS, and LVPECL I/O standards. In addition, high-speed DDR interfaces can be implemented using LVDS I/O.
## _**Input Support for DDR**_
The basic structure to support a DDR input is shown in Figure 2-101. Three input registers are used to capture incoming data, which is presented to the core on each rising edge of the I/O register clock. Each I/O tile on Fusion devices supports DDR inputs.
## _**Output Support for DDR**_
The basic DDR output structure is shown in Figure 2-102 on page 2-140. New data is presented to the output every half clock cycle. Note: DDR macros and I/O registers do not require additional routing. The combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the edge of the chip. The routing delay from the I/O registers to the I/O buffers is already taken into account in the DDR macro.
Refer to the application note _Using DDR for Fusion Devices_ for more information.
**==> picture [294 x 234] intentionally omitted <==**
**----- Start of picture text -----**<br>
Input DDR<br>A<br>D<br>Data Out_QF<br>(to core)<br>INBUF<br>FF1<br>B E<br>Out_QR<br>CLK<br>(to core)<br>CLKBUF<br>FF2<br>C<br>CL R<br>INBUF DDR_IN<br>**----- End of picture text -----**<br>
_**Figure 2-101 •**_ **DDR Input Register Support in Fusion Devices**
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**==> picture [353 x 218] intentionally omitted <==**
**----- Start of picture text -----**<br>
A<br>Data_F<br>(from core)<br>FF1<br>Out<br>B<br>CLK 0<br>CLKBUF E<br>C<br>OUTBUF<br>Data_R D 1<br>(from core)<br>FF2<br>B<br>CLR<br>INBUF<br>C<br>DDR_OUT<br>**----- End of picture text -----**<br>
_**Figure 2-102 •**_ **DDR Output Support in Fusion Devices**
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_Device Architecture_
## **Hot-Swap Support**
Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered-up system. The levels of hot-swap support and examples of related applications are described in Table 2-74. The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required.
_**Table 2-74 •**_ **Levels of Hot-Swap Support**
|**Hot**<br>**Swapping**<br>**Level**|**Description**|**Power**<br>**Applied**<br>**to Device **|**Bus State**|**Card**<br>**Ground**<br>**Connection**|**Device**<br>**Circuitry**<br>**Connected**<br>**to Bus Pins**|**Example of**<br>**Application with**<br>**Cards that Contain**<br>**Fusion Devices**|**Compliance of**<br>**Fusion Devices**|
|---|---|---|---|---|---|---|---|
|1|Cold-swap|No|–|–|–|System and card with<br>Microsemi FPGA chip<br>are powered down,<br>then card gets<br>plugged into system,<br>then power supplies<br>are turned on for<br>system but not for<br>FPGA on card.|Compliant I/Os<br>can but do not<br>have to be set to<br>hot insertion<br>mode.|
|2|Hot-swap<br>while reset|Yes|Held in<br>reset state|Must be made<br>and<br>maintained for<br>1 ms before,<br>during, and<br>after insertion/<br>removal|–|In PCI hot plug<br>specification, reset<br>control circuitry<br>isolates the card<br>busses until the card<br>supplies are at their<br>nominal operating<br>levels and stable.|Compliant I/Os<br>can but do not<br>have to be set to<br>hot insertion<br>mode.|
|3|Hot-swap<br>while bus<br>idle|Yes|Held idle<br>(no ongoing<br>I/O<br>processes<br>during<br>insertion/re<br>moval)|Same as<br>Level 2|Must remain<br>glitch-free<br>during<br>power-up or<br>power-down|Must remain<br>Board bus shared<br>with card bus is<br>"frozen," and there is<br>no toggling activity on<br>bus. It is critical that<br>the logic states set on<br>the bus signal do not<br>get disturbed during<br>card<br>insertion/removal.|Compliant with<br>cards with two<br>levels of staging.<br>I/Os have to be<br>set to hot<br>insertion mode.|
|4|Hot-swap on<br>an active<br>bus|Hot-swap on<br>Yes|Bus may<br>have active<br>I/O<br>processes<br>ongoing,<br>but device<br>being<br>inserted or<br>removed<br>must be<br>idle.|Same as<br>Level 2|Same as<br>Level 3|There is activity on<br>the system bus, and it<br>is critical that the logic<br>states set on the bus<br>signal do not get<br>disturbed during card<br>insertion/removal.|Compliant with<br>cards with two<br>levels of staging.<br>I/Os have to be<br>set to hot<br>insertion mode.|
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For Fusion devices requiring Level 3 and/or Level 4 compliance, the board drivers connected to Fusion I/Os need to have 10 k (or lower) output drive resistance at hot insertion, and 1 k (or lower) output drive resistance at hot removal. This is the resistance of the transmitter sending a signal to the Fusion I/O, and no additional resistance is needed on the board. If that cannot be assured, three levels of staging can be used to meet Level 3 and/or Level 4 compliance. Cards with two levels of staging should have the following sequence:
1. Grounds
2. Powers, I/Os, other pins
## **Cold-Sparing Support**
Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically connected to the system that is in operation. This means that all input buffers of the subsystem must present very high input impedance with no power applied so as not to disturb the operating portion of the system.
Pro I/O banks and standard I/O banks fully support cold-sparing.
For Pro I/O banks, standards such as PCI that require I/O clamp diodes, can also achieve cold-sparing compliance, since clamp diodes get disconnected internally when the supplies are at 0 V.
For Advanced I/O banks, since the I/O clamp diode is always active, cold-sparing can be accomplished either by employing a bus switch to isolate the device I/Os from the rest of the system or by driving each advanced I/O pin to 0 V.
If Standard I/O banks are used in applications requiring cold-sparing, a discharge path from the power supply to ground should be provided. This can be done with a discharge resistor or a switched resistor. This is necessary because the standard I/O buffers do not have built-in I/O clamp diodes.
If a resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitor is in parallel with the resistor). The RC time constant should ensure full discharge of supplies before cold-sparing functionality is required. The resistor is necessary to ensure that the power pins are discharged to ground every time there is an interruption of power to the device.
I/O cold-sparing may add additional current if the pin is configured with either a pull-up or pull down resistor and driven in the opposite direction. A small static current is induced on each IO pin when the pin is driven to a voltage opposite to the weak pull resistor. The current is equal to the voltage drop across the input pin divided by the pull resistor. Please refer to Table 2-95 on page 2-169, Table 2-96 on page 2-169, and Table 2-97 on page 2-171 for the specific pull resistor value for the corresponding I/O standard.
For example, assuming an LVTTL 3.3 V input pin is configured with a weak Pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven low. For an LVTTL 3.3 V, pull-up resistor is ~45 k and the resulting current is equal to 3.3 V / 45 k = 73 µA for the I/O pin. This is true also when a weak pull-down is chosen and the input pin is driven high. Avoiding this current can be done by driving the input low when a weak pull-down resistor is used, and driving it high when a weak pull-up resistor is used.
In Active and Static modes, this current draw can occur in the following cases:
- Input buffers with pull-up, driven low
- Input buffers with pull-down, driven high
- Bidirectional buffers with pull-up, driven low
- Bidirectional buffers with pull-down, driven high
- Output buffers with pull-up, driven low
- Output buffers with pull-down, driven high
- Tristate buffers with pull-up, driven low
- Tristate buffers with pull-down, driven high
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## **Electrostatic Discharge (ESD) Protection**
Fusion devices are tested per JEDEC Standard JESD22-A114-B.
Fusion devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage transients.
Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative (N) side connected to VCCI. The second diode has its P side connected to GND and its N side connected to the pad. During operation, these diodes are normally biased in the Off state, except when transient voltage is significantly above VCCI or below GND levels.
By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 2-75 and Table 2-76 on page 2-143 for more information about I/O standards and the clamp diode.
The second diode is always connected to the pad, regardless of the I/O configuration selected.
_**Table 2-75 •**_ **Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance Capabilities**
|**I/O Assignment**<br>~~a~~ <br>~~es~~|**Clamp Diode**<br>~~es~~<br>~~ce~~~~**e**e~~|**Clamp Diode**<br>~~es~~<br>~~ce~~~~**e**e~~|**Hot Insertion**<br>~~es~~<br>~~ee~~<br>~~**e**eee~~|**Hot Insertion**<br>~~es~~<br>~~ee~~<br>~~**e**eee~~|**5 V Input Tolerance 1**<br>~~es~~<br>~~ee~~|**5 V Input Tolerance 1**<br>~~es~~<br>~~ee~~|**Input**<br>**Buffer**<br>~~ee~~|**Output**<br>**Buffer**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
||**Standard**<br>**I/O**<br> ~~ce~~<br>~~ee~~|**Advanced**<br>**I/O**<br>~~**e**e~~<br>~~Gers~~|**Advanced**<br>**Standard**<br>**I/O**<br>~~ee~~<br>~~**e**e~~<br>~~Grs~~|**Advanced**<br>**I/O**<br>~~ee~~<br>~~ee~~<br>~~rere~~|**Standard**<br>**I/O**<br>~~ee~~<br>~~nt~~|**Advanced**<br>**I/O**<br>~~ee~~<br>~~tn~~|||
|3.3 V LVTTL/LVCMOS<br> <br>~~es~~|No<br> ~~ce~~<br>~~ee~~|Yes<br>~~**e**e~~<br>~~Gers~~|Yes<br>~~**e**e~~<br>~~Grs~~|No<br>~~ee~~<br>~~rere~~|Yes1<br>~~ee~~<br>~~nt~~|Yes1<br>~~ee~~<br>~~tn~~|Enabled/Disabled<br>~~ee~~||
|3.3 V PCI, 3.3 V PCI-X<br> <br>~~es~~<br>~~Po~~|N/A<br> ~~ce ~~<br>~~ee ~~<br>~~Po~~|Yes<br> ~~**e**e ~~<br> ~~G ers ~~<br>~~Po~~|N/A<br> ~~**e**e ~~<br> ~~G rs ~~<br>~~Po~~|No<br> ~~ee~~<br> ~~rere~~<br>~~Po~~|N/A<br>~~ee~~<br>~~nt ~~<br>~~Po~~|Yes1<br>~~ee~~<br> ~~tn~~<br>~~Po~~|Enabled/Disabled<br>~~ee~~<br>~~Po~~||
|LVCMOS 2.5 V<br>~~Po~~|No<br>~~Po~~|Yes<br>~~Po~~|Yes<br>~~Po~~|No<br>~~Po~~|No<br>~~Po~~|No<br>~~Po~~|Enabled/Disabled<br>~~Po~~||
|LVCMOS 2.5 V / 5.0 V<br>~~Po~~|N/A<br>~~Po~~|Yes<br>~~Po~~|N/A<br>~~Po~~|No<br>~~Po~~|N/A<br>~~Po~~|Yes2<br>~~Po~~|Enabled/Disabled<br>~~Po~~||
|LVCMOS 1.8 V<br>~~Po~~|No<br>~~Po~~|Yes<br>~~Po~~|Yes<br>~~Po~~|No<br>~~Po~~|No<br>~~Po~~|No<br>~~Po~~|Enabled/Disabled<br>~~Po~~||
|LVCMOS 1.5 V<br>~~Ft~~|No<br>~~Fttt~~|Yes<br>~~tt~~|Yes<br>~~ttEE~~|No<br>~~EE~~|No<br>~~EE~~|No|Enabled/Disabled||
|Differential,<br>LVDS/BLVDS/M-<br>LVDS/ LVPECL3<br>~~Ft~~|N/A<br>~~Fttt~~|Yes<br>~~tt~~|N/A<br>~~ttEE~~|No<br>~~EE~~|N/A<br>~~EE~~|No|Enabled/Disabled||
## _Notes:_
_1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor._
_2. Can be implemented with an external resistor and an internal clamp diode._
_3. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers._
_**Table 2-76 •**_ **Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities**
|**I/O Assignment**<br>~~eS~~|**Clamp**<br>**Diode**<br>~~eS~~<br>~~(rrr~~|**Hot**<br>**Insertion**<br>~~eS~~<br>~~rs~~|**5 V Input**<br>**Tolerance**<br>~~eS~~<br>~~Uns~~|**Input Buffer**<br>~~eS~~|**Output Buffer**<br>~~eS~~|
|---|---|---|---|---|---|
|3.3 V LVTTL/LVCMOS<br>~~rr~~|No<br>~~rr~~<br>~~(rrr~~<br>~~errr~~|Yes<br>~~rr~~<br>~~rs~~<br>~~rents~~|Yes1<br>~~rr~~<br>~~Uns~~<br>~~nts~~|Enabled/Disabled<br>~~rr~~||
|3.3 V PCI, 3.3 V PCI-X<br>~~rr~~<br>~~rs~~|Yes<br>~~rr~~<br>~~(rrr ~~<br>~~rs~~<br>~~errr~~|No<br>~~rr~~<br> ~~rs ~~<br>~~rs~~<br>~~rents~~<br>~~rs~~|Yes1<br>~~rr~~<br> ~~Uns~~<br>~~rs~~<br>~~nts~~<br>~~ns~~|Enabled/Disabled<br>~~rr~~<br>~~rs~~<br>~~ns~~||
|LVCMOS 2.5 V3<br>~~(Rr~~|No<br>~~errr~~<br>~~(Rr~~<br>~~errr~~|Yes<br>~~rents~~<br>~~(Rr~~<br>~~rs~~<br>~~rents~~|No<br>~~nts~~<br>~~(Rr~~<br>~~ns~~<br>~~nts~~|Enabled/Disabled<br>~~(Rr~~<br>~~ns~~||
|LVCMOS 2.5 V / 5.0 V3<br>~~(Rr~~<br>~~rs~~|Yes<br>~~(Rr~~<br>~~rs~~<br>~~errr~~|No<br>~~(Rr~~<br>~~rs~~<br>~~rs~~<br>~~rents~~<br>~~rs~~|Yes2<br>~~(Rr~~<br>~~ns~~<br>~~rs~~<br>~~nts~~<br>~~ns~~|Enabled/Disabled<br>~~(Rr~~<br>~~ns~~<br>~~rs~~<br>~~ns~~||
|LVCMOS 1.8 V<br>~~(Rr~~|No<br>~~errr~~<br>~~(Rr~~<br>~~errr~~|Yes<br>~~rents~~<br>~~(Rr~~<br>~~rs~~<br>~~rents~~|No<br>~~nts~~<br>~~(Rr~~<br>~~ns~~<br>~~nts~~|Enabled/Disabled<br>~~(Rr~~<br>~~ns~~||
|LVCMOS 1.5 V<br>~~(Rr~~<br>~~rs~~|No<br>~~(Rr~~<br>~~rs~~<br>~~errr~~|Yes<br>~~(Rr~~<br>~~rs~~<br>~~rs~~<br>~~rents~~<br>~~rs~~|No<br>~~(Rr~~<br>~~ns~~<br>~~rs~~<br>~~nts~~<br>~~ns~~|Enabled/Disabled<br>~~(Rr~~<br>~~ns~~<br>~~rs~~<br>~~ns~~||
|Voltage-Referenced Input Buffer<br>~~(Rr~~|No<br>~~errr~~<br>~~(Rr~~<br>~~rrr~~|Yes<br>~~rents~~<br>~~(Rr~~<br>~~rs~~<br>~~es~~|No<br>~~nts~~<br>~~(Rr~~<br>~~ns~~<br>~~ts~~|Enabled/Disabled<br>~~(Rr~~<br>~~ns~~||
|Differential, LVDS/BLVDS/M-LVDS/LVPECL4<br>~~(Rr~~<br>~~ny~~|No<br>~~(Rr~~<br>~~ny~~<br>~~rrr~~|Yes<br>~~(Rr~~<br>~~rs~~<br>~~ny~~<br>~~es~~|No<br>~~(Rr~~<br>~~ns~~<br>~~ny~~<br>~~ts~~|Enabled/Disabled<br>~~(Rr~~<br>~~ns~~<br>~~ny~~||
## _Notes:_
_1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor._
_2. Can be implemented with an external resistor and an internal clamp diode._
_3. In the_ SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User Guide _, select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O standard._
_4. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers._
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## **5 V Input Tolerance**
I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V / 5 V, and LVCMOS 2.5 V configurations are used (see Table 2-77 on page 2-147 for more details). There are four recommended solutions (see Figure 2-103 to Figure 2-106 on page 2-146 for details of board and macro setups) to achieve 5 V receiver tolerance. All the solutions meet a common requirement of limiting the voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any voltage above 3.6 V may cause long-term gate oxide failures.
## _**Solution 1**_
The board-level design needs to ensure that the reflected waveform at the pad does not exceed the limits provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI / PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the two external resistors, as explained below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
The following are some examples of possible resistor values (based on a simplified simulation model with no line effects and 10 transmitter output resistance, where Rtx_out_high = (VCCI – VOH) / IOH, Rtx_out_low = VOL / IOL).
Example 1 (high speed, high current):
Rtx_out_high = Rtx_out_low = 10
- R1 = 36 (±5%), P(r1)min = 0.069
- R2 = 82 (±5%), P(r2)min = 0.158
Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 + 10) = 45.04 mA
- tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin)
- tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin)
Example 2 (low–medium speed, medium current):
- Rtx_out_high = Rtx_out_low = 10
- R1 = 220 (±5%), P(r1)min = 0.018
- R2 = 390 (±5%), P(r2)min = 0.032
- Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 + 10) = 9.17 mA
- tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin)
- tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin)
Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This range of Vin_dc(rx) must be assured for any combination of transmitter supply (5 V ± 0.5 V), transmitter output resistance, and board resistor tolerances.
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Temporary overshoots are allowed according to Table 3-4 on page 3-4.
**==> picture [188 x 207] intentionally omitted <==**
**----- Start of picture text -----**<br>
Solution 1<br>Fusion I/O Input<br>Off-Chip On-Chip<br>gl 5.5 V 3.3 V<br>Rext1<br>Rext2<br>Requires two board resistors,<br>LVCMOS 3.3 V I/Os<br>**----- End of picture text -----**<br>
_**Figure 2-103 •**_ **Solution 1**
## _**Solution 2**_
The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and Zener, as shown in Figure 2- 104. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
**==> picture [197 x 226] intentionally omitted <==**
**----- Start of picture text -----**<br>
Solution 2<br>Fusion I/O Input<br>Off-Chip On-Chip<br>3.3 V<br>5.5 V<br>|<br>Rext1<br>Zener<br>3.3 V<br>Requires one board resistor, one<br>Zener 3.3 V diode, LVCMOS 3.3 V I/Os<br>**----- End of picture text -----**<br>
_**Figure 2-104 •**_ **Solution 2**
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## _**Solution 3**_
The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in Figure 2-105. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
**==> picture [225 x 226] intentionally omitted <==**
**----- Start of picture text -----**<br>
Solution 3<br>Fusion I/O Input<br>Off-Chip On-Chip<br>3.3 V<br>Bus<br>Switch<br>IDTQS32X23<br>5.5 V<br>5.5 V<br>Requires a bus switch on the board,<br>LVTTL/LVCMOS 3.3 V I/Os.<br>**----- End of picture text -----**<br>
_**Figure 2-105 •**_ **Solution 3**
## _**Solution 4**_
**==> picture [233 x 205] intentionally omitted <==**
**----- Start of picture text -----**<br>
Solution 4<br>Fusion I/O Input<br>Off-Chip On-Chip<br>5.5 V 2.5 V On-Chip 2.5 V<br>Clamp<br>Diode<br>gl<br>Rext1<br>Requires one board resistor.<br>Available for LVCMOS 2.5 V / 5.0 V.<br>**----- End of picture text -----**<br>
_**Figure 2-106 •**_ **Solution 4**
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_**Table 2-77 •**_ **Comparison Table for 5 V–Compliant Receiver Scheme**
|**Scheme**|**Board Components**|**Speed**|**Current Limitations**|
|---|---|---|---|
|1|Two resistors|Low to high1|Limited by transmitter's drive strength|
|2|Resistor and Zener 3.3 V|Medium|Limited by transmitter's drive strength|
|3|Bus switch|High|N/A|
|4|Minimum resistor value2<br>R = 47at TJ= 70°C<br>R = 150at TJ= 85°C<br>R = 420at TJ= 100°C|Medium|Maximum diode current at 100% duty cycle, signal constantly at<br>'1'<br>52.7 mA at TJ=70°C / 10-year lifetime<br>16.5 mA at TJ= 85°C / 10-year lifetime<br>5.9 mA at TJ= 100°C / 10-year lifetime<br>For duty cycles other than 100%, the currents can be increased<br>by a factor = 1 / (duty cycle).<br>Example: 20% duty cycle at 70°C<br>Maximum current = (1 / 0.2) * 52.7 mA = 5 * 52.7 mA = 263.5 mA|
_Notes:_
_1. Speed and current consumption increase as the board resistance values decrease._
_2. Resistor values ensure I/O diode long-term reliability._
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## **5 V Output Tolerance**
Fusion I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad voltage beyond the 3.6 V absolute maximum value and consequently cause damage to the I/O.
When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, Fusion I/Os can directly drive signals into 5 V TTL receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceed the VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level '1' and level '0' will be recognized correctly by 5 V TTL receivers.
## **Simultaneously Switching Outputs and PCB Layout**
- Simultaneously switching outputs (SSOs) can produce signal integrity problems on adjacent signals that are not part of the SSO bus. Both inductive and capacitive coupling parasitics of bond wires inside packages and of traces on PCBs will transfer noise from SSO busses onto signals adjacent to those busses. Additionally, SSOs can produce ground bounce noise and VCCI dip noise. These two noise types are caused by rapidly changing currents through GND and VCCI package pin inductances during switching activities:
- Ground bounce noise voltage = L(GND) * di/dt
- VCCI dip noise voltage = L(VCCI) * di/dt
Any group of four or more input pins switching on the same clock edge is considered an SSO bus. The shielding should be done both on the board and inside the package unless otherwise described.
In-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to be adequately shielded from mutual coupling and inductive noise that can be generated by the SSO bus. Also, noise generated by the SSO bus needs to be reduced inside the package.
PCBs perform an important function in feeding stable supply voltages to the IC and, at the same time, maintaining signal integrity between devices.
Key issues that need to considered are as follows:
- Power and ground plane design and decoupling network design
- Transmission line reflections and terminations
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## **Selectable Skew between Output Buffer Enable/Disable Time**
The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion (disable) time.
**==> picture [364 x 144] intentionally omitted <==**
**----- Start of picture text -----**<br>
Output Enable ENABLE (IN)<br>(from FPGA core)<br> ENABLE (OUT)<br> MUX<br>Skew Circuit<br>I/O Output<br>Buffers<br> Skew Select<br>**----- End of picture text -----**<br>
_**Figure 2-107 •**_ **Block Diagram of Output Enable Path**
**==> picture [266 x 94] intentionally omitted <==**
**----- Start of picture text -----**<br>
ENABLE (IN)<br>ENABLE (OUT)<br>Less than Less than<br>0.1 ns 0.1 ns<br>**----- End of picture text -----**<br>
_**Figure 2-108 •**_ **Timing Diagram (option1: bypasses skew circuit)**
**==> picture [264 x 104] intentionally omitted <==**
**----- Start of picture text -----**<br>
ENABLE (IN)<br>ENABLE (OUT)<br>1.2 ns<br>(typical)<br>Less than<br>0.1 ns<br>**----- End of picture text -----**<br>
_**Figure 2-109 •**_ **Timing Diagram (option 2: enables skew circuit)**
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At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention and subsequent data loss or transmitter over-stress due to transmitter-totransmitter current shorts. Figure 2-110 presents an example of the skew circuit implementation in a bidirectional communication system. Figure 2-111 shows how bus contention is created, and Figure 2- 112 on page 2-151 shows how it can be avoided with the skew circuit.
**==> picture [432 x 496] intentionally omitted <==**
**----- Start of picture text -----**<br>
Transmitter<br>ENABLE/<br>Transmitter 1: Fusion I/O DISABLE Transmitter 2: Generic I/O<br>Skew or Routing Routing<br>[ Bypass EN(r1) Ld Delay (t1) EN(b1) = EN(b2) | Delay (t2) ENABLE(t2)<br>Skew<br>ENABLE(t1)<br>Bidirectional Data Bus<br>pte<br>a<br>Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using<br>Fusion Devices<br>EN (b1)<br>ee es ee<br>EN (b2)<br>SS<br>ENABLE (r1)<br>en<br>ENABLE (t1)<br>ee<br>Transmitter 1: OFF Transmitter 1: ON Transmitter 1: OFF<br>ENABLE (t2)<br>Transmitter 2: ON Transmitter 2: OFF<br>ae Bus Se Ga<br>Contention<br>**----- End of picture text -----**<br>
_**Figure 2-110 •**_ **Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using Fusion Devices**
_**Figure 2-111 •**_ **Timing Diagram (bypasses skew circuit)**
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**==> picture [399 x 274] intentionally omitted <==**
**----- Start of picture text -----**<br>
EN (b1)<br>ee<br>EN (b2)<br>— oo<br>ENABLE (t1) ee ee<br>Transmitter 1: OFF Transmitter 1: ON Transmitter 1: OFF<br>ee<br>ENABLE (t2)<br>ee aee eeee<br>Transmitter 2: ON Transmitter 2: OFF<br>es ee<br>Result: No Bus Contention<br>**----- End of picture text -----**<br>
_**Figure 2-112 •**_ **Timing Diagram (with skew circuit selected)**
## **Weak Pull-Up and Weak Pull-Down Resistors**
Fusion devices support optional weak pull-up and pull-down resistors for each I/O pin. When the I/O is pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled down, it is connected to GND. Refer to Table 2-97 on page 2-171 for more information.
## **Slew Rate Control and Drive Strength**
Fusion devices support output slew rate control: high and low. The high slew rate option is recommended to minimize the propagation delay. This high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of noise but adds some delays in the system. Low slew rate is recommended when bus transients are expected. Drive strength should also be selected according to the design requirements and noise immunity of the system.
The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O standards have a high output slew rate by default.
For Fusion slew rate and drive strength specifications, refer to the appropriate I/O bank table:
- Fusion Standard I/O (Table 2-78 on page 2-152)
- Fusion Advanced I/O (Table 2-79 on page 2-152)
- Fusion Pro I/O (Table 2-80 on page 2-152)
Table 2-83 on page 2-155 lists the default values for the above selectable I/O attributes as well as those that are preset for each I/O standard.
Refer to Table 2-78, Table 2-79, and Table 2-80 on page 2-152 for SLEW and OUT_DRIVE settings. Table 2-81 on page 2-153 and Table 2-82 on page 2-154 list the I/O default attributes. Table 2-83 on page 2-155 lists the voltages for the supported I/O standards.
**2-151**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-78 •**_ **Fusion Standard I/O Standards—OUT_DRIVE Settings**
|**I/O Standards**|**OUT_DRIVE (mA)**|**OUT_DRIVE (mA)**|**OUT_DRIVE (mA)**|**OUT_DRIVE (mA)**|**OUT_DRIVE (mA)**|**OUT_DRIVE (mA)**|
|---|---|---|---|---|---|---|
||**2**|**4**|**6**|**8**|**Slew**||
|LVTTL/LVCMOS 3.3 V|||||High|Low|
|LVCMOS 2.5 V|||||High|Low|
|LVCMOS 1.8 V|||–|–|High|Low|
|LVCMOS 1.5 V||–|–|–|High|Low|
_**Table 2-79 •**_ **Fusion Advanced I/O Standards—SLEW and OUT_DRIVE Settings**
|**_Table 2-79 •_Fusion Advanced I/O Standards—SLEW and OUT_DRIVE Settings**|**_Table 2-79 •_Fusion Advanced I/O Standards—SLEW and OUT_DRIVE Settings**|||||
|---|---|---|---|---|---|
|**OUT_DRIVE (mA)**||||||
|**I/O Standards**<br>**2**<br>**4**<br>**6**<br>**8**|**12**||**16**||**Slew**|
|LVTTL/LVCMOS 3.3 V<br><br><br><br>|||||High<br>Low|
|LVCMOS 2.5 V<br><br><br><br>|||–||High<br>Low|
|LVCMOS 1.8 V<br><br><br><br>|–||–||High<br>Low|
|LVCMOS 1.5 V<br><br><br>–<br>–|–||–||High<br>Low|
|**_Table 2-80 •_Fusion Pro I/O Standards—SLEW and OUT_DRIVE Settings**||||||
|**I/O Standards**<br>**OUT_DRIVE (mA)**<br>**Slew**<br>**2**<br>**4**<br>**6**<br>**8**<br>**12**<br>**16**<br>**24**<br>LVTTL/LVCMOS 3.3 V<br><br><br><br><br><br><br><br>High<br>Low<br>LVCMOS 2.5 V<br><br><br><br><br><br><br><br>High<br>Low<br>LVCMOS 2.5 V/5.0 V<br><br><br><br><br><br><br><br>High<br>Low<br>LVCMOS 1.8 V<br><br><br><br><br><br><br>–<br>High<br>Low<br>LVCMOS 1.5 V<br><br><br><br><br><br>–<br>–<br>High<br>Low<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~ee ee ee ee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~ee ee ee~~<br>~~ee ee ee~~<br>~~ee~~<br>~~ee~~<br>~~eseeeees~~||||||
_**Table 2-80 •**_ **Fusion Pro I/O Standards—SLEW and OUT_DRIVE Settings**
**Revision 8**
**2-152**
_Device Architecture_
_**Table 2-81 •**_ **Fusion Pro I/O Default Attributes**
|**I/O Standards**|**SLEW**<br>**(output only)**|**OUT_DRIVE**<br>**(output only)**|**SKEW (tribuf and bibuf only)**|**RES_PULL**|**OUT_LOAD (output only)**|**COMBINE_REGISTER**|**IN_DELAY (input only)**|**IN_DELAY_VAL (input only)**|**SCHMITT_TRIGGER (input only)**|
|---|---|---|---|---|---|---|---|---|---|
|LVTTL/LVCMO<br>S 3.3 V|Refer to the following<br>tables for more<br>information:<br>Table 2-78 on page 2-152<br>Table 2-79 on page 2-152<br>Table 2-80 on page 2-152|Refer to the following<br>tables for more<br>information:<br>Table 2-78 on page 2-152<br>Table 2-79 on page 2-152<br>Table 2-80 on page 2-152|Off|None|35 pF|–|Off|0|Off|
|LVCMOS 2.5 V<br>~~—~~|||Off<br>~~TT~~|None<br>~~TT~~|35 pF<br>~~TT~~|–<br>~~TT~~|Off<br>~~TT~~|0<br>~~TT~~|Off<br>~~TT~~|
|LVCMOS<br>2.5/5.0 V<br>~~—~~<br>~~|~~|||Off<br>~~TT~~<br>~~Pt~~|None<br>~~TT~~<br>~~Pt~~<br>~~[|~~|35 pF<br>~~TT~~<br>~~[|~~<br>~~Tt~~|–<br>~~TT~~<br>~~Tt~~|Off<br>~~TT~~<br>~~Tt~~|0<br>~~TT~~|Off<br>~~TT~~|
|LVCMOS 1.8 V<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~Pt~~|None<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~tf~~|35 pF<br>~~[|~~<br>~~Tt~~<br>~~tf~~<br>~~Ty~~|–<br>~~Tt~~<br>~~Ty~~|Off<br>~~Tt~~<br>~~Ty~~|0|Off|
|LVCMOS 1.5 V<br>~~|~~<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~Pt~~<br>~~PT~~|None<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~tf~~<br>~~PT~~<br>~~|~~|35 pF<br>~~[|~~<br>~~Tt~~<br>~~tf~~<br>~~Ty~~<br>~~Ty~~|–<br>~~Tt~~<br>~~Ty~~<br>~~Ty~~|Off<br>~~Tt~~<br>~~Ty~~<br>~~Ty~~|0|Off|
|PCI (3.3 V)<br>~~|~~<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~PT~~<br>~~Pt~~|None<br>~~Pt~~<br>~~tf~~<br>~~PT~~<br>~~|~~<br>~~Pt~~<br>~~[|~~|10 pF<br>~~tf~~<br>~~Ty~~<br>~~Ty~~<br>~~[|~~<br>~~ft~~|–<br>~~Ty~~<br>~~Ty~~<br>~~ft~~|Off<br>~~Ty~~<br>~~Ty~~<br>~~ftft~~|0<br>~~ft~~|Off|
|PCI-X (3.3 V)<br>~~|~~<br>~~|~~<br>~~|~~|||Off<br>~~PT~~<br>~~Pt~~<br>~~Pt~~|None<br>~~PT~~<br>~~|~~<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~[|~~|10 pF<br>~~Ty~~<br>~~[|~~<br>~~ft~~<br>~~[|~~<br>~~Tt~~|–<br>~~Ty~~<br>~~ft~~<br>~~Tt~~|Off<br>~~Ty~~<br>~~ftft~~<br>~~Tt~~|0<br>~~ft~~|Off|
|GTL+ (3.3 V)<br>~~|~~<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~Pt~~<br>~~Pt~~|None<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~[|~~|10 pF<br>~~[|~~<br>~~ft~~<br>~~[|~~<br>~~Tt~~<br>~~[|~~<br>~~fT~~|–<br>~~ft~~<br>~~Tt~~<br>~~fTft~~|Off<br>~~ft ft~~<br>~~Tt~~<br>~~ftft~~|0<br>~~ft~~<br>~~ft~~|Off|
|GTL+ (2.5 V)<br>~~|~~<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~Pt~~<br>~~Pt~~|None<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~[|~~|10 pF<br>~~[|~~<br>~~Tt~~<br>~~[|~~<br>~~fT~~<br>~~[|~~<br>~~Tt~~|–<br>~~Tt~~<br>~~fTft~~<br>~~Tt~~|Off<br>~~Tt~~<br>~~ftft~~<br>~~Tt~~|0<br>~~ft~~|Off|
|GTL (3.3 V)<br>~~|~~<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~Pt~~<br>~~Pt~~|None<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~tf~~|10 pF<br>~~[|~~<br>~~fT~~<br>~~[|~~<br>~~Tt~~<br>~~tf~~<br>~~Ty~~|–<br>~~fT ft~~<br>~~Tt~~<br>~~Ty~~|Off<br>~~ft ft~~<br>~~Tt~~<br>~~Ty~~|0<br>~~ft~~|Off|
|GTL (2.5 V)<br>~~|~~<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~Pt~~<br>~~PT~~|None<br>~~Pt~~<br>~~[|~~<br>~~Pt~~<br>~~tf~~<br>~~PT~~<br>~~|~~|10 pF<br>~~[|~~<br>~~Tt~~<br>~~tf~~<br>~~Ty~~<br>~~Ty~~|–<br>~~Tt~~<br>~~Ty~~<br>~~Ty~~|Off<br>~~Tt~~<br>~~Ty~~<br>~~Ty~~|0|Off|
|HSTL Class I<br>~~|~~<br>~~|~~|||Off<br>~~Pt~~<br>~~PT~~|None<br>~~Pt~~<br>~~tf~~<br>~~PT~~<br>~~|~~|20 pF<br>~~tf~~<br>~~Ty~~<br>~~Ty~~|–<br>~~Ty~~<br>~~Ty~~|Off<br>~~Ty~~<br>~~Ty~~|0|Off|
|HSTL Class II<br>~~|~~<br>~~—~~|||Off<br>~~PT~~<br>~~TT~~|None<br>~~PT~~<br>~~|~~<br>~~TT~~|20 pF<br>~~Ty~~<br>~~TT~~|–<br>~~Ty~~<br>~~TT~~|Off<br>~~Ty~~<br>~~TT~~|0<br>~~TT~~|Off<br>~~TT~~|
|SSTL2<br>Class I and II<br>~~—~~|||Off<br>~~TT~~|None<br>~~TT~~|30 pF<br>~~TT~~|–<br>~~TT~~|Off<br>~~TT~~|0<br>~~TT~~|Off<br>~~TT~~|
|SSTL3<br>Class I and II|||Off|None|30 pF|–|Off|0|Off|
|LVDS, BLVDS,<br>M-LVDS<br>~~|~~|||Off<br>~~Pt~~|None<br>~~Pt~~<br>~~[|~~|0 pF<br>~~[|~~<br>~~[Tt~~|–<br>~~[Tt~~|Off<br>~~[Ttft~~|0<br>~~ft~~|Off|
|LVPECL<br>~~|~~|||Off<br>~~Pt~~|None<br>~~Pt~~<br>~~[|~~|0 pF<br>~~[|~~<br>~~[Tt~~|–<br>~~[Tt~~|Off<br>~~[Ttft~~|0<br>~~ft~~|Off|
**2-153**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-82 •**_ **Advanced I/O Default Attributes**
|**I/O Standards**<br>~~Pp~~|**SLEW (output only)**|**OUT_DRIVE (output only)**|**SKEW (tribuf and bibuf only)**<br>~~of~~|**RES_PULL**<br>~~offt~~|**OUT_LOAD (output only)**<br>~~ft~~|**COMBINE_REGISTER**|
|---|---|---|---|---|---|---|
|LVTTL/LVCMOS 3.3 V<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~|Refer to the following<br>tables for more<br>information:<br>Table 2-78 on page 2-152<br>Table 2-79 on page 2-152<br>Table 2-80 on page 2-152|Refer to the following tables<br>for more information:<br>Table 2-78 on page 2-152<br>Table 2-79 on page 2-152<br>Table 2-80 on page 2-152|Off<br>~~of~~<br>~~|~~|None<br>~~offt~~<br>~~|~~<br>~~|~~|35 pF<br>~~ft~~<br>~~|~~<br>~~|~~|–<br>~~|~~|
|LVCMOS 2.5 V<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~|||Off<br>~~of~~<br>~~|~~|None<br>~~of ft~~<br>~~|~~<br>~~|~~<br>~~|~~|35 pF<br>~~ft~~<br>~~|~~<br>~~|~~<br>~~|~~|–<br>~~|~~|
|LVCMOS 2.5/5.0 V<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~|||Off<br>~~|~~<br>~~|~~|None<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|35 pF<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|–<br>~~|~~<br>~~|~~|
|LVCMOS 1.8 V<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~|||Off<br>~~|~~|None<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|35 pF<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|–<br>~~|~~|
|LVCMOS 1.5 V<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~|||Off<br>~~|~~<br>~~|~~<br>~~ef~~|None<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~efft~~|35 pF<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~ft~~|–<br>~~|~~<br>~~|~~|
|PCI (3.3 V)<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~|||Off<br>~~|~~<br>~~ef~~<br>~~ef~~|None<br>~~|~~<br>~~|~~<br>~~|~~<br>~~efft~~<br>~~efft~~|10 pF<br>~~|~~<br>~~|~~<br>~~|~~<br>~~ft~~<br>~~ft~~|–<br>~~|~~|
|PCI-X (3.3 V)<br>~~Pp~~<br>~~Pp~~<br>~~Pp~~<br>~~fF~~|||Off<br>~~ef~~<br>~~ef~~|None<br>~~|~~<br>~~efft~~<br>~~efft~~<br>~~**|**~~|10 pF<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~**|**~~|–|
|LVDS, BLVDS, M-LVDS<br>~~Pp~~<br>~~Pp~~<br>~~fF~~|||Off<br>~~ef~~<br>~~ef~~<br>~~|~~|None<br>~~ef ft~~<br>~~efft~~<br>~~|~~<br>~~**|**~~|–<br>~~ft~~<br>~~ft~~<br>~~|~~<br>~~**|**~~<br>~~ft~~|–<br>~~|~~<br>~~ft~~|
|LVPECL<br>~~Pp~~<br>~~fF~~|||Off<br>~~ef~~<br>~~|~~|None<br>~~ef ft~~<br>~~**|**~~<br>~~|~~|–<br>~~ft~~<br>~~**|**~~<br>~~|~~<br>~~ft~~|–<br>~~|~~<br>~~ft~~|
**Revision 8**
**2-154**
_Device Architecture_
_**Table 2-83 •**_ **Fusion Pro I/O Supported Standards and Corresponding VREF and VTT Voltages**
|**I/O Standard**|**Input/Output Supply**<br>**Voltage (VCCI_TYP)**|**Input Reference Voltage**<br>**(VREF_TYP)**|**Board Termination Voltage**<br>**(VTT_TYP)**|
|---|---|---|---|
|LVTTL/LVCMOS 3.3 V<br>~~eG~~<br>~~a~~|3.30 V<br>~~eG~~<br>|–<br>~~eG~~<br>|–<br>~~eG~~<br>|
|LVCMOS 2.5 V<br>~~a~~|2.50 V<br>|–<br>|–<br>|
|LVCMOS 2.5 V / 5.0 V<br>Input<br>~~a~~|2.50 V<br>|–<br>|–<br>|
|LVCMOS 1.8 V<br>~~se~~|1.80 V<br>~~se~~|–<br>~~se~~|–<br>~~se~~|
|LVCMOS 1.5 V<br>~~se~~<br>~~eG~~<br>~~ee~~|1.50 V<br>~~se~~<br>~~eG~~|–<br>~~se~~<br>~~eG~~|–<br>~~se~~<br>~~eG~~|
|PCI 3.3 V<br>~~eG~~<br>~~ee~~<br>~~a~~|3.30 V<br>~~eG~~<br>|–<br>~~eG~~<br>|–<br>~~eG~~<br>|
|PCI-X 3.3 V<br>~~ee~~<br>~~a~~|3.30 V<br>|–<br>|–<br>|
|GTL+ 3.3 V<br>~~aeG~~|3.30 V<br>~~eG~~|1.00 V<br>~~eG~~|1.50 V<br>~~eG~~|
|GTL+ 2.5 V<br>~~eG~~|2.50 V<br>~~eG~~|1.00 V<br>~~eG~~|1.50 V<br>~~eG~~|
|GTL 3.3 V<br>~~se~~|3.30 V<br>~~se~~|0.80 V<br>~~se~~|1.20 V<br>~~se~~|
|GTL 2.5 V<br>~~se~~<br>~~eG~~<br>~~ee~~|2.50 V<br>~~se~~<br>~~eG~~|0.80 V<br>~~se~~<br>~~eG~~|1.20 V<br>~~se~~<br>~~eG~~|
|HSTL Class I<br>~~eG~~<br>~~ee~~<br>~~a~~|1.50 V<br>~~eG~~<br>|0.75 V<br>~~eG~~<br>|0.75 V<br>~~eG~~<br>|
|HSTL Class II<br>~~ee~~<br>~~a~~|1.50 V<br>|0.75 V<br>|0.75 V<br>|
|SSTL3 Class I<br>~~aeG~~|3.30 V<br>~~eG~~|1.50 V<br>~~eG~~|1.50 V<br>~~eG~~|
|SSTL3 Class II<br>~~eG~~|3.30 V<br>~~eG~~|1.50 V<br>~~eG~~|1.50 V<br>~~eG~~|
|SSTL2 Class I<br>~~eG~~|2.50 V<br>~~eG~~|1.25 V<br>~~eG~~|1.25 V<br>~~eG~~|
|SSTL2 Class II<br>~~eG~~<br>~~eG~~<br>~~ee~~|2.50 V<br>~~eG~~<br>~~eG~~|1.25 V<br>~~eG~~<br>~~eG~~|1.25 V<br>~~eG~~<br>~~eG~~|
|LVDS, BLVDS, M-LVDS<br>~~eG~~<br>~~ee~~|2.50 V<br>~~eG~~|–<br>~~eG~~|–<br>~~eG~~|
|LVPECL<br>~~ee~~<br>~~ee~~|3.30 V<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|
**2-155**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **I/O Software Support**
In the Fusion development software, default settings have been defined for the various I/O standards supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are applicable for all I/O standards. Table 2-84 and Table 2-85 list the valid I/O attributes that can be manipulated by the user for each I/O standard.
Single-ended I/O standards in Fusion support up to five different drive strengths.
_**Table 2-84 •**_ **Fusion Standard and Advanced I/O Attributes vs. I/O Standard Applications**
|**I/O Standards**<br>~~ee~~|**SLEW**<br>**(output**<br>**only)**<br>~~ee~~|**OUT_DRIVE**<br>**(output only)**<br>~~ss~~|**SKEW**<br>**(all macros**<br>**with OE)***<br>~~ss~~|**RES_PULL**<br>~~ss~~|**RES_PULL**<br>**OUT_LOAD**<br>**(output only) **<br>~~ss~~|**COMBINE_REGISTER**<br>~~ss~~|
|---|---|---|---|---|---|---|
|LVTTL/LVCMOS 3.3 V<br>~~ee~~|3<br>~~ee~~|3<br>~~ss~~|3<br>~~ss~~<br>~~ee~~|3<br>~~ss~~<br>~~ee~~|3<br>~~ss~~|3<br>~~ss~~|
|LVCMOS 2.5 V<br>~~ee~~<br>~~es~~<br>~~ee~~|3<br>~~ee~~<br>~~es~~|3<br>~~ss~~<br>~~es~~<br>~~se~~|3<br>~~ss~~<br>~~es~~<br>~~ee~~<br>~~se~~|3<br>~~ss~~<br>~~es~~<br>~~ee~~|3<br>~~ss~~<br>~~es~~|3<br>~~ss~~<br>~~es~~|
|LVCMOS 2.5/5.0 V<br>~~ee~~<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~<br>~~se~~|3<br>~~ee~~<br>~~ee~~<br>~~se~~|3<br>~~ee~~<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|
|LVCMOS 1.8 V<br>~~ee~~<br>~~ee~~|3|3<br>~~se~~|3<br>~~se~~|3|3|3|
|LVCMOS 1.5 V<br>~~ee~~<br>~~ee~~<br>~~ee~~|3<br>|3<br>~~se~~<br>~~ss~~<br>|3<br>~~se~~<br>~~ss~~<br>|3<br>|3<br>|3<br>|
|PCI (3.3 V)<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ss~~<br>~~ss~~|3<br>~~ee~~<br>~~ss~~<br>~~ss~~|~~ee~~<br>~~ss~~|3<br>~~ee~~<br>~~ss~~|3<br>~~ee~~<br>~~ss~~|
|PCI-X (3.3 V)<br>~~ee~~|3<br>~~ee~~|~~ss~~<br>~~ss~~|3<br>~~ss~~<br>~~ss~~<br>~~ee~~|~~ss~~<br>~~ee~~|3<br>~~ss~~|3<br>~~ss~~|
|LVDS, BLVDS, M-LVDS<br>~~ee~~<br>~~es~~|~~ee~~<br>~~es~~|~~ss~~<br>~~ss~~<br>~~es~~|3<br>~~ss~~<br>~~ss~~<br>~~es~~<br>~~ee~~|~~ss~~<br>~~es~~<br>~~ee~~|~~ss~~<br>~~es~~|3<br>~~ss~~<br>~~es~~|
|LVPECL<br>~~ee~~|~~ee~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|3<br>~~ee~~|
**Revision 8**
**2-156**
_Device Architecture_
_**Table 2-85 •**_ **Fusion Pro I/O Attributes vs. I/O Standard Applications**
|**I/O Standards**<br>~~Re~~<br>~~re~~|**SLEW (output only)**<br>~~ee~~<br>|**OUT_DRIVE (output only)**<br>~~ee~~<br>|**SKEW (all macros with OE)**<br>~~ee~~|**RES_PULL**<br>~~ee~~|**OUT_LOAD (output only)**<br>~~ee~~<br>~~Oe~~|**COMBINE_REGISTER**<br>~~ee~~<br>~~Oe~~|**IN_DELAY (input only)**<br>~~ee~~|**IN_DELAY_VAL (input only)**<br>~~ee~~|**SCHMITT_TRIGGER (input only)**<br>~~ee~~|**HOT_SWAPPABLE**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|
|LVTTL/LVCMOS 3.3 V<br>~~Re~~<br>~~re~~|3<br>~~ee~~<br>|3<br>~~ee~~<br>|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~<br>~~Oe~~|3<br>~~ee~~<br>~~Oe~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|
|LVCMOS 2.5 V<br>~~Re~~<br>~~re~~<br>~~Re~~<br>~~Re~~|3<br>~~ee~~<br>~~eG~~<br><br>|3<br>~~ee~~<br>~~eG~~<br><br>|3<br>~~ee~~<br>|3<br>~~ee~~<br>|3<br>~~ee~~<br>~~Oe~~<br><br>~~Oe~~|3<br>~~ee~~<br>~~Oe~~<br><br>~~Oe~~|3<br>~~ee~~<br>|3<br>~~ee~~<br>|3<br>~~ee~~<br>|3<br>~~ee~~<br>|
|LVCMOS 2.5/5.0 V<br>~~re ~~<br>~~Re~~<br>~~Re~~|3<br> ~~eG~~<br>~~ee~~<br>|3<br>~~eG~~<br>~~ee~~<br>|3<br>~~ee~~|3<br>~~ee~~|3<br>~~Oe~~<br>~~ee~~<br>~~Oe~~|3<br>~~Oe~~<br>~~ee~~<br>~~Oe~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|
|LVCMOS 1.8 V<br> <br>~~Re~~<br>~~Re~~|3<br> ~~eG~~<br><br>~~eG~~|3<br>~~eG~~<br><br>~~eG~~|3<br>|3<br>|3<br><br>~~Oe~~|3<br><br>~~Oe~~|3<br>|3<br>|3<br>|3<br>|
|LVCMOS 1.5 V<br>~~Re ~~<br>~~ee~~<br>~~Re~~|3<br> <br>~~ee~~<br>~~eG~~|3<br><br>~~ee~~<br>~~eG~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~Oe~~<br>~~ee~~|3<br>~~Oe~~<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|
|PCI (3.3 V)<br>~~Re~~|~~eG~~|~~eG~~|3||3|3|3|3|||
|PCI-X (3.3 V)<br>~~Re ~~<br>~~ee~~<br>~~Re~~|3<br> ~~eG~~<br>~~ee~~<br>~~eG~~|~~eG~~<br>~~ee~~<br>~~eG~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|~~ee~~|~~ee~~|
|GTL+ (3.3 V)<br>~~Re~~|~~eG~~|~~eG~~|3||3|3|3|3||3|
|GTL+ (2.5 V)<br>~~Re ~~<br>~~ee~~<br>~~Re~~|~~eG~~<br>~~ee~~<br>~~eG~~|~~eG~~<br>~~ee~~<br>~~eG~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|
|GTL (3.3 V)<br>~~Re~~|~~eG~~|~~eG~~|3||3|3|3|3||3|
|GTL (2.5 V)<br>~~Re ~~<br>~~ee~~<br>~~Re~~|~~eG~~<br>~~ee~~<br>~~eG~~|~~eG~~<br>~~ee~~<br>~~eG~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|
|HSTL Class I<br>~~Re~~|~~eG~~|~~eG~~|3||3|3|3|3||3|
|HSTL Class II<br>~~Re ~~<br>~~ee~~<br>~~Re~~|~~eG~~<br>~~ee~~<br>~~eG~~|~~eG~~<br>~~ee~~<br>~~eG~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|
|SSTL2 Class I and II<br>~~Re~~|~~eG~~|~~eG~~|3||3|3|3|3||3|
|SSTL3 Class I and II<br>~~Re ~~<br>~~ee~~<br>~~Re~~|~~eG~~<br>~~ee~~<br>~~eG~~|~~eG~~<br>~~ee~~<br>~~eG~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|3<br>~~ee~~|~~ee~~|3<br>~~ee~~|
|LVDS, BLVDS, M-LVDS<br>~~Re~~<br>~~Re re~~|~~eG~~<br>~~re~~|~~eG~~<br>~~re~~|3|||3|3|3||3|
|LVPECL<br>~~Re ~~<br>~~Re re~~|~~eG~~<br>~~re~~|~~eG~~<br>~~re~~||||3|3|3||3|
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## **User I/O Naming Convention**
Due to the comprehensive and flexible nature of Fusion device user I/Os, a naming scheme is used to show the details of the I/O (Figure 2-113 on page 2-158 and Figure 2-114 on page 2-159). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os.
I/O Nomenclature = Gmn/IOuxwByVz
Gmn is only used for I/Os that also have CCC access—i.e., global pins.
- G = Global
- m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west middle).
- n = Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or C2. Figure 2-22 on page 2-25 shows the three input pins per clock source MUX at CCC location m.
- u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction.
- x = P (Positive) or N (Negative) for differential pairs, or R (Regular – single-ended) for the I/Os that support singleended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS only) restrict the I/O differential pair from being selected as an LVPECL pair.
- w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair.
- B = Bank
- y = Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise direction.
- V = Reference voltage
- z = Minibank number
**==> picture [291 x 262] intentionally omitted <==**
**----- Start of picture text -----**<br>
Standard I/O Bank<br>CCC Bank 0 CCC<br>"A" "B"<br>ye<br>Bank 3 Bank 1<br>AFS090<br>CCC/PLL CCC<br>"F" AFS250 "C"<br>| |_|<br>Bank 3 Bank 1<br>if _<br>CCC CCC<br>"E" Bank 2 (analog) "D"<br>| jd<br>Analog Quads<br>Advanced I/O Bank Advanced I/O Bank<br>**----- End of picture text -----**<br>
_**Figure 2-113 •**_ **Naming Conventions of Fusion Devices with Three Digital I/O Banks**
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**==> picture [284 x 236] intentionally omitted <==**
**----- Start of picture text -----**<br>
Pro I/O Bank<br>CCC Bank 0 Bank 1 CCC<br>"A" "B"<br>| ee<br>Bank 4 Bank 2<br>AFS600<br>CCC/PLL CCC/PLL<br>AFS1500<br>"F" "C"<br>| ma<br>Bank 4 Bank 2<br>i a<br>CCC CCC<br>"E" Bank 3 (analog) "D"<br>ee<br>Advanced I/O Bank Advnaced I/O Bank<br>**----- End of picture text -----**<br>
**Analog Quads**
_**Figure 2-114 •**_ **Naming Conventions of Fusion Devices with Four I/O Banks**
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## **User I/O Characteristics**
## _**Timing Model**_
**==> picture [462 x 372] intentionally omitted <==**
**----- Start of picture text -----**<br>
I/O Module<br>(Non-Registered)<br>Combinational Cell Combinational Cell<br>Y Y<br>LVPECL (Pro IO banks)<br>tPD = 0.56 ns tPD = 0.49 ns<br>tDp = 1.60 ns<br>I/O Module<br>(Non-Registered)<br>Combinational Cell<br>Y<br>LVTTL/LVCMOS 3.3 V (Pro I/O banks)<br>tPD = 0.87 ns tDP = 2.74 ns Output drive strength = 12 mAHigh slew rate<br>I/O Module<br>Combinational Cell<br>(Non-Registered)<br>Y<br>I/O Module<br>(Registered) LVTTL/LVCMOS 3.3 V (Pro I/O banks)<br>Output drive strength = 24 mA<br>tPY = 1.22 ns tDP = 2.39 ns High slew rate<br>tPD = 0.51 ns<br>LVPECL D Q I/O Module<br>(Pro IO Banks) (Non-Registered)<br>Combinational Cell<br>Y<br>LVCMOS 1.5 V (Pro IO banks)<br>Input LVTTL/LVCMOS ttICLKQISUD = 0.26 ns = 0.24 ns tPD = 0.47 ns tDP = 3.30 ns Output drive strength = 12 mAHigh slew<br>3.3 V (Pro IO banks)<br>I/O Module<br>Register Cell Combinational Cell Register Cell (Registered)<br>tPY = 0.90 ns D Q Y D Q D Q<br>(Non-Registered)I/O Module tPD = 0.47 ns tDP = 1.53 nsGTL+ 3.3 V<br>Gia<br>BLVDS,LVDS, ttCLKQSUD = 0.43 ns = 0.55 ns ttCLKQSUD = 0.43 ns = 0.55 ns ttOCLKQOSUD = 0.31 ns = 0.59 ns<br>M-LVDS (Pro IO Banks) Input LVTTL/LVCMOS IInput LVTTL/LVCMOS<br>tPY = 1.36 ns 3.3 V (Pro IO banks) 3.3 V (Pro IO banks)<br>tPY = 0.90 ns tPY = 0.90 ns<br>**----- End of picture text -----**<br>
_**Figure 2-115 •**_ **Timing Model**
**Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V**
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**==> picture [396 x 478] intentionally omitted <==**
**----- Start of picture text -----**<br>
tPY tDIN<br>t<br>PYS<br>D Q<br>PAD DIN<br>Y<br>CLK To Array<br>I/O interface<br>tPY = MAX(tPY (R), tPY (F))<br>tPYs = MAX(tPYS (R), tPYS (F))<br>tDIN = MAX(tDIN (R), tDIN (F))<br>VIH<br>V V<br>PAD trip trip VIL<br>VCC<br>50% 50%<br>Y<br>GND tPY tPY<br>(R) (F)<br>t t<br>PYS PYS<br>(R) (F)<br>VCC<br>50% 50%<br>DIN<br>GND tDIN tDIN<br>(R) (F)<br>**----- End of picture text -----**<br>
_**Figure 2-116 •**_ **Input Buffer Timing Model and Delays (example)**
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**==> picture [407 x 328] intentionally omitted <==**
**----- Start of picture text -----**<br>
tDOUT tDP<br>D Q PAD<br>DOUT<br>D CLK Std<br>Load<br>From Array<br>tDP = MAX(tDP(R), tDP(F))<br>I/O Interface<br>tDOUT = MAX(tDOUT(R), tDOUT(F))<br>t t<br>DOUT DOUT<br>(R) VCC<br>(F)<br>50% 50%<br>D 0 V<br>VCC<br>50% 50%<br>DOUT 0 V<br>VOH<br>V V<br>trip trip<br>PAD VOL<br>tDP tDP<br>(R) (F)<br>**----- End of picture text -----**<br>
_**Figure 2-117 •**_ **Output Buffer Model and Delays (example)**
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**==> picture [384 x 508] intentionally omitted <==**
**----- Start of picture text -----**<br>
t E OUT<br>D Q<br>E CLK tZL, tZH, tHZ, tLZ, tZLS, tZHS<br>EOUT<br>D Q PAD<br>DOUT<br>D CLK<br>I/O Interface tEOUT = MAX(tEOUT (R). tEOUT (F))<br>VCC<br>D<br>VCC<br>50% 50%<br>E t<br>t EOUT (F)<br>EOUT (R)<br>VCC<br>50%<br>EOUT 50% 50% tZH50% t LZ<br>tZL tHZ VCCI<br>PAD 90% VCCI<br>Vtrip VOL Vtrip 10% VCCI<br>VCC<br>D<br>VCC<br>E 50% tEOUT (R) 50% tEOUT (F)<br>VCC<br>50% 50%<br>EOUT 50%<br>tZLS VOH tZHS<br>PAD<br>Vtrip VOL Vtrip<br>**----- End of picture text -----**<br>
_**Figure 2-118 •**_ **Tristate Output Buffer Timing Model and Delays (example)**
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## _**Overview of I/O Performance**_
## _**Summary of I/O DC Input and Output Levels – Default I/O Software Settings**_
_**Table 2-86 •**_ **Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions**
**Applicable to Pro I/Os**
|**I/O Standard**<br>~~eee~~<br>~~eee~~|**Drive**<br>**Strength**<br>~~eee~~<br>~~eee~~|**Slew**<br>**Rate**<br>~~eee~~<br>~~eee~~|**VIL**<br>~~eee~~|**VIL**<br>~~eee~~|**VIH**<br>~~eee~~|**VIH**<br>~~eee~~|**VOL**<br>~~eee~~|**VOH**<br>~~eee~~|**IOL **<br>~~eee~~|**IOH**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>**V**<br>~~eee~~<br>~~pp~~<br>~~eee~~|**Max.**<br>**V**<br>~~eee~~<br>~~pp~~<br>~~eee~~|**Min.**<br>**V**<br>~~eee~~<br>~~eee~~|**Max.**<br>**V**<br>~~eee~~<br>~~eee~~|**Max.**<br>**V**<br>~~eee~~<br>~~eee~~|**Min.**<br>**V**<br>~~eee~~<br>~~eee~~|**mA **<br>~~eee~~<br>~~eee~~|**mA**<br>~~eee~~<br>~~eee~~|
|3.3 V LVTTL /<br>3.3 V LVCMOS<br>~~eee~~<br>~~eee~~<br>~~i~~|12 mA<br>~~eee~~<br>~~eee~~<br>~~i~~|High –0.3<br>~~eee~~<br>~~eee~~<br>~~ee~~|High –0.3<br>~~eee~~<br>~~pp~~<br>~~eee~~<br>~~ee~~|0.8<br>~~eee~~<br>~~pp~~<br>~~eee~~<br>~~ee~~|2<br>~~eee~~<br>~~eee~~|3.6<br>~~eee~~<br>~~eee~~|0.4<br>~~eee~~<br>~~eee~~|2.4<br>~~eee~~<br>~~eee~~|12 12<br>~~eee~~<br>~~eee~~|12 12<br>~~eee~~<br>~~eee~~|
|2.5 V LVCMOS<br>~~eee~~<br>~~i~~<br>~~Rs~~|12 mA<br>~~eee~~<br>~~i~~|High –0.3<br>~~eee~~<br>~~ee~~|High –0.3<br>~~eee~~<br>~~ee~~|0.7<br>~~eee~~<br>~~ee~~|1.7<br>~~eee ~~|3.6<br> ~~eee~~|0.7<br>~~eee~~|1.7<br>~~eee~~|12 12<br>~~eee~~|12 12<br>~~eee~~|
|1.8 V LVCMOS<br>~~i~~<br>~~Rs~~<br>~~Rs~~|12 mA<br>~~i~~<br>~~ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI<br>~~ee ~~<br>~~ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI<br> ~~ee~~<br>~~ee ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI<br>~~ee~~<br>~~ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI|3.6|0.45|VCCI – 0.45 12 12|VCCI – 0.45 12 12|VCCI – 0.45 12 12|
|1.5 V LVCMOS<br>~~Rs~~<br>~~Rs~~|12 mA<br>~~ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI<br>~~ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI<br>~~ee ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI<br>~~ee~~|High –0.3 0.35 * VCCI 0.65 * VCCI|3.6|0.25 * VCCI 0.75 * VCCI 12 12|0.25 * VCCI 0.75 * VCCI 12 12|0.25 * VCCI 0.75 * VCCI 12 12|0.25 * VCCI 0.75 * VCCI 12 12|
|3.3 V PCI<br>~~Rs ~~<br>~~a~~<br>~~en~~|Per PCI Specification<br> ~~ee ee ee~~||||||||||
|3.3 V PCI-X<br>~~a~~<br>~~en~~<br>~~es~~|Per PCI-X Specification<br>~~eeee~~||||||||||
|3.3 V GTL<br>~~en~~<br>~~es~~<br>~~i~~|20 mA2<br>~~ee~~<br>~~i~~|High –0.3 VREF – 0.05 VREF + 0.05<br>~~ee~~<br>~~ee~~|High –0.3 VREF – 0.05 VREF + 0.05<br>~~ee~~<br>~~ee~~|High –0.3 VREF – 0.05 VREF + 0.05<br>~~ee~~|High –0.3 VREF – 0.05 VREF + 0.05|3.6|0.4|–|20 20|20 20|
|2.5 V GTL<br>~~es ~~<br>~~i~~<br>~~Rs~~|20 mA2<br> ~~ee~~<br>~~i~~|High –0.3 VREF – 0.05 VREF + 0.05<br>~~ee ~~<br>~~ee~~|High –0.3 VREF – 0.05 VREF + 0.05<br> ~~ee~~<br>~~ee~~|High –0.3 VREF – 0.05 VREF + 0.05<br>~~ee~~|High –0.3 VREF – 0.05 VREF + 0.05|3.6|0.4|–|20 20|20 20|
|3.3 V GTL+<br>~~i~~<br>~~Rs~~<br>~~es~~|35 mA<br>~~i~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee ~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br> ~~ee~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1|3.6|0.6|–|35|35|
|2.5 V GTL+<br>~~Rs~~<br>~~es~~<br>~~i~~|33 mA<br>~~ee~~<br>~~i~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1|3.6|0.6|–|33|33|
|HSTL (I)<br>~~es ~~<br>~~i~~<br>~~Rs~~|8 mA<br> ~~ee~~<br>~~i~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee ~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br> ~~ee~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1|3.6|0.4|VCCI – 0.4|8|8|
|HSTL (II)<br>~~i~~<br>~~Rs~~<br>~~es~~|15 mA2High –0.3 VREF – 0.1 VREF + 0.1<br>~~i~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee ~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br> ~~ee~~<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1<br>~~ee~~|High –0.3 VREF – 0.1 VREF + 0.1|3.6|0.4|VCCI – 0.4 15 15|VCCI – 0.4 15 15|VCCI – 0.4 15 15|
|SSTL2 (I)<br>~~Rs~~<br>~~es~~<br>~~i~~|15 mA<br>~~ee~~<br>~~i~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee~~<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee~~<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2|3.6|0.54|VCCI – 0.62 15|VCCI – 0.62 15|15|
|SSTL2 (II)<br>~~es ~~<br>~~i~~<br>~~Rs~~|18 mA<br> ~~ee~~<br>~~i~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee ~~<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br> ~~ee~~<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2|3.6|0.35|VCCI – 0.43 18|VCCI – 0.43 18|18|
|SSTL3 (I)<br>~~i~~<br>~~Rs~~<br>~~es~~|14 mA<br>~~i~~<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee ~~<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br> ~~ee~~<br>~~ee ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee~~<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2|3.6|0.7|VCCI – 1.1|14|14|
|SSTL3 (II)<br>~~Rs~~<br>~~es~~|21 mA<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee ee~~|High –0.3 VREF – 0.2 VREF + 0.2<br>~~ee~~|High –0.3 VREF – 0.2 VREF + 0.2|3.6|0.5|VCCI – 0.9|21|21|
_Notes:_
_1. Currents are measured at 85°C junction temperature._
_2. Output drive strength is below JEDEC specification._
_3. Output slew rate can be extracted by the IBIS models._
_**Table 2-87 •**_ **Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions**
**Applicable to Advanced I/Os**
|**I/O Standard**<br>~~eee~~<br>~~po~~|**Drive**<br>**Strength**<br>~~eee~~|**Slew**<br>**Rate**<br>~~eee~~<br>~~eft~~|**VIL**<br>~~eee~~|**VIL**<br>~~eee~~|**VIH**<br>~~eee~~<br>~~| |~~|**VIH**<br>~~eee~~<br>~~| |~~|**VOL**<br>~~eee~~<br>~~|~~|**VOH**<br>~~eee~~<br>~~|~~|**IOL**<br>~~eee~~<br>~~|~~|**IOH**<br>~~eee~~<br>~~|~~|
|---|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>**V**<br>~~eee~~<br>~~eft~~<br>~~ee~~|**Max.**<br>**V**<br>~~eee~~<br>~~eft~~<br>~~ee~~|**Min.**<br>**V**<br>~~eee~~<br>~~eft~~<br>~~|~~<br>~~eee~~|**Max.**<br>**V**<br>~~eee~~<br>~~eft~~<br>~~| |~~<br>~~eee ee~~|**Max.**<br>**V**<br>~~eee~~<br>~~eft~~<br>~~|~~<br>~~ee~~|**Min.**<br>**V**<br>~~eee~~<br>~~eft~~<br>~~|~~<br>~~ee~~|**mA**<br>~~eee~~<br>~~eft~~<br>~~|~~<br>~~ee~~|**mA**<br>~~eee~~<br>~~eft~~<br>~~|~~<br>~~ee~~|
|3.3 V LVTTL /<br>3.3 V LVCMOS<br>~~ee~~<br>~~po~~|12 mA<br>~~ee~~|High –0.3<br>~~ee~~|High –0.3<br>~~ee~~<br>~~ee~~|0.8<br>~~ee~~<br>~~ee~~|2<br>~~|~~<br>~~ee~~<br>~~eee~~|3.6<br>~~| |~~<br>~~ee~~<br>~~eee ee~~|0.4<br>~~|~~<br>~~ee~~<br>~~ee~~|2.4<br>~~|~~<br>~~ee~~<br>~~ee~~|12 12<br>~~|~~<br>~~ee~~<br>~~ee~~|12 12<br>~~|~~<br>~~ee~~<br>~~ee~~|
|2.5 V LVCMOS<br>~~ee~~<br>~~po~~<br>~~po~~|12 mA High –0.3<br>~~ee~~|12 mA High –0.3<br>~~ee~~|12 mA High –0.3<br>~~ee~~<br>~~ee~~|0.7<br>~~ee~~<br>~~ee~~|1.7<br>~~ee~~<br>~~eee~~|2.7<br>~~ee~~<br>~~eee ee~~|0.7<br>~~ee~~<br>~~ee~~|1.7<br>~~ee~~<br>~~ee~~|12 12<br>~~ee~~<br>~~ee~~|12 12<br>~~ee~~<br>~~ee~~|
|1.8 V LVCMOS<br>~~po~~<br>~~po~~<br>~~po~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI<br>~~ee~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI<br>~~ee ~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI<br> ~~eee~~|1.9<br>~~eee ee~~|0.45<br>~~ee~~|VCCI – 0.45<br>~~ee~~|12<br>~~ee~~|12<br>~~ee~~|
|1.5 V LVCMOS<br>~~po~~<br>~~po~~<br>~~Rs~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575|0.25 * VCCI 0.75 * VCCI|0.25 * VCCI 0.75 * VCCI|12|12|
|3.3 V PCI<br>~~po~~<br>~~Rs~~<br>~~es~~|Per PCI specifications||||||||||
|3.3 V PCI-X<br>~~Rs~~<br>~~es~~|Per PCI-X specifications||||||||||
_Note: Currents are measured at 85°C junction temperature._
**Revision 8**
**2-164**
_Device Architecture_
_**Table 2-88 •**_ **Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions**
**Applicable to Standard I/Os**
**VIL VIH VOL VOH IOL IOH Drive Slew Min. Max. Min. Max. Max. Min. I/O Standard Strength Rate V V V V V V mA mA** ~~eeeeto~~ 3.3 V LVTTL / 8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8 3.3 V LVCMOS ~~|Et~~ 2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8 ~~Re ee Ge OO~~ 1.8 V LVCMOS 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 ~~Re ee Ge OO~~ 1.5 V LVCMOS 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 ~~De ee Ge Ge~~ _Note: Currents are measured at 85°C junction temperature._
_**Table 2-89 •**_ **Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions**
**Applicable to All I/O Bank Types**
|**DC I/O Standards**<br>~~re~~<br>~~ee~~|**Commercial1**<br>~~ee~~<br>~~re~~|**Commercial1**<br>~~ee~~<br>~~re~~|**Industrial2**<br>~~ee~~<br>~~re~~|**Industrial2**<br>~~ee~~<br>~~re~~|
|---|---|---|---|---|
||**IIL3**<br>~~re~~|**IIH4**<br>~~re~~|**IIL3**<br>~~re~~|**IIH4**<br>~~re~~|
||**µA**<br>~~re~~<br>~~ee~~<br>~~Gs~~|**µA**<br>~~re~~<br>~~ee~~<br>~~Gs~~|**µA**<br>~~re~~<br>~~ee~~|**µA**<br>~~re~~<br>~~ee~~|
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~re~~<br>~~ee~~|10<br>~~re~~<br>~~ee~~<br>~~Gs~~|10<br>~~re~~<br>~~ee~~<br>~~Gs~~|15<br>~~re~~<br>~~ee~~|15<br>~~re~~<br>~~ee~~|
|2.5 V LVCMOS<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~Gs~~<br>~~ee~~|10<br>~~ee~~<br>~~Gs~~<br>~~ee~~|15<br>~~ee~~<br>~~ee~~|15<br>~~ee~~<br>~~ee~~|
|1.8 V LVCMOS<br>~~ee~~<br>~~es~~|10<br>~~ee~~<br>~~es~~|10<br>~~ee~~<br>~~es~~|15<br>~~ee~~<br>~~es~~|15<br>~~ee~~<br>~~es~~|
|1.5 V LVCMOS<br>~~es~~<br>~~Re~~|10<br>~~es~~<br>~~GG~~|10<br>~~es~~<br>~~GG~~|15<br>~~es~~<br>~~GG~~|15<br>~~es~~|
|3.3 V PCI<br>~~Re~~<br>~~Re~~|10<br>~~GG~~<br>~~eG~~|10<br>~~GG~~<br>~~eG~~|15<br>~~GG~~|15|
|3.3 V PCI-X<br>~~Re ~~<br>~~Re~~<br>~~ee~~|10<br> ~~GG~~<br>~~eG~~<br>~~Gs~~|10<br>~~GG~~<br>~~eG~~<br>~~Gs~~|15<br>~~GG~~|15|
|3.3 V GTL<br>~~Re ~~<br>~~ee~~|10<br> ~~eG~~<br>~~Gs~~|10<br>~~eG~~<br>~~Gs~~|15|15|
|2.5 V GTL<br>~~ee~~<br>~~ee~~|10<br>~~Gs~~<br>~~ee~~|10<br>~~Gs~~<br>~~ee~~|15<br>~~ee~~|15<br>~~ee~~|
|3.3 V GTL+<br>~~ee~~<br>~~es~~|10<br>~~ee~~<br>~~es~~|10<br>~~ee~~<br>~~es~~|15<br>~~ee~~<br>~~es~~|15<br>~~ee~~<br>~~es~~|
|2.5 V GTL+<br>~~es~~<br>~~Re~~|10<br>~~es~~<br>~~GG~~|10<br>~~es~~<br>~~GG~~|15<br>~~es~~<br>~~GG~~|15<br>~~es~~|
|HSTL (I)<br>~~Re~~<br>~~Re~~|10<br>~~GG~~<br>~~eG~~|10<br>~~GG~~<br>~~eG~~|15<br>~~GG~~|15|
|HSTL (II)<br>~~Re ~~<br>~~Re~~<br>~~ee~~|10<br> ~~GG~~<br>~~eG~~<br>~~Gs~~|10<br>~~GG~~<br>~~eG~~<br>~~Gs~~|15<br>~~GG~~|15|
|SSTL2 (I)<br>~~Re ~~<br>~~ee~~|10<br> ~~eG~~<br>~~Gs~~|10<br>~~eG~~<br>~~Gs~~|15|15|
|SSTL2 (II)<br>~~ee~~<br>~~ee~~|10<br>~~Gs~~<br>~~ee~~|10<br>~~Gs~~<br>~~ee~~|15<br>~~ee~~|15<br>~~ee~~|
|SSTL3 (I)<br>~~ee~~<br>~~es~~<br>~~ee~~|10<br>~~ee~~<br>~~es~~|10<br>~~ee~~<br>~~es~~|15<br>~~ee~~<br>~~es~~|15<br>~~ee~~<br>~~es~~|
|SSTL3 (II)<br>~~ee~~|10|10|15|15|
_Notes:_
_1. Commercial range (0°C < TJ < 85°C)_
_2. Industrial range (–40°C < TJ < 100°C)_
_3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
**2-165**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Summary of I/O Timing Characteristics – Default I/O Software Settings**_
_**Table 2-90 •**_ **Summary of AC Measuring Points Applicable to All I/O Bank Types**
|**Standard**|**Input Reference Voltage**<br>**(VREF_TYP)**|**Board Termination Voltage**<br>**(VTT_REF)**|**Measuring Trip Point**<br>**(Vtrip)**|
|---|---|---|---|
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~a~~|–<br>|–<br>|1.4 V<br>|
|2.5 V LVCMOS<br>~~eG~~|–<br>~~eG~~|–<br>~~eG~~|1.2 V<br>~~eG~~|
|1.8 V LVCMOS<br>~~Rs~~|–<br>~~Rs~~|–<br>~~Rs~~|0.90 V<br>~~Rs~~|
|1.5 V LVCMOS<br>~~se~~|–<br>~~se~~|–<br>~~se~~|0.75 V<br>~~se~~|
|3.3 V PCI|–|–|0.285 * VCCI (RR)<br>0.615 * VCCI (FF))|
|3.3 V PCI-X<br>~~Rs~~|–<br>~~Ge~~|–|0.285 * VCCI (RR)<br>0.615 * VCCI (FF)|
|3.3 V GTL<br>~~Rs~~|0.8 V<br>~~Ge~~|1.2 V|VREF|
|2.5 V GTL<br>~~Rs~~<br>~~rs~~|0.8 V<br>~~Ge~~<br>~~rs~~|1.2 V<br>~~rs~~|VREF<br>~~rs~~|
|3.3 V GTL+<br>~~rs~~<br>~~ee~~|1.0 V<br>~~rs~~<br>~~ee~~|1.5 V<br>~~rs~~<br>~~ee~~|VREF<br>~~rs~~<br>~~ee~~|
|2.5 V GTL+<br>~~eG~~|1.0 V<br>~~eG~~|1.5 V<br>~~eG~~|VREF<br>~~eG~~|
|HSTL (I)<br>~~Rs~~|0.75 V<br>~~Rs~~|0.75 V<br>~~Rs~~|VREF<br>~~Rs~~|
|HSTL (II)<br>~~se~~|0.75 V<br>~~se~~|0.75 V<br>~~se~~|VREF<br>~~se~~|
|SSTL2 (I)<br>~~rs~~|1.25 V<br>~~rs~~|1.25 V<br>~~rs~~|VREF<br>~~rs~~|
|SSTL2 (II)<br>~~rs~~<br>~~rs~~|1.25 V<br>~~rs~~<br>~~rs~~|1.25 V<br>~~rs~~<br>~~rs~~|VREF<br>~~rs~~<br>~~rs~~|
|SSTL3 (I)<br>~~rs~~<br>~~ee~~|1.5 V<br>~~rs~~<br>~~ee~~|1.485 V<br>~~rs~~<br>~~ee~~|VREF<br>~~rs~~<br>~~ee~~|
|SSTL3 (II)<br>~~eG~~|1.5 V<br>~~eG~~|1.485 V<br>~~eG~~|VREF<br>~~eG~~|
|LVDS<br>~~Rs~~|–<br>~~Rs~~|–<br>~~Rs~~|Cross point<br>~~Rs~~|
|LVPECL<br>~~es~~|–<br>~~es~~|–<br>~~es~~|Cross point<br>~~es~~|
## _**Table 2-91 •**_ **I/O AC Parameter Definitions**
|**Parameter**|**Definition**|
|---|---|
|tDP|Data to Pad delay through the Output Buffer|
|tPY|Pad to Data delay through the Input Buffer with Schmitt trigger disabled|
|tDOUT|Data to Output Buffer delay through the I/O interface|
|tEOUT|Enable to Output Buffer Tristate Control delay through the I/O interface|
|tDIN|Input Buffer to Data delay through the I/O interface|
|tPYS|Pad to Data delay through the Input Buffer with Schmitt trigger enabled|
|tHZ|Enable to Pad delay through the Output Buffer—High to Z|
|tZH|Enable to Pad delay through the Output Buffer—Z to High|
|tLZ|Enable to Pad delay through the Output Buffer—Low to Z|
|tZL|Enable to Pad delay through the Output Buffer—Z to Low|
|tZHS|Enable to Pad delay through the Output Buffer with delayed enable—Z to High|
|tZLS|Enable to Pad delay through the Output Buffer with delayed enable—Z to Low|
**Revision 8**
**2-166**
_Device Architecture_
_**Table 2-92 •**_ **Summary of I/O Timing Characteristics – Software Default Settings Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = I/O Standard Dependent Applicable to Pro I/Os**
|**I/O Standard**|**Drive Strength (mA)**|**Slew Rate**|**Capacitive Load (pF)**|**External Resistor (Ohm)**|**t DOUT**|**tDP**|**tDIN**|**tPY**|**tPYS **|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|3.3 V LVTTL/<br>3.3 V LVCMOS<br>~~Re~~|12 mA <br>|High 35<br>~~ee~~|High 35<br>~~ee~~|–<br>~~ee~~|0.49 <br>~~ee~~|2.74 <br>~~ee~~|0.03|0.90|1.17|0.32|2.79|2.14|2.45|2.70|4.46|3.81|ns|
|2.5 V LVCMOS <br>~~Re~~<br>~~—~~<br>~~|~~|12 mA <br><br>~~|~~|High 35<br>~~ee~~<br>~~fe~~|High 35<br>~~ee~~<br>~~fe~~|–<br>~~ee~~<br>~~fePp~~|0.49 <br>~~ee~~<br>~~Pp~~|2.80 <br>~~ee~~<br>~~Pptt~~|0.03 <br>~~tt~~|1.13 <br>~~tt~~|1.24|0.32|2.85|2.61|2.51|2.61|4.52|4.28|ns|
|1.8 V LVCMOS <br>~~Re ~~<br>~~—~~<br>~~|~~|12 mA <br> <br>~~|~~|High 35<br> ~~ee~~<br>~~fe~~|High 35<br>~~ee~~<br>~~fe~~|–<br>~~ee~~<br>~~fePp~~|0.49 <br>~~ee~~<br>~~Pp~~|2.83 <br>~~ee~~<br>~~Pptt~~|0.03 <br>~~tt~~|1.08 <br>~~tt~~|1.42|0.32|2.89|2.31|2.79|3.16|4.56|3.98|ns|
|1.5 V LVCMOS <br>~~—~~<br>~~|~~|12 mA <br>~~|~~|High 35<br>~~fe~~|High 35<br>~~fe~~|–<br>~~fe Pp~~|0.49 <br>~~Pp~~|3.30 <br>~~Pp tt~~|0.03 <br>~~tt~~|1.27 <br>~~tt~~|1.60|0.32|3.36|2.70|2.96|3.27|5.03|4.37|ns|
|3.3 V PCI|Per<br>PCI<br>spec|High 10 25|High 10 25|High 10 25 2|0.49|2.09|0.03|0.78|1.25|0.32|2.13|1.49|2.45|2.70|3.80|3.16|ns|
|3.3 V PCI-X|Per<br>PCI-X<br>spec|High 10 25|High 10 25|High 10 25 2|0.49|2.09|0.03|0.77|1.17|0.32|2.13|1.49|2.45|2.70|3.80|3.16|ns|
|3.3 V GTL<br>~~ee~~<br>~~—~~<br>~~|~~|20 mA <br>~~ee~~<br>~~|~~|High 10 25 0.49<br>~~ee~~<br>~~Pe~~|High 10 25 0.49<br>~~ee~~<br>~~Pe~~|High 10 25 0.49<br>~~ee~~<br>~~Pe~~|High 10 25 0.49 <br>~~ee~~|1.55 <br>~~ee~~|0.03 <br>~~ee~~|2.19<br>~~ee~~|–<br>~~ee~~|0.32 <br>~~ee~~|1.52 <br>~~ee~~|1.55<br>~~ee~~|0.00<br>~~ee~~|0.00 <br>~~ee~~|3.19 <br>~~ee~~|3.22 <br>~~ee~~|ns<br>~~ee~~|
|2.5 V GTL<br>~~ee~~<br>~~—~~<br>~~|~~<br>~~Fe~~|20 mA <br>~~ee~~<br>~~|~~<br>~~ee~~|High 10 25 0.49<br>~~ee~~<br>~~Pe~~<br>~~ee~~|High 10 25 0.49<br>~~ee~~<br>~~Pe~~<br>~~ee~~|High 10 25 0.49<br>~~ee~~<br>~~Pe~~<br>~~ee~~|High 10 25 0.49 <br>~~ee~~<br>~~ee~~|1.59 <br>~~ee~~<br>~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.83<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.32 <br>~~ee~~<br>~~ee~~|1.61 <br>~~ee~~<br>~~ee~~|1.59<br>~~ee~~<br>~~ee~~|0.00<br>~~ee~~<br>~~ee~~|0.00 <br>~~ee~~<br>~~ee~~|3.28 <br>~~ee~~<br>~~ee~~|3.26 <br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|3.3 V GTL+<br>~~—~~<br>~~|~~<br>~~Fe~~<br>~~Re~~|35 mA <br>~~|~~<br>~~ee~~<br>|High 10 25 0.49<br>~~Pe~~<br>~~ee~~<br>~~ee~~|High 10 25 0.49<br>~~Pe~~<br>~~ee~~<br>~~ee~~|High 10 25 0.49<br>~~Pe~~<br>~~ee~~<br>~~ee~~|High 10 25 0.49 <br>~~ee~~<br>~~ee~~|1.53 <br>~~ee~~<br>~~ee~~|0.03 <br>~~ee~~|1.19<br>~~ee~~|–<br>~~ee~~|0.32 <br>~~ee~~|1.56 <br>~~ee~~|1.53<br>~~ee~~|0.00<br>~~ee~~|0.00 <br>~~ee~~|3.23 <br>~~ee~~|3.20 <br>~~ee~~|ns<br>~~ee~~|
|2.5 V GTL+<br>~~Fe~~<br>~~Re~~<br>~~—~~<br>~~|~~|33 mA <br>~~ee~~<br><br>~~|~~|High 10 25 0.49<br>~~ee~~<br>~~ee~~<br>~~fe~~|High 10 25 0.49<br>~~ee~~<br>~~ee~~<br>~~fe~~|High 10 25 0.49<br>~~ee~~<br>~~ee~~<br>~~fePp~~|High 10 25 0.49 <br>~~ee~~<br>~~ee~~<br>~~Pp~~|1.65 <br>~~ee~~<br>~~ee~~<br>~~Pptt~~|0.03 <br>~~ee~~<br>~~tt~~|1.13<br>~~ee~~<br>~~tt~~|–<br>~~ee~~|0.32 <br>~~ee~~|1.68 <br>~~ee~~|1.57<br>~~ee~~|0.00<br>~~ee~~|0.00 <br>~~ee~~|3.35 <br>~~ee~~|3.24 <br>~~ee~~|ns<br>~~ee~~|
|HSTL (I)<br>~~Re ~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|8 mA<br> <br>~~|~~<br>~~|~~|High 20 50 0.49<br> ~~ee~~<br>~~fe~~<br>~~fet~~|High 20 50 0.49<br>~~ee~~<br>~~fe~~<br>~~fet~~|High 20 50 0.49<br>~~ee~~<br>~~fePp~~<br>~~fet~~|High 20 50 0.49 <br>~~ee~~<br>~~Pp~~<br>~~fet~~<br>~~|~~|2.37 <br>~~ee~~<br>~~Pptt~~<br>||0.03 <br>~~tt~~<br>||1.59<br>~~tt~~<br>||–<br>~~et~~|0.32 <br>~~et~~|2.42 <br>~~et~~|2.35|0.00<br>~~|~~|0.00|4.09|4.02|ns|
|HSTL (II)<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|15 mA <br>~~|~~<br>~~|~~|High 20 25 0.49<br>~~fe~~<br>~~fet~~|High 20 25 0.49<br>~~fe~~<br>~~fet~~|High 20 25 0.49<br>~~fe Pp~~<br>~~fet~~|High 20 25 0.49 <br>~~Pp~~<br>~~fet~~<br>~~|~~|2.26 <br>~~Pp tt~~<br>||0.03 <br>~~tt~~<br>||1.59<br>~~tt~~<br>||–<br>~~et~~|0.32 <br>~~et~~|2.30 <br>~~et~~|2.03|0.00<br>~~|~~|0.00|3.97|3.70|ns|
|SSTL2 (I)<br>~~—~~<br>~~|~~<br>~~ee~~<br>~~—~~<br>~~|~~|17 mA <br>~~|~~<br>~~ee~~<br>~~|~~|High 30 50 0.49<br>~~fet~~<br>~~ee~~<br>~~Pe~~|High 30 50 0.49<br>~~fet~~<br>~~ee~~<br>~~Pe~~|High 30 50 0.49<br>~~fet~~<br>~~ee~~<br>~~Pe~~|High 30 50 0.49 <br>~~fet~~<br>~~|~~<br>~~ee~~|1.59 <br>|<br>~~ee~~|0.03 <br>|<br>~~ee~~|1.00<br>| <br>~~ee~~|–<br> ~~et~~<br>~~ee~~|0.32 <br>~~et~~<br>~~ee~~|1.62 <br>~~et~~<br>~~ee~~|1.38<br>~~ee~~|0.00<br>~~|~~<br>~~ee~~|0.00 <br>~~ee~~|3.29 <br>~~ee~~|3.05 <br>~~ee~~|ns<br>~~ee~~|
|SSTL2 (II)<br>~~ee~~<br>~~—~~<br>~~|~~<br>~~Fe~~|21 mA <br>~~ee~~<br>~~|~~<br>~~ee~~|High 30 25 0.49<br>~~ee~~<br>~~Pe~~<br>~~ee~~|High 30 25 0.49<br>~~ee~~<br>~~Pe~~<br>~~ee~~|High 30 25 0.49<br>~~ee~~<br>~~Pe~~<br>~~ee~~|High 30 25 0.49 <br>~~ee~~<br>~~ee~~|1.62 <br>~~ee~~<br>~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.32 <br>~~ee~~<br>~~ee~~|1.65 <br>~~ee~~<br>~~ee~~|1.32<br>~~ee~~<br>~~ee~~|0.00<br>~~ee~~<br>~~ee~~|0.00 <br>~~ee~~<br>~~ee~~|3.32 <br>~~ee~~<br>~~ee~~|2.99 <br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|SSTL3 (I)<br>~~—~~<br>~~|~~<br>~~Fe~~<br>~~Re~~|16 mA <br>~~|~~<br>~~ee~~<br>|High 30 50 0.49<br>~~Pe~~<br>~~ee~~<br>~~ee~~|High 30 50 0.49<br>~~Pe~~<br>~~ee~~<br>~~ee~~|High 30 50 0.49<br>~~Pe~~<br>~~ee~~<br>~~ee~~|High 30 50 0.49 <br>~~ee~~<br>~~ee~~|1.72 <br>~~ee~~<br>~~ee~~|0.03 <br>~~ee~~|0.93<br>~~ee~~|–<br>~~ee~~|0.32 <br>~~ee~~|1.75 <br>~~ee~~|1.37<br>~~ee~~|0.00<br>~~ee~~|0.00 <br>~~ee~~|3.42 <br>~~ee~~|3.04 <br>~~ee~~|ns<br>~~ee~~|
|SSTL3 (II)<br>~~Fe~~<br>~~Re~~<br>~~—~~<br>~~|~~|24 mA <br>~~ee~~<br><br>~~|~~|High 30 25 0.49<br>~~ee~~<br>~~ee~~<br>~~fe~~|High 30 25 0.49<br>~~ee~~<br>~~ee~~<br>~~fe~~|High 30 25 0.49<br>~~ee~~<br>~~ee~~<br>~~fePp~~|High 30 25 0.49 <br>~~ee~~<br>~~ee~~<br>~~Pp~~|1.54 <br>~~ee~~<br>~~ee~~<br>~~Pptt~~|0.03 <br>~~ee~~<br>~~tt~~|0.93<br>~~ee~~<br>~~tt~~|–<br>~~ee~~|0.32 <br>~~ee~~|1.57 <br>~~ee~~|1.25<br>~~ee~~|0.00<br>~~ee~~|0.00 <br>~~ee~~|3.24 <br>~~ee~~|2.92 <br>~~ee~~|ns<br>~~ee~~|
|LVDS<br>~~Re ~~<br>~~—~~<br>~~|~~|24 mA <br> <br>~~|~~|High –<br> ~~ee~~<br>~~fe~~|High –<br>~~ee~~<br>~~fe~~|–<br>~~ee~~<br>~~fePp~~|0.49 <br>~~ee~~<br>~~Pp~~|1.57 <br>~~ee~~<br>~~Pptt~~|0.03 <br>~~tt~~|1.36<br>~~tt~~|–|–|–|–|–|–|–|–|ns|
|LVPECL<br>~~—~~<br>~~|~~<br>~~a~~|24 mA <br>~~|~~|High –<br>~~fe~~<br>~~ee~~|High –<br>~~fe~~<br>~~ee~~|–<br>~~fe Pp~~<br>~~ee ~~|0.49 <br>~~Pp~~<br> ~~ee~~|1.60 <br>~~Pp tt~~<br>~~ee~~|0.03 <br>~~tt~~<br>~~eee~~|1.22<br>~~tt~~<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|ns<br>~~eee~~|
_Notes:_
_1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values._
_2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-123 on page 2-197 for connectivity. This resistor is not required during normal operation._
**2-167**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-93 •**_ **Summary of I/O Timing Characteristics – Software Default Settings Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = I/O Standard Dependent Applicable to Advanced I/Os**
|**I/O Standard**|**Drive Strength (mA)**|**Slew Rate**|**Capacitive Load (pF)**|**External Resistor (Ohm)**|**t DOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|3.3 V LVTTL/<br>3.3 V LVCMOS<br>~~ee~~|12 mA<br>~~ee~~|High 35 pF<br>~~ee~~|High 35 pF<br>~~ee~~|–|0.49|2.64|0.03|0.90|0.32|2.69|2.11|2.40|2.68|4.36|3.78|ns|
|2.5 V LVCMOS<br>~~ee~~<br>~~PR~~|12 mA<br>~~ee~~|High 35 pF<br>~~ee~~|High 35 pF<br>~~ee~~|–|0.49|2.66|0.03|0.98|0.32|2.71|2.56|2.47|2.57|4.38|4.23|ns|
|1.8 V LVCMOS<br>~~ee~~<br>~~PR~~|12 mA<br>~~ee ~~|High 35 pF<br> ~~ee ~~|High 35 pF<br> ~~ee~~|–|0.49|2.64|0.03|0.91|0.32|2.69|2.27|2.76|3.05|4.36|3.94|ns|
|1.5 V LVCMOS<br>~~PR~~|12 mA|High 35 pF|High 35 pF|–|0.49|3.05|0.03|1.07|0.32|3.10|2.67|2.95|3.14|4.77|4.34|ns|
|3.3 V PCI|Per PCI<br>spec|High 10 pF|High 10 pF|25 2|0.49|2.00|0.03|0.65|0.32|2.04|1.46|2.40|2.68|3.71|3.13|ns|
|3.3 V PCI-X<br>~~PR~~|Per PCI-X<br>spec|Per PCI-X<br>High 10 pF|High 10 pF|25 2|0.49|2.00|0.03|0.62|0.32|2.04|1.46|2.40|2.68|3.71|3.13|ns|
|LVDS<br>~~PR~~<br>~~Pe~~|24 mA<br>~~es~~|High<br>~~es~~|–<br>~~es~~|–|0.49 <br>~~ee~~|1.37 <br>~~ee~~|0.03 <br>~~ee~~|1.20<br>~~ee~~|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|LVPECL<br>~~PR~~<br>~~Pe~~|24 mA<br>~~es~~|High<br>~~es~~|–<br>~~es~~|–|0.49 <br>~~ee~~|1.34 <br>~~ee~~|0.03 <br>~~ee~~|1.05<br>~~ee~~|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
_1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values._
_2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-123 on page 2-197 for connectivity. This resistor is not required during normal operation._
_**Table 2-94 •**_ **Summary of I/O Timing Characteristics – Software Default Settings**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = I/O Standard Dependent Applicable to Standard I/Os**
|**I/O Standard**|**Drive Strength (mA)**|**Slew Rate**|**Capacitive Load (pF)**|**External Resistor (Ohm)**|**t DOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|3.3 V LVTTL/<br>3.3 V LVCMOS|8 mA|High|35 pF|–|0.49|3.29|0.03|0.75|0.32|3.36|2.80|1.79|2.01|ns|
|2.5 V LVCMOS<br>~~se~~<br>~~Rs~~|8 mA<br>~~se~~<br>~~ee~~|High<br>~~ee~~|35pF<br>~~ee~~|–<br>~~ee~~|0.49<br>~~ee~~|3.56<br>~~ee~~|0.03<br>~~ee~~|0.96<br>~~ee~~|0.32<br>~~ee~~|3.40<br>~~ee~~|3.56<br>~~ee~~|1.78<br>~~ee~~|1.91<br>~~ee~~|ns<br>~~ee~~|
|1.8 V LVCMOS<br>~~Rs~~|4 mA<br>~~ee~~|High<br>~~ee~~|35pF<br>~~ee~~|–<br>~~ee~~|0.49<br>~~ee~~|4.74<br>~~ee~~|0.03<br>~~ee~~|0.90<br>~~ee~~|0.32<br>~~ee~~|4.02<br>~~ee~~|4.74<br>~~ee~~|1.80<br>~~ee~~|1.85<br>~~ee~~|ns<br>~~ee~~|
|1.5 V LVCMOS<br>~~Rs~~<br>~~se~~|2 mA<br>~~ee~~<br>~~se~~|High<br>~~ee~~|35pF<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.49<br>~~ee~~<br>~~ee~~|5.71<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|1.06<br>~~ee~~|0.32<br>~~ee~~|4.71<br>~~ee~~|5.71<br>~~ee~~|1.83<br>~~ee~~|1.83<br>~~ee~~|ns<br>~~ee~~|
_Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values._
**Revision 8**
**2-168**
_Device Architecture_
## _**Detailed I/O DC Characteristics**_
_**Table 2-95 •**_ **Input Capacitance**
|**_Table 2-95 •_**|**_Table 2-95 •_Input Capacitance**|||||
|---|---|---|---|---|---|
|**Symbol**|**Definition**|**Conditions**|**Min.**|**Max.**|**Units**|
|CIN|Input capacitance|VIN = 0, f = 1.0 MHz||8|pF|
|CINCLK|Input capacitance on the clock pin|VIN = 0, f = 1.0 MHz||8|pF|
_**Table 2-96 •**_ **I/O Output Buffer Maximum Resistances[1]**
|**Standard**|**Drive Strength**|**RPULL-DOWN**<br>**(ohms) 2**|**RPULL-UP**<br>**(ohms) 3**|
|---|---|---|---|
|**Applicable to Pro I/O Banks**<br>~~Ce~~<br>~~a~~||||
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~Ce~~<br>~~a~~|4 mA<br>~~Ce~~<br>~~a~~|100<br>~~Ce~~<br>|300<br>~~Ce~~<br>|
||8 mA<br>~~a~~|50<br>|150<br>|
||12 mA<br>~~es~~|25<br>~~es~~|75<br>~~es~~|
||16 mA<br>~~es~~<br>~~ee~~|17<br>~~es~~<br>~~ee~~|50<br>~~es~~<br>~~ee~~|
||24 mA|11|33|
|2.5 V LVCMOS|4 mA<br>~~es~~|100<br>~~es~~|200<br>~~es~~|
||8 mA<br>~~es~~<br>~~ee~~|50<br>~~es~~<br>~~ee~~|100<br>~~es~~<br>~~ee~~|
||12 mA<br>~~es~~|25<br>~~es~~|50<br>~~es~~|
||16 mA|20|40|
||24 mA<br>~~ee~~|11<br>~~ee~~|22<br>~~ee~~|
|1.8 V LVCMOS|2 mA<br>~~es~~|200<br>~~es~~|225<br>~~es~~|
||4 mA|100|112|
||6 mA<br>~~ee~~|50<br>~~ee~~|56<br>~~ee~~|
||8 mA<br>~~es~~|50<br>~~es~~|56<br>~~es~~|
||12 mA|20|22|
||16 mA<br>~~ee~~|20<br>~~ee~~|22<br>~~ee~~|
|1.5 V LVCMOS<br>~~I~~|2 mA<br>~~es~~|200<br>~~es~~|224<br>~~es~~|
||4 mA<br>~~es~~|100<br>~~es~~|112<br>~~es~~|
||6 mA<br>~~ee~~|67<br>~~ee~~|75<br>~~ee~~|
||8 mA|33|37|
||12 mA<br>~~es~~<br>|33<br>~~es~~<br>|37<br>~~es~~<br>|
|3.3 V PCI/PCI-X<br>~~I~~|Per PCI/PCI-X specification<br>~~es~~<br>|25<br>~~es~~<br>|75<br>~~es~~<br>|
|3.3 V GTL<br>~~IeG~~|20 mA<br>~~es~~<br>~~eG~~|11<br>~~es~~<br>~~eG~~|–<br>~~es~~<br>~~eG~~|
|2.5 V GTL<br>~~Re~~<br>~~I~~|20 mA<br>~~Re~~|14<br>~~Re~~|–<br>~~Re~~|
|3.3 V GTL+<br>~~Re~~<br>~~Ia~~|35 mA<br>~~Re~~|12<br>~~Re~~|–<br>~~Re~~|
|2.5 V GTL+<br>~~Ia~~|33 mA|15|–|
_1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCC_ , _drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/techdocs/models/ibis.html._
_2. R(PULL-DOWN-MAX) = VOLspec / IOLspec_
_3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec_
**2-169**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-96 •**_ **I/O Output Buffer Maximum Resistances[1] (continued)**
|**Standard**<br>~~a~~|**Drive Strength**<br>|**RPULL-DOWN**<br>**(ohms) 2**<br>|**RPULL-UP**<br>**(ohms) 3**<br>|
|---|---|---|---|
|HSTL (I)<br>~~a~~|8 mA<br>|50<br>|50<br>|
|HSTL (II)<br>~~aee~~|15 mA<br>~~ee~~|25<br>~~ee~~|25<br>~~ee~~|
|SSTL2 (I)<br>~~ee~~<br>~~se~~|17 mA<br>~~ee~~<br>~~se~~|27<br>~~ee~~<br>~~se~~|31<br>~~ee~~<br>~~se~~|
|SSTL2 (II)<br>~~eG~~|21 mA<br>~~eG~~|13<br>~~eG~~|15<br>~~eG~~|
|SSTL3 (I)<br>~~eG~~|16 mA<br>~~eG~~|44<br>~~eG~~|69<br>~~eG~~|
|SSTL3 (II)<br>~~eG~~<br>~~ee~~|24 mA<br>~~eG~~<br>~~ee~~|18<br>~~eG~~<br>~~ee~~|32<br>~~eG~~<br>~~ee~~|
|**Applicable to Advanced I/O Banks**<br>~~Ct~~||||
|3.3 V LVTTL / 3.3 V LVCMOS|2 mA<br>~~ee~~|100<br>~~ee~~|300<br>~~ee~~|
||4 mA<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~|300<br>~~ee~~<br>~~ee~~|
||6 mA<br>~~ee~~|50<br>~~ee~~|150<br>~~ee~~|
||8 mA<br>~~ee~~|50<br>~~ee~~|150<br>~~ee~~|
||12 mA<br>~~ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~|75<br>~~ee~~<br>~~ee~~|
||16 mA<br>~~ee~~|17<br>~~ee~~|50<br>~~ee~~|
||24 mA<br>~~ee~~|11<br>~~ee~~|33<br>~~ee~~|
|2.5 V LVCMOS|2 mA<br>~~ee~~<br>~~a~~|100<br>~~ee~~|200<br>~~ee~~|
||4 mA<br>~~ee~~|100<br>~~ee~~|200<br>~~ee~~|
||6 mA<br>~~ee~~|50<br>~~ee~~|100<br>~~ee~~|
||8 mA<br>~~ee~~<br>~~ee~~|50<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~|
||12 mA<br>~~ee~~|25<br>~~ee~~|50<br>~~ee~~|
||16 mA<br>~~ee~~|20<br>~~ee~~|40<br>~~ee~~|
||24 mA<br>~~ee~~<br>~~ee~~|11<br>~~ee~~<br>~~ee~~|22<br>~~ee~~<br>~~ee~~|
|1.8 V LVCMOS|2 mA<br>~~ee~~|200<br>~~ee~~|225<br>~~ee~~|
||4 mA<br>~~ee~~|100<br>~~ee~~|112<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~ee~~|50<br>~~ee~~<br>~~ee~~|56<br>~~ee~~<br>~~ee~~|
||8 mA<br>~~ee~~|50<br>~~ee~~|56<br>~~ee~~|
||12 mA<br>~~ee~~|20<br>~~ee~~|22<br>~~ee~~|
||16 mA<br>~~ee~~<br>~~ee~~|20<br>~~ee~~<br>~~ee~~|22<br>~~ee~~<br>~~ee~~|
|1.5 V LVCMOS|2 mA<br>~~ee~~|200<br>~~ee~~|224<br>~~ee~~|
||4 mA<br>~~ee~~|100<br>~~ee~~|112<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~ee~~|67<br>~~ee~~<br>~~ee~~|75<br>~~ee~~<br>~~ee~~|
||8 mA<br>~~ee~~|33<br>~~ee~~|37<br>~~ee~~|
||12 mA<br>~~ee~~|33<br>~~ee~~|37<br>~~ee~~|
|3.3 V PCI/PCI-X|Per PCI/PCI-X specification<br>~~ee~~|25<br>~~ee~~|75<br>~~ee~~|
_Notes:_
_1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCC_ , _drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/techdocs/models/ibis.html._
_2. R(PULL-DOWN-MAX) = VOLspec / IOLspec_
_3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec_
**Revision 8**
**2-170**
_Device Architecture_
_**Table 2-96 •**_ **I/O Output Buffer Maximum Resistances[1] (continued)**
|**Standard**|**Drive Strength**|**RPULL-DOWN**<br>**(ohms) 2**|**RPULL-UP**<br>**(ohms) 3**|
|---|---|---|---|
|**Applicable to Standard I/O Banks**||||
|3.3 V LVTTL / 3.3 V LVCMOS|2 mA|100|300|
||4 mA|100|300|
||6 mA|50|150|
||8 mA|50|150|
|2.5 V LVCMOS|2 mA|100|200|
||4 mA|100|200|
||6 mA|50|100|
||8 mA|50|100|
|1.8 V LVCMOS|2 mA|200|225|
||4 mA|100|112|
|1.5 V LVCMOS|2 mA|200|224|
_Notes:_
_1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCC_ , _drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/techdocs/models/ibis.html._
_2. R(PULL-DOWN-MAX) = VOLspec / IOLspec_
_3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec_
## _**Table 2-97 •**_ **I/O Weak Pull-Up/Pull-Down Resistances**
**Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values**
|**VCCI**|**R(WEAK PULL-UP)**<br>**1**<br>**(ohms)**|**R(WEAK PULL-UP)**<br>**1**<br>**(ohms)**|**R(WEAK PULL-DOWN)**<br>**2**<br>**(ohms)**|**R(WEAK PULL-DOWN)**<br>**2**<br>**(ohms)**|
|---|---|---|---|---|
||**Min.**|**Max.**|**Min.**|**Max.**|
|3.3 V|10 k|45 k|10 k|45 k|
|2.5 V|11 k|55 k|12 k|74 k|
|1.8 V|18 k|70 k|17 k|110 k|
|1.5 V|19 k|90 k|19 k|140 k|
_Notes:_
_1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN_
_2. R(WEAK PULL-DOWN-MAX) = VOLspec / IWEAK PULL-DOWN-MIN_
**2-171**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-98 •**_ **I/O Short Currents IOSH/IOSL**
|~~RO~~|**Drive Strength**<br>~~RO~~|**IOSH (mA)***<br>~~RO~~|**IOSL (mA)***<br>~~RO~~|
|---|---|---|---|
|**Applicable to Pro I/O Banks**<br>~~Ce~~||||
|3.3 V LVTTL / 3.3 V LVCMOS|4 mA<br>~~es~~|25<br>~~es~~|27<br>~~es~~|
||8 mA<br>~~ee~~|51<br>~~ee~~|54<br>~~ee~~|
||12 mA<br>~~ee~~|103<br>~~ee~~|109<br>~~ee~~|
||16 mA<br>~~es~~|132<br>~~es~~|127<br>~~es~~|
||24 mA<br>~~es~~|268<br>~~es~~|181<br>~~es~~|
|2.5 V LVCMOS|4 mA<br>~~es~~<br>~~es~~|16<br>~~es~~<br>~~es~~|18<br>~~es~~<br>~~es~~|
||8 mA<br>~~es~~|32<br>~~es~~|37<br>~~es~~|
||12 mA<br>~~es~~|65<br>~~es~~|74<br>~~es~~|
||16 mA<br>~~es~~<br>~~es~~|83<br>~~es~~<br>~~es~~|87<br>~~es~~<br>~~es~~|
||24 mA<br>~~es~~|169<br>~~es~~|124<br>~~es~~|
|1.8 V LVCMOS|2 mA<br>~~es~~|9<br>~~es~~|11<br>~~es~~|
||4 mA<br>~~es~~<br>~~es~~|17<br>~~es~~<br>~~es~~|22<br>~~es~~<br>~~es~~|
||6 mA<br>~~es~~|35<br>~~es~~|44<br>~~es~~|
||8 mA<br>~~es~~|45<br>~~es~~|51<br>~~es~~|
||12 mA<br>~~es~~<br>~~es~~|91<br>~~es~~<br>~~es~~|74<br>~~es~~<br>~~es~~|
||16 mA<br>~~es~~|91<br>~~es~~|74<br>~~es~~|
|1.5 V LVCMOS<br>~~Ce~~|2 mA<br>~~es~~|13<br>~~es~~|16<br>~~es~~|
||4 mA<br>~~es~~<br>~~es~~|25<br>~~es~~<br>~~es~~|33<br>~~es~~<br>~~es~~|
||6 mA<br>~~es~~|32<br>~~es~~|39<br>~~es~~|
||8 mA<br>~~es~~|66<br>~~es~~|55<br>~~es~~|
||12 mA<br>~~es~~<br>~~es~~|66<br>~~es~~<br>~~es~~|55<br>~~es~~<br>~~es~~|
|**Applicable to Advanced I/O Banks**<br>~~es~~<br>~~Ce~~||||
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~Ce~~|2 mA<br>~~es~~<br>~~es~~|25<br>~~es~~<br>~~es~~|27<br>~~es~~<br>~~es~~|
||4 mA<br>~~es~~<br>~~es~~|25<br>~~es~~<br>~~es~~|27<br>~~es~~<br>~~es~~|
||6 mA<br>~~es~~|51<br>~~es~~|54<br>~~es~~|
||8 mA<br>~~es~~|51<br>~~es~~|54<br>~~es~~|
||12 mA<br>~~es~~<br>~~es~~|103<br>~~es~~<br>~~es~~|109<br>~~es~~<br>~~es~~|
||16 mA<br>~~es~~|132<br>~~es~~|127<br>~~es~~|
||24 mA<br>~~es~~|268<br>~~es~~|181<br>~~es~~|
|3.3 V LVCMOS|2 mA<br>~~es~~<br>~~es~~|25<br>~~es~~<br>~~es~~|27<br>~~es~~<br>~~es~~|
||4 mA<br>~~es~~|25<br>~~es~~|27<br>~~es~~|
||6 mA<br>~~es~~<br>~~ee es~~|51<br>~~es~~<br>~~es~~|54<br>~~es~~|
||8 mA<br>~~es~~<br>~~ee es~~|51<br>~~es~~<br>~~es~~|54<br>~~es~~|
||12 mA<br>~~ee es~~<br>~~a~~|103<br>~~es~~<br>~~a~~|109<br>~~a~~|
||16 mA<br>~~es~~|132<br>~~es~~|127<br>~~es~~|
||24 mA<br>~~es~~<br>~~es~~|268<br>~~es~~<br>~~es~~|181<br>~~es~~<br>~~es~~|
_Note: *TJ = 100°C_
**Revision 8**
**2-172**
_Device Architecture_
_**Table 2-98 •**_ **I/O Short Currents IOSH/IOSL (continued)**
|~~a~~|**Drive Strength**|**IOSH (mA)***|**IOSL (mA)***|
|---|---|---|---|
|2.5 V LVCMOS|2 mA<br>~~es~~|16<br>~~es~~|18<br>~~es~~|
||4 mA<br>~~ee~~|16<br>~~ee~~|18<br>~~ee~~|
||6 mA<br>~~es~~|32<br>~~es~~|37<br>~~es~~|
||8 mA<br>~~es~~|32<br>~~es~~|37<br>~~es~~|
||12 mA<br>~~ee~~|65<br>~~ee~~|74<br>~~ee~~|
||16 mA<br>~~ee~~|83<br>~~ee~~|87<br>~~ee~~|
||24 mA<br>~~ee~~<br>~~es~~|169<br>~~ee~~<br>~~es~~|124<br>~~ee~~<br>~~es~~|
|1.8 V LVCMOS|2 mA<br>~~Re~~|9<br>~~Re~~|11<br>~~Re~~|
||4 mA<br>~~ee~~|17<br>~~ee~~|22<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~es~~|35<br>~~ee~~<br>~~es~~|44<br>~~ee~~<br>~~es~~|
||8 mA<br>~~ee~~|45<br>~~ee~~|51<br>~~ee~~|
||12 mA<br>~~ee~~|91<br>~~ee~~|74<br>~~ee~~|
||16 mA<br>~~ee~~<br>~~es~~|91<br>~~ee~~<br>~~es~~|74<br>~~ee~~<br>~~es~~|
|1.5 V LVCMOS|2 mA<br>~~ee~~|13<br>~~ee~~|16<br>~~ee~~|
||4 mA<br>~~ee~~|25<br>~~ee~~|33<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~es~~|32<br>~~ee~~<br>~~es~~|39<br>~~ee~~<br>~~es~~|
||8 mA<br>~~ee~~|66<br>~~ee~~|55<br>~~ee~~|
||12 mA<br>~~ee~~|66<br>~~ee~~|55<br>~~ee~~|
|3.3 V PCI/PCI-X|Per PCI/PCI-X<br>specification<br>~~ee~~|103<br>~~ee~~|109<br>~~ee~~|
|**Applicable to Standard I/O Banks**<br>~~Ce~~||||
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~Ce~~|2 mA<br>~~Ce~~<br>~~es~~|25<br>~~Ce~~<br>~~es~~|27<br>~~Ce~~<br>~~es~~|
||4 mA<br>~~es~~|25<br>~~es~~|27<br>~~es~~|
||6 mA<br>~~ee~~|51<br>~~ee~~|54<br>~~ee~~|
||8 mA<br>~~ee~~<br>~~es~~|51<br>~~ee~~<br>~~es~~|54<br>~~ee~~<br>~~es~~|
|2.5 V LVCMOS<br>~~a~~|2 mA<br>~~es~~|16<br>~~es~~|18<br>~~es~~|
||4 mA<br>~~ee~~|16<br>~~ee~~|18<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~es~~|32<br>~~ee~~<br>~~es~~|37<br>~~ee~~<br>~~es~~|
||8 mA<br>~~es~~<br>~~a~~|32<br>~~es~~<br>|37<br>~~es~~<br>|
|1.8 V LVCMOS<br>~~a~~|2 mA<br>~~a~~|9<br>|11<br>|
||4 mA<br>~~aes~~|17<br>~~es~~|22<br>~~es~~|
|1.5 V LVCMOS<br>~~ee~~|2 mA<br>~~ee~~|13<br>~~ee~~|16<br>~~ee~~|
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions.
**2-173**
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_Fusion Family of Mixed Signal FPGAs_
_**Table 2-99 •**_ **Short Current Event Duration before Failure**
|**Temperature**|**Time Before Failure**|
|---|---|
|–40°C|>20 years|
|0°C|>20 years|
|25°C|>20 years|
|70°C|5 years|
|85°C|2 years|
|100°C|6 months|
_**Table 2-100 •**_ **Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers**
|**Input Buffer Configuration**|**Hysteresis Value (typ.)**|
|---|---|
|3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)|240 mV|
|2.5 V LVCMOS (Schmitt trigger mode)|140 mV|
|1.8 V LVCMOS (Schmitt trigger mode)|80 mV|
|1.5 V LVCMOS (Schmitt trigger mode)|60 mV|
_**Table 2-101 •**_ **I/O Input Rise Time, Fall Time, and Related I/O Reliability**
|**Input Buffer**|**Input Rise/Fall Time (min.)**|**Input Rise/Fall Time (max.)**|**Reliability**|
|---|---|---|---|
|LVTTL/LVCMOS (Schmitt trigger<br>disabled)|No requirement|10 ns*|20 years (100°C)|
|LVTTL/LVCMOS (Schmitt trigger<br>enabled)|No requirement|No requirement, but input<br>noise voltage cannot exceed<br>Schmitt hysteresis|20 years (100°C)|
|HSTL/SSTL/GTL|No requirement|10 ns*|10 years (100°C)|
|LVDS/BLVDS/M-LVDS/LVPECL|No requirement|10 ns*|10 years (100°C)|
_Note: * The maximum input rise/fall time is related only to the noise induced into the input buffer trace. If the noise is low, the rise time and fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure there is no excessive noise coupling into input signals._
**Revision 8**
**2-174**
_Device Architecture_
## _**Single-Ended I/O Characteristics**_
## _**3.3 V LVTTL / 3.3 V LVCMOS**_
Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL support.
_**Table 2-102 •**_ **Minimum and Maximum DC Input and Output Levels**
|**3.3 V LVTTL /**<br>**3.3 V LVCMOS**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA **|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|**Applicable to Pro I/O Banks**<br>~~DR~~<br>~~eeGeQs~~|||||||||||||
|4 mA<br>~~DR~~<br>~~ee~~<br>~~Rs~~|–0.3<br>~~DR~~<br>~~ee~~<br>~~es~~|0.8<br>~~DR~~<br>~~Ge~~<br>~~es~~|2<br>~~DR~~<br>~~Ge~~<br>~~ee~~|3.6<br>~~DR~~<br>~~Qs~~<br>~~se~~|0.4<br>~~DR~~<br>~~Qs~~<br>~~se~~|2.4<br>~~DR~~<br>~~Qs~~<br>~~Oe~~|4<br>~~DR~~<br>~~Qs~~<br>~~Oe~~|4<br>~~DR~~<br>~~Qs~~<br>~~Oe~~|27<br>~~DR~~<br>~~Qs~~<br>~~OO~~|25<br>~~DR~~<br>~~Qs~~<br>~~OO~~|10<br>~~DR~~<br>~~Qs~~<br>~~OO~~|10<br>~~DR~~<br>~~Qs~~|
|8 mA<br>~~ee~~<br>~~Rs~~|–0.3<br>~~ee ~~<br>~~es~~|0.8<br> ~~Ge~~<br>~~es~~|2<br>~~Ge~~<br>~~ee~~|3.6<br>~~Qs~~<br>~~se~~|0.4<br>~~Qs~~<br>~~se~~|2.4<br>~~Qs~~<br>~~Oe~~|8<br>~~Qs~~<br>~~Oe~~|8<br>~~Qs~~<br>~~Oe~~|54<br>~~Qs~~<br>~~OO~~|51<br>~~Qs~~<br>~~OO~~|10<br>~~Qs~~<br>~~OO~~|10<br>~~Qs~~|
|12 mA<br>~~Rs~~<br>~~a~~<br>~~De~~|–0.3<br>~~es ~~<br>~~a~~<br>~~a~~<br>~~es~~<br>|0.8<br> ~~es ~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~es~~<br>|2<br> ~~ee ~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~es~~<br>|3.6<br> ~~se~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~<br>|0.4<br>~~se~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~sO~~<br>|2.4<br>~~Oe~~<br>~~a~~<br>~~a~~<br>~~sO~~|12<br>~~Oe~~<br>~~a~~<br>~~sO~~|12<br>~~Oe~~<br>~~a~~<br>~~sO~~|109<br>~~OO~~|103<br>~~OO~~|10<br>~~OO~~|10|
|16 mA<br>~~a~~<br>~~De~~|–0.3<br>~~a~~<br>~~es~~<br>~~ss~~|0.8<br>~~a~~<br>~~es~~<br>~~ss~~|2<br>~~a~~<br>~~es~~<br>~~Gs~~|3.6<br>~~ee~~<br>~~Ge~~|0.4<br>~~sO~~<br>~~Ge~~|2.4<br>~~sO~~|16<br>~~sO~~|16<br>~~sO~~|127|132|10|10|
|24 mA<br>~~De~~|–0.3<br>~~es~~<br>~~ss~~|0.8<br>~~es~~<br>~~ss~~|2<br>~~es~~<br>~~Gs~~|3.6<br>~~ee~~<br>~~Ge~~|0.4<br>~~sO~~<br>~~Ge~~|2.4<br>~~sO~~|24<br>~~sO~~|24<br>~~sO~~|181|268|10|10|
|**Applicable to Advanced I/O Banks**<br>~~es ee sO~~<br>~~De ssGs Ge~~<br>~~Ce~~<br>~~Po~~|||||||||||||
|2 mA<br>~~Po~~<br>~~Po~~|–0.3|0.8|2|3.6|0.4|2.4|2|2|27|25|10|10|
|4 mA<br>~~Po~~<br>~~Po~~<br>~~po~~|–0.3|0.8|2|3.6|0.4|2.4|4|4|27|25|10|10|
|6 mA<br>~~Po~~<br>~~po~~<br>~~a~~|–0.3<br>~~a~~|0.8<br>~~ae i~~|2<br>~~i~~|3.6<br>~~ee~~|0.4<br>~~es~~|2.4<br>~~ee~~|6<br>~~Oe~~|6<br>~~Oe~~|54|51|10|10|
|8 mA<br>~~po~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~es~~|0.8<br>~~ae i~~<br>~~es~~|2<br>~~i~~<br>~~es~~|3.6<br>~~ee~~<br>~~es es~~|0.4<br>~~es~~<br>~~es~~|2.4<br>~~ee~~|8<br>~~Oe~~<br>~~ss~~|8<br>~~Oe~~<br>~~ss~~|54<br>~~ss~~|51|10|10|
|12 mA<br>~~a~~<br>~~a~~<br>~~Re~~|–0.3<br>~~a ~~<br>~~es~~<br>~~Gs~~|0.8<br> ~~ae i~~<br>~~es~~<br>~~Gs~~|2<br>~~i ~~<br>~~es~~<br>~~Ge~~|3.6<br> ~~ee~~<br>~~es es~~<br>~~GQ~~|0.4<br>~~es ~~<br>~~es~~<br>~~GQ~~|2.4<br> ~~ee ~~|12<br> ~~Oe~~<br>~~ss~~|12<br>~~Oe~~<br>~~ss~~|109<br>~~ss~~|103|10|10|
|16 mA<br>~~a~~<br>~~Re~~<br>~~po~~|–0.3<br>~~es ~~<br>~~Gs~~<br>|0.8<br> ~~es~~<br>~~Gs~~<br>|2<br>~~es~~<br>~~Ge~~<br>|3.6<br>~~es es~~<br>~~GQ~~<br>|0.4<br>~~es~~<br>~~GQ~~<br>|2.4<br>|16<br>~~ss~~<br>|16<br>~~ss~~<br>|127<br>~~ss~~<br>|132<br>|10<br>|10<br>|
|24 mA<br>~~Re ~~<br>~~po~~|–0.3<br> ~~Gs~~<br>|0.8<br>~~Gs~~<br>|2<br>~~Ge~~<br>|3.6<br>~~GQ~~<br>|0.4<br>~~GQ~~<br>|2.4<br>|24<br>|24<br>|181<br>|268<br>|10<br>|10<br>|
|**Applicable to Standard I/O Banks**<br>~~poRe~~<br>~~eeGeOeGQ~~|||||||||||||
|2 mA<br>~~ee~~<br>~~po~~|–0.3<br>~~ee~~|0.8<br>~~GeOe~~|2<br>~~GeOe~~|3.6<br>~~GQ~~|0.4<br>~~GQ~~|2.4|2|2|27|25|10|10|
|4 mA<br>~~ee~~<br>~~po~~<br>~~es~~|–0.3<br>~~ee~~<br>~~es es ee~~|0.8<br>~~GeOe~~<br>~~es ee~~|2<br>~~GeOe~~<br>~~es ee~~|3.6<br>~~GQ~~<br>~~se~~|0.4<br>~~GQ~~<br>~~se~~|2.4<br>~~ee~~|4<br>~~Oe~~|4<br>~~Oe~~|27<br>~~ee~~|25|10|10|
|6 mA<br>~~po~~<br>~~es~~<br>~~a~~|–0.3<br>~~es es ee~~<br>~~es~~|0.8<br>~~es ee~~<br>~~re ae~~|2<br>~~es ee~~<br>~~ae ee~~|3.6<br>~~se~~<br>~~ee es~~|0.4<br>~~se~~<br>~~es ee~~|2.4<br>~~ee~~<br>~~ee~~|6<br>~~Oe~~<br>~~Oe~~|6<br>~~Oe~~<br>~~es~~|54<br>~~ee~~<br>~~es~~|51|10|10|
|8 mA<br>~~es~~<br>~~a~~|–0.3<br>~~es es ee~~<br>~~es~~|0.8<br>~~es ee~~<br>~~re ae~~|2<br>~~es ee ~~<br>~~ae ee~~|3.6<br> ~~se~~<br>~~ee es~~|0.4<br>~~se~~<br>~~es ee~~|2.4<br>~~ee~~<br>~~ee~~|8<br>~~Oe~~<br>~~Oe~~|8<br>~~Oe ~~<br>~~es~~|54<br> ~~ee~~<br>~~es~~|51|10|10|
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**==> picture [344 x 68] intentionally omitted <==**
**----- Start of picture text -----**<br>
R = 1 k R to VCCI for tLZ / tZL / tZLS<br>Test Point<br>Test Point R to GND for tHZ / tZH / tZHS<br>Data Path 1 35 pF Enable Path 4 35 pF for tZH / tZHS / tZL / tZLS<br>} } 35 pF for tHZ / tLZ<br>**----- End of picture text -----**<br>
_**Figure 2-119 •**_ **AC Loading**
**2-175**
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_Fusion Family of Mixed Signal FPGAs_
_**Table 2-103 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|
|**0**|**3.3**|**1.4**|**–**|**35**|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-104 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V**
**Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tPYS**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a~~|0.66<br>~~a ~~|11.01<br> ~~a~~|0.04|1.20<br>~~ee~~|1.57<br>~~ee~~|0.43<br>~~ee ~~|11.21<br> ~~ee~~|9.05<br>~~ee~~|2.69|2.44|13.45|11.29|ns|
||–1<br>~~a ~~|0.56<br> ~~a ~~|9.36<br> ~~a~~|0.04|1.02<br>~~ee~~|1.33<br>~~ee~~|0.36<br>~~ee ~~|9.54<br> ~~ee~~|7.70<br>~~ee~~|2.29|2.08|11.44|9.60|ns|
||–2<br>~~a~~|0.49<br>~~a~~|8.22|0.03<br>~~ee~~|0.90<br>~~ee~~|1.17<br>~~ee~~|0.32<br>~~ee~~|8.37<br>~~ee~~|6.76<br>~~ee~~|2.01<br>~~ee~~|1.82<br>~~ee~~|10.04<br>~~ee~~|8.43<br>~~ee~~|ns<br>~~ee~~|
|8 mA|Std.<br>~~a~~|0.66<br>~~a ~~|7.86<br> ~~a~~|0.04|1.20<br>~~ee~~|1.57<br>~~ee~~|0.43<br>~~ee ~~|8.01<br> ~~ee~~|6.44<br>~~ee~~|3.04|3.06<br>~~ee~~|10.24<br>~~ee~~|8.68<br>~~ee~~|ns|
||–1<br>~~a~~|0.56<br>~~a~~|6.69|0.04<br>~~ee~~|1.02<br>~~ee~~|1.33<br>~~ee~~|0.36<br>~~ee~~|6.81<br>~~ee~~|5.48<br>~~ee~~|2.58<br>~~ee~~|2.61<br>~~ee~~|8.71<br>~~ee~~|7.38<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~a~~|5.87|0.03<br>~~ee~~|0.90<br>~~ee~~|1.17<br>~~ee~~|0.32<br>~~ee~~|5.98<br>~~ee~~|4.81<br>~~ee~~|2.27<br>~~ee~~|2.29<br>~~ee~~|7.65<br>~~ee~~|6.48<br>~~ee~~|ns<br>~~ee~~|
|12 mA|Std.<br>~~a~~|0.66<br>~~a ~~|6.03<br> ~~a~~|0.04|1.20<br>~~ee~~|1.57<br>~~ee~~|0.43<br>~~ee ~~|6.14<br> ~~ee~~|5.02<br>~~ee~~|3.28|3.47<br>~~ee~~|8.37<br>~~ee~~|7.26<br>~~ee~~|ns|
||–1<br>~~a~~|0.56<br>~~a~~|5.13|0.04<br>~~ee~~|1.02<br>~~ee~~|1.33<br>~~ee~~|0.36<br>~~ee~~|5.22<br>~~ee~~|4.27<br>~~ee~~|2.79<br>~~ee~~|2.95<br>~~ee~~|7.12<br>~~ee~~|6.17<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~a ~~<br>~~a~~|4.50<br> ~~a~~|0.03<br>~~ee~~|0.90<br>~~ee~~<br>~~ee~~|1.17<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|4.58<br>~~ee~~|3.75<br>~~ee~~|2.45<br>~~ee~~|2.59|6.25<br>~~ee~~|5.42<br>~~ee~~|ns<br>~~ee~~|
|16 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>|5.62<br>|0.04<br>~~ee~~|1.20<br>~~ee~~|1.57<br>~~ee~~|0.43<br>~~ee~~|5.72<br>~~ee~~|4.72<br>~~ee~~<br>~~ee~~|3.32<br>~~ee~~<br>~~ee~~|3.58|7.96<br>~~ee~~<br>~~ee~~|6.96<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~a ~~<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br> ~~a~~<br>|4.78<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~|1.33<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|4.87<br>~~ee~~<br>~~ee~~|4.02<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.83<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.04<br>~~ee~~|6.77<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.92<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br>~~a ~~|0.49<br> ~~a ~~|4.20<br> ~~a~~|0.03|0.90<br>~~ee~~|1.17<br>~~ee ~~|0.32<br> ~~ee~~|4.27<br>~~ee~~|3.53<br>~~ee~~|2.48<br>~~ee~~|2.67|5.94<br>~~ee~~|5.20<br>~~ee~~|ns<br>~~ee~~|
|24 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~|5.24<br>~~ee~~<br>|0.04<br>~~ee~~|1.20<br>~~ee~~|1.57|0.43<br>~~ee~~|5.34<br>~~ee~~|4.69<br>~~ee~~|3.39<br>~~ee~~|3.96|7.58<br>~~ee~~|6.93<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>~~a~~|4.46<br>~~ee~~<br>|0.04<br>~~ee~~|1.02<br>~~ee~~|1.33<br>~~ee~~|0.36<br>~~ee~~|4.54<br>~~ee~~|3.99<br>~~ee~~<br>~~ee~~|2.88<br>~~ee~~<br>~~ee~~|3.37<br>~~ee~~|6.44<br>~~ee~~<br>~~ee~~|5.89<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~a ~~|3.92<br> ~~a~~|0.03|0.90<br>~~ee~~|1.17<br>~~ee~~|0.32|3.99|3.50<br>~~ee~~|2.53<br>~~ee~~|2.96|5.66<br>~~ee~~|5.17<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-176**
_Device Architecture_
_**Table 2-105 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tPYS**|**tEOU**<br>**T**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA<br>~~Pa~~|Std.<br>~~a~~|0.66<br>|7.88<br>|0.04<br>|1.20<br>|1.57<br>|0.43<br>|8.03<br>|6.70<br>|2.69<br>|2.59<br>|10.26<br>|8.94<br>|ns<br>|
||–1<br>~~Be~~<br>~~Pa~~|0.56<br>~~Be~~<br>~~ee~~|6.71<br>~~Be~~<br>~~ee~~|0.04<br>~~Be~~<br>~~ee~~|1.02<br>~~Be~~<br>~~ee~~|1.33<br>~~Be~~<br>~~ee~~|0.36<br>~~Be~~<br>~~ee~~|6.83<br>~~Be~~|5.70<br>~~Be~~|2.29<br>~~Be~~|2.20<br>~~Be~~|8.73<br>~~Be~~|7.60<br>~~Be~~|ns<br>~~Be~~|
||–2<br>~~Be~~<br>~~Pa~~|0.49<br>~~Be~~<br>~~ee~~|5.89<br>~~Be~~<br>~~ee~~|0.03<br>~~Be~~<br>~~ee~~|0.90<br>~~Be~~<br>~~ee~~|1.17<br>~~Be~~<br>~~ee~~|0.32<br>~~Be~~<br>~~ee~~|6.00<br>~~Be~~|5.01<br>~~Be~~|2.01<br>~~Be~~|1.93<br>~~Be~~|7.67<br>~~Be~~|6.67<br>~~Be~~|ns<br>~~Be~~|
|8 mA<br>~~Pa~~<br>~~Pot~~|Std.<br>~~Pa~~<br>~~i~~<br>~~a~~|0.66<br>~~ee~~<br>~~i~~<br>~~i~~|5.08<br>~~ee~~<br>~~i~~<br>~~i~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.20<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.57<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|5.17<br>~~ee~~|4.14|3.05|3.21|7.41|6.38|ns|
||–1<br>~~a~~<br>~~Pot~~|0.56<br>~~i~~<br>~~Pot~~|4.32<br>~~i~~<br>|0.04<br>~~ee~~<br>|1.02<br>~~ee~~<br>|1.33<br>~~ee~~<br>|0.36<br>|4.40<br>|3.52<br>|2.59<br>|2.73<br>|6.30<br>|5.43<br>|ns<br>|
||–2<br>~~a~~<br>~~Pot~~<br>~~a~~|0.49<br>~~i~~<br>~~PotTt~~<br>~~a~~|3.79<br>~~i~~<br>~~Tt~~|0.03<br>~~ee~~<br>~~Tt~~<br>~~ee~~|0.90<br>~~ee~~<br>~~Tt~~<br>~~ee~~|1.17<br>~~ee~~<br>~~Tt~~<br>~~ee~~|0.32<br>~~Tt~~<br>~~eee~~|3.86<br>~~Tt~~<br>~~eee~~|3.09<br>~~Tt~~<br>~~eee~~|2.28<br>~~Tt~~<br>~~ee~~|2.40<br>~~Tt~~<br>~~eee~~|5.53<br>~~Tt~~<br>~~eee~~|4.76<br>~~Tt~~<br>~~eee~~|ns<br>~~Tt~~<br>~~eee~~|
|12 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~a~~<br>~~a~~|0.66<br>~~Pot~~<br>~~a~~|3.67<br>|0.04<br><br>~~ee~~|1.20<br><br>~~ee~~|1.57<br><br>~~ee~~|0.43<br><br>~~eee~~|3.74<br><br>~~eee~~|2.87<br><br>~~eee~~|3.28<br><br>~~ee~~<br>~~ee~~|3.61<br><br>~~eee~~<br>~~eee~~|5.97<br><br>~~eee~~<br>~~eee~~|5.11<br><br>~~eee~~<br>~~eee~~|ns<br><br>~~eee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~eee~~<br>~~a~~<br>~~a~~|0.56<br> ~~a~~<br>~~eee~~<br>|3.12<br>~~eee~~<br>|0.04<br>~~ee~~<br>~~eee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~eee~~<br>~~ee~~|1.33<br>~~ee ~~<br>~~eee~~<br>~~ee~~|0.36<br> ~~eee~~<br>~~eee~~<br>~~ee~~|3.18<br>~~eee~~<br>~~eee~~<br>~~eee~~|2.44<br>~~eee ~~<br>~~eee~~<br>~~eee~~|2.79<br> ~~ee ~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|3.07<br> ~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|5.08<br>~~eee ~~<br>~~eee~~<br>~~eee~~<br>~~eee eee~~|4.34<br> ~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>|2.74<br>|0.03<br>~~ee~~|0.90<br>~~ee~~|1.17<br>~~ee~~|0.32<br>~~ee~~|2.79<br>~~eee~~|2.14<br>~~eee~~|2.45<br>~~ee ~~<br>~~ee~~|2.70<br> ~~eee~~<br>~~eee~~|4.46<br>~~eee ~~<br>~~eee eee~~|3.81<br> ~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|16 mA|Std.<br>~~a~~|0.66<br>~~a~~|3.46<br>~~a~~|0.04<br>~~ee~~<br>a|1.20<br>~~ee~~<br>~~ee~~|1.57<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|3.53<br>~~eee~~<br>~~ee~~|2.61<br>~~eee~~<br>~~ee~~|3.33<br>~~ee~~<br>~~ee~~|3.72<br>~~eee~~|5.76<br>~~eee eee~~|4.84<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~a ~~<br>~~a~~<br><br>~~a~~|0.56<br> ~~a ~~<br>~~i~~<br>|2.95<br> ~~a~~<br>~~i~~<br>|0.04<br>~~ee~~<br>a<br>~~es~~<br>|1.02<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.33<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee ~~<br>~~ee ~~<br>|3.00<br> ~~eee~~<br> ~~ee~~<br>|2.22<br>~~eee ~~<br>~~ee~~<br>|2.83<br> ~~ee ~~<br>~~ee~~<br>|3.17<br> ~~eee~~<br>|4.90<br>~~eee eee~~<br>|4.12<br>~~eee~~<br>|ns<br>~~eee~~<br>|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~i~~<br>|2.59<br>~~i~~<br>|0.03<br>~~es~~<br>|0.90<br>~~ee~~<br>|1.17<br>~~ee~~<br>|0.32<br>|2.63<br>|1.95<br>|2.49<br>|2.78<br>|4.30<br>|3.62<br>|ns<br>|
|24 mA|Std.<br> <br>~~a~~|0.66<br> ~~i~~<br>|3.21<br>~~i~~<br>|0.04<br>~~es ~~<br>|1.20<br> ~~ee~~<br>|1.57<br>~~ee~~<br>|0.43<br>|3.27<br>|2.16<br>|3.39<br>|4.13<br>|5.50<br>|4.39<br>|ns<br>|
||–1<br>~~Be~~|0.56<br>~~Be~~|2.73<br>~~Be~~|0.04<br>~~Be~~|1.02<br>~~Be~~|1.33<br>~~Be~~|0.36<br>~~Be~~|2.78<br>~~Be~~|1.83<br>~~Be~~|2.88<br>~~Be~~|3.51<br>~~Be~~|4.68<br>~~Be~~|3.74<br>~~Be~~|ns<br>~~Be~~|
||–2<br>~~Be~~<br>~~Pe~~|0.49<br>~~Be~~<br>~~Pe~~|2.39<br>~~Be~~<br>~~Pe~~|0.03<br>~~Be~~<br>~~Pe~~|0.90<br>~~Be~~<br>~~Pe~~|1.17<br>~~Be~~<br>~~Pe~~|0.32<br>~~Be~~<br>~~Pe~~|2.44<br>~~Be~~<br>~~Pe~~|1.61<br>~~Be~~<br>~~Pe~~|2.53<br>~~Be~~<br>~~Pe~~|3.08<br>~~Be~~<br>~~Pe~~|4.11<br>~~Be~~<br>~~Pe~~|3.28<br>~~Be~~<br>~~Pe~~|ns<br>~~Be~~<br>~~Pe~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-177**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Table 2-106 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V**
**Applicable to Advanced I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~a~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a~~|0.66<br>~~a~~|10.26<br>~~ee~~|0.04<br>~~ee~~|1.20<br>~~ee~~|0.43<br>~~ee~~|10.45<br>~~ee~~|8.90<br>~~ee~~|2.64<br>~~ee~~|2.46<br>~~ee~~|12.68<br>~~ee~~|11.13<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>~~a~~|8.72<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~a eee~~|0.36<br>~~ee~~<br>~~eee~~|8.89<br>~~ee ~~<br>~~eee~~|7.57<br> ~~ee~~<br>~~eee~~|2.25<br>~~ee~~<br>~~eee~~|2.09<br>~~ee~~<br>~~eee~~|10.79<br>~~ee~~<br>~~eee~~|9.47<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~a ~~|0.49<br> ~~a~~<br> ~~a~~|7.66<br>~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee ~~|0.90<br> ~~a eee~~<br> ~~a~~|0.32<br>~~eee~~<br>~~ee~~|7.80<br>~~eee~~<br>~~ee~~|6.64<br>~~eee~~<br>~~ee~~|1.98<br>~~eee~~<br>~~ee~~|1.83<br>~~eee~~<br>~~ee~~|9.47<br>~~eee~~<br>~~ee~~|8.31<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|8 mA|Std.<br>~~a~~|0.66<br>~~a~~|7.27<br>~~ee~~|0.04<br>~~ee~~|1.20<br>~~a~~|0.43<br>~~ee~~|7.41<br>~~ee~~|6.28<br>~~ee~~|2.98<br>~~ee~~|3.04<br>~~ee~~|9.65<br>~~ee~~|8.52<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a ~~<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br> ~~a~~<br>~~a~~|6.19<br>~~ee~~<br>~~ee~~<br>~~a~~|0.04<br>~~ee ~~<br>~~ee ~~<br>~~ae a~~|1.02<br> ~~a~~<br> ~~i~~<br>~~a ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.30<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.35<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.54<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.59<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.20<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.25<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~a~~<br>~~a~~|5.43<br>~~a~~<br>~~ee~~|0.03<br>~~ae a~~<br>~~ee~~|0.90<br>~~a ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|5.53<br>~~ee~~<br>~~ee~~|4.69<br>~~ee~~<br>~~ee~~|2.23<br>~~ee~~<br>~~ee~~|2.27<br>~~ee~~<br>~~ee~~|7.20<br>~~ee~~<br>~~ee~~|6.36<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|12 mA|Std.<br>~~a ~~<br>~~a~~|0.66<br> ~~a ~~<br>~~a~~|5.58<br> ~~a ~~<br>~~ee~~|0.04<br> ~~ae a~~<br>~~ee~~|1.20<br>~~a ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|5.68<br>~~ee~~<br>~~ee~~|4.87<br>~~ee~~<br>~~ee~~|3.21<br>~~ee~~<br>~~ee~~|3.42<br>~~ee~~<br>~~ee~~|7.92<br>~~ee~~<br>~~ee~~|7.11<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>~~a~~|4.75<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~a eee~~|0.36<br>~~ee~~<br>~~eee~~|4.84<br>~~ee ~~<br>~~eee~~|4.14<br> ~~ee~~<br>~~eee~~|2.73<br>~~ee~~<br>~~eee~~|2.91<br>~~ee~~<br>~~eee~~|6.74<br>~~ee~~<br>~~eee~~|6.05<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~a ~~|0.49<br> ~~a~~<br> ~~a~~|4.17<br>~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee ~~|0.90<br> ~~a eee~~<br> ~~a~~|0.32<br>~~eee~~<br>~~ee~~|4.24<br>~~eee~~<br>~~ee~~|3.64<br>~~eee~~<br>~~ee~~|2.39<br>~~eee~~<br>~~ee~~|2.55<br>~~eee~~<br>~~ee~~|5.91<br>~~eee~~<br>~~ee~~|5.31<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|16 mA|Std.<br>~~a~~|0.66<br>~~a~~|5.21<br>~~ee~~|0.04<br>~~ee~~|1.20<br>~~a~~|0.43<br>~~ee~~|5.30<br>~~ee~~|4.56<br>~~ee~~|3.26<br>~~ee~~|3.51<br>~~ee~~|7.54<br>~~ee~~|6.80<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a ~~<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br> ~~a~~<br>~~a~~|4.43<br>~~ee~~<br>~~ee~~<br>~~ae~~|0.04<br>~~ee ~~<br>~~ee ~~<br>~~ae a~~|1.02<br> ~~a~~<br> ~~ee~~<br>~~a~~|0.36<br>~~ee~~<br>~~ee ~~<br>~~ee~~|4.51<br>~~ee~~<br> ~~ee~~<br>~~ee~~|3.88<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.77<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.99<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.41<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.79<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~a~~<br>~~a~~|3.89<br>~~ae~~<br>~~ee a~~|0.03<br>~~ae a~~<br>~~a~~|0.90<br>~~a~~<br>~~a~~|0.32<br>~~ee~~<br>~~ee~~|3.96<br>~~ee~~<br>~~ee~~|3.41<br>~~ee~~<br>~~ee~~|2.43<br>~~ee~~<br>~~ee~~|2.62<br>~~ee~~<br>~~ee~~|5.63<br>~~ee~~<br>~~ee~~|5.08<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|24 mA|Std.<br>~~a ~~<br>~~a~~|0.66<br> ~~a~~<br>~~a~~|4.85<br>~~ae~~<br>~~ee a~~|0.04<br>~~ae a~~<br>~~a~~|1.20<br>~~a~~<br>~~a~~|0.43<br>~~ee~~<br>~~ee~~|4.94<br>~~ee~~<br>~~ee~~|4.54<br>~~ee~~<br>~~ee~~|3.32<br>~~ee~~<br>~~ee~~|3.88<br>~~ee~~<br>~~ee~~|7.18<br>~~ee~~<br>~~ee~~|6.78<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a ~~<br>~~a~~|4.13<br> ~~ee a~~<br>~~a~~|0.04<br>~~a ~~<br>~~a~~|1.02<br> ~~a~~<br>~~a~~|0.36<br>~~ee~~<br>~~ee~~|4.20<br>~~ee~~<br>~~ee~~|3.87<br>~~ee~~<br>~~ee~~|2.82<br>~~ee~~<br>~~ee~~|3.30<br>~~ee~~<br>~~ee~~|6.10<br>~~ee~~<br>~~ee~~|5.77<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a~~<br>~~ee~~|3.62<br>~~a ~~<br>~~ee~~|0.03<br> ~~a ~~<br>~~ee ~~|0.90<br> ~~a~~<br> ~~a ee~~|0.32<br>~~ee~~<br>~~ee~~|3.69<br>~~ee~~<br>~~ee~~|3.39<br>~~ee~~<br>~~ee~~|2.48<br>~~ee~~<br>~~ee~~|2.90<br>~~ee~~<br>~~ee~~|5.36<br>~~ee~~<br>~~ee~~|5.06<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-178**
_Device Architecture_
_**Table 2-107 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~a~~|7.66<br>~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee~~|1.20<br> ~~i~~<br>~~ee~~|0.43|7.80|6.59|2.65|2.61|10.03|8.82|ns|
||–1<br>~~a~~|0.56<br>~~a~~|6.51<br>~~ee~~|0.04<br>~~ee~~|1.02<br>~~ee~~|0.36|6.63|5.60|2.25|2.22|8.54|7.51|ns|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a~~<br>~~Oe~~|5.72<br>~~ee~~<br>~~Oe~~|0.03<br>~~ee~~<br>~~Oe~~|0.90<br>~~ee~~<br>~~Oe~~|0.32<br>~~Oe~~|5.82<br>~~Oe~~|4.92<br>~~Oe~~|1.98<br>~~Oe~~|1.95<br>~~Oe~~|7.49<br>~~Oe~~|6.59<br>~~Oe~~|ns<br>~~Oe~~|
|8 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>|4.91<br>~~se~~<br>|0.04<br>~~se~~<br>|1.20<br>|0.43<br>|5.00<br>|4.07<br>|2.99<br>|3.20<br>|7.23<br>|6.31<br>~~ee~~<br>|ns<br>~~ee~~<br>|
||–1<br>~~a ~~<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br> ~~a~~<br>|4.17<br>~~se~~<br>|0.04<br>~~se~~<br>~~i ee~~<br>|1.02<br>~~ee~~<br>|0.36<br>~~ee~~<br>|4.25<br>~~ee~~<br>|3.46<br>~~ee~~<br>|2.54<br>~~ee~~<br><br>~~ee~~|2.73<br>~~ee~~<br><br>~~ee~~|6.15<br>~~ee~~<br><br>~~ee~~|5.36<br>~~ee~~<br>~~ee~~<br><br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br><br>~~eee~~|
||–2<br>~~a ~~<br>~~rr~~|0.49<br> ~~a~~|3.66<br>~~ee~~|0.03<br>~~ee~~|0.90<br>~~ee~~|0.32<br>~~ee~~|3.73<br>~~ee~~|3.04<br>~~ee~~|2.23<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~|2.39<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~|5.40<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|4.71<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~**eee**~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~**eee**~~|
|12 mA|Std.<br>~~ee~~<br>~~rr~~|0.66<br>~~ee~~|3.53<br>~~ee~~|0.04<br>~~ee~~|1.20<br>~~ee~~|0.43<br>~~ee~~|3.60<br>~~ee~~|2.82<br>~~ee~~|3.21<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~|3.58<br>~~ee ~~<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|5.83<br> ~~ee ~~<br>~~ee~~<br>~~**e**e~~<br>~~ee~~|5.06<br> ~~eee~~<br>~~ee~~<br>~~**eee**~~|ns<br>~~eee~~<br>~~ee~~<br>~~**eee**~~|
||–1<br>~~rr~~<br>~~a~~|0.56<br>~~ee~~|3.00<br>~~ee~~|0.04<br>~~ee~~|1.02<br>~~e~~|0.36<br>~~e~~|3.06<br>~~e~~<br>~~eee~~|2.40<br>~~e~~<br>~~eee~~|2.73<br>~~e~~~~**e**~~<br>~~e~~<br>~~eee~~|3.05<br>~~e~~~~**e**~~<br>~~e~~<br>~~ee~~|4.96<br>~~**e**e~~<br>~~ee~~<br>~~ee~~|4.30<br>~~**eee**~~<br>~~eee~~|ns<br>~~**eee**~~<br>~~eee~~|
||–2<br>~~rr~~<br>~~ee~~<br>~~a~~|0.49<br>~~ee~~|2.64<br>~~ee~~|0.03<br>~~ee~~|0.90<br>~~ee~~|0.32<br>~~ee~~|2.69<br>~~ee~~<br>~~eee~~|2.11<br>~~ee~~<br>~~eee~~|2.40<br>~~e~~~~**e** ~~<br>~~ee~~<br>~~eee~~|2.68<br> ~~e~~~~**e** ~~<br>~~e~~<br>~~ee~~<br>~~ee~~|4.36<br> ~~**e**e ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.78<br> ~~**eee**~~<br>~~ee~~<br>~~eee~~|ns<br>~~**eee**~~<br>~~ee~~<br>~~eee~~|
|16 mA|Std.<br>~~a~~|0.66|3.33|0.04|1.20|0.43|3.39<br>~~eee~~|2.56<br>~~eee~~|3.26<br>~~eee~~|3.68<br>~~ee~~|5.63<br>~~ee~~|4.80<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~a~~<br>~~a a~~<br>~~a~~|0.56<br>~~a~~<br>~~a~~|2.83<br>~~ee~~<br>~~se~~|0.04<br>~~ee~~<br>~~se~~|1.02<br>~~ee~~<br>~~es~~|0.36<br>~~ee~~|2.89<br>~~eee~~<br>~~ee~~|2.18<br>~~eee~~<br>~~ee~~|2.77<br>~~eee ~~<br>~~ee~~|3.13<br> ~~ee ~~<br>~~ee~~|4.79<br> ~~ee ~~<br>~~ee~~|4.08<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~a~~|2.49<br>~~se~~|0.03<br>~~se~~|0.90<br>~~es~~|0.32|2.53|1.91|2.44|2.75|4.20|3.58|ns|
|24 mA|Std.<br>~~a ~~<br>~~a ~~<br>~~a~~|0.66<br> ~~a~~<br> ~~a~~<br>~~a~~|3.08<br>~~se~~<br>~~ee~~|0.04<br>~~se ~~<br>Oe|1.20<br> ~~es~~|0.43<br>~~ee~~|3.13<br>~~ee~~|2.12<br>~~ee~~|3.32|4.06|5.37|4.35|ns|
||–1<br>~~a~~|0.56<br>~~a~~|2.62<br>~~ee~~|0.04|1.02|0.36|2.66|1.80|2.83|3.45|4.57|3.70|ns|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a~~<br>~~a~~|2.30<br>~~ee~~|0.03|0.90|0.32|2.34|1.58|2.48|3.03|4.01|3.25|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
_**Table 2-108 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a ~~|0.66<br> ~~i~~|9.46<br>~~i ee~~|0.04<br>~~ee~~|1.00<br>~~ee~~|0.43<br>~~ee~~|9.64<br>~~ee~~|8.54<br>~~ee~~|2.07<br>~~ee~~|2.04<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~|0.56<br>~~a ~~|8.05<br> ~~ee~~|0.04<br>~~ee~~|0.85<br>~~ee~~|0.36<br>~~ee~~|8.20<br>~~ee~~|7.27<br>~~ee~~|1.76<br>~~ee~~|1.73<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a ee~~|0.49<br>~~ee~~|7.07<br>~~ee~~|0.03<br>~~ee~~|0.75<br>~~ee~~|0.32<br>~~ee~~|7.20<br>~~ee~~|6.38<br>~~ee~~|1.55<br>~~ee~~|1.52<br>~~ee~~|ns<br>~~ee~~|
|4 mA|Std.<br>~~ee~~|0.66<br>~~ee~~|9.46<br>~~ee~~|0.04<br>~~ee~~|1.00<br>~~ee~~|0.43<br>~~ee~~|9.64<br>~~ee~~|8.54<br>~~ee~~|2.07|2.04|ns|
||–1<br>~~a~~|0.56<br>~~ai~~|8.05<br>~~ai~~|0.04<br>~~i~~|0.85<br>~~i~~|0.36|8.20|7.27|1.76|1.73|ns|
||–2<br>~~a~~|0.49<br>~~a~~|7.07<br>~~aee~~|0.03<br>~~ee~~|0.75<br>~~ee~~|0.32<br>~~ee~~|7.20<br>~~ee~~|6.38<br>~~ee~~|1.55<br>~~ee~~|1.52<br>~~ee~~|ns<br>~~ee~~|
|6 mA|Std.<br>~~a~~|0.66<br>~~i~~|6.57<br>~~i ee~~|0.04<br>~~ee~~|1.00<br>~~ee~~|0.43<br>~~ee~~|6.69<br>~~ee~~|5.98<br>~~ee~~|2.40<br>~~ee~~|2.57<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~|0.56<br>~~a ~~|5.59<br> ~~ee~~|0.04<br>~~ee~~|0.85<br>~~ee~~|0.36<br>~~ee~~|5.69<br>~~ee~~|5.09<br>~~ee~~|2.04<br>~~ee~~|2.19<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~ai~~|4.91<br>~~ai~~|0.03<br>~~i~~|0.75<br>~~i~~|0.32|5.00|4.47|1.79|1.92|ns|
|8 mA|Std.<br>~~a~~|0.66<br>~~a~~|6.57<br>~~aee~~|0.04<br>~~ee~~|1.00<br>~~ee~~|0.43<br>~~ee~~|6.69<br>~~ee~~|5.98<br>~~ee~~|2.40<br>~~ee~~|2.57<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~|0.56<br>~~i~~|5.59<br>~~i~~|0.04|0.85|0.36<br>~~ee~~|5.69<br>~~ee~~|5.09<br>~~ee~~|2.04|2.19|ns|
||–2<br>~~ee~~|0.49<br>~~ee~~|4.91<br>~~ee~~|0.03<br>~~ee~~|0.75<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|5.00<br>~~ee~~<br>~~ee~~|4.47<br>~~ee~~<br>~~ee~~|1.79<br>~~ee~~|1.92<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-179**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-109 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~es ie~~|**tDOUT**<br>~~ie es~~|**tDP**<br>~~es~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~es~~|**tZL**<br>~~es~~|**tZH**<br>~~es~~|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~es ie~~<br>~~ee~~|0.66<br>~~ie es~~<br>~~ee~~|7.07<br>~~es~~<br>~~es ee~~|0.04<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee es ee~~|0.43<br>~~es~~<br>~~es ee~~|7.20<br>~~es~~<br>~~es ee~~|6.23<br>~~es~~<br>~~es es~~|2.07<br>~~es ee~~|2.15<br>~~ee~~|ns|
||–1<br>~~es ie~~<br>~~ee~~<br>~~es ee~~|0.56<br>~~ie es~~<br>~~ee~~<br>~~ee es~~|6.01<br>~~es ~~<br>~~es ee~~<br>~~es~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.85<br>~~ee ~~<br>~~ee es ee~~<br>~~re~~|0.36<br> ~~es ~~<br>~~es ee~~<br>~~se~~|6.12<br> ~~es~~<br>~~es ee~~<br>~~se~~|5.30<br>~~es~~<br>~~es es~~|1.76<br>~~es ee~~|1.83<br>~~ee~~|ns|
||–22<br>~~ee~~<br>~~es ee~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee es~~<br>~~i~~|5.28<br> ~~es ee~~<br>~~es~~|0.03<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.75<br> ~~ee es ee~~<br>~~re~~<br>~~ee~~|0.32<br>~~es ee~~<br>~~se~~<br>~~es~~|5.37<br>~~es ee ~~<br>~~se~~<br>~~ee~~|4.65<br> ~~es es~~<br>~~es~~|1.55<br>~~es ee~~<br>~~ee ee~~|1.60<br>~~ee~~<br>~~ee~~|ns|
|4 mA|Std.<br>~~es ee~~<br>~~a~~<br>~~es ie~~|0.66<br>~~ee es~~<br>~~i~~<br>~~ie es~~|7.07<br>~~es ~~<br>~~es~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~es~~|1.00<br>~~re~~<br>~~ee~~<br>~~ee~~|0.43<br>~~se~~<br>~~es~~<br>~~es~~|7.20<br>~~se~~<br>~~ee~~<br>~~ee~~|6.23<br>~~es~~|2.07<br>~~ee ee~~|2.15<br>~~ee~~|ns|
||–1<br>~~a~~<br>~~es ie~~<br>~~a~~|0.56<br>~~i~~<br>~~ie es~~<br>~~ee~~|6.01<br>~~es~~<br>~~se~~|0.04<br>~~ee~~<br>~~es~~<br>~~se~~|0.85<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~es ~~<br>~~es~~<br>~~es ee~~|6.12<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|5.30<br> ~~es ~~<br>~~es~~|1.76<br> ~~ee ee~~<br>~~es ee~~|1.83<br>~~ee~~<br>~~ee~~|ns|
||–2<br>~~es ie~~<br>~~a~~<br>~~es ie~~|0.49<br>~~ie es~~<br>~~ee~~<br>~~ie es~~|5.28<br>~~es ~~<br>~~se~~<br>~~es~~|0.03<br> ~~es ~~<br>~~se~~<br>~~ee~~|0.75<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.32<br> ~~es ~~<br>~~es ee~~<br>~~es~~|5.37<br> ~~ee~~<br>~~ee~~<br>~~es~~|4.65<br>~~es~~<br>~~es~~|1.55<br>~~es ee~~|1.60<br>~~ee~~|ns|
|6 mA|Std.<br>~~a~~<br>~~es ie~~<br>~~ee~~|0.66<br>~~ee ~~<br>~~ie es~~<br>~~ee~~|4.41<br> ~~se~~<br>~~es~~<br>~~es ee~~|0.04<br>~~se~~<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~<br>~~ee es ee~~|0.43<br>~~es ee~~<br>~~es~~<br>~~es ee~~|4.49<br>~~ee ~~<br>~~es~~<br>~~es ee~~|3.75<br> ~~es ~~<br>~~es~~<br>~~es es~~|2.39<br> ~~es ee~~<br>~~es ee~~|2.69<br>~~ee~~<br>~~ee~~|ns|
||–1<br>~~es ie~~<br>~~ee~~<br>~~a~~|0.56<br>~~ie es~~<br>~~ee~~<br>~~ee~~|3.75<br>~~es ~~<br>~~es ee~~<br>~~es es~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~es~~|0.85<br>~~ee ~~<br>~~ee es ee~~<br>~~ed~~|0.36<br> ~~es ~~<br>~~es ee~~<br>~~es~~|3.82<br> ~~es~~<br>~~es ee~~<br>~~es~~|3.19<br>~~es~~<br>~~es es~~<br>~~ee~~|2.04<br>~~es ee~~<br>~~ee~~|2.29<br>~~ee~~<br>~~ee~~|ns|
||–2<br>~~ee~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee~~|3.29<br> ~~es ee~~<br>~~es es~~|0.03<br>~~ee ~~<br>~~es~~|0.75<br> ~~ee es ee~~<br>~~ed~~|0.32<br>~~es ee~~<br>~~es~~|3.36<br>~~es ee ~~<br>~~es~~|2.80<br> ~~es es~~<br>~~ee~~|1.79<br>~~es ee~~<br>~~ee~~|2.01<br>~~ee~~<br>~~ee~~|ns|
|8 mA|Std.<br>~~a~~|0.66<br>~~ee ~~|4.41<br> ~~es es~~|0.04<br>~~es~~|1.00<br>~~ed~~|0.43<br>~~es~~|4.49<br>~~es ~~|3.75<br> ~~ee ~~|2.39<br> ~~ee ~~|2.69<br> ~~ee~~|ns|
||–1|0.56|3.75|0.04|0.85|0.36|3.82|3.19|2.04|2.29|ns|
||–2|0.49|3.29|0.03|0.75|0.32|3.36|2.80|1.79|2.01|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-180**
_Device Architecture_
## _**2.5 V LVCMOS**_
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications.
_**Table 2-110 •**_ **Minimum and Maximum DC Input and Output Levels**
|**2.5 V**<br>**LVCMOS**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~Cn~~|**Min.**<br>**V**<br>~~Cn~~|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|**Applicable to Pro I/O Banks**<br>~~Cn~~<br>~~aaa~~<br>~~es es~~|||||||||||||
|4 mA<br>~~Cn~~<br>~~a~~<br>~~a~~|–0.3<br>~~Cn~~<br>~~a~~<br>~~a~~|0.7<br>~~a~~<br>~~a~~|1.7<br>~~es~~<br>~~ee~~|3.6<br>~~es es~~<br>~~ee~~|0.7<br>~~es~~<br>~~ee~~|1.7<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|18<br>~~ee~~|16<br>~~ee~~|10<br>~~ee~~|10|
|8 mA<br>~~a ~~<br>~~a~~<br>~~a~~|–0.3<br> ~~a ~~<br>~~a~~<br>~~se~~|0.7<br> ~~a~~<br>~~a~~<br>~~se~~|1.7<br>~~es~~<br>~~ee~~<br>~~re~~|3.6<br>~~es es~~<br>~~ee~~|0.7<br>~~es~~<br>~~ee~~<br>~~GO~~|1.7<br>~~ee~~<br>~~GO~~|8<br>~~ee~~<br>~~GO~~|8<br>~~ee~~<br>~~GO~~|37<br>~~ee~~|32<br>~~ee~~|10<br>~~ee~~|10|
|12 mA<br>~~a ~~<br>~~a~~<br>~~a~~|–0.3<br> ~~a ~~<br>~~se~~<br>~~a~~|0.7<br> ~~a~~<br>~~se~~<br>~~ee~~|1.7<br>~~ee ~~<br>~~re~~<br>~~ee~~|3.6<br> ~~ee~~<br>~~es ee~~|0.7<br>~~ee ~~<br>~~GO~~<br>~~ee~~|1.7<br> ~~ee~~<br>~~GO~~|12<br>~~ee ~~<br>~~GO~~|12<br> ~~ee ~~<br>~~GO~~|74<br> ~~ee~~|65<br>~~ee ~~|10<br> ~~ee~~|10|
|16 mA<br>~~a ~~<br>~~a~~|–0.3<br> ~~se~~<br>~~a~~|0.7<br>~~se ~~<br>~~ee~~|1.7<br> ~~re~~<br>~~ee~~<br>~~es~~|3.6<br>~~es ee~~<br>~~sD~~|0.7<br>~~GO~~<br>~~ee~~<br>~~sD~~|1.7<br>~~GO~~<br>~~sD~~|16<br>~~GO~~<br>~~sD~~|16<br>~~GO~~<br>~~sD~~|87|83|10|10|
|24 mA<br>~~a ~~<br>~~ee~~|–0.3<br> ~~a ~~<br>~~ee~~|0.7<br> ~~ee~~<br>~~ee~~|1.7<br>~~ee~~<br>~~ee~~<br>~~es~~|3.6<br>~~es ee~~<br>~~ee~~<br>~~sD~~|0.7<br>~~ee~~<br>~~ee~~<br>~~sD~~|1.7<br>~~ee~~<br>~~sD~~|24<br>~~ee~~<br>~~sD~~|24<br>~~ee~~<br>~~sD~~|124<br>~~ee~~|169<br>~~ee~~|10<br>~~ee~~|10<br>~~ee~~|
|**Applicable to Advanced I/O Banks**<br>~~es sD~~<br>~~Ce~~<br>~~aaa~~<br>~~es es~~|||||||||||||
|2 mA<br>~~a~~|–0.3<br>~~a~~|0.7<br>~~a~~|1.7<br>~~es~~<br>~~es~~|2.7<br>~~es es~~|0.7<br>~~es~~<br>~~OO~~|1.7<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|18<br>~~OO~~|16|10|10|
|4 mA<br>~~a ~~<br>~~Rs~~|–0.3<br> ~~a ~~<br>~~Rs~~|0.7<br> ~~a~~<br>~~Rs~~|1.7<br>~~es~~<br>~~Rs~~<br>~~es~~|2.7<br>~~es es~~<br>~~Rs~~|0.7<br>~~es~~<br>~~Rs~~<br>~~OO~~|1.7<br>~~Rs~~<br>~~OO~~|4<br>~~Rs~~<br>~~OO~~|4<br>~~Rs~~<br>~~OO~~|18<br>~~Rs~~<br>~~OO~~|16<br>~~Rs~~|10<br>~~Rs~~|10<br>~~Rs~~|
|6 mA<br>~~GO~~<br>~~es~~|–0.3<br>~~GO~~<br>~~ee~~|0.7<br>~~GO~~<br>~~ee~~|1.7<br>~~es~~<br>~~GO~~<br>~~ee~~|2.7<br>~~GO~~<br>~~ee~~|0.7<br>~~OO~~<br>~~GO~~<br>~~ee~~|1.7<br>~~OO~~<br>~~GO~~<br>~~ee~~|6<br>~~OO~~<br>~~GO~~<br>~~ee~~|6<br>~~OO~~<br>~~GO~~<br>~~ee~~|37<br>~~OO~~<br>~~GO~~<br>~~eee~~|32<br>~~GO~~<br>~~eee~~|10<br>~~GO~~<br>~~eee~~|10<br>~~GO~~<br>~~eee~~|
|8 mA<br>~~es~~<br>~~a Be~~|–0.3<br>~~ee~~<br>~~Be~~|0.7<br>~~ee~~<br>~~ee~~|1.7<br>~~ee~~<br>~~ee~~|2.7<br>~~ee~~<br>~~es es~~|0.7<br>~~ee~~<br>~~es~~|1.7<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~es~~|37<br>~~eee~~|32<br>~~eee~~|10<br>~~eee~~|10<br>~~eee~~|
|12 mA<br>~~es ~~<br>~~a Be~~|–0.3<br> ~~ee~~<br>~~Be~~|0.7<br>~~ee~~<br>~~ee~~|1.7<br>~~ee ~~<br>~~ee~~|2.7<br> ~~ee~~<br>~~es es~~|0.7<br>~~ee ~~<br>~~es~~|1.7<br> ~~ee ~~<br>~~ee~~|12<br> ~~ee~~<br>~~ee~~|12<br>~~ee ~~<br>~~es~~|74<br> ~~eee ~~|65<br> ~~eee ~~|10<br> ~~eee~~|10<br>~~eee~~|
|16 mA<br>~~a Be~~<br>~~GG~~<br>~~a~~|–0.3<br>~~Be ~~<br>~~GG~~<br>~~a~~|0.7<br> ~~ee~~<br>~~GG~~<br>~~ee~~|1.7<br>~~ee~~<br>~~GG~~<br>~~ee~~|2.7<br>~~es es~~<br>~~GG~~<br>~~es~~|0.7<br>~~es ~~<br>~~GG~~<br>~~es~~|1.7<br> ~~ee~~<br>~~GG~~|16<br>~~ee ~~<br>~~GG~~|16<br> ~~es~~<br>~~GG~~|87<br>~~GG~~|83<br>~~GG~~|10<br>~~GG~~|10<br>~~GG~~|
|24 mA<br>~~a~~|–0.3<br>~~a~~|0.7<br>~~ee~~|1.7<br>~~ee~~|2.7<br>~~es~~|0.7<br>~~es~~|1.7|24|24|124|169|10|10|
|**Applicable to Standard I/O Banks**<br>~~a a ee~~<br>~~es~~<br>~~es~~<br>~~Ce~~<br>~~ee~~<br>~~OO~~<br>~~a~~|||||||||||||
|2 mA<br>~~se~~<br>~~a~~<br>~~ae~~|–0.3<br>~~se~~<br>~~a~~<br>|0.7<br>~~se~~<br>~~a~~<br>|1.7<br>~~se~~<br>~~ee~~<br>~~es~~<br>|3.6<br>~~se~~<br>~~es~~<br>|0.7<br>~~se~~<br>~~OO~~<br>~~es~~<br>|1.7<br>~~se~~<br>~~OO~~<br>|2<br>~~se~~<br>~~OO~~<br>|2<br>~~se~~<br>~~OO~~<br>|18<br>~~se~~<br>~~OO~~<br>|16<br>~~se~~<br>|10<br>~~se~~<br>|10<br>~~se~~<br>|
|4 mA<br>~~a ~~<br>~~ae~~<br>~~a~~|–0.3<br> ~~a~~<br>~~a~~|0.7<br>~~a~~<br>~~a~~|1.7<br>~~ee~~<br>~~es~~<br>~~ee~~|3.6<br>~~es~~<br>~~ee~~|0.7<br>~~OO~~<br>~~es~~<br>~~ee~~|1.7<br>~~OO~~<br>~~ee~~|4<br>~~OO~~<br>~~ee~~|4<br>~~OO~~<br>~~ee~~|18<br>~~OO~~<br>~~ee~~|16<br>~~ee~~|10<br>~~ee~~|10<br>~~ee~~|
|6 mA<br> <br>~~ae~~<br>~~a~~|–0.3<br> ~~a~~<br>~~a~~|0.7<br>~~a~~<br>~~a~~|1.7<br>~~es~~<br>~~ee~~|3.6<br>~~es~~<br>~~ee~~|0.7<br>~~es~~<br>~~ee~~|1.7<br>~~ee~~|6<br>~~ee~~|6<br>~~ee~~|37<br>~~ee~~|32<br>~~ee~~|10<br>~~ee~~|10<br>~~ee~~|
|8 mA<br> <br>~~ae ~~<br>~~a~~|–0.3<br> ~~a ~~<br> ~~a ~~|0.7<br> ~~a ~~<br> ~~a ~~|1.7<br> ~~es~~<br> ~~ee~~|3.6<br>~~es ~~<br>~~ee ~~|0.7<br> ~~es~~<br> ~~ee~~|1.7<br>~~ee ~~|8<br> ~~ee~~<br>O|8<br>~~ee ~~<br>O|37<br> ~~ee ~~|32<br> ~~ee~~|10<br>~~ee~~|10<br>~~ee~~|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
|Test Point<br>Data Path|35 pF<br>~~1~~<br>¥|Test Point<br>Enable Path<br>R = 1 k<br>~~4~~<br>+|Test Point<br>Enable Path<br>R = 1 k<br>~~4~~<br>+|R to VCCI for tLZ/ tZL/ tZLS<br>R to GND for tHZ/ tZH/ tZHS<br>35 pF for tZH/ tZHS/ tZL/ tZLS<br>35 pF for tHZ/ tLZ||
|---|---|---|---|---|---|
|**_Figure 2-120 •_AC Loading**||||||
|**_Table 2-111 •_AC Waveforms, Measuring Points, and Capacitive Loads**|**AC Waveforms, Measuring Points, and Capacitive Loads**|**AC Waveforms, Measuring Points, and Capacitive Loads**||**AC Waveforms, Measuring Points, and Capacitive Loads**||
|**Input Low (V)**<br>**Input High (V)**||**Measuring Point* (V)**<br>**VREF (typ.) (V)**|||**CLOAD (pF)**|
|0|2.5|1.2||–|35|
## _**Figure 2-120 •**_ **AC Loading**
_**Table 2-111 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
**2-181**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Timing Characteristics**_
## _**Table 2-112 •**_ **2.5 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tPYS**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~ee~~|0.60<br>~~ee~~|12.00<br>~~ee~~|0.04<br>~~ee~~|1.51<br>~~ee~~|1.66<br>~~ee~~|0.43<br>~~ee~~|12.23<br>~~ee ~~|11.61<br> ~~eee~~|2.72<br>~~eee~~|2.20<br>~~eee~~|14.46<br>~~eee~~|13.85<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~eee~~<br>~~a~~|0.51<br>~~eee~~<br>|10.21<br>~~eee~~<br>|0.04<br>~~eee~~<br>|1.29<br>~~eee~~<br>|1.41<br>~~eee~~<br>|0.36<br>~~eee~~<br>|10.40<br>~~eee~~<br>|9.88<br>~~eee~~<br>~~eee~~<br>|2.31<br>~~eee~~<br>~~eee~~<br>|1.87<br>~~eee~~<br>~~eee~~<br>|12.30<br>~~eee~~<br>~~eee~~<br>|11.78<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>|
||–2<br>~~ee~~<br>~~a~~|0.45<br>~~ee~~<br>|8.96<br>~~ee~~<br>|0.03<br>~~ee~~<br>|1.13<br>~~ee~~<br>|1.24<br>~~ee~~<br>|0.32<br>~~ee~~<br>|9.13<br>~~ee~~<br><br>~~ee~~|8.67<br>~~ee~~<br>~~eee~~<br><br>~~ee ee~~|2.03<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|1.64<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|10.80<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|10.34<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|
|8 mA|Std.<br>~~a~~<br>~~a~~|0.60<br>~~ee~~|8.73<br>~~ee~~|0.04<br>~~ee~~|1.51<br>~~ee~~|1.66<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee ee~~|8.89<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.01<br>~~eee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee eee~~|3.10<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.93<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|11.13<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|10.25<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~a~~|0.51<br>~~ee~~|7.43<br>~~ee~~|0.04<br>~~ee~~|1.29<br>~~ee~~|1.41<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee ee~~|7.57<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.82<br>~~ee ee~~<br>~~ee~~<br>~~ee eee~~|2.64<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.49<br>~~ee~~<br>~~ee~~<br>~~eee~~|9.47<br>~~ee ~~<br>~~ee~~<br>~~eee~~|8.72<br> ~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~a~~|0.45<br>~~a~~|6.52<br> a|0.03<br>~~ee~~|1.13<br>~~ee~~|1.24<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ee~~<br>~~ee~~|6.64<br>~~ee~~<br>~~ee ee~~|5.98<br>~~ee eee~~<br>~~ee~~|2.32<br>~~eee~~<br>~~ee~~|2.19<br>~~eee~~<br>~~ee~~|8.31<br>~~eee~~<br>~~ee~~|7.65<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|12 mA|Std.<br>~~ee~~|0.66<br>~~ee~~|6.77<br>~~ee~~|0.04<br>~~ee~~|1.51<br>~~ee~~|1.66<br>~~ee~~|0.43<br>~~ee~~|6.90<br>~~ee ~~|6.11<br> ~~eee~~|3.37<br>~~eee~~|3.39<br>~~eee~~|9.14<br>~~eee~~|8.34<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~eee~~|0.56<br>~~eee~~|5.76<br>~~eee~~|0.04<br>~~eee~~|1.29<br>~~eee~~|1.41<br>~~eee~~|0.36<br>~~eee~~|5.87<br>~~eee~~|5.20<br>~~eee~~|2.86<br>~~eee~~|2.89<br>~~eee~~|7.77<br>~~eee~~|7.10<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~eee~~|0.49<br>~~eee~~|5.06<br>~~eee~~|0.03<br>~~eee~~|1.13<br>~~eee~~|1.24<br>~~eee~~|0.32<br>~~eee~~|5.15<br>~~eee~~<br>~~ee~~|4.56<br>~~eee~~<br>~~ee ee~~|2.51<br>~~eee~~<br>~~ee~~|2.53<br>~~eee~~<br>~~ee~~|6.82<br>~~eee~~<br>~~ee~~|6.23<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|16 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~|6.31<br>~~ee~~|0.04<br>~~ee~~|1.51<br>~~ee~~|1.66<br>~~ee~~|0.43<br>~~ee~~|6.42<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.73<br>~~ee~~<br>~~ee ee~~<br>~~ee eee~~|3.42<br>~~ee~~<br>~~ee~~<br>~~eee~~|3.52<br>~~ee~~<br>~~ee~~<br>~~eee~~|8.66<br>~~ee~~<br>~~ee~~<br>~~eee~~|7.96<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~a~~|0.56<br>~~ee~~|5.37<br>~~ee~~|0.04<br>~~ee~~|1.29<br>~~ee~~|1.41<br>~~ee~~|0.36<br>~~ee~~|5.46<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.87<br>~~ee ee~~<br>~~ee~~<br>~~ee eee~~|2.91<br>~~ee~~<br>~~ee~~<br>~~eee~~|3.00<br>~~ee~~<br>~~ee~~<br>~~eee~~|7.37<br>~~ee~~<br>~~ee~~<br>~~eee~~|6.77<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~a~~|0.49<br>~~a~~|4.71<br> a|0.03<br>~~ee~~|1.13<br>~~ee~~|1.24<br>~~ee~~|0.32<br>~~ee~~|4.80<br>~~ee~~<br>~~ee ee~~|4.28<br>~~ee eee~~<br>~~ee~~|2.56<br>~~eee~~<br>~~ee~~|2.63<br>~~eee~~<br>~~ee~~|6.47<br>~~eee~~<br>~~ee~~|5.95<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|24 mA|Std.<br>~~ee~~|0.66<br>~~ee~~|5.93<br>~~ee~~|0.04<br>~~ee~~|1.51<br>~~ee~~|1.66<br>~~ee~~|0.43<br>~~ee~~|6.04<br>~~ee ~~|5.70<br> ~~eee~~|3.49<br>~~eee~~|4.00<br>~~eee~~|8.28<br>~~eee~~|7.94<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~eee~~|0.56<br>~~eee~~|5.05<br>~~eee~~|0.04<br>~~eee~~|1.29<br>~~eee~~|1.41<br>~~eee~~|0.36<br>~~eee~~|5.14<br>~~eee~~|4.85<br>~~eee~~|2.97<br>~~eee~~|3.40<br>~~eee~~|7.04<br>~~eee~~|6.75<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~ee~~|0.49<br>~~ee~~|4.43<br>~~ee~~|0.03<br>~~ee~~|1.13<br>~~ee~~|1.24<br>~~ee~~|0.32<br>~~ee~~|4.51<br>~~ee~~|4.26<br>~~ee ~~|2.61<br> ~~eee~~|2.99<br>~~eee~~|6.18<br>~~eee~~|5.93<br>~~eee~~|ns<br>~~eee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-182**
_Device Architecture_
_**Table 2-113 •**_ **2.5 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tPYS**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**<br>~~ee~~|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a ~~<br>~~a~~<br>~~a~~|0.60<br> ~~ee~~<br>~~ee~~|8.82<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.51<br>~~ee~~|1.66<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|8.13<br>~~ee~~<br>~~ee~~|8.82<br>~~ee~~<br>~~ee~~|2.72<br>~~ee~~<br>~~ee~~|2.29<br>~~ee~~<br>~~ee~~|10.37<br>~~ee~~<br>~~ee~~<br>~~ee~~|11.05<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~|0.51<br>~~ee~~|7.50<br>~~ee~~|0.04<br>~~ee~~|1.29|1.41|0.36<br>~~ee~~|6.92<br>~~ee~~|7.50<br>~~ee~~|2.31<br>~~ee~~|1.95<br>~~ee~~|8.82<br>~~ee~~<br>~~ee~~|9.40<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~|0.45<br>~~ee~~<br>a|6.58<br>~~ee~~<br> ~~ee~~|0.03<br>~~ee~~<br>~~ee~~|1.13|1.24<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|6.07<br>~~ee~~<br>~~eee~~|6.58<br>~~ee~~<br>~~eee~~|2.03<br>~~ee ~~<br>~~eee~~|1.71<br> ~~ee~~<br>~~eee~~|7.74<br>~~ee ~~<br>~~eee~~<br>~~ee~~|8.25<br> ~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|8 mA|Std.<br>~~a ~~<br>~~a~~|0.60<br> ~~ee~~<br>~~ee~~|5.27<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.51<br>~~ee~~|1.66<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|5.27<br>~~ee~~<br>~~ee~~|5.27<br>~~ee~~<br>~~ee~~|3.10<br>~~ee~~<br>~~ee~~|3.03<br>~~ee~~<br>~~ee~~|7.50<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.51<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~PTT~~|0.51<br>~~ee~~<br>~~PTT~~|4.48<br>~~ee~~<br>~~PTT|~~|0.04<br>~~ee~~|1.29|1.41|0.36<br>~~ee~~|4.48<br>~~ee~~|4.48<br>~~ee~~|2.64<br>~~ee~~|2.58<br>~~ee~~|6.38<br>~~ee~~<br>~~ee~~|6.38<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~PTT~~<br>~~ee~~|0.45<br>~~ee~~<br>~~PTT~~<br>~~ee~~|3.94<br>~~ee~~<br>~~PTT|~~|0.03<br>~~ee~~|1.13|1.24|0.32<br>~~ee~~|3.93<br>~~ee~~<br>~~eee~~|3.94<br>~~ee~~<br>~~eee~~|2.32<br>~~ee ~~<br>~~eee~~|2.26<br> ~~ee~~<br>~~eee~~|5.60<br>~~ee ~~<br>~~eee~~|5.61<br> ~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|12 mA|Std.<br>~~PTT~~<br>~~ee~~<br>~~ee~~<br>~~a~~|0.66<br>~~PTT~~<br>~~ee~~<br>~~ee~~<br>|3.74<br>~~PTT |~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.51<br>~~ee~~<br>~~ee~~<br>|1.66<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~ee~~<br>~~ee~~<br>|3.81<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|3.49<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|3.37<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|3.49<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|6.05<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|5.73<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br><br>|3.18<br><br>|0.04<br><br>|1.29<br>~~ee~~<br><br>|1.41<br>~~ee~~<br><br>|0.36<br>~~ee~~<br><br>|3.24<br>~~eee~~<br>~~ee~~<br><br>~~ee~~<br>|2.97<br>~~eee~~<br>~~eee~~<br><br>~~ee~~<br>|2.86<br>~~eee~~<br>~~eee~~<br><br>~~ee~~<br>|2.97<br>~~eee~~<br>~~eee~~<br><br>~~ee~~<br>|5.15<br>~~eee~~<br>~~eee~~<br><br>~~ee~~<br>|4.87<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|
||–2<br>~~ee~~<br>~~a ee~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~ee~~<br><br>|2.80<br>~~ee~~<br><br>|0.03<br>~~ee~~<br><br>|1.13<br>~~ee~~<br>~~ee~~<br><br>|1.24<br>~~ee~~<br>~~ee~~<br><br>|0.32<br>~~ee~~<br>~~ee~~<br><br>|2.85<br>~~eee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.61<br>~~eee~~<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.51<br>~~eee ~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee eee~~<br>|2.61<br> ~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br><br>~~eee~~<br>|4.52<br>~~eee ~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br><br>~~eee~~<br>|4.28<br> ~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
|16 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br><br>|3.53<br>~~ee~~<br><br>|0.04<br>~~ee~~<br><br>|1.51<br>~~ee~~<br><br>|1.66<br>~~ee~~<br><br>|0.43<br>~~ee~~<br><br>|3.59<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>|3.12<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>|3.42<br>~~ee ~~<br>~~ee~~<br>~~ee eee~~<br><br>|3.62<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~e~~~~**e**~~<br>|5.83<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br><br>~~**e**e~~|5.35<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>|3.00<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.29<br>~~ee~~<br>|1.41<br>~~ee~~<br>|0.36<br>~~ee~~<br>|3.06<br>~~ee~~<br>~~ee~~<br>|2.65<br>~~ee~~<br>~~ee~~<br>|2.91<br>~~ee eee~~<br>~~ee~~<br>|3.08<br>~~eee~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|4.96<br>~~eee~~<br>~~ee~~<br>~~**e**e~~|4.55<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a ~~<br>|2.63<br> ~~ee~~<br>|0.03<br>~~ee~~<br>|1.13<br>~~ee~~<br>|1.24<br>~~ee~~<br>|0.32<br>~~ee~~<br>|2.68<br>~~ee~~<br>|2.33<br>~~ee~~<br>|2.56<br>~~ee~~<br>|2.71<br>~~e~~~~**e**~~<br>~~ee~~<br>|4.35<br>~~**e**e ~~<br>~~ee~~<br>|4.00<br> ~~eee~~<br>~~ee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>|
|24 mA|Std.<br>~~a ~~<br>~~a~~<br>~~a~~|0.66<br> ~~ee~~<br><br>|3.26<br>~~ee~~<br><br>|0.04<br>~~ee~~<br><br>|1.51<br>~~ee~~<br>|1.66<br>~~ee~~<br>|0.43<br>~~ee~~<br>|3.32<br>~~ee~~<br>|2.48<br>~~ee~~<br>|3.49<br>~~ee~~<br>|4.11<br>~~ee~~<br><br>~~eee~~|5.56<br>~~ee~~<br>~~ee~~<br><br>~~eee~~|4.72<br>~~ee~~<br>~~ee~~<br><br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br><br>~~eee~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~a~~|2.77<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|1.41<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|2.83<br>~~ee~~|2.11<br>~~ee~~<br>~~ee~~|2.97<br>~~ee~~<br>~~ee~~|3.49<br>~~ee~~<br>~~eee~~|4.73<br>~~ee~~<br>~~ee~~<br>~~eee~~|4.01<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~a ~~|0.49<br> ~~a~~|2.44<br>~~ee~~|0.03<br>~~ee~~|1.13<br>~~ee~~|1.24<br>~~ee~~|0.32<br>~~ee~~|2.48|1.85<br>~~ee~~|2.61<br>~~ee~~|3.07<br>~~eee~~|4.15<br>~~eee ~~|3.52<br> ~~eee~~|ns<br>~~eee~~|
**2-183**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-114 •**_ **2.5 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V**
**Applicable to Advanced I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**<br>|**tPY**<br>|**tEOUT**<br>|**tZL**<br>|**tZH**<br>~~eee~~<br>|**tLZ**<br>~~eee~~<br>|**tHZ**<br>~~eee eee~~<br>|**tZLS**<br>~~eee~~<br>|**tZHS**<br>~~eee~~<br>|**Units**<br>~~eee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a ee~~<br>~~a~~|0.66<br>~~ee~~<br>|11.40<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.31<br>~~ee~~<br>|0.43<br>~~ee~~<br>|11.22<br>~~ee~~<br>|11.40<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|2.68<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|2.20<br>~~ee~~<br>~~eee eee~~<br><br>~~ee~~|13.45<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|13.63<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee~~|9.69<br>~~ee~~|0.04<br>~~ee~~|1.11<br>~~ee~~|0.36<br>~~ee~~|9.54<br>~~ee~~|9.69<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.28<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|1.88<br>~~eee eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|11.44<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|11.60<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~ee~~|8.51<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.98<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|8.38<br>~~ee~~<br>~~ee~~|8.51<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|2.00<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|1.65<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|10.05<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|10.18<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|8 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>|7.96<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.31<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~ee~~<br>~~ee~~<br>|8.11<br>~~ee~~<br>~~ee~~<br>|7.81<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|3.05<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|2.89<br>~~eee ~~<br>~~ee~~<br>~~eee~~<br>|10.34<br> ~~eee~~<br>~~eee~~<br>~~eee~~<br>|10.05<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~a~~<br>|6.77<br>~~ee~~<br>~~ee~~<br>|0.04<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|1.11<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|6.90<br>~~ee ~~<br>~~ee~~<br>~~e~~<br>|6.65<br> ~~ee ~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|2.59<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.46<br> ~~ee ~~<br>~~eee~~<br>~~ee~~<br>|8.80<br> ~~eee~~<br>~~eee~~<br>~~eee~~<br>|8.55<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
||–2<br>~~a ~~<br>~~a~~<br>~~a~~|0.49<br> ~~a~~<br><br>|5.94<br>~~ee~~<br><br>|0.03<br>~~ee~~<br>~~ee~~<br><br>|0.98<br>~~ee~~<br>~~ee~~<br><br>|0.32<br>~~ee~~<br>~~ee~~<br><br>|6.05<br>~~ee ~~<br>~~e~~<br>~~eee~~<br>|5.84<br> ~~ee~~<br>~~e~~~~**e**~~<br>~~eee~~<br>|2.28<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|2.16<br>~~eee~~<br>~~ee~~<br>~~eee eee~~<br>|7.72<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|7.50<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
|12 mA|Std.<br> <br>~~a e~~<br>~~a~~|0.66<br> ~~a ~~<br>~~e~~<br>|6.18<br> ~~ee~~<br>~~e~~<br>|0.04<br>~~ee ~~<br>~~e~~<br>|1.31<br> ~~ee~~<br>~~e~~<br>|0.43<br>~~ee ~~<br>~~e~~<br>|6.29<br> ~~e~~<br>~~e eee~~<br>|5.92<br>~~e~~~~**e** ~~<br>~~eee~~<br><br>~~ee~~|3.30<br> ~~ee ~~<br>~~eee~~<br><br>~~ee~~|3.32<br> ~~ee ~~<br>~~eee eee~~<br><br>~~ee~~|8.53<br> ~~eee~~<br>~~eee~~<br><br>~~eee~~|8.15<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|
||–1<br><br>~~a~~<br>~~a~~|0.56<br><br>~~ee~~|5.26<br><br>~~ee~~|0.04<br><br>~~ee~~|1.11<br><br>~~ee~~|0.36<br><br>~~ee~~|5.35<br>~~eee~~<br>~~ee~~|5.03<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.81<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.83<br>~~eee eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|7.26<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|6.94<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~e~~|4.61<br>~~ee~~<br>~~e~~~~**e**~~|0.03<br>~~ee~~<br>~~**e**~~|0.98<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|4.70<br>~~ee~~<br>~~ee~~|4.42<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|2.47<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~**e**e~~|2.48<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|6.37<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~**eee**~~|6.09<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~**eee**~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~**eee**~~|
|16 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~e~~|6.18<br>~~e~~~~**e**~~|0.04<br>~~**e**~~|1.31<br>~~ee~~|0.43<br>~~ee~~|6.29<br>~~ee~~|5.92<br>~~eee~~<br>~~ee~~|3.30<br>~~eee~~<br>~~**e**e~~|3.32<br>~~eee ~~<br>~~ee~~|8.53<br> ~~eee~~<br>~~**eee**~~|8.15<br>~~eee~~<br>~~**eee**~~|ns<br>~~eee~~<br>~~**eee**~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~e~~<br>~~ee~~|5.26<br>~~e~~~~**e**~~<br>~~ee~~|0.04<br>~~**e** ~~<br>~~ee~~|1.11<br> ~~ee~~<br>~~e~~|0.36<br>~~ee~~<br>~~e ~~<br>~~ee~~|5.35<br>~~ee ~~<br> ~~ee~~<br>~~ee~~|5.03<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2.81<br> ~~**e**e ~~<br>~~ee~~|2.83<br> ~~ee ~~<br>~~e~~<br>~~ee~~|7.26<br> ~~**eee**~~<br>~~eee~~|6.94<br>~~**eee**~~<br>~~eee~~|ns<br>~~**eee**~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~ee~~|4.61<br>~~ee~~|0.03<br>~~ee~~|0.98|0.32<br>~~ee~~|4.70<br>~~ee~~|4.42<br>~~ee~~<br>~~ee~~|2.47<br>~~ee~~<br>~~ee~~|2.48<br>~~ee~~<br>~~eee~~|6.37<br>~~eee~~<br>~~eee~~|6.09<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|24 mA|Std.<br>~~a~~<br>~~a ee~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~|6.18<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.29<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.92<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.30<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.32<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|8.53<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|8.15<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~|0.56|5.26<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.11<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|5.35<br>~~ee~~<br>~~ee~~|5.03<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.81<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.83<br> ~~eee~~<br>~~ee~~<br>~~ee~~|7.26<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.94<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a~~|0.49|4.61<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.98<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~|4.70<br>~~ee ~~<br>~~ee~~|4.42<br> ~~ee~~<br>~~ee~~|2.47<br>~~ee ~~<br>~~ee~~|2.48<br> ~~ee ~~<br>~~ee~~|6.37<br> ~~eee~~<br>~~eee~~|6.09<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
**Revision 8**
**2-184**
_Device Architecture_
_**Table 2-115 •**_ **2.5 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/Os**
|**Drive**<br>**Strength**|Speed<br>Grade<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**<br>|**tPY**<br>|**tEOUT**<br>|**tZL**<br>|**tZH**<br>~~ee~~<br>|**tLZ**<br>~~ee~~<br>|**tHZ**<br>~~ee~~<br>|**tZLS**<br>~~ee~~<br>|**tZHS**<br>~~eee~~<br>|**Units**<br>~~eee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~eee~~<br>|8.66<br>~~eee~~<br>|0.04<br>~~eee~~<br>|1.31<br>~~eee~~<br>|0.43<br>~~eee~~<br>|7.83<br>~~eee~~<br>|8.66<br>~~eee~~<br>~~ee~~<br><br>~~eee~~|2.68<br>~~eee~~<br>~~ee~~<br><br>~~eee~~|2.30<br>~~eee~~<br>~~ee~~<br><br>~~eee~~|10.07<br>~~eee~~<br>~~ee~~<br><br>~~eee~~|10.90<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|
||–1<br>~~a ee~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~|7.37<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.11<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|6.66<br>~~ee~~<br>~~ee~~|7.37<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|2.28<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|1.96<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|8.56<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|9.27<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~<br>~~ee~~|0.49<br>~~ee~~<br>~~ee~~|6.47<br>~~ee~~<br>~~**e**~~|0.03<br>~~ee~~<br>~~**e**e~~|0.98<br>~~ee~~<br>~~e~~|0.32<br>~~ee~~<br>~~ee~~|5.85<br>~~ee~~<br>~~ee~~|6.47<br>~~eee~~<br>~~ee~~<br>~~**e**ee~~|2.00<br>~~eee ~~<br>~~ee~~<br>~~ee~~|1.72<br> ~~eee~~<br>~~eee~~<br>~~**e**e~~|7.52<br>~~eee ~~<br>~~eee~~<br>~~e~~~~**e**~~|8.14<br> ~~eee~~<br>~~eee~~<br>~~**e**ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|8 mA|Std.<br>~~a~~<br>~~ee~~|0.66<br>~~ee~~<br>~~ee~~<br>~~e~~|5.17<br>~~ee~~<br>~~**e**~~<br>~~e~~|0.04<br>~~ee ~~<br>~~**e**e~~|1.31<br> ~~ee~~<br>~~e~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.04<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.17<br> ~~ee~~<br>~~**e**ee~~|3.05<br>~~ee ~~<br>~~ee~~<br>~~e~~|3.00<br> ~~eee~~<br>~~**e**e~~<br>~~e~~|7.27<br>~~eee ~~<br>~~e~~~~**e**~~|7.40<br> ~~eee~~<br>~~**e**ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~e~~|
||–1<br>~~ee~~|0.56<br>~~ee~~<br>~~e~~|4.39<br>~~**e**~~<br>~~e~~|0.04<br>~~**e**e~~|1.11<br>~~e~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|4.28<br>~~ee~~<br>~~ee~~|4.39<br>~~**e**ee~~|2.59<br>~~ee~~<br>~~e~~|2.55<br>~~**e**e~~<br>~~e~~|6.19<br>~~e~~~~**e**~~|6.30<br>~~**e**ee~~|ns<br>~~ee~~<br>~~e~~|
||–2<br>~~ee~~<br>~~Pot~~<br>~~a~~|0.49<br>~~ee ~~<br>~~e~~<br>~~Pot~~<br>~~a~~|3.86<br> ~~**e**~~<br>~~e~~<br>~~Pot~~<br>~~ee~~|0.03<br>~~**e**e~~<br>~~Pot~~<br>~~ee~~|0.98<br>~~e ~~<br>~~ee~~<br>~~Pot~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~<br>~~Pot~~<br>~~ee~~|3.76<br>~~ee ~~<br>~~ee~~<br>~~Pot~~<br>~~ee~~|3.86<br> ~~**e**ee~~<br>~~Pot~~<br>~~ee~~|2.28<br>~~ee ~~<br>~~e~~<br>~~Pot~~<br>~~ee~~|2.24<br> ~~**e**e~~<br>~~e~~<br>~~Pot~~<br>~~ee~~|5.43<br>~~e~~~~**e** ~~<br>~~Pot~~<br>~~ee~~|5.53<br> ~~**e**ee~~<br>~~Pot~~<br>~~eee~~|ns<br>~~ee~~<br>~~e~~<br>~~Pot~~<br>~~eee~~|
|12 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~|3.56<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~a~~|1.31<br>~~ee~~<br>~~a~~|0.43<br>~~ee~~<br>~~a~~|3.63<br>~~ee~~<br>~~ee~~|3.43<br>~~ee~~<br>~~ee~~|3.30<br>~~ee~~<br>~~ee~~|3.44<br>~~ee~~<br>~~ee~~|5.86<br>~~ee~~<br>~~ee~~|5.67<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~a~~<br>~~a~~<br>~~a~~|3.03<br>~~ee~~<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~a~~|1.11<br>~~ee~~<br>~~a~~<br>~~ee~~|0.36<br>~~ee ~~<br>~~a~~<br>~~ee~~|3.08<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.92<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.81<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.92<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4.99<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4.82<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~a~~<br>~~a~~|0.49<br> ~~a ~~<br>~~a~~<br>~~ee~~|2.66<br> ~~a ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~a ~~<br>~~ee~~|0.98<br> ~~a ~~<br>~~ee~~<br>~~ee~~|0.32<br> ~~a ~~<br>~~ee~~<br>~~ee~~|2.71<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.56<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.47<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.57<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4.38<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|4.23<br> ~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|16 mA|Std.<br>~~a ~~<br>~~a~~<br>~~a~~|0.66<br> ~~a~~<br>~~ee~~<br>~~ee~~|3.35<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.41<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.06<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.36<br> ~~ee ~~<br>~~ee~~<br>~~ee eee~~|3.55<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|5.65<br> ~~ee ~~<br>~~eee~~<br>~~eee~~|5.30<br> ~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~re~~<br>~~ee~~|0.56<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.85<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>|0.04<br> ~~ee~~<br>~~ee~~<br>~~eee~~|1.11<br>~~ee~~<br>~~ee~~<br>~~eee~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~eee~~|2.90<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|2.60<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|2.86<br>~~ee ~~<br>~~ee eee~~<br>~~eee~~<br>~~ee~~|3.02<br> ~~ee ~~<br>~~eee~~<br>~~eee~~<br>~~ee eee~~|4.81<br> ~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|4.51<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~re~~<br>~~ee~~<br>~~re~~|0.49<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.50<br>~~ee ~~<br>~~eee~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~eee~~|0.98<br>~~ee~~<br>~~eee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~eee~~<br>~~ee~~|2.55<br>~~ee ~~<br>~~eee~~<br>~~ee~~|2.29<br> ~~ee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|2.51<br>~~ee eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|2.65<br>~~eee~~<br>~~eee~~<br>~~ee eee~~<br>~~ee~~|4.22<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|3.96<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|24 mA|Std.<br>~~re ~~<br>~~ee~~<br>~~re~~<br>~~a~~|0.66<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.56<br>~~eee~~<br>~~ee~~<br>|0.04<br>~~eee~~<br>~~ee~~<br>|1.31<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|3.63<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|3.43<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|3.30<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|3.44<br>~~eee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>|5.86<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|5.67<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
||–1<br>~~ee ~~<br>~~re~~<br>~~a~~|0.56<br> ~~ee~~<br>~~ee~~<br>|3.03<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.11<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>|3.08<br>~~ee~~<br>~~ee~~<br>|2.92<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|2.81<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|2.92<br> ~~ee eee~~<br>~~ee~~<br>~~ee~~<br><br>~~eee~~|4.99<br>~~eee~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|4.82<br>~~eee~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|
||–2<br> <br>~~re ~~<br>~~a~~|0.49<br> ~~ee~~<br> ~~ee~~<br>~~ee~~|2.66<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.98<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.71<br>~~ee ~~<br>~~ee ~~<br>~~ee~~|2.56<br> ~~ee~~<br> ~~eee~~<br>~~ee~~<br>~~eee~~|2.47<br>~~ee ~~<br>~~eee ~~<br>~~ee~~<br>~~eee~~|2.57<br> ~~ee ~~<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|4.38<br> ~~eee~~<br> ~~eee~~<br>~~ee~~<br>~~eee~~|4.23<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|
_**Table 2-116 •**_ **2.5 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V**
## **Applicable to Standard I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**<br>|**tPY**<br>|**tEOUT**<br>|**tZL**<br>|**tZH**<br>|**tLZ**<br>~~ee~~<br>|**tHZ**<br>|**Units**<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a ~~<br>~~a~~|0.66<br> ~~a~~<br>|11.00<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.29<br>~~ee~~<br>|0.43<br>~~ee~~<br>|10.37<br>~~ee~~<br>|11.00<br>~~ee~~<br>|2.03<br>~~ee~~<br>~~ee~~<br>|1.83<br>~~ee~~<br>|ns<br>~~ee~~<br>|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~se~~<br>~~a~~|9.35<br>~~se~~<br>~~ee~~|0.04<br>~~se~~<br>~~ee~~|1.10<br>~~se~~<br>~~ee~~|0.36<br>~~se~~<br>~~ee~~|8.83<br>~~se~~<br>~~ee~~|9.35<br>~~se~~<br>~~ee~~|1.73<br>~~ee~~<br>~~se~~<br>~~ee~~|1.56<br>~~se~~<br>~~ee~~|ns<br>~~se~~|
||–2<br>~~a~~|0.49<br>~~a~~|8.21<br>~~ee~~|0.03<br>~~ee~~|0.96<br>~~ee~~|0.32<br>~~ee~~|7.75<br>~~ee~~|8.21<br>~~ee~~|1.52<br>~~ee~~|1.37<br>~~ee~~|ns|
|4 mA|Std.<br>~~a ~~<br>~~a ~~<br>~~a~~|0.66<br> ~~a~~<br> ~~se~~<br>|11.00<br>~~ee~~<br>~~se~~<br>|0.04<br>~~ee~~<br>~~se ~~<br>|1.29<br>~~ee ~~<br> ~~ee~~<br>|0.43<br> ~~ee~~<br>~~ee~~<br>|10.37<br>~~ee ~~<br>|11.00<br> ~~ee~~<br>~~ee~~<br>|2.03<br>~~ee ~~<br>~~ee ~~<br>~~ee~~<br>|1.83<br> ~~ee~~<br> ~~ee~~<br>|ns<br>~~ee~~<br>|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>|9.35<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.10<br>~~ee~~<br>|0.36<br>~~ee~~<br>|8.83<br>~~ee~~<br>|9.35<br>~~ee~~<br>|1.73<br>~~ee~~<br>~~ee~~<br>|1.56<br>~~ee~~<br>|ns<br>~~ee~~<br>|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~se~~<br>|8.21<br>~~se~~<br>|0.03<br>~~se~~<br>|0.96<br>~~se~~<br>|0.32<br>~~se~~<br>|7.75<br>~~se~~<br>|8.21<br>~~se~~<br>|1.52<br>~~ee~~<br>~~se~~<br>~~ee~~<br>|1.37<br>~~se~~<br>|ns<br>~~se~~<br>|
|6 mA|Std.<br>~~a ~~<br>~~a~~|0.66<br> ~~a~~<br>|7.50<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.29<br>~~ee~~<br>|0.43<br>~~ee~~<br>|7.36<br>~~ee~~<br>|7.50<br>~~ee~~<br>|2.39<br>~~ee~~<br>~~ee~~<br>|2.46<br>~~ee~~<br>|ns<br>~~ee~~<br>|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~se~~<br>|6.38<br>~~se~~<br>|0.04<br>~~se~~<br>|1.10<br>~~se~~<br>|0.36<br>~~se~~<br>|6.26<br>~~se~~<br>|6.38<br>~~se~~<br>|2.03<br>~~ee~~<br>~~se~~<br>~~ee~~<br>|2.10<br>~~se~~<br>|ns<br>~~se~~<br>|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a~~<br>|5.60<br>~~ee~~<br>|0.03<br>~~ee~~<br>|0.96<br>~~ee~~<br>|0.32<br>~~ee~~<br>|5.49<br>~~ee~~<br>|5.60<br>~~ee~~<br>|1.78<br>~~ee~~<br>~~ee~~<br>|1.84<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|8 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~se~~<br>|7.50<br>~~se~~<br>|0.04<br>~~se~~<br>|1.29<br>~~se~~<br>|0.43<br>~~se~~<br>|7.36<br>~~se~~<br>|7.50<br>~~se~~<br>|2.39<br>~~ee~~<br>~~se~~<br>~~ee~~<br>|2.46<br>~~se~~<br>|ns<br>~~se~~<br>|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>|6.38<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.10<br>~~ee~~<br>|0.36<br>~~ee~~<br>|6.26<br>~~ee~~<br>|6.38<br>~~ee~~<br><br>~~ee~~|2.03<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|2.10<br>~~ee~~<br>|ns<br>~~ee~~<br>|
||–2<br>~~a~~|0.49<br>~~ee~~|5.60<br>~~ee~~|0.03<br>~~ee~~|0.96<br>~~ee~~|0.32<br>~~ee~~|5.49<br>~~ee~~|5.60<br>~~ee~~<br>~~ee~~|1.78<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.84<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-185**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-117 •**_ **2.5 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V**
**Applicable to Standard I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~|0.66<br>~~a~~|8.20<br>~~ee~~|0.04<br>~~ee ~~|1.29<br> ~~ee~~|0.43<br>~~ee~~|7.24<br>~~ee~~|8.20<br>~~ee~~|2.03<br>~~ee~~|1.91<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~|0.56<br>~~ee~~|6.98<br>~~ee~~|0.04<br>~~ee~~|1.10<br>~~ee~~|0.36<br>~~ee~~|6.16<br>~~ee~~|6.98<br>~~ee~~|1.73<br>~~ee~~|1.62<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~a~~|6.13<br>~~ee~~|0.03<br>~~ee ~~|0.96<br> ~~ee~~|0.32<br>~~ee~~|5.41<br>~~ee~~|6.13<br>~~ee~~|1.52<br>~~ee~~|1.43<br>~~ee~~|ns<br>~~ee~~|
|4 mA|Std.<br>~~a~~|0.66<br>~~ee~~|8.20<br>~~ee~~|0.04<br>~~ee~~|1.29<br>~~ee~~|0.43<br>~~ee~~|7.24<br>~~ee~~|8.20<br>~~ee~~|2.03<br>~~ee~~|1.91<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~|0.56<br>~~a~~|6.98<br>~~ee~~|0.04<br>~~ee ~~|1.10<br> ~~ee~~|0.36<br>~~ee~~|6.16<br>~~ee~~|6.98<br>~~ee~~|1.73<br>~~ee~~|1.62<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~ee~~|6.13<br>~~ee~~|0.03<br>~~ee~~|0.96<br>~~ee~~|0.32<br>~~ee~~|5.41<br>~~ee~~|6.13<br>~~ee~~|1.52<br>~~ee~~|1.43<br>~~ee~~|ns<br>~~ee~~|
|6 mA|Std.<br>~~a~~|0.66<br>~~a~~|4.77<br>~~ee~~|0.04<br>~~ee ~~|1.29<br> ~~ee~~|0.43<br>~~ee~~|4.55<br>~~ee~~|4.77<br>~~ee~~|2.38<br>~~ee~~|2.55<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee~~|4.05<br>~~ee~~|0.04<br>~~ee~~|1.10<br>~~ee~~<br>~~eee~~|0.36<br>~~ee~~<br>~~eee~~|3.87<br>~~ee~~<br>~~eee~~|4.05<br>~~ee~~<br>~~ee~~|2.03<br>~~ee~~<br>~~eee~~|2.17<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~|
||–2<br>~~ee~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~ee~~|3.56<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.96<br>~~ee~~<br>~~eee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~eee~~<br>~~ee~~|3.40<br>~~ee~~<br>~~eee~~<br>~~ee~~|3.56<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.78<br>~~ee~~<br>~~eee~~<br>~~ee~~|1.91<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|8 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~<br>|4.77<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.29<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|4.55<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>|4.77<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.38<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>|2.55<br>~~eee ~~<br>~~ee~~<br>~~eee~~<br>|ns<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>|4.05<br> ~~ee~~<br>|0.04<br>~~ee ~~<br>~~ee~~<br>|1.10<br> ~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|3.87<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|4.05<br>~~ee ~~<br>~~ee~~<br><br>~~ee~~|2.03<br> ~~ee ~~<br>~~ee~~<br><br>~~ee~~|2.17<br> ~~ee ~~<br>~~eee~~<br><br>~~ee~~|ns<br> ~~ee~~<br>~~eee~~<br><br>~~ee~~|
||–2<br>~~a ee~~|0.49<br>~~ee~~<br>~~ee~~|3.56<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.96<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.40<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.56<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.78<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.91<br> ~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-186**
_Device Architecture_
## _**1.8 V LVCMOS**_
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and push-pull output buffer.
_**Table 2-118 •**_ **Minimum and Maximum DC Input and Output Levels**
|**1.8 V**<br>**LVCMOS**<br>~~ee~~<br>~~po}~~|**VIL**<br>~~ee~~<br>~~po}tt~~|**VIL**<br>~~ee~~<br>~~po}tt~~|**VIH**<br>~~ee~~<br>~~ttEE~~|**VIH**<br>~~ee~~<br>~~ttEE~~|**VOL**<br><br>~~EE~~|**VOH**<br>~~eee~~<br>~~EE~~|**IOL **<br>~~eee~~|**IOH**<br>~~eee~~|**IOSL**<br>~~eee~~|**IOSH**<br>~~eee~~|**IIL1**<br>~~eee~~|**IIH2**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~ee~~<br>~~po}~~|**Min.**<br>**V**<br>~~ee~~<br>~~po}tt~~|**Max.**<br>**V**<br>~~ee~~<br>~~tt~~|**Min.**<br>**V**<br>~~ee~~<br>~~ttEE~~|**Max.**<br>**V**<br>~~ee ~~<br>~~EE~~|**Max.**<br>**V**<br> <br>~~EE~~|**Min.**<br>**V**<br> ~~eee~~<br>~~EE~~|**mA **<br>~~eee~~|**mA**<br>~~eee~~|**Max.**<br>**mA3**<br>~~eee~~|**Max.**<br>**mA3**<br>~~eee~~|**µA4**<br>~~eee~~|**µA4**<br>~~eee~~|
|**Applicable to Pro I/O Banks**<br>~~po} tt EE~~<br>~~en~~<br>~~eeeeee eee~~<br>~~a~~|||||||||||||
|2 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~<br>~~ee~~|3.6<br>~~ee~~<br>~~ee~~|0.45<br>~~ee~~<br>~~ee~~|VCCI – 0.45<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|11<br>~~ee~~<br>~~ee~~|9<br>~~ee~~<br>~~ee eee~~|10<br>~~ee~~<br>~~eee~~|10<br>~~ee~~<br>~~eee~~|
|4 mA<br>~~a~~<br>~~a~~|–0.3|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|3.6<br>~~ee~~|0.45<br>~~ee~~|VCCI – 0.45|4<br>~~ee~~|4<br>~~ee ~~|22<br> ~~ee ~~|17<br> ~~ee eee~~|10<br>~~eee~~|10<br>~~eee~~|
|6 mA<br>~~a~~|–0.3<br>~~a~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~<br>~~ee~~|3.6<br>~~ee ~~<br>~~ee~~|0.45<br> ~~ee~~|VCCI – 0.45<br>~~ee~~|6<br>~~ee~~|6<br>~~ee~~|44|35|10|10|
|8 mA<br>~~pt~~|–0.3<br>~~pt~~|0.35 * VCCI|0.65 * VCCI|3.6|0.45|VCCI – 0.45|8|8|51|45|10|10|
|12 mA<br>~~a~~|–0.3<br>~~a ~~|0.35 * VCCI<br> ~~ee~~|0.65 * VCCI<br>~~ee~~|3.6|0.45|VCCI – 0.45<br>~~ee~~|12<br>~~ee~~|12<br>~~ee~~|74<br>~~ee ~~|91<br> ~~ee~~|10<br>~~ee~~|10<br>~~ee~~|
|16 mA<br>~~a~~|–0.3<br>~~a ~~|0.35 * VCCI 0.65 * VCCI<br> ~~a~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|3.6<br>~~ee~~|0.45|VCCI – 0.45 16<br>~~ee~~|VCCI – 0.45 16<br>~~ee~~|16|74|91|10|10|
|**Applicable to Advanced I/O Banks**<br>~~en~~<br>~~ee~~<br>~~a~~|||||||||||||
|2 mA<br>~~a~~<br>~~a~~|–0.3<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|1.9<br>~~ee~~|0.45<br>~~ee~~|VCCI – 0.45<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|11<br>~~ee~~|9<br>~~ee~~|10<br>~~ee~~|10<br>~~ee~~|
|4 mA<br>~~a~~|–0.3<br>~~a~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|1.9<br>~~ee~~|0.45|VCCI – 0.45<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|22|17|10|10|
|6 mA<br>~~a~~<br>~~a~~|–0.3<br>~~a ~~<br>~~a~~|0.35 * VCCI 0.65 * VCCI<br> ~~a~~<br>~~a~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~<br>~~ee~~|1.9<br>~~ee~~<br>~~ie~~|0.45|VCCI – 0.45<br>~~ee~~<br>~~ee~~|6<br>~~ee ~~<br>~~ee~~|6<br> ~~ee~~<br>~~ee~~|44<br>~~ee ~~<br>~~ee~~|35<br> ~~eee~~<br>~~ee ee~~|10<br>~~eee~~<br>~~ee~~|10<br>~~eee~~<br>~~ee~~|
|8 mA<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|0.35 * VCCI <br>~~a~~<br>~~ee~~|0.65 * VCCI<br>~~ee~~<br>~~ee~~|1.9<br>~~ie~~<br>~~ee~~|0.45<br>~~ee~~|VCCI – 0.45<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|51<br>~~ee~~<br>~~ee~~|45<br>~~ee ee~~|10<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|
|12 mA<br>~~a ~~<br>~~a~~<br>~~**a**~~|–0.3<br> ~~a ~~<br>~~a~~<br>~~a~~|0.35 * VCCI<br> ~~a ~~<br>~~ee~~<br>~~a~~|0.65 * VCCI<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.9<br> ~~ie~~<br>~~ee~~|0.45<br>~~ee~~|VCCI – 0.45<br>~~ee~~<br>~~ee~~<br>~~ee~~|12<br>~~ee ~~<br>~~ee~~<br>~~ee~~|12<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|74<br> ~~ee~~<br>~~ee~~<br>~~ee~~|91<br>~~ee ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|
|16 mA<br>~~a ~~<br>~~**a**~~|–0.3<br> ~~a~~<br>~~a~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~<br>~~a~~|0.35 * VCCI 0.65 * VCCI<br>~~ee ~~<br>~~ee~~|1.9<br> ~~ee~~|0.45<br>~~ee~~|VCCI – 0.45 16<br>~~ee~~<br>~~ee~~|VCCI – 0.45 16<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|74<br>~~ee~~<br>~~ee~~|91<br>~~ee~~|10<br>~~ee~~|10<br>~~ee~~|
|**Applicable to Standard I/O Banks**<br>~~**a** a a~~<br>~~ee~~<br>~~ee ee~~<br>~~rr~~<br>~~eeeeeeeeeee~~<br>~~eee eee~~|||||||||||||
|2 mA<br>~~rr~~|–0.3<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|0.35 * VCCI 0.65 * VCCI<br>~~ee~~|3.6<br>~~ee~~|0.45<br>~~eee~~|VCCI – 0.45<br>~~eee~~|2<br>~~eee~~|2<br>~~eee~~|11<br>~~eee eee~~|9<br>~~eee~~|10<br>~~eee~~|10<br>~~eee~~|
|4 mA<br>~~rr~~<br>~~a~~|–0.3<br>~~ee ~~<br>~~ee~~|0.35 * VCCI<br> ~~ee ~~<br>~~ee~~|0.65 * VCCI<br> ~~ee ~~<br>~~ee~~|3.6<br> ~~ee ~~<br>~~ee~~|0.45<br> ~~eee~~<br>~~ee~~|VCCI – 0.45<br>~~eee~~<br>~~ee~~|4<br>~~eee~~<br>~~ee~~|4<br>~~eee~~<br>~~ee~~|22<br>~~eee eee~~<br>~~ee~~|17<br>~~eee~~<br>~~ee~~|10<br>~~eee~~<br>~~ee~~|10<br>~~eee~~<br>~~ee~~|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**==> picture [310 x 61] intentionally omitted <==**
**----- Start of picture text -----**<br>
R = 1 k R to VCCI for tLZ / tZL / tZLS<br>Test Point<br>Test Point R to GND for tHZ / tZH / tZHS<br>Data Path 1 35 pF Enable Path 4 35 pF for tZH / tZHS / tZL / tZLS<br>1 1 35 pF for tHZ / tLZ<br>**----- End of picture text -----**<br>
_**Figure 2-121 •**_ **AC Loading**
_**Table 2-119 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input Low (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|
|0|1.8|0.9|–|35|
**2-187**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Timing Characteristics**_
## _**Table 2-120 •**_ **1.8 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V**
## **Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade t**|**Grade tDOUT**|**tDP**|**tDIN**|**tPY**|**tPYS**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a ~~<br>~~a~~<br>~~a~~|0.66<br> ~~a ~~<br>~~a~~<br>|15.84<br> ~~ee~~<br>~~ae~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.45<br>~~ee~~<br>~~ee~~<br>|1.91<br>~~eee~~<br>~~ee~~<br>|0.43<br>~~eee~~<br>~~ee~~<br>|15.65<br>~~eee~~<br>~~ee~~|15.84<br>~~eee~~<br>~~ee~~|2.78<br>~~eee~~<br>~~ee~~|1.58<br>~~eee~~<br>~~ee~~<br>~~ee~~|17.89<br>~~eee~~<br>~~ee~~<br>~~eee~~|18.07<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~a~~<br>~~ee~~<br>|13.47<br>~~ae~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.23<br>~~ee~~<br>~~ee~~<br>|1.62<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>|13.31<br>~~ee~~<br>|13.47<br>~~ee~~<br>~~ee~~<br>|2.37<br>~~ee~~<br>~~ee~~<br>|1.35<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|15.22<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|15.37<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
||–2<br>~~a ~~<br>~~a ~~<br>~~a~~<br>~~a~~|0.49<br> ~~a ~~<br> ~~ee~~<br><br>|11.83<br> ~~ae ~~<br>~~ee~~<br><br>|0.03<br> ~~ee~~<br>~~ee~~<br><br>|1.08<br>~~ee~~<br>~~ee~~<br><br>|1.42<br>~~ee~~<br>~~ee~~<br><br>|0.32<br>~~ee~~<br>~~ee~~<br><br>|11.69<br>~~ee~~<br><br>|11.83<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.08<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|1.18<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br><br>~~ee~~<br>|13.36<br>~~ee~~<br> ~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|13.50<br>~~ee~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|
|4 mA|Std.<br> <br>~~a~~<br>~~a~~<br>~~a~~|0.66<br> ~~ee~~<br>~~ee~~<br>|11.39<br>~~ee ~~<br>~~ee~~<br>|0.04<br> ~~ee~~<br>~~ee~~<br>|1.45<br>~~ee~~<br>~~ee~~<br>|1.91<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~ee~~<br>~~ee~~<br>|11.60<br>~~ee~~<br>|10.76<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.26<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.77<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|13.84<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|12.99<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~a~~|0.56<br> ~~a~~<br>|9.69<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.23<br>~~ee~~<br>~~ee~~<br>|1.62<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>|9.87<br>~~ee~~<br>~~ee~~<br>|9.15<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.77<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.36<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|11.77<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|11.05<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|
||–2<br>~~a~~<br>~~a~~|0.49<br>|8.51<br>|0.03<br>~~ee~~<br>|1.08<br>~~ee~~<br>|1.42<br>~~ee~~<br>|0.32<br>~~ee~~<br>|8.66<br>~~ee~~<br>|8.03<br>~~ee~~<br>|2.43<br>~~ee~~<br>|2.07<br>~~ee~~<br>|10.33<br>~~ee~~<br>~~eee~~<br>|9.70<br>~~ee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>|
|8 mA|Std.<br>~~a ~~<br>~~a~~<br>~~a~~|0.66<br> ~~a ~~<br>~~a~~<br>|8.97<br> ~~ee~~<br>~~ae~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.45<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.91<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|9.14<br> ~~ee~~<br>~~ee~~<br>~~ee~~|8.10<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.57<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.36<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|11.37<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|10.33<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~a~~<br>~~ee~~<br>|7.63<br>~~ae~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.23<br>~~ee~~<br>~~ee~~<br>|1.62<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>|7.77<br>~~ee~~<br>|6.89<br>~~ee~~<br>~~ee~~<br>|3.04<br>~~ee~~<br>~~ee~~<br>|2.86<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|9.67<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|8.79<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
||–2<br>~~a ~~<br>~~a ~~<br>~~a~~<br>~~a~~|0.49<br> ~~a ~~<br> ~~ee~~<br><br>|6.70<br> ~~ae ~~<br>~~ee~~<br><br>|0.03<br> ~~ee~~<br>~~ee~~<br><br>|1.08<br>~~ee~~<br>~~ee~~<br><br>|1.42<br>~~ee~~<br>~~ee~~<br><br>|0.32<br>~~ee~~<br>~~ee~~<br><br>|6.82<br>~~ee~~<br><br>|6.05<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.66<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.51<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br><br>~~ee~~<br>|8.49<br>~~ee~~<br> ~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|7.72<br>~~ee~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|
|12 mA|Std.<br> <br>~~a~~<br>~~a~~<br>~~a~~|0.66<br> ~~ee~~<br>~~ee~~<br>|8.35<br>~~ee ~~<br>~~ee~~<br>|0.04<br> ~~ee~~<br>~~ee~~<br>|1.45<br>~~ee~~<br>~~ee~~<br>|1.91<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~ee~~<br>~~ee~~<br>|8.50<br>~~ee~~<br>|7.59<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.64<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|3.52<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|10.74<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|9.82<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~a~~|0.56<br> ~~a~~<br>|7.10<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~e~~<br>|1.23<br>~~ee~~<br>~~e~~<br>|1.62<br>~~ee~~<br>~~e~~~~**e**~~|0.36<br>~~ee~~<br>~~**e**~~|7.23<br>~~ee~~<br>~~e~~|6.45<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~|3.10<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.00<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|9.14<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.35<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>|6.24<br>|0.03<br>~~e~~<br>|1.08<br>~~e~~<br>|1.42<br>~~e~~~~**e**~~|0.32<br>~~**e**~~|6.35<br>~~e~~|5.66<br>~~e~~~~**e**~~|2.72<br>~~ee~~|2.63<br>~~ee~~|8.02<br>~~ee~~<br>~~ee~~|7.33<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|16 mA|Std.<br>~~a ~~<br>~~a~~<br>~~a~~|0.66<br> ~~a ~~<br>~~a~~<br>|7.94<br> ~~ee~~<br>~~ae~~<br>|0.04<br>~~e~~<br>~~ee~~<br>~~ee~~<br>|1.45<br>~~e~~<br>~~ee~~<br>~~ee~~<br>|1.91<br>~~e~~~~**e**~~<br>~~ee~~<br>|0.43<br>~~**e** ~~<br>~~ee~~<br>|8.09<br> ~~e~~<br>~~ee~~<br>|7.56<br>~~e~~~~**e** ~~<br>~~ee~~<br>|3.74<br> ~~ee ~~<br>~~ee~~<br>|4.11<br> ~~ee ~~<br>~~e~~<br>~~ee~~<br>~~ee~~<br>|10.32<br> ~~ee ~~<br>~~e~~<br>~~ee~~<br>~~eee~~<br>|9.80<br> ~~eee~~<br>~~e~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~e~~<br>~~ee~~<br>~~eee~~<br>|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~a~~<br>|6.75<br>~~ae~~<br>|0.04<br>~~ee~~<br>|1.23<br>~~ee~~<br>|1.62<br>~~ee~~<br>|0.36<br>~~ee~~<br>|6.88<br>~~ee~~<br>|6.43<br>~~ee~~<br>|3.18<br>~~ee~~<br>|3.49<br>~~ee~~<br>~~ee~~<br>|8.78<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|8.33<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|
||–2<br>~~a ~~<br>~~a ~~|0.49<br> ~~a ~~<br> ~~a~~|5.93<br> ~~ae ~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~|1.08<br>~~ee~~<br>~~ee~~|1.42<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|6.04<br>~~ee~~<br>~~ee~~|5.65<br>~~ee~~<br>~~ee~~|2.79<br>~~ee~~<br>~~ee~~|3.07<br>~~ee~~<br>~~ee ~~<br>~~ee~~|7.71<br>~~ee~~<br> ~~eee~~<br>~~ee~~<br>~~eee~~|7.32<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|
**Revision 8**
**2-188**
_Device Architecture_
_**Table 2-121 •**_ **1.8 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade t**|**Grade tDOUT**|**tDP**|**tDIN**|**tPY**|**tPYS**|**tEOUT**|**tZL**|**tZH**|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~|0.66<br>~~a~~|12.10<br>~~ee~~|0.04<br>~~ee~~|1.45<br>~~ee~~|1.91<br>~~ee~~|0.43<br>~~ee~~<br>~~eee~~|9.59<br>~~ee~~<br>~~eee~~|12.10<br>~~ee~~<br>~~eee~~|2.78<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.64<br>~~ee~~<br>~~ee~~<br>~~eee~~|11.83<br>~~ee~~<br>~~ee~~<br>~~eee~~|14.34<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~a~~|0.56<br>~~ee~~<br>|10.30<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.23<br>~~ee~~|1.62<br>~~ee~~|0.36<br>~~ee~~<br>~~eee~~|8.16<br>~~ee~~<br>~~eee~~<br>~~ee~~|10.30<br>~~ee~~<br>~~eee~~<br>~~ee~~|2.37<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.39<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|10.06<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|12.20<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~**a**~~|9.04<br>~~ee~~<br>~~**ee**~~|0.03<br>~~ee~~<br>~~**ee**~~|1.08<br>~~ee~~|1.42<br>~~ee~~<br>~~ee~~|0.32<br>~~eee~~<br>~~ee~~<br>~~ee~~|7.16<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|9.04<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.08<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.22<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|8.83<br>~~eee ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|10.71<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|4 mA|Std.<br>~~a ~~<br>~~a~~|0.66<br> ~~**a**~~|7.05<br>~~**ee**~~|0.04<br>~~**ee**~~|1.45|1.91<br>~~ee~~|0.43<br>~~ee~~|6.20<br>~~ee~~<br>~~ee~~|7.05<br>~~ee ~~<br>~~ee~~|3.25<br> ~~ee ~~<br>~~ee~~|2.86<br> ~~eee~~<br>~~ee~~|8.44<br>~~eee ~~<br>~~ee~~<br>~~ee~~|9.29<br> ~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~|
||–1<br> <br>~~a~~<br>~~re~~|0.56<br> ~~**a** ~~<br>|6.00<br> ~~**ee**~~<br>|0.04<br>~~**ee**~~<br>|1.23<br>~~ee~~<br>|1.62<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee ~~<br>~~ee~~<br>|5.28<br> ~~ee~~<br>~~ee~~<br>|6.00<br>~~ee ~~<br>~~ee~~<br>|2.76<br> ~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|2.44<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>|7.18<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|7.90<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|
||–2<br>~~ee~~<br>~~re~~<br>~~a~~|0.49<br>~~ee~~<br><br>|5.27<br>~~ee~~<br><br>|0.03<br>~~ee~~<br><br>|1.08<br>~~ee~~<br><br>|1.42<br>~~ee~~<br><br>|0.32<br>~~ee~~<br><br>|4.63<br>~~ee~~<br><br>|5.27<br>~~ee~~<br><br>|2.43<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~~~**e**~~<br>|2.14<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|6.30<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|6.94<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
|8 mA|Std.<br>~~re~~<br>~~a~~|0.66<br>~~ee~~<br>|4.52<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.45<br>~~ee~~<br>|1.91<br>~~ee~~<br>|0.43<br>~~ee~~<br>|4.47<br>~~ee~~<br>|4.52<br>~~ee~~<br>|3.57<br>~~e~~~~**e**~~<br>~~eee~~~~**e**~~<br>~~ee~~|3.47<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.70<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.76<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~re~~<br>~~a ee~~<br>~~a~~|0.56<br><br>~~ee~~<br>|3.85<br><br>~~ee~~<br>|0.04<br><br>~~ee~~<br>|1.23<br><br>~~ee~~<br>|1.62<br><br>~~ee~~<br>~~ee~~<br>|0.36<br><br>~~ee~~<br>~~ee~~<br>|3.80<br><br>~~ee~~<br>~~ee~~~~**e**~~<br>|3.85<br><br>~~ee~~<br>~~**e**~~|3.04<br>~~e~~~~**e** ~~<br>~~e~~~~**e** ~~<br>~~eeee~~<br>~~ee~~|2.95<br> ~~eee~~<br> ~~eee~~<br>~~eee~~<br>~~eee~~|5.70<br>~~eee ~~<br>~~eee ~~<br>~~eee~~<br>~~eee~~|5.75<br> ~~eee~~<br> ~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br><br>~~ee~~<br>~~a~~<br>~~a~~|0.49<br><br>~~ee~~<br><br>|3.38<br><br>~~ee~~<br><br>|0.03<br><br>~~ee~~<br><br>|1.08<br><br>~~ee~~<br><br>|1.42<br><br>~~ee~~<br>~~ee~~<br><br>|0.32<br><br>~~ee~~<br>~~ee~~<br><br>|3.33<br><br>~~ee~~<br>~~ee~~~~**e**~~<br><br>|3.38<br><br>~~ee~~<br>~~**e**~~<br>|2.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.59<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|5.00<br>~~eee ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|5.05<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
|12 mA|Std.<br>~~a ~~<br>~~a~~<br>~~ae~~|0.66<br> ~~a e~~<br>|4.12<br>~~e~~<br>|0.04<br>~~e~~<br>|1.45<br>~~e~~<br>|1.91<br>~~ee~~<br>~~e~~<br>|0.43<br>~~ee~~<br>~~e~~<br>|4.20<br>~~ee~~~~**e**~~<br>~~e~~<br>|3.99<br>~~**e** ~~<br>|3.63<br> ~~ee ~~<br>|3.62<br> ~~eee~~<br>~~ee~~<br>|6.43<br>~~eee ~~<br>~~ee~~<br><br>~~ee~~|6.23<br> ~~eee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|
||–1<br>~~a ~~<br>~~ae~~<br>~~a~~|0.56<br> ~~a eee~~|3.51<br>~~eee~~<br>~~ee~~|0.04<br>~~eee~~<br>~~ee~~|1.23<br>~~eee~~<br>~~ee~~|1.62<br>~~eee~~|0.36<br>~~eee~~<br>~~e~~|3.57<br>~~eee~~<br>~~e~~~~**e**~~|3.40<br>~~eee~~<br>~~**e**~~|3.09<br>~~eee~~<br>~~ee~~|3.08<br>~~ee ~~<br>~~eee~~<br>~~eee~~|5.47<br> ~~ee ~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|5.30<br> ~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ae~~<br>~~a~~|0.49|3.08<br>~~ee~~|0.03<br>~~ee~~|1.08<br>~~ee~~|1.42|0.32<br>~~e~~|3.14<br>~~e~~~~**e**~~|2.98<br>~~**e**~~|2.71<br>~~ee~~<br>~~ee~~|2.71<br>~~eee~~<br>~~ee~~|4.81<br>~~ee~~<br>~~eee~~<br>~~ee~~|4.65<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|16 mA|Std.<br>~~ae~~<br>~~a~~|0.66<br>~~a~~|3.80<br>~~ee~~<br>~~e~~|0.04<br>~~ee~~<br>~~e~~|1.45<br>~~ee~~<br>~~e~~|1.91<br>~~e~~|0.43<br>~~e~~<br>~~e~~<br>~~eee~~|3.87<br>~~e~~~~**e**~~<br>~~e~~<br>~~eee~~|3.09<br>~~**e** ~~<br>~~eee~~|3.73<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4.24<br> ~~eee~~<br>~~ee~~<br>~~eee~~|6.10<br>~~ee ~~<br>~~eee ~~<br>~~ee~~<br>~~eee~~|5.32<br> ~~eee~~<br> ~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee~~|0.56<br>~~ee~~|3.23<br>~~ee~~|0.04<br>~~ee~~|1.23<br>~~ee~~|1.62<br>~~ee~~|0.36<br>~~ee~~<br>~~eee~~<br>~~eee~~|3.29<br>~~ee~~<br>~~eee~~<br>~~eee~~|2.63<br>~~ee~~<br>~~eee~~<br>~~eee~~|3.18<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.60<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|5.19<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|4.53<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee~~|0.49<br>~~ee~~|2.83<br>~~ee~~|0.03<br>~~ee~~|1.08<br>~~ee~~|1.42<br>~~ee~~|0.32<br>~~eee~~<br>~~ee~~<br>~~eee~~|2.89<br>~~eee~~<br>~~ee~~<br>~~eee~~|2.31<br>~~eee ~~<br>~~ee~~<br>~~eee~~|2.79<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.16<br> ~~eee~~<br>~~ee~~<br>~~eee~~|4.56<br>~~eee ~~<br>~~ee~~<br>~~eee~~|3.98<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
**2-189**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 2-122 •**_ **1.8 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V**
**Applicable to Advanced I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~ee~~|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**<br>~~**ee**~~|**tLZ**<br>~~**ee**~~|**tHZ**<br>~~**ee**~~|**tZLS**<br>~~**eee**~~|**tZHS**<br>~~**eee**~~|**Units**<br>~~**eee**~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~ee~~|0.66<br>~~ee~~|15.53<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|14.11<br>~~ee~~<br>~~ee~~|15.53<br>~~ee~~<br>~~**ee**~~|2.78<br>~~ee~~<br>~~**ee**~~|1.60<br>~~ee~~<br>~~**ee**~~|16.35<br>~~ee~~<br>~~**eee**~~|17.77<br>~~ee~~<br>~~**eee**~~|ns<br>~~ee~~<br>~~**eee**~~|
||–1<br>~~ee~~<br>~~ee~~|0.56|13.21|0.04<br>~~ee~~|1.11<br>~~ee~~|0.36<br>~~ee~~|12.01<br>~~ee~~|13.21<br>~~**ee**~~<br>~~ee~~|2.36<br>~~**ee**~~<br>~~ee~~|1.36<br>~~**ee**~~<br>~~ee~~|13.91<br>~~**eee**~~<br>~~eee~~|15.11<br>~~**eee**~~<br>~~eee~~|ns<br>~~**eee**~~<br>~~eee~~|
||–22<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|0.49<br>~~ee~~<br>|11.60<br>~~ee~~<br>|0.03<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.98<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|10.54<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|11.60<br>~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.07<br>~~**ee** ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.19<br> ~~**ee** ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|12.21<br> ~~**eee**~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|13.27<br>~~**eee**~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~**eee**~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
|4 mA|Std.<br>~~ee~~<br>~~a~~<br>~~ee~~|0.66<br><br>|10.48<br><br>|0.04<br>~~ee~~<br><br>|1.31<br>~~ee~~<br><br>|0.43<br>~~ee~~<br><br>|10.41<br>~~ee~~<br><br>|10.48<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|3.23<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.73<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|12.65<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|12.71<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~|0.56<br>~~ee~~<br><br>|8.91<br>~~ee~~<br><br>|0.04<br>~~ee~~<br>~~ee~~<br><br>|1.11<br>~~ee~~<br>~~ee~~<br><br>|0.36<br>~~ee ~~<br>~~ee~~<br><br>|8.86<br> ~~ee ~~<br>~~ee~~<br><br>|8.91<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.75<br>~~ee ~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.33<br> ~~ee ~~<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|10.76<br> ~~eee~~<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|10.81<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
||–2<br>~~ee~~<br>~~a~~<br>~~ee~~|0.49<br>~~eee~~<br>|7.82<br>~~eee~~<br>|0.03<br>~~eee~~<br>|0.98<br>~~eee~~<br>|0.32<br>~~eee~~<br>|7.77<br>~~eee~~<br>|7.82<br>~~ee~~<br>~~eee~~<br>~~ee~~<br><br>~~**ee**~~|2.41<br>~~ee~~<br>~~eee~~<br>~~ee~~<br><br>~~**ee**~~|2.04<br>~~ee~~<br>~~eee~~<br>~~ee~~<br><br>~~**ee**~~|9.44<br>~~eee~~<br>~~eee~~<br>~~eee~~<br><br>~~**eee**~~|9.49<br>~~eee~~<br>~~eee~~<br>~~eee~~<br><br>~~**eee**~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br><br>~~**eee**~~|
|8 mA|Std.<br>~~ee~~<br>~~a~~<br>~~ee~~|0.66<br><br>~~ee~~|8.05<br><br>~~ee~~|0.04<br><br>~~ee~~<br>~~ee~~|1.31<br><br>~~ee~~<br>~~ee~~|0.43<br><br>~~ee~~<br>~~ee~~|8.20<br><br>~~ee~~<br>~~ee~~|7.84<br>~~ee~~<br><br>~~ee~~<br>~~ee~~<br>~~**ee**~~|3.54<br>~~ee ~~<br><br>~~ee ~~<br>~~ee~~<br>~~**ee**~~|3.27<br> ~~ee ~~<br><br> ~~ee ~~<br>~~ee~~<br>~~**ee**~~|10.43<br> ~~eee~~<br><br> ~~eee~~<br>~~ee~~<br>~~**eee**~~|10.08<br>~~eee~~<br><br>~~eee~~<br>~~ee~~<br>~~**eee**~~|ns<br>~~eee~~<br><br>~~eee~~<br>~~ee~~<br>~~**eee**~~|
||–1<br>~~ee~~<br>~~ee~~|0.56|6.85|0.04<br>~~ee~~|1.11<br>~~ee~~|0.36<br>~~ee~~|6.97<br>~~ee~~|6.67<br>~~**ee**~~<br>~~ee~~|3.01<br>~~**ee**~~<br>~~ee~~|2.78<br>~~**ee**~~<br>~~ee~~|8.88<br>~~**eee**~~<br>~~eee~~|8.57<br>~~**eee**~~<br>~~eee~~|ns<br>~~**eee**~~<br>~~eee~~|
||–2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|0.49<br>~~ee~~<br>|6.01<br>~~ee~~<br>|0.03<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.98<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|6.12<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|5.86<br>~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.64<br>~~**ee** ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.44<br> ~~**ee** ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|7.79<br> ~~**eee**~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|7.53<br>~~**eee**~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~**eee**~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
|12 mA|Std.<br>~~ee~~<br>~~a~~<br>~~a~~|0.66<br>|7.50<br>|0.04<br>~~ee~~<br>|1.31<br>~~ee~~<br>|0.43<br>~~ee~~<br>|7.64<br>~~ee~~<br>|7.30<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|3.61<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|3.41<br>~~ee~~<br>~~ee~~<br><br>~~eee~~|9.88<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|9.53<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|
||–1<br>~~ee~~<br>~~a ee~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~|6.38<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.11<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.50<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.21<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.07<br>~~ee ~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.90<br> ~~ee ~~<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|8.40<br> ~~eee~~<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|8.11<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~<br>~~ee~~|0.49<br>|5.60<br>|0.03<br>~~ee~~<br>~~ee~~<br>|0.98<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~ee~~<br>~~ee~~<br>|5.71<br>~~ee~~<br>~~ee~~<br>|5.45<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.69<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.55<br> ~~eee~~<br>~~eee~~<br>~~ee~~<br>|7.38<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|7.12<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
|16 mA|Std.<br>~~a~~<br>~~ee~~<br>~~a~~|0.66<br><br>|7.29<br><br>|0.04<br>~~ee~~<br>~~ee~~<br><br>|1.31<br>~~ee~~<br>~~ee~~<br><br>|0.43<br>~~ee~~<br>~~ee~~<br><br>|7.23<br>~~ee ~~<br>~~ee~~<br><br>|7.29<br> ~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|3.71<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|3.95<br>~~eee~~<br>~~ee~~<br><br>~~eee~~<br>|9.47<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|9.53<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~|0.56<br>~~ee~~<br>|6.20<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.11<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>|6.15<br>~~ee~~<br>~~ee~~<br>|6.20<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|3.15<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|3.36<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|8.06<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|8.11<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|
||–2<br>~~ee~~<br>~~a~~|0.49<br><br>~~ee~~|5.45<br><br>~~ee~~|0.03<br>~~ee~~<br><br>~~ee~~|0.98<br>~~ee~~<br><br>~~ee~~|0.32<br>~~ee~~<br><br>~~ee~~|5.40<br>~~ee ~~<br><br>~~ee~~|5.45<br> ~~ee ~~<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|2.77<br> ~~ee~~<br><br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.95<br>~~ee ~~<br><br> ~~eee~~<br>~~ee~~<br>~~ee~~|7.07<br> ~~eee~~<br><br>~~eee~~<br>~~ee~~<br>~~eee~~|7.12<br>~~eee~~<br><br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br><br>~~eee~~<br>~~ee~~<br>~~eee~~|
**Revision 8**
**2-190**
_Device Architecture_
_**Table 2-123 •**_ **1.8 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V**
**Applicable to Advanced I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~ee~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~eee~~|**tLZ**<br>~~eee~~|**tHZ**<br>~~eee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~ee~~<br>~~a~~|0.66<br>~~ee~~<br>|11.86<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.22<br>~~ee~~<br>|0.43<br>~~ee~~<br>|9.14<br>~~ee~~<br>|11.86<br>~~eee~~<br>~~eee~~<br>|2.77<br>~~eee~~<br>~~eee~~<br>|1.66<br>~~eee~~<br>~~eee eee~~<br>|11.37<br>~~eee~~<br>~~eee~~<br>|14.10<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~ee~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|10.09<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.04<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|0.36<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|7.77<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|10.09<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|2.36<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|1.41<br>~~eee ~~<br>~~ee~~<br>~~eee eee~~<br>~~ee~~<br>|9.67<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|11.99<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|
||–2<br>~~a~~ <br>~~ee~~<br>~~a~~|0.49<br> ~~ee~~<br>~~ee ee~~<br>|8.86<br>~~ee~~<br>~~ee~~<br>|0.03<br>~~ee~~<br>~~ee~~<br>|0.91<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~ee~~<br>~~ee~~<br>|6.82<br>~~ee~~<br>~~ee~~<br>|8.86<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>|2.07<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>|1.24<br>~~eee eee~~<br>~~ee~~<br>~~eee~~<br>|8.49<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|10.53<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|
|4 mA|Std.<br> <br>~~ee~~<br>~~a~~<br>~~pT~~|0.66<br> ~~ee ~~<br>~~ee ee~~<br><br>~~pT~~|6.91<br> ~~ee~~<br>~~ee~~<br><br>|0.04<br>~~ee~~<br>~~ee~~<br><br>|1.22<br>~~ee~~<br>~~ee~~<br><br>|0.43<br>~~ee~~<br>~~ee~~<br><br>|5.86<br>~~ee~~<br>~~ee~~<br><br>|6.91<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|3.22<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|2.84<br>~~ee~~<br>~~eee~~<br><br>~~eee eee~~<br>|8.10<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|9.15<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~<br>~~pT~~|0.56<br>~~ee ee~~<br>~~ee~~<br>~~pT~~|5.88<br>~~ee~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.04<br>~~ee ~~<br>~~ee~~<br>|0.36<br> ~~ee~~<br>~~ee~~<br>|4.99<br>~~ee ~~<br>~~ee~~<br>|5.88<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>|2.74<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>|2.41<br>~~eee ~~<br>~~ee~~<br>~~eee eee~~<br>|6.89<br>~~ee~~<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>|7.78<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>|
||–2<br>~~pT~~<br>~~re~~<br>~~re~~|0.49<br>~~pTTE~~<br>|5.16<br>~~TE~~<br>|0.03<br>~~TE~~<br>|0.91<br>~~TE~~<br>|0.32<br>~~TE~~<br>|4.38<br>~~TE~~<br>|5.16<br>~~eee~~<br>~~TE~~<br>|2.41<br>~~eee~~<br>~~TE~~<br><br>~~eee~~|2.12<br>~~eee eee~~<br>~~TE~~<br><br>~~eee~~|6.05<br>~~eee~~<br>~~TE~~<br><br>~~eee~~|6.83<br>~~eee~~<br>~~TE~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~TE~~<br><br>~~eee~~|
|8 mA|Std.<br>~~pT~~<br>~~re ~~<br>~~re~~<br>~~ee~~|0.66<br>~~pTTE~~<br> ~~ee~~<br>|4.45<br>~~TE~~<br>~~ee~~<br>~~ee~~<br>|0.04<br>~~TE~~<br>~~eee~~<br>~~ee~~<br>|1.22<br>~~TE~~<br>~~eee~~<br>~~ee~~<br>|0.43<br>~~TE~~<br>~~eee~~<br>~~ee~~<br>|4.18<br>~~TE~~<br>~~eee~~<br>~~eee~~<br>|4.45<br>~~eee~~<br>~~TE~~<br>~~eee~~<br>~~eee~~<br>|3.53<br>~~eee~~<br>~~TE~~<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|3.38<br>~~eee eee~~<br>~~TE~~<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|6.42<br>~~eee~~<br>~~TE~~<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|6.68<br>~~eee~~<br>~~TE~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~TE~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
||–1<br><br>~~re ~~<br>~~re~~<br>~~ee~~<br>~~rr~~|0.56<br>~~TE~~<br> <br>~~ee~~|3.78<br>~~TE~~<br><br>~~ee~~<br>~~ee~~|0.04<br>~~TE~~<br><br>~~ee~~<br>~~ee~~|1.04<br>~~TE~~<br><br>~~ee~~<br>~~ee~~|0.36<br>~~TE~~<br><br>~~ee~~<br>~~e~~|3.56<br>~~TE~~<br><br>~~eee~~<br>~~e~~~~**e**~~|3.78<br>~~TE~~<br><br>~~eee~~<br>~~**e**e~~|3.00<br>~~TE~~<br><br>~~eee~~<br>~~ee~~<br>~~**e**ee~~|2.88<br>~~TE~~<br><br>~~eee~~<br>~~ee~~<br>~~ee~~|5.46<br>~~TE~~<br><br>~~eee~~<br>~~ee~~<br>~~eee~~|5.69<br>~~TE~~<br><br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~TE~~<br><br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~re~~<br>~~ee~~<br>~~rr~~<br>~~a~~|0.49<br>~~ee~~<br>|3.32<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|0.03<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|0.91<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|0.32<br>~~ee~~<br>~~e~~<br>~~eee~~<br>|3.12<br>~~eee~~<br>~~e~~~~**e**~~<br>|3.32<br>~~eee~~<br>~~**e**e~~<br>|2.64<br>~~eee~~<br>~~ee~~<br>~~**e**ee~~<br>|2.53<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>|4.79<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~e~~<br>~~eee~~<br>|4.99<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~e~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~e~~<br>~~eee~~<br>|
|12 mA|Std.<br>~~ee ~~<br>~~rr~~<br>~~a~~<br>~~a~~|0.66<br> ~~ee~~<br><br>|3.92<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>|0.04<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>|1.22<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br><br>|0.43<br> ~~ee ~~<br>~~e~~<br>~~eee~~<br><br>|3.93<br> ~~eee~~<br>~~e~~~~**e**~~<br><br>|3.92<br>~~eee ~~<br>~~**e**e~~<br><br>|3.60<br> ~~ee ~~<br>~~**e**ee~~<br><br>|3.52<br> ~~ee ~~<br>~~ee~~<br><br>|6.16<br> ~~ee ~~<br>~~eee~~<br>~~e~~<br>~~eee~~<br><br>~~eee~~<br>|6.16<br> ~~eee~~<br>~~eee~~<br>~~e~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~e~~<br>~~eee~~<br><br>~~eee~~<br>|
||–1<br> <br>~~rr~~<br>~~a~~<br>~~a~~|0.56<br> ~~ee ~~<br>~~eee~~<br>|3.34<br> ~~ee~~<br>~~eee~~<br>~~eee~~<br>|0.04<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|1.04<br>~~ee ~~<br>~~eee~~<br>~~eee~~<br>|0.36<br> ~~e~~<br>~~eee~~<br>~~eee~~<br>|3.34<br>~~e~~~~**e**~~<br>~~eee~~<br>|3.34<br>~~**e**e ~~<br>~~eee~~<br>|3.06<br> ~~**e**ee~~<br>~~eee~~<br>|3.00<br>~~ee ~~<br>~~eee~~<br>|5.24<br> ~~eee~~<br>~~e~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|5.24<br>~~eee~~<br>~~e~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~e~~<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
||–2<br>~~a ~~<br>~~ee~~<br>~~a~~|0.49<br> ~~ee~~<br>~~ee ee~~<br>|2.93<br>~~ee~~<br>~~ee~~<br>|0.03<br>~~ee~~<br>~~ee~~<br>|0.91<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~eeeee~~<br>~~ee~~<br>|2.93<br>~~eee~~<br>~~ee~~<br>|2.93<br>~~eee~~<br>~~ee~~<br>|2.69<br>~~eee~~<br>~~ee~~~~**e**~~<br>|2.63<br>~~eee~~<br>~~**e**~~<br>|4.60<br>~~eee~~<br>~~eee~~<br>~~eee~~|4.60<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|16 mA|Std.<br> <br>~~ee~~<br>~~a~~<br>~~a~~|0.66<br> ~~ee~~<br>~~ee ee~~<br>|3.53<br>~~ee~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.22<br>~~ee~~<br>~~ee~~<br>|0.43<br>~~eeeee~~<br>~~ee~~<br>|3.60<br>~~eee~~<br>~~ee~~<br>|3.04<br>~~eee~~<br>~~ee~~<br>|3.70<br>~~eee~~<br>~~ee~~~~**e**~~<br>|4.08<br>~~eee~~<br>~~**e**~~<br>|5.84<br>~~eee~~<br>~~eee~~<br>~~eee~~|5.28<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br> <br>~~ee~~<br>~~a~~<br>~~a~~|0.56<br> ~~ee~~<br>~~ee ee~~<br>~~ee~~|3.01<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.04<br> ~~ee~~<br>~~ee ~~<br>~~ee~~|0.36<br>~~eeeee~~<br> ~~ee~~<br>~~ee~~|3.06<br>~~eee~~<br>~~ee ~~<br>~~ee~~|2.59<br>~~eee~~<br> ~~ee~~<br>~~ee~~|3.15<br>~~eee~~<br>~~ee~~~~**e**~~<br>~~ee~~|3.47<br>~~eee~~<br>~~**e** ~~<br>~~ee~~|4.96<br>~~eee~~<br> ~~eee~~<br>~~eee~~|4.49<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a~~|0.49<br>~~ee~~|2.64<br>~~ee~~|0.03<br>~~ee~~|0.91<br>~~ee~~|0.32<br>~~ee~~|2.69<br>~~ee~~|2.27<br>~~ee~~|2.76<br>~~ee~~|3.05<br>~~ee~~|4.36<br>~~eee~~<br>~~ee~~|3.94<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
_**Table 2-124 •**_ **1.8 V LVCMOS Low Slew Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V**
## **Applicable to Standard I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~a~~|**tDP**<br>~~se~~|**tDIN**<br>~~se~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~|0.66<br>~~a~~|15.01<br>~~se~~|0.04<br>~~se~~|1.20<br>~~ee~~|0.43<br>~~ee~~|13.15<br>~~ee~~|15.01|1.99<br>~~ee~~|1.99<br>~~ee~~|ns|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~a ~~<br>~~ee~~<br>|12.77<br> ~~se~~<br>~~ee~~<br>|0.04<br>~~se~~<br>~~ee~~<br>|1.02<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>|11.19<br>~~ee~~<br>~~ee~~<br>|12.77<br>~~ee~~<br>|1.70<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|1.70<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a ~~<br>|11.21<br> ~~a ee~~<br>|0.03<br>~~ee~~<br>|0.90<br>~~ee~~<br>|0.32<br>~~ee~~<br>|9.82<br>~~ee~~<br>|11.21<br>~~ee~~<br>|1.49<br>~~ee~~<br>~~ee~~<br>|1.49<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|4 mA|Std.<br>~~a ~~|0.66<br> ~~ee~~|10.10<br>~~ee~~|0.04<br>~~ee~~|1.20<br>~~ee~~|0.43<br>~~ee~~|9.55<br>~~ee~~|10.10<br>~~ee~~<br>~~ee~~|2.41<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.37<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~|0.56<br>~~a ee~~|8.59<br>~~ee~~|0.04<br>~~ee~~|1.02<br>~~ee~~|0.36<br>~~ee~~|8.13<br>~~ee~~|8.59<br>~~ee~~<br>~~ee~~|2.05<br>~~ee~~<br>~~ee~~|2.02<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~ee~~|0.49<br>~~ee~~|7.54<br>~~ee~~|0.03<br>~~ee~~|0.90<br>~~ee~~|0.32<br>~~ee~~|7.13<br>~~ee~~|7.54<br>~~ee~~<br>~~ee~~|1.80<br>~~ee ~~<br>~~ee~~|1.77<br> ~~ee~~<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-191**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Table 2-125 •**_ **1.8 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V**
**Applicable to Standard I/Os**
|**Drive**<br>**Strength**<br>~~a~~|**Speed**<br>**Grade**<br>~~ee~~|**tDOUT**<br>~~ee~~<br>~~ee~~|**tDP**<br>~~ee~~<br>~~ee~~|**tDIN**<br>~~ee~~<br>~~es~~|**tPY**<br>~~ee~~<br>~~es~~|**tEOUT**<br>~~es~~|**tZL**<br>~~es~~|**tZH**<br>~~ee~~<br>~~es~~|**tLZ**<br>~~ee~~<br>~~es~~|**tHZ**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~a~~|Std.<br>~~ee~~<br>~~es~~|0.66<br>~~ee~~<br>~~ee~~|11.21<br>~~ee~~<br>~~ee~~<br>~~Gn~~|0.04<br>~~ee~~<br>~~es~~<br>~~Gn~~|1.20<br>~~ee~~<br>~~es~~<br>~~Gn~~|0.43<br>~~es~~|8.53<br>~~es~~|11.21<br>~~ee~~<br>~~es~~|1.99<br>~~ee~~<br>~~es~~|1.21<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~ee~~<br>~~es~~<br>~~ee~~|0.56<br>~~ee ~~<br>~~ee~~|9.54<br> ~~ee ~~<br>~~Gn~~<br>~~ee~~|0.04<br> ~~es ~~<br>~~Gn~~<br>~~es~~|1.02<br> ~~es ~~<br>~~Gn~~<br>~~es~~|0.36<br> ~~es~~<br>~~Gs~~|7.26<br>~~es~~<br>~~Gs~~|9.54<br>~~es~~<br>~~es~~|1.69<br>~~es~~|1.03|ns|
||–2<br>~~es~~<br>~~ee~~|0.49<br>~~ee~~|8.37<br>~~Gn~~<br>~~ee~~|0.03<br>~~Gn ~~<br>~~es~~|0.90<br> ~~Gn~~<br>~~es~~|0.32<br>~~Gs~~|6.37<br>~~Gs~~|8.37<br>~~es~~|1.49|0.90|ns|
|4 mA|Std.<br>~~ee~~|0.66<br>~~ee ~~|6.34<br> ~~ee ~~|0.04<br> ~~es~~|1.20<br>~~es ~~|0.43<br> ~~Gs~~|5.38<br>~~Gs ~~|6.34<br> ~~es~~|2.41|2.48|ns|
||–1|0.56|5.40|0.04|1.02|0.36|4.58|5.40|2.05|2.11|ns|
||–2|0.49|4.74|0.03|0.90|0.32|4.02|4.74|1.80|1.85|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-192**
_Device Architecture_
## _**1.5 V LVCMOS (JESD8-11)**_
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and push-pull output buffer.
_**Table 2-126 •**_ **Minimum and Maximum DC Input and Output Levels**
|**1.5 V**<br>**LVCMOS**<br>~~ee~~<br>~~pot~~|**VIL**<br>~~ee~~<br>~~pot~~|**VIL**<br>~~ee~~<br>~~pot~~|**VIH**<br>~~ee~~<br>~~ee~~<br>|**VIH**<br>~~ee~~<br>~~ee~~<br>|**VOL**<br>~~ee~~<br>~~ee~~|**VOH**<br>~~ee~~|**IOL **<br>~~ee~~<br>~~eee~~|**IOH **<br>~~ee~~<br>~~eee~~|**IOSL **<br>~~ee~~<br>~~eee~~|**IOSH **<br>~~ee~~<br>~~eee~~|**IIL1**<br>~~ee~~<br>~~eee~~|**IIH2**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~pot~~|**Min.**<br>**V**<br>~~pot tt~~|**Max.**<br>**V**<br>~~tt~~|**Min.**<br>**V**<br>~~ee~~<br>~~tt~~|**Max.**<br>**V**<br>~~ee~~|**Max.**<br>**V**<br>~~ee~~|**Min.**<br>**V**|**mA **<br>~~eee~~|**mA**<br>~~eee~~|**Max.**<br>**mA3**<br>~~eee~~|**Max.**<br>**mA3**<br>~~eee~~|**µA4 **<br>~~eee~~|**µA4**<br>~~eee~~|
|**Applicable to Pro I/O Banks**<br>~~ee~~<br>~~eee~~<br>~~pot ~~<br>~~Ce~~|||||||||||||
|2 mA<br>~~ss~~|–0.3<br>~~ss~~|0.35 * VCCI <br>~~ss~~|0.65 * VCCI<br>~~ss~~|3.6<br>~~ss~~|0.25 * VCCI <br>~~ss~~|0.75 * VCCI<br>~~ss~~|2<br>~~ss~~|2<br>~~ss~~|16<br>~~ss~~|13<br>~~ss~~|10<br>~~ss~~|10<br>~~ss~~|
|4 mA<br>~~es~~<br>~~a~~|–0.3<br>~~es~~|0.35 * VCCI <br>~~es~~|0.65 * VCCI<br>~~es~~|3.6<br>~~es~~<br>~~ee~~|0.25 * VCCI <br>~~es~~<br>~~ee~~|0.75 * VCCI<br>~~es~~|4<br>~~es~~|4<br>~~es~~|33<br>~~es~~|25<br>~~es~~|10<br>~~es~~|10<br>~~es~~|
|6 mA<br>~~es~~<br>~~a~~|–0.3<br>~~es~~|0.35 * VCCI <br>~~es~~<br>~~ee~~|0.65 * VCCI<br>~~es~~<br>~~ee~~|3.6<br>~~es~~<br>~~ee~~<br>~~ee~~|0.25 * VCCI <br>~~es~~<br>~~ee~~<br>~~ee~~|0.75 * VCCI<br>~~es~~<br>~~ee~~|6<br>~~es~~<br>~~ee~~|6<br>~~es~~<br>~~ee~~|39<br>~~es~~<br>~~ee~~|32<br>~~es~~<br>~~eee~~|10<br>~~es~~<br>~~eee~~|10<br>~~es~~<br>~~eee~~|
|8 mA<br>~~a~~|–0.3|0.35 * VCCI <br>~~ee~~|0.65 * VCCI<br>~~ee~~|3.6<br>~~ee~~<br>~~ee~~|0.25 * VCCI <br>~~ee~~<br>~~ee~~|0.75 * VCCI<br>~~ee~~|8<br>~~ee~~|8<br>~~ee~~|55<br>~~ee~~|66<br>~~eee~~|10<br>~~eee~~|10<br>~~eee~~|
|12 mA<br>~~ss~~<br>~~eo~~|–0.3<br>~~ss~~<br>~~eo~~|0.35 * VCCI<br>~~ee~~<br>~~ss~~<br>~~eo~~|0.65 * VCCI<br>~~ee~~<br>~~ss~~|3.6<br>~~ee~~<br>~~ss~~|0.25 * VCCI<br>~~ee~~<br>~~ss~~|0.75 * VCCI<br>~~ee~~<br>~~ss~~|12<br>~~ee~~<br>~~ss~~|12<br>~~ee~~<br>~~ss~~|55<br>~~ee ~~<br>~~ss~~|66<br> ~~eee~~<br>~~ss~~|10<br>~~eee~~<br>~~ss~~|10<br>~~eee~~<br>~~ss~~|
|**Applicable to Advanced I/O Banks**<br>~~eo~~|||||||||||||
|2 mA<br>~~eo~~<br>~~a~~|–0.3<br>~~eo~~<br>~~a~~|0.35 * VCCI <br>~~eo~~<br>~~a~~|0.65 * VCCI|1.575|0.25 * VCCI|0.75 * VCCI|2|2|16|13|10|10|
|4 mA<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>|0.35 * VCCI <br>~~a~~<br>|0.65 * VCCI<br>~~ss~~<br>|1.575<br>~~ss~~<br>~~ee~~<br>|0.25 * VCCI <br>~~ss~~<br>~~ee~~<br>|0.75 * VCCI<br>|4<br>|4<br>|33<br>|25<br>|10<br>|10<br>|
|6 mA<br>~~es~~<br>~~a~~<br>~~PR~~|–0.3<br>~~es~~<br><br>|0.35 * VCCI <br>~~es~~<br><br>|0.65 * VCCI<br>~~es~~<br><br>|1.575<br>~~es~~<br>~~ee~~<br><br>|0.25 * VCCI <br>~~es~~<br>~~ee~~<br><br>|0.75 * VCCI<br>~~es~~<br><br>|6<br>~~es~~<br><br>|6<br>~~es~~<br><br>|39<br>~~es~~<br><br>|32<br>~~es~~<br><br>~~eee~~<br>|10<br>~~es~~<br><br>~~eee~~<br>|10<br>~~es~~<br><br>~~eee~~<br>|
|8 mA<br>~~a eee~~<br>~~PR~~|–0.3<br>~~eee~~<br>|0.35 * VCCI <br>~~eee~~<br>|0.65 * VCCI<br>~~eee~~<br>|1.575<br>~~ee~~<br>~~eee~~<br>|0.25 * VCCI <br>~~ee~~<br>~~eee~~<br>|0.75 * VCCI<br>~~eee~~<br>|8<br>~~eee~~<br>|8<br>~~eee~~<br>|55<br>~~eee~~<br>|66<br>~~eee~~<br>~~eee~~<br>|10<br>~~eee~~<br>~~eee~~<br>|10<br>~~eee~~<br>~~eee~~<br>|
|12 mA<br>~~PR~~|–0.3<br>|0.35 * VCCI<br>|0.65 * VCCI<br>|1.575<br>|0.25 * VCCI<br>|0.75 * VCCI<br>|12<br>|12<br>|55<br>|66<br>~~eee~~<br>|10<br>~~eee~~<br>|10<br>~~eee~~<br>|
|**Applicable to Pro I/O Banks**<br>~~eee~~<br>~~PRee~~|||||||||||||
|2 mA<br>~~a~~|–0.3|0.35 * VCCI|0.65 * VCCI|3.6|0.25 * VCCI|0.75 * VCCI|2|2|16|13|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**==> picture [344 x 67] intentionally omitted <==**
**----- Start of picture text -----**<br>
R = 1 k R to VCCI for tLZ / tZL / tZLS<br>Test Point<br>Test Point R to GND for tHZ / tZH / tZHS<br>Data Path 1 35 pF Enable Path 4 35 pF for tZH / tZHS / tZL / tZLS<br>1 1 35 pF for tHZ / tLZ<br>**----- End of picture text -----**<br>
_**Figure 2-122 •**_ **AC Loading**
_**Table 2-127 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|
|0|1.5|0.75|–|35|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
**2-193**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Timing Characteristics**_
_**Table 2-128 •**_ **1.5 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~ee~~|**tDOUT**<br>~~ee~~|**tDP**|**tDIN**|**tPY**|**tPYS**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**<br>~~ee~~|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~eee~~<br>~~ee~~|0.66<br>~~eee~~<br>~~ee~~|14.11<br>~~eee~~|0.04<br>~~eee~~|1.70<br>~~eee~~|2.14<br>~~eee~~|0.43<br>~~eee~~|14.37 <br>~~eee~~|13.14<br>~~eee~~|3.40<br>~~eee~~|2.68<br>~~eee~~|16.61 <br>~~eee~~<br>~~ee~~|15.37<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–1<br>~~ee~~<br>~~a~~|0.56<br>~~ee~~|12.00|0.04<br>~~ee~~|1.44<br>~~ee~~|1.82<br>~~ee ~~|0.36<br> ~~eee~~|12.22<br>~~eee~~<br>~~ee~~|11.17<br>~~eee~~<br>~~ee~~|2.90<br>~~eee eee~~<br>~~ee~~|2.28<br>~~eee~~<br>~~**eee**~~|14.13 <br>~~ee~~<br>~~eee~~<br>~~**eee**~~|13.08<br>~~ee~~<br>~~eee~~<br>~~**eee**~~|ns<br>~~ee~~<br>~~eee~~<br>~~**eee**~~|
||–2<br>~~ee~~<br>~~ee~~<br>~~a~~|0.49<br>~~ee~~<br>~~ee~~|10.54<br>~~ee~~|0.03<br>~~ee~~|1.27<br>~~ee~~|1.60<br>~~ee~~|0.32<br>~~ee~~|10.73<br>~~ee~~<br>~~ee~~|9.81<br>~~ee~~<br>~~ee~~|2.54<br>~~ee~~<br>~~ee~~|2.00<br>~~ee~~<br>~~**eee**~~|12.40 <br>~~ee~~<br>~~ee~~<br>~~**eee**~~|11.48<br>~~ee~~<br>~~ee~~<br>~~**eee**~~|ns<br>~~ee~~<br>~~ee~~<br>~~**eee**~~|
|4 mA|Std.<br>~~a~~<br>~~ee~~|0.66<br>|11.23<br>|0.04<br>~~eee~~<br>|1.70<br>~~eee~~<br>|2.14<br>~~eee~~<br>~~ee~~<br>|0.43<br>~~eee~~<br>~~ee~~<br>|11.44<br>~~ee~~<br>~~eee~~<br><br>|9.87<br>~~ee~~<br>~~eee~~<br>~~e~~<br>|3.77<br>~~ee ~~<br>~~eee~~<br>~~e~~<br>|3.36<br> ~~**eee**~~<br>~~e~~<br>|13.68 <br>~~**eee**~~<br>~~e~~~~**e**~~|12.10<br>~~**eee**~~<br>~~**e**~~|ns<br>~~**eee**~~<br>~~**e**~~|
||–1<br>~~i~~<br>~~ee~~|0.56<br>~~i~~<br>~~ee~~|9.55<br>~~i~~<br>~~ee~~|0.04<br>~~i~~<br>~~ee~~|1.44<br>~~i~~<br>~~ee~~|1.82<br>~~i~~<br>~~ee~~<br>~~ee~~|0.36<br>~~i~~<br>~~ee~~<br>~~ee~~|9.73<br>~~i~~<br><br>~~ee~~|8.39<br>~~i~~<br>~~e~~<br>~~ee~~|3.21<br>~~i~~<br>~~e~~<br>~~ee~~|2.86<br>~~i~~<br>~~e~~<br>~~ee~~|11.63 <br>~~i~~<br>~~e~~~~**e**~~|10.29<br>~~i~~<br>~~**e**~~<br>~~ee~~|ns<br>~~i~~<br>~~**e**~~<br>~~ee~~|
||–2<br>~~ee~~<br>~~ee~~|0.49<br>~~ee~~<br>~~ee~~|8.39<br>~~ee~~|0.03<br>~~ee~~|1.27<br>~~ee~~|1.60<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|8.54<br><br>~~ee~~|7.37<br>~~e~~<br>~~ee~~|2.81<br>~~e~~<br>~~ee~~|2.51<br>~~e~~<br>~~ee~~|10.21<br>~~e~~~~**e**~~<br>~~ee~~|9.04<br>~~**e**~~<br>~~ee~~<br>~~ee~~|ns<br>~~**e**~~<br>~~ee~~<br>~~ee~~|
|8 mA|Std.<br>~~ee ~~<br>~~eee~~<br>~~ee~~|0.66<br> ~~ee ~~<br>~~eee~~<br>~~ee~~|10.45<br> ~~ee~~<br>~~eee~~|0.04<br>~~ee~~<br>~~eee~~|1.70<br>~~ee~~<br>~~eee~~|2.14<br>~~ee~~<br>~~ee ~~<br>~~eee~~|0.43<br>~~ee ~~<br> ~~ee~~<br>~~eee~~|10.65<br> <br>~~ee~~<br>~~eee~~|9.24<br> ~~e~~<br>~~ee ~~<br>~~eee~~|3.84<br>~~e~~<br> ~~ee~~<br>~~eee~~|3.55<br>~~e~~<br>~~ee~~<br>~~eee~~|12.88 <br>~~e~~~~**e**~~<br>~~eee~~<br>~~ee~~|11.48<br>~~**e**~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~**e**~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|
||–1<br>~~ee~~|0.56<br>~~ee~~|8.89|0.04<br>~~ee~~|1.44<br>~~ee~~|1.82<br>~~ee ~~|0.36<br> ~~eee~~|9.06<br>~~eee~~<br>~~ee~~|7.86<br>~~eee~~<br>~~ee~~|3.27<br>~~eee eee~~<br>~~ee~~|3.02<br>~~eee~~<br>~~eee~~|10.96<br>~~ee~~<br>~~eee~~<br>~~eee~~|9.76<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.49<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.81<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|1.27<br>~~ee~~<br>~~ee~~|1.60<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|7.95<br>~~ee~~<br>~~ee~~|6.90<br>~~ee~~<br>~~ee~~|2.87<br>~~ee~~<br>~~ee~~<br>~~**e**~~|2.65<br>~~ee~~<br>~~eee~~<br>~~**e**e~~|9.62<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|8.57<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|12 mA|Std.<br>~~eee~~<br>~~ee~~|0.66<br>~~eee~~<br>~~ee~~|10.02<br>~~eee~~<br>~~ee~~|0.04<br>~~eee~~<br>~~ee~~|1.70<br>~~eee~~<br>~~ee~~|2.14<br>~~eee~~<br>~~ee~~|0.43<br>~~eee~~<br>~~ee~~|10.20<br>~~ee~~<br>~~eee~~|9.23<br>~~ee~~<br>~~eee~~|3.97<br>~~ee ~~<br>~~eee~~<br>~~**e**~~|4.22<br> ~~eee~~<br>~~eee~~<br>~~**e**e~~|12.44 <br>~~eee~~<br>~~eee~~<br>~~eee~~|11.47<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee~~|0.56<br>~~ee~~|8.52<br>~~ee~~|0.04<br>~~ee~~|1.44<br>~~ee~~|1.82<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|8.68<br>~~ee~~|7.85<br>~~ee~~|3.38<br>~~**e**~~<br>~~eee~~|3.59<br>~~**e**e ~~<br>~~eee~~|10.58<br> ~~eee~~<br>~~e~~<br>~~eee~~|9.75<br>~~eee~~<br>~~e~~<br>~~eee~~|ns<br>~~eee~~<br>~~e~~<br>~~eee~~|
||–2<br>~~a ee~~|0.49<br>~~ee~~|7.48<br>~~ee~~|0.03<br>~~ee~~|1.27<br>~~ee~~|1.60<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|7.62<br>~~ee~~<br>~~ee~~|6.89<br>~~ee~~<br>~~ee~~|2.97<br>~~ee~~<br>~~eee~~|3.15<br>~~ee~~<br>~~eee~~|9.29<br>~~ee~~<br>~~eee~~|8.56<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
## _**Table 2-129 •**_ **1.5 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tPYS**<br>~~ee~~|**tEOU**<br>**T**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee eee~~|**tLZ**<br>~~eee~~|**tHZ**<br>~~eee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~ee~~<br>~~a~~|0.66<br>~~ee~~|8.53<br>~~ee~~|0.04<br>~~ee~~|1.70<br>~~ee~~|2.14<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|7.26<br>~~ee~~<br>~~ee~~|8.53<br>~~ee~~<br>~~ee eee~~|3.39<br>~~ee~~<br>~~eee~~|2.79<br>~~ee~~<br>~~eee~~|9.50<br>~~ee~~<br>~~eee~~|10.77<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~|0.56<br>~~a~~|7.26|0.04<br>~~ee~~|1.44<br>~~ee~~|1.82<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee ~~|6.18<br>~~ee~~<br> ~~ee~~|7.26<br>~~ee eee~~<br>~~ee~~|2.89<br>~~eee~~<br>~~ee~~|2.37<br>~~eee~~|8.08<br>~~eee~~|9.16<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~a~~|0.49|6.37<br>~~ee~~|0.03<br>~~ee~~|1.27<br>~~ee~~|1.60<br>~~ee~~|0.32<br>~~ee~~|5.42|6.37|2.53<br>~~ee~~|2.08<br>~~ee~~|7.09<br>~~ee~~|8.04<br>~~ee~~|ns<br>~~ee~~|
|4 mA|Std.<br>~~a~~|0.66<br>~~ee~~|5.41<br>~~ee ~~|0.04<br> ~~ee~~|1.70<br>~~ee~~|2.14<br>~~ee~~|0.43<br>~~ee~~|5.22<br>~~ee~~<br>~~eee~~|5.41<br>~~eee~~|3.75<br>~~ee~~<br>~~eee~~|3.48<br>~~ee~~<br>~~eee~~|7.45<br>~~ee~~<br>~~eee~~|7.65<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–1<br>~~eee~~|0.56<br>~~eee~~|4.60<br>~~eee~~|0.04<br>~~eee~~|1.44<br>~~eee~~|1.82<br>~~eee~~|0.36<br>~~eee~~|4.44<br>~~eee~~<br>~~eee~~|4.60<br>~~eee~~<br>~~eee~~<br>~~ee~~|3.19<br>~~eee~~<br>~~eee~~<br>~~ee~~|2.96<br>~~eee~~<br>~~eee~~<br>~~ee~~|6.34<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.50<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee~~<br>~~a~~|0.49<br>~~ee~~|4.04<br>~~ee~~|0.03<br>~~ee~~|1.27<br>~~ee~~|1.60<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|3.89<br>~~eee~~<br>~~ee~~<br>~~ee~~|4.04<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|2.80<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.60<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|5.56<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|5.71<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|8 mA|Std.<br>~~ee~~<br>~~a~~|0.66<br>~~ee~~|4.80<br>~~ee~~|0.04<br>~~ee~~|1.70<br>~~ee~~|2.14<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|4.89<br>~~ee~~<br>~~ee~~|4.75<br>~~ee ~~<br>~~ee~~<br>~~ee eee~~|3.83<br> ~~ee~~<br>~~ee~~<br>~~eee~~|3.67<br>~~ee ~~<br>~~ee~~<br>~~eee~~|7.13<br> ~~eee~~<br>~~ee~~<br>~~eee~~|6.98<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~|0.56<br>~~a~~|4.09|0.04<br>~~ee~~|1.44<br>~~ee~~|1.82<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee ~~|4.16<br>~~ee~~<br> ~~ee~~|4.04<br>~~ee eee~~<br>~~ee~~|3.26<br>~~eee~~<br>~~ee~~|3.12<br>~~eee~~|6.06<br>~~eee~~|5.94<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~pt~~<br>~~re~~|0.49<br>~~pt~~<br>~~ee~~|3.59<br>~~Tt~~<br>~~ee~~|0.03<br>~~Tt~~<br>~~ee~~|1.27<br>~~Tt~~<br>~~ee~~|1.60<br>~~Tt~~|0.32<br>~~Tt~~|3.65<br>~~Tt~~<br>~~eee~~|3.54<br>~~Tt~~<br>~~eee~~|2.86<br>~~Tt~~<br>~~eee~~|2.74<br>~~Tt~~<br>~~eee~~|5.32<br>~~Tt~~<br>~~eee~~|5.21<br>~~Tt~~<br>~~eee~~|ns<br>~~Tt~~<br>~~eee~~|
|12 mA|Std.<br>~~re~~|0.66<br>~~ee~~|4.42<br>~~ee~~|0.04<br>~~ee~~|1.70<br>~~ee~~|2.14|0.43|4.50<br>~~eee~~<br>~~ee~~|3.62<br>~~eee~~<br>~~ee~~|3.96<br>~~eee~~<br>~~ee eee~~|4.37<br>~~eee~~<br>~~eee~~|6.74<br>~~eee~~<br>~~eee~~|5.86<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~re ~~<br>~~a~~|0.56<br> ~~ee~~<br>~~ee~~|3.76<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.44<br>~~ee~~<br>~~ee~~|1.82<br>~~ee~~|0.36<br>~~ee~~|3.83<br>~~eee~~<br>~~ee~~<br>~~ee~~|3.08<br>~~eee~~<br>~~ee~~<br>~~ee~~|3.37<br>~~eee ~~<br>~~ee~~<br>~~ee eee~~|3.72<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|5.73<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|4.98<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee~~|0.49<br>~~ee~~|3.30<br>~~ee~~|0.03<br>~~ee~~|1.27<br>~~ee~~|1.60<br>~~ee~~|0.32<br>~~ee~~|3.36<br>~~ee~~<br>~~ee~~|2.70<br>~~ee ~~<br>~~ee~~|2.96<br> ~~ee eee~~<br>~~ee~~|3.27<br>~~eee~~<br>~~ee~~<br>~~eee~~|5.03<br>~~eee~~<br>~~ee~~<br>~~eee~~|4.37<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-194**
_Device Architecture_
_**Table 2-130 •**_ **1.5 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**<br>~~ee~~|**tZH**<br>~~eee~~|**tLZ**<br>~~eee~~|**tHZ**<br>~~eee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~ee~~<br>~~a~~|0.66<br>~~ee~~<br>|12.78<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.31<br>~~ee~~<br>|0.43<br>~~ee~~<br>|12.81<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>|12.78<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|3.40<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|2.64<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|15.05<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|15.02<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br><br>|10.87<br>~~ee~~<br><br>|0.04<br>~~ee~~<br><br>|1.11<br>~~ee~~<br><br>|0.36<br>~~ee~~<br><br>|10.90<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~<br><br>|10.87<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.89<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.25<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~<br>|12.80<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~<br>|12.78<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
||–2<br>~~a ee~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br><br>|9.55<br>~~ee~~<br><br>|0.03<br>~~ee~~<br><br>|0.98<br>~~ee~~<br><br>|0.32<br>~~ee~~<br><br>|9.57<br>~~ee ee~~<br>~~ee~~<br><br>|9.55<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|2.54<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|1.97<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br><br>~~e~~|11.24<br>~~eee~~<br>~~ee~~<br>~~ee~~<br><br>~~e~~~~**e**~~|11.22<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|
|4 mA|Std.<br>~~a ee~~<br>~~a~~|0.66<br>~~ee~~<br>|10.01<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.31<br>~~ee~~<br>|0.43<br>~~ee~~<br>|10.19<br>~~ee~~<br>|9.55<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.75<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|3.27<br> ~~ee~~<br>~~ee~~<br>~~e~~|12.43<br>~~ee ~~<br>~~ee~~<br>~~e~~~~**e**~~|11.78<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a ~~<br>~~a~~|8.51<br> ~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.11<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|8.67<br>~~ee~~<br>~~ee~~|8.12<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.19<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.78<br> ~~e~~<br>~~e~~<br>~~ee ee~~|10.57<br>~~e~~~~**e** ~~<br>~~e~~<br>~~ee~~|10.02<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~a~~<br>~~ae~~|7.47<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.98<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|7.61<br>~~ee~~<br>~~ee~~|7.13<br>~~ee~~<br>~~ee~~|2.80<br>~~ee~~<br>~~ee~~|2.44<br>~~ee ee~~<br>~~ee~~|9.28<br>~~ee~~<br>~~ee~~|8.80<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|8 mA|Std.<br>~~a ~~<br>~~a~~<br>~~a~~|0.66<br> ~~a ~~<br>~~ae~~<br>|9.33<br> ~~ee~~<br>~~ee~~<br>|0.04<br>~~ee ~~<br>~~ee~~<br>|1.31<br> ~~ee~~<br>~~ee~~<br>|0.43<br>~~ee~~<br>~~ee~~<br>|9.51<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>|8.89<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.83<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.43<br>~~ee ee~~<br>~~ee~~<br>~~eee~~<br>|11.74<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|11.13<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|
||–1<br>~~a ~~<br>~~ee~~<br>~~a~~|0.56<br> ~~ae~~<br>~~ee~~<br>|7.94<br>~~ee~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|1.11<br>~~ee ~~<br>~~ee~~<br>|0.36<br> ~~ee~~<br>~~ee~~<br>|8.09<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~<br>|7.56<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|3.26<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|2.92<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|9.99<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|9.47<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|
||–2<br>~~a ee~~<br>~~a~~|0.49<br>~~ee~~<br>|6.97<br>~~ee~~<br>|0.03<br>~~ee~~<br>|0.98<br>~~ee~~<br>|0.32<br>~~ee~~<br>|7.10<br>~~ee ee~~<br>~~ee~~<br>|6.64<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.86<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.56<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|8.77<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|8.31<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
|12 mA|Std.<br>~~ee~~<br>~~a~~|0.66<br>~~ee~~<br>|8.91<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.31<br>~~ee~~<br>|0.43<br>~~ee~~<br>|9.07<br>~~ee~~<br>|8.89<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.95<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|4.05<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|11.31<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|11.13<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>|
||–1<br>~~a ~~|0.56<br> ~~a ~~|7.58<br> ~~ee~~|0.04<br>~~ee~~|1.11<br>~~ee~~|0.36<br>~~ee~~|7.72<br>~~ee~~|7.57<br>~~ee~~<br>~~ee~~|3.36<br>~~ee ~~<br>~~ee~~|3.44<br> ~~ee~~<br>~~ee~~|9.62<br>~~ee ~~<br>~~ee~~|9.47<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~ee~~|6.65<br>~~ee~~|0.03<br>~~ee ~~|0.98<br> ~~ee~~|0.32<br>~~ee~~|6.78<br>~~ee~~|6.64<br>~~ee~~|2.95|3.02<br>~~ee~~|8.45<br>~~ee~~|8.31<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
_**Table 2-131 •**_ **1.5 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V**
**Applicable to Advanced I/Os**
|**Drive**<br>**Strength**<br>~~Oa~~|**Speed**<br>**Grade**<br>~~Oa~~|**tDOUT**<br>~~a~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~Oa~~|Std.<br>~~Oa~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~|8.36<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~|1.44<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|6.82<br>~~ee~~|8.36|3.39<br>~~ee~~|2.77<br>~~ee~~|9.06<br>~~ee~~|10.60|ns|
||–1<br>~~Oa~~<br>~~a~~|0.56<br>~~a ~~<br>~~a~~|7.11<br> ~~ee~~<br>~~a~~|0.04<br>~~ee ~~|1.22<br> ~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|5.80<br>~~ee~~|7.11|2.88<br>~~ee~~|2.35<br>~~ee~~|7.71<br>~~ee~~|9.02|ns|
||–2<br>~~a ~~<br>~~a ~~<br>~~a~~|0.49<br> ~~a ~~<br> ~~a~~|6.24<br> ~~a~~<br> a|0.03<br> ~~ee~~|1.07<br>~~ee~~<br>~~ee ~~|0.32<br>~~ee~~<br> ~~ee~~|5.10<br>~~ee~~<br>~~ee~~|6.24<br>~~eeee~~|2.53<br>~~ee ~~<br>~~ee~~|2.06<br> ~~ee~~<br>~~ee~~<br>~~ee eee~~|6.76<br>~~ee~~<br>~~ee~~<br>~~eee~~|7.91<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|4 mA<br>~~Oa~~|Std.<br>~~aeee~~<br>~~a~~<br>~~a~~|0.66<br>~~eee~~<br>|5.31<br>~~eee~~<br>~~ee~~<br>|0.04<br>~~eee~~<br>~~ee~~<br>|1.44<br>~~eee~~<br>~~ee~~<br>|0.43<br>~~eee~~<br>~~ee ee~~<br>|4.85<br>~~eee~~<br>~~ee~~<br>|5.31<br>~~eee~~<br>~~ee~~<br>|3.74<br>~~eee~~<br>~~ee~~<br>|3.40<br>~~eee~~<br>~~ee eee~~<br>~~ee~~<br>|7.09<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|7.55<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>|
||–1<br>~~a~~<br>~~a~~<br>~~Oa~~|0.56<br>|4.52<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.22<br>~~ee~~<br>|0.36<br>~~ee ee~~<br>|4.13<br>~~ee~~<br>|4.52<br>~~ee~~<br><br>~~ee~~|3.18<br>~~ee~~<br><br>~~ee~~|2.89<br>~~ee eee~~<br>~~ee~~<br><br>~~ee eee~~|6.03<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|6.42<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|
||–2<br>~~aee~~<br>~~Oa~~|0.49<br>~~ee~~|3.97<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|1.07<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ee~~<br>~~ee~~|3.62<br>~~ee~~<br>~~ee~~|3.97<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.79<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.54<br> ~~ee ~~<br>~~ee~~<br>~~ee eee~~|5.29<br> ~~eee~~<br>~~ee~~<br>~~eee~~|5.64<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|8 mA<br>~~Oa~~|Std.<br>~~Oa~~<br>~~a~~|0.66<br>~~a ~~<br>~~a~~|4.67<br> ~~ee~~<br>~~a~~|0.04<br>~~ee ~~|1.44<br> ~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|4.55<br>~~ee~~|4.67<br>~~ee~~|3.82<br>~~ee~~<br>~~ee~~|3.56<br>~~ee eee~~<br>~~ee~~|6.78<br>~~eee~~<br>~~ee~~|6.90<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~Oa~~<br>~~a~~<br>~~pt~~|0.56<br>~~a~~<br>~~pt~~|3.97<br>~~a~~<br>|0.04<br>|1.22<br>~~ee~~<br>|0.36<br>~~ee~~<br>|3.87<br>~~ee~~<br>|3.97<br>~~ee~~<br>|3.25<br>~~ee ~~<br>~~ee~~<br>|3.03<br> ~~ee eee~~<br>~~ee~~<br>|5.77<br>~~eee~~<br>~~ee~~<br>|5.87<br>~~eee~~<br>|ns<br>~~eee~~<br>|
||–2<br>~~a ~~<br>~~ptTT~~<br>~~re~~<br>~~a~~|0.49<br> ~~a ~~<br>~~ptTT~~<br>~~ee~~<br>|3.49<br> ~~a~~<br>~~TT~~<br>~~ee~~<br>|0.03<br>~~TT~~<br>~~ee~~<br>|1.07<br>~~ee~~<br>~~TT~~<br>~~ee~~<br>|0.32<br>~~ee~~<br>~~TT~~<br>~~ee~~<br>|3.40<br>~~ee~~<br>~~TT~~<br>~~e~~<br>|3.49<br>~~TT~~<br>~~e~~~~**e**e~~|2.85<br>~~ee ~~<br>~~TT~~<br>~~eeee~~|2.66<br> ~~ee~~<br>~~TT~~<br>~~eee~~|5.07<br>~~ee~~<br>~~TT~~<br>~~eee~~|5.16<br>~~TT~~<br>~~eee~~|ns<br>~~TT~~<br>~~eee~~|
|12 mA|Std.<br>~~ptTT~~<br>~~re~~<br>~~a~~<br>~~a~~|0.66<br>~~ptTT~~<br>~~ee~~<br><br>|4.08<br>~~TT~~<br>~~ee~~<br><br>|0.04<br>~~TT~~<br>~~ee~~<br><br>|1.44<br>~~TT~~<br>~~ee~~<br><br>|0.43<br>~~TT~~<br>~~ee~~<br><br>|4.15<br>~~TT~~<br>~~e~~<br><br>|3.58<br>~~TT~~<br>~~e~~~~**e**e~~<br>|3.94<br>~~TT~~<br>~~eeee~~<br>|4.20<br>~~TT~~<br>~~eee~~<br>~~ee~~<br>|6.39<br>~~TT~~<br>~~eee~~<br>~~eee~~<br>|5.81<br>~~TT~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~TT~~<br>~~eee~~<br>~~ee~~<br>|
||–1<br>~~TT~~<br>~~re ~~<br>~~ae~~<br>~~a~~|0.56<br>~~TT~~<br> ~~ee ~~<br>~~e~~<br>|3.47<br>~~TT~~<br> ~~ee~~<br>~~e~~<br>|0.04<br>~~TT~~<br>~~ee~~<br>~~e~~<br>|1.22<br>~~TT~~<br>~~ee~~<br>~~e~~<br>|0.36<br>~~TT~~<br>~~ee ~~<br>~~e~~<br>|3.53<br>~~TT~~<br> ~~e~~<br>~~e~~<br>|3.04<br>~~TT~~<br>~~e~~~~**e**e~~<br><br>~~ee~~|3.36<br>~~TT~~<br>~~eeee~~<br><br>~~ee~~|3.58<br>~~TT~~<br>~~eee~~<br>~~ee~~<br><br>~~ee~~|5.44<br>~~TT~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|4.95<br>~~TT~~<br>~~eee~~<br>~~eee~~<br><br>~~eee~~|ns<br>~~TT~~<br>~~eee~~<br>~~ee~~<br><br>~~eee~~|
||–2<br>~~aee~~|0.49<br>~~ee~~|3.05<br>~~ee~~|0.03<br>~~ee~~|1.07<br>~~ee~~|0.32<br>~~ee~~|3.10<br>~~ee~~|2.67<br>~~ee~~<br>~~ee~~|2.95<br>~~ee~~<br>~~ee~~|3.14<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.77<br> ~~eee~~<br>~~ee~~<br>~~eee~~|4.34<br>~~eee ~~<br>~~ee~~<br>~~eee~~|ns<br> ~~ee~~<br>~~ee~~<br>~~eee~~|
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## _**Table 2-132 •**_ **1.5 V LVCMOS Low Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V**
**Applicable to Standard I/Os**
|**Drive**<br>**Strength**<br>~~|~~<br>~~ee~~|**Speed**<br>**Grade**<br>~~ft~~<br>~~ee~~|**tDOUT**<br>~~ft~~<br>~~ee~~|**tDP**<br>~~ftrt~~<br>~~es~~|**tDIN**<br>~~rt~~<br>~~es~~|**tPY**<br>~~es es~~|**tEOUT**<br>~~es~~|**tZL**<br>~~es~~|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~|~~<br>~~ee~~<br>~~a~~<br>~~ae~~|Std.<br>~~ft~~<br>~~ee~~<br>~~a~~|0.66<br>~~ft~~<br>~~ee~~<br>~~es~~|12.33<br>~~ft rt~~<br>~~es~~<br>~~es~~|0.04<br>~~rt~~<br>~~es~~<br>~~en~~|1.42<br>~~es es~~<br>~~(~~|0.43<br>~~es~~<br>~~(~~|11.79<br>~~es~~|12.33|2.45|2.32|ns|
||–1<br>~~ee~~<br>~~a~~<br>~~ae~~|0.56<br>~~ee~~<br>~~es~~<br>~~ee~~|10.49<br>~~es~~<br>~~es~~<br>~~es Gs~~|0.04<br>~~es ~~<br>~~en~~<br>~~Gs~~|1.21<br> ~~es es~~<br>~~(~~<br>~~ee~~|0.36<br>~~es~~<br>~~(~~<br>~~s(n~~|10.03<br>~~es~~<br>~~s(n~~|10.49|2.08|1.98|ns|
||–2<br>~~a~~<br>~~ae~~|0.49<br>~~es ~~<br>~~ee~~|9.21<br> ~~es ~~<br>~~es Gs~~|0.03<br> ~~en ~~<br>~~Gs~~|1.06<br> ~~( ~~<br>~~ee~~|0.32<br> ~~(~~<br>~~s(n~~|8.81<br>~~s(n~~|9.21|1.83|1.73|ns|
_**Table 2-133 •**_ **1.5 V LVCMOS High Slew**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V**
## **Applicable to Standard I/Os**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.|0.66|7.65|0.04|1.42|0.43|6.31|7.65|2.45|2.45|ns|
||–1|0.56|6.50|0.04|1.21|0.36|5.37|6.50|2.08|2.08|ns|
||–2|0.49|5.71|0.03|1.06|0.32|4.71|5.71|1.83|1.83|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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_Device Architecture_
## _**3.3 V PCI, 3.3 V PCI-X**_
The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.
_**Table 2-134 •**_ **Minimum and Maximum DC Input and Output Levels**
|**3.3 V PCI/PCI-X**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|Per PCI<br>specification|Per PCI curves||||||||||10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable path characterization are described in Figure 2-123.
**==> picture [403 x 57] intentionally omitted <==**
**----- Start of picture text -----**<br>
R = 25 R to VCCI for tDP (F) R = 1 k R to VCCI for tLZ / tZL / tZLS<br>Test Point R to GND for tDP (R) Test Point R to GND for tHZ / tZH / tZHS<br>Data Path Enable Path 10 pF for tZH / tZHS / tZL / tZLS<br>{ 7 10 pF for tHZ / tLZ<br>**----- End of picture text -----**<br>
## _**Figure 2-123 •**_ **AC Loading**
AC loadings are defined per PCI/PCI-X specifications for the data path; Microsemi loading for tristate is described in Table 2-135.
_**Table 2-135 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|
|0|3.3|0.285 * VCCI for tDP(R)<br>0.615 * VCCI for tDP(F)|–|10|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
**2-197**
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## _**Timing Characteristics**_
## _**Table 2-136 •**_ **3.3 V PCI/PCI-X**
## **Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os**
|**Speed**<br>**Grade**<br>~~pt~~<br>~~ee~~|**tDOUT**<br>~~pt~~<br>~~|~~<br>~~ee~~|**tDP**<br>~~tt~~<br>~~ee~~|**tDIN**<br>~~tt~~|**tPY**<br>~~tt~~<br>~~eee~~|**tPYS**<br>~~eee~~|**tEOUT**<br>~~eee~~|**tZL**<br>~~eee~~|**tZH**<br>~~eee~~|**tLZ**<br>~~eee~~|**tHZ**<br>~~eee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~pt~~<br>~~ee~~|0.66<br>~~pt~~<br>~~|~~<br>~~ee~~|2.81<br>~~tt~~<br>~~ee~~|0.04<br>~~tt~~|1.05<br>~~tt~~<br>~~eee~~|1.67<br>~~eee~~|0.43<br>~~eee~~|2.86<br>~~eee~~<br>~~ee~~|2.00<br>~~eee~~<br>~~ee~~|3.28<br>~~eee~~<br>~~ee~~|3.61<br>~~eee~~<br>~~eee~~|5.09<br>~~eee~~<br>~~eee~~|4.23<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|–1<br>~~ee~~<br>~~a ee~~|0.56<br>~~ee~~<br>~~ee~~|2.39<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~|0.89<br>~~eee~~<br>~~ee~~|1.42<br>~~eee~~<br>~~ee~~|0.36<br>~~eee ~~<br>~~ee~~|2.43<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.70<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.79<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.07<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|4.33<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|3.60<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|–2<br>~~ee~~|0.49<br>~~ee~~|2.09<br>~~ee~~|0.03<br>~~ee~~|0.78<br>~~ee~~|1.25<br>~~ee~~|0.32<br>~~ee~~|2.13<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.49<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.45<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.70<br> ~~eee~~<br>~~ee~~<br>~~eee~~|3.80<br>~~eee ~~<br>~~ee~~<br>~~eee~~|3.16<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
_**Table 2-137 •**_ **3.3 V PCI/PCI-X**
## **Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os**
|**Speed**<br>**Grade**<br>~~et~~<br>~~a~~|**tDOUT**<br>~~et~~<br>|<br>|**tDP**<br>~~tte~~<br>|**tDIN**<br>~~tte~~<br>|**tPY**<br>~~tte~~<br>|**tPYS**<br>~~tte~~<br>|**tEOUT**<br>~~|~~<br>|**tZL**<br>|**tZH**<br>~~ee~~<br>|**tLZ**<br>~~ee~~<br>|**tHZ**<br>~~ee~~<br>|**tZLS**<br>~~eee~~<br>|**tZHS**<br>~~eee~~<br>|**Units**<br>~~eee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~et~~<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~et~~<br>| <br>~~ee~~<br><br>|2.68<br> ~~tte~~<br>~~ee~~<br><br>|0.04<br>~~tte~~<br>~~ee~~<br><br>|0.86<br>~~tte~~<br>~~ee~~<br><br>|0.43<br>~~tte~~<br>~~ee~~<br><br>|2.73<br>~~|~~<br>~~ee~~<br><br>|1.95<br>~~ee~~<br><br>~~**e**~~<br>|3.21<br>~~ee~~<br>~~ee~~<br><br>~~**e**e~~<br>|3.58<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|4.97<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|4.19<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|0.66<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
|–1<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>|2.28<br>~~ee~~<br>|0.04<br>~~ee~~<br>|0.73<br>~~ee~~<br>|0.36<br>~~ee~~<br>|2.32<br>~~ee~~<br>|1.66<br>~~ee~~<br>~~**e**~~<br>~~ee~~|2.73<br>~~ee~~<br>~~ee~~<br>~~**e**e~~<br>~~ee~~|3.05<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.22<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.56<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|0.56<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|–2<br>~~a~~|0.49<br>~~e~~|2.00<br>~~e~~|0.03<br>~~e~~|0.65<br>~~e~~|0.32<br>~~e~~|2.04<br>~~e~~|1.46<br>~~**e**~~<br>~~eee~~|2.40<br>~~**e**e ~~<br>~~ee~~|2.68<br> ~~ee~~<br>~~ee~~|3.71<br>~~ee ~~<br>~~ee~~|3.13<br> ~~eee~~<br>~~eee~~|0.49<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
**Revision 8**
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## _**Voltage Referenced I/O Characteristics**_
## _**3.3 V GTL**_
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
_**Table 2-138 •**_ **Minimum and Maximum DC Input and Output Levels**
|**3.3 V GTL**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA **|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4 **|**µA4**|
|20 mA3|–0.3|VREF – 0.05|VREF + 0.05|3.6|0.4|–|20|20|181|268|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [109 x 68] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>GTL<br>25<br>Test Point<br>10 pF<br>**----- End of picture text -----**<br>
_**Figure 2-124 •**_ **AC Loading**
_**Table 2-139 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.05|VREF + 0.05|0.8|0.8|1.2|10|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
## _**Table 2-140 •**_ **3.3 V GTL**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V**
|**Speed**<br>**Grade**<br>~~Pot~~<br>~~a~~|**tDOUT**<br>~~Pot~~<br>~~|~~<br>~~a~~|**tDP**<br>~~tt~~<br>~~ee~~|**tDIN**<br>~~tt~~<br>~~ee~~|**tPY**<br>~~tttt~~<br>~~ee~~|**tEOUT**<br>~~tt~~<br>~~ee~~|**tZL**<br>~~tt~~<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~Pot~~<br>~~a~~<br>~~a~~|0.66<br>~~Pot~~<br>~~|~~<br>~~a~~<br>|2.08<br>~~tt~~<br>~~ee~~|0.04<br>~~tt~~<br>~~ee~~|2.93<br>~~tt tt~~<br>~~ee~~|0.43<br>~~tt~~<br>~~ee~~|2.04<br>~~tt~~<br>~~ee~~|2.08<br>~~ee~~|~~ee~~|~~ee~~|4.27<br>~~ee~~<br>~~ee~~|4.31<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|–1<br>~~a ~~<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br> ~~a~~<br>|1.77<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~|2.50<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|1.73<br>~~ee~~<br>~~ee~~|1.77<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|3.63<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.67<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|–2<br>~~a ~~|0.49<br> ~~a~~|1.55<br>~~a~~|0.03<br>~~ee~~|2.19<br>~~ee~~|0.32<br>~~ee~~|1.52<br>~~ee~~|1.55<br>~~ee~~|~~ee~~|~~ee~~|3.19<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.22<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
**2-199**
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_Fusion Family of Mixed Signal FPGAs_
## _**2.5 V GTL**_
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
_**Table 2-141 •**_ **Minimum and Maximum DC Input and Output Levels**
|**2.5 GTL**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|20 mA3|–0.3|VREF – 0.05|VREF + 0.05|3.6|0.4|–|20|20|124|169|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
VTT GTL 25 Test Point 10 pF ~~SO~~
_**Figure 2-125 •**_ **AC Loading**
_**Table 2-142 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.05|VREF + 0.05|0.8|0.8|1.2|10|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-143 •**_ **2.5 V GTL**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V**
|**Speed**<br>**Grade**<br>~~pt~~|**tDOUT**<br>~~pttp~~|**tDP**<br>~~tpPe~~|**tDIN**<br>~~Pe~~|**tPY**<br>~~Pe~~|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~pt~~<br>~~a ~~<br>~~a~~|0.66<br>~~pt tp~~<br> ~~a ~~<br>~~a~~|2.13<br>~~tp Pe~~<br> ~~a~~|0.04<br>~~Pe~~<br>~~ee~~<br>~~ee~~|2.46<br>~~Pe~~<br>~~ee ~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee~~|2.16<br>~~ee~~<br>~~ee~~|2.13<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|4.40<br>~~eee~~<br>~~ee~~|4.36<br>~~eee~~|ns<br>~~eee~~|
|–1<br>~~a~~|0.56<br>~~a~~|1.81|0.04<br>~~ee~~|2.09<br>~~ee~~|0.36<br>~~ee~~|1.84<br>~~ee~~|1.81<br>~~ee~~|~~ee~~|~~ee~~|3.74<br>~~ee~~|3.71|ns|
|–2<br>~~a ~~<br>~~a ~~|0.49<br> ~~a~~<br> ~~a~~|1.59<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|1.83<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|1.61<br> ~~ee~~<br>~~ee~~|1.59<br>~~ee ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|3.28<br>~~ee~~<br>~~ee~~|3.26<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-200**
_Device Architecture_
## _**3.3 V GTL+**_
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
_**Table 2-144 •**_ **Minimum and Maximum DC Input and Output Levels**
|**3.3 V GTL+**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA **|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|35 mA|–0.3|VREF – 0.1|VREF + 0.1|3.6|0.6|–|35|35|181|268|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [109 x 67] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>GTL+<br>25<br>Test Point<br>10 pF<br>**----- End of picture text -----**<br>
_**Figure 2-126 •**_ **AC Loading**
_**Table 2-145 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.1|VREF + 0.1|1.0|1.0|1.5|10|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
## _**Table 2-146 •**_ **3.3 V GTL+**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V**
|**Speed**<br>**Grade**<br>~~P|~~|**tDOUT**<br>~~P|tt~~|**tDP**<br>~~tt~~|**tDIN**<br>~~tttt~~|**tPY**<br>~~tt~~|**tEOUT**<br>~~tttt~~|**tZL**<br>~~tt~~|**tZH**<br>~~tttt~~|**tLZ**<br>~~tt~~|**tHZ**<br>~~tt~~|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~P|~~<br>~~a~~|0.66<br>~~P| tt~~|2.06<br>~~tt~~<br>~~a~~|0.04<br>~~tt tt~~<br>~~a~~|1.59<br>~~tt~~<br>~~ee~~|0.43<br>~~tt tt~~<br>~~ee~~|2.09<br>~~tt~~<br>~~ee ~~|2.06<br>~~tt tt~~<br> ~~ee~~|~~tt~~<br>~~ee~~|~~tt~~<br>~~ee~~|4.33|4.29<br>~~ee~~|ns<br>~~ee~~|
|–1<br>~~a ~~|0.56<br> ~~ee~~|1.75<br>~~ee~~|0.04<br>~~ee~~|1.35<br>~~ee~~|0.36<br>~~ee~~|1.78<br>~~ee~~|1.75<br>~~ee~~|~~ee~~|~~ee~~|3.68<br>~~ee~~|3.65<br>~~ee~~|ns<br>~~ee~~|
|–2<br>~~a~~|0.49|1.53<br>~~ee~~|0.03<br>~~ee~~|1.19<br>~~ee~~|0.32<br>~~ee~~|1.56<br>~~ee~~|1.53||~~ee~~|3.23<br>~~ee~~|3.20<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-201**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**2.5 V GTL+**_
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
_**Table 2-147 •**_ **Minimum and Maximum DC Input and Output Levels**
|**2.5 V**<br>**GTL+**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|33 mA|–0.3|VREF – 0.1|VREF + 0.1|3.6|0.6|–|33|33|124|169|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [91 x 51] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>GTL+<br>25<br>Test Point<br>**----- End of picture text -----**<br>
10 pF
~~a~~
_**Figure 2-127 •**_ **AC Loading**
_**Table 2-148 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.1|VREF + 0.1|1.0|1.0|1.5|10|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-149 •**_ **2.5 V GTL+**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V**
|**Speed**<br>**Grade**<br>~~pt~~|**tDOUT**<br>~~pt~~<br>~~|~~|**tDP**<br>~~tT~~|**tDIN**<br>~~tTtt~~|**tPY**<br>~~tt~~|**tEOUT**<br>~~tt~~|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~pt~~<br>~~a ~~|0.66<br>~~pt~~<br>~~|~~<br> ~~a ~~|2.21<br>~~tT~~<br> ~~ee~~|0.04<br>~~tT tt~~<br>~~ee~~|1.51<br>~~tt~~<br>~~ee ~~|0.43<br>~~tt~~<br> ~~ee~~|2.25<br>~~ee~~|2.10|~~ee~~|~~ee~~|4.48<br>~~ee~~|4.34|ns|
|–1<br>~~a~~|0.56<br>~~a ~~|1.88<br> ~~ee~~|0.04<br>~~ee~~|1.29<br>~~ee~~|0.36<br>~~ee~~|1.91<br>~~ee~~|1.79|~~ee~~|~~ee~~|3.81<br>~~ee~~|3.69<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|–2<br>~~a~~|0.49<br>~~a~~|1.65<br>~~ee~~|0.03<br>~~ee~~|1.13<br>~~ee~~|0.32<br>~~ee~~|1.68<br>~~ee~~|1.57<br>~~ee~~|~~ee~~|~~ee~~|3.35<br>~~ee~~|4.34<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
**2-202**
_Device Architecture_
## _**HSTL Class I**_
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
_**Table 2-150 •**_ **Minimum and Maximum DC Input and Output Levels**
|**HSTL**<br>**Class I**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|8 mA|–0.3|VREF – 0.1|VREF + 0.1|3.6|0.4|VCCI – 0.4|8|8|39|32|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [108 x 68] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>HSTL<br>Class I 50<br>Test Point<br>20 pF<br>**----- End of picture text -----**<br>
_**Figure 2-128 •**_ **AC Loading**
_**Table 2-151 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.1|VREF + 0.1|0.75|0.75|0.75|20|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
## _**Table 2-152 •**_ **HSTL Class I**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V**
|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**<br>|**tPY**|**tEOUT**|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~<br>|3.18<br>~~ee~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>|2.12<br>~~ee~~<br>|0.43<br>~~ee~~<br>~~e~~<br>|3.24<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|3.14<br>~~ee~~<br>~~ee~~<br>~~**e**~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|5.47<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.38<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>|2.70<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.81<br>|0.36<br>~~e~~<br>|2.75<br>~~ee~~<br>~~e~~~~**e**~~<br>|2.67<br>~~ee~~<br>~~**e**~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|4.66<br> ~~ee~~<br>~~ee~~<br>~~ee~~|4.58<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|–2<br> <br>~~a~~|0.49<br> ~~a ~~<br>~~e~~|2.37<br> ~~ee~~<br>~~e~~|0.03<br>~~ee~~<br>~~e~~|1.59<br>~~e~~|0.32<br>~~e~~<br>~~e~~|2.42<br>~~e~~~~**e**~~<br>~~e~~|2.35<br>~~**e**~~|~~ee~~|~~ee ~~<br>~~ee~~|4.09<br> ~~ee ~~<br>~~ee~~|4.02<br> ~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-203**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**HSTL Class II**_
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
_**Table 2-153 •**_ **Minimum and Maximum DC Input and Output Levels**
|**HSTL Class II**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL1 **|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4 **|**µA4**|
|15 mA3|–0.3|VREF – 0.1|VREF + 0.1|3.6|0.4|VCCI – 0.4|15|15|55|66|10|10|
_Note:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Output drive strength is below JEDEC specification._
**==> picture [64 x 31] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>HSTL<br>Class II 25<br>**----- End of picture text -----**<br>
Test Point
## 20 pF
## ~~a~~
_**Figure 2-129 •**_ **AC Loading**
_**Table 2-154 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.1|VREF + 0.1|0.75|0.75|0.75|20|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-155 •**_ **HSTL Class II**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V**
|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**<br>|**tPY**<br>|**tEOUT**<br>|**tZL**<br>|**tZH**<br>|**tLZ**<br>|**tHZ**<br>|**tZLS**<br>~~ee ee~~<br>|**tZHS**<br>~~ee~~<br>|**Units**<br>~~ee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~ee~~<br><br>|3.02<br>~~a~~<br>~~ee~~<br><br>|0.04<br>~~a~~<br>~~ee~~<br><br>|2.12<br>~~a~~<br>~~ee~~<br><br>|0.43<br>~~a~~<br>~~ee~~<br><br>|3.08<br>~~a~~<br>~~ee~~<br><br>|2.71<br>~~a~~<br>~~ee~~<br><br>|~~a~~<br>~~ee~~<br><br>|~~a~~<br>~~ee~~<br>|5.32<br>~~a~~<br>~~ee~~<br>~~ee ee~~<br><br>~~ee~~|4.95<br>~~a~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|ns<br>~~a~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|
|–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>~~a~~|2.57<br>~~ee~~<br>~~ae~~|0.04<br>~~ee~~<br>~~De~~|1.81<br>~~ee~~<br>~~De~~|0.36<br>~~ee~~<br>~~ee~~|2.62<br>~~ee~~<br>~~ee~~|2.31<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|4.52<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|4.21<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|–2<br>~~a ~~|0.49<br> ~~a~~|2.26<br>~~ae~~|0.03<br>~~De~~|1.59<br>~~De~~|0.32<br>~~ee~~|2.30<br>~~ee~~|2.03<br>~~ee~~|~~ee~~||3.97<br>~~ee ~~|3.70<br> ~~ee~~|ns<br>~~ee~~|
**Revision 8**
**2-204**
_Device Architecture_
## _**SSTL2 Class I**_
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
_**Table 2-156 •**_ **Minimum and Maximum DC Input and Output Levels**
|**SSTL2 Class I**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH **|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|15 mA|–0.3|VREF – 0.2|VREF + 0.2|3.6|0.54|VCCI – 0.62|15|15|87|83|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [131 x 65] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>SSTL2<br>Class I 50<br>Test Point<br>25<br>30 pF<br>**----- End of picture text -----**<br>
_**Figure 2-130 •**_ **AC Loading**
_**Table 2-157 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.2|VREF + 0.2|1.25|1.25|1.25|30|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-158 •**_ **SSTL 2 Class I**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V**
|**Speed**<br>**Grade**<br>~~pt~~<br>~~a~~|**tDOUT**<br>~~ptttt~~<br>|**tDP**<br>~~ttt~~<br>|**tDIN**<br>~~ttt~~<br>|**tPY**<br>~~tttyt~~<br>|**tEOUT**<br>~~yttp~~<br>|**tZL**<br>~~tp~~<br>|**tZH**<br>~~tp~~<br>|**tLZ**<br>~~ee~~<br>|**tHZ**<br>~~ee~~<br>|**tZLS**<br>~~ee~~<br>|**tZHS**<br>~~ee~~<br>|**Units**<br>~~ee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~pt~~<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~pt ttt~~<br>~~ee~~<br>|2.13<br>~~ttt~~<br>~~ee~~<br>|0.04<br>~~ttt~~<br>~~ee~~<br>|1.33<br>~~ttt yt~~<br>~~ee~~<br>|0.43<br>~~yt tp~~<br>~~ee~~<br>|2.17<br>~~tp~~<br>~~ee~~<br>|1.85<br>~~tp~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~<br>|4.40<br>~~ee~~<br>~~ee~~<br>|4.08<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|
|–1<br>~~a~~<br>~~a~~|0.56<br>~~ee~~|1.81<br>~~ee~~|0.04<br>~~ee~~|1.14<br>~~ee~~|0.36<br>~~ee~~|1.84<br>~~ee~~|1.57<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|3.74<br> ~~ee~~<br>~~ee~~|3.47<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|–2<br>~~a~~|0.49|1.59|0.03|1.00<br>~~eee~~|0.32<br>~~eee~~|1.62<br>~~eee~~|1.38<br>~~eee~~|~~eee ~~|~~eee~~|3.29<br>~~eee~~|3.05<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
**2-205**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**SSTL2 Class II**_
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
_**Table 2-159 •**_ **Minimum and Maximum DC Input and Output Levels**
|**SSTL2 Class II**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4 **|**µA4**|
|18 mA|–0.3|VREF – 0.2|VREF + 0.2|3.6|0.35|VCCI – 0.43|18|18|124|169|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [131 x 67] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>SSTL2<br>Class II 25<br>Test Point<br>25<br>30 pF<br>**----- End of picture text -----**<br>
_**Figure 2-131 •**_ **AC Loading**
_**Table 2-160 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.2|VREF + 0.2|1.25|1.25|1.25|30|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-161 •**_ **SSTL 2 Class II**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V**
|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**<br>~~ee~~|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~a ~~<br>~~a~~|0.66<br> ~~a~~<br>|2.17<br>~~ee~~<br>|0.04<br>~~ee~~|1.33<br>~~ee~~|0.43<br>~~ee~~|2.21<br>~~ee~~|1.77<br>~~ee~~|~~ee~~|~~ee~~|4.44<br>~~ee~~<br>~~ee~~|4.01<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|–1<br>~~a ~~|0.56<br> ~~a~~|1.84<br>~~a~~|0.04|1.14|0.36<br>~~ee~~|1.88<br>~~ee~~|1.51<br>~~ee ~~|~~ee~~|~~ee~~|3.78<br>~~ee~~|3.41<br>~~ee~~|ns<br>~~ee~~|
|–2<br>~~a~~|0.49<br>~~ee~~|1.62<br>~~ee~~|0.03<br>~~ee~~|1.00<br>~~ee~~|0.32<br>~~ee~~|1.65<br>~~ee~~|1.32<br>~~ee~~|~~ee~~|~~ee~~|3.32<br>~~ee~~|2.99<br>~~ee~~|ns<br>~~ee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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_Device Architecture_
## _**SSTL3 Class I**_
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
_**Table 2-162 •**_ **Minimum and Maximum DC Input and Output Levels**
|**SSTL3 Class I**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|14 mA|–0.3|VREF – 0.2 VREF + 0.2|VREF – 0.2 VREF + 0.2|3.6|0.7|VCCI – 1.1|14|14|54|51|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [131 x 65] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>SSTL3<br>Class I 50<br>Test Point<br>25<br>30 pF<br>**----- End of picture text -----**<br>
_**Figure 2-132 •**_ **AC Loading**
_**Table 2-163 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.2|VREF + 0.2|1.5|1.5|1.485|30|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
## _**Table 2-164 •**_ **SSTL3 Class I**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V**
|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**<br>|**tPY**<br>|**tEOUT**<br>|**tZL**<br>|**tZH**<br>~~ee~~<br>|**tLZ**<br>~~ee~~<br>|**tHZ**<br>~~eee~~<br>|**tZLS**<br>~~eee~~<br>|**tZHS**<br>~~eee~~<br>|**Units**<br>~~eee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br><br>|2.31<br>~~ee~~<br><br>|0.04<br>~~ee~~<br><br>|1.25<br>~~ee~~<br><br>|0.43<br>~~ee~~<br><br>|2.35<br>~~ee~~<br><br>~~ee~~<br>|1.84<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|4.59<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|4.07<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
|–1<br>~~a ee~~<br>~~a~~|0.56<br>~~ee~~<br>|1.96<br>~~ee~~<br>|0.04<br>~~ee~~<br>|1.06<br>~~ee~~<br>|0.36<br>~~ee~~<br>|2.00<br>~~ee~~<br>~~ee~~<br>|1.56<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|3.90<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|3.46<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~|
|–2<br>~~a~~|0.49<br>~~ee~~|1.72<br>~~ee~~|0.03<br>~~ee~~|0.93<br>~~ee~~|0.32<br>~~ee~~|1.75<br>~~ee ~~<br>~~ee~~|1.37<br> ~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~eee~~|3.42<br>~~eee~~<br>~~ee~~<br>~~eee~~|3.04<br>~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~|
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_Fusion Family of Mixed Signal FPGAs_
## _**SSTL3 Class II**_
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
_**Table 2-165 •**_ **Minimum and Maximum DC Input and Output Levels**
|**SSTL3 Class II**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|**IOSL**|**IOSH**|**IIL1**|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA**|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4**|**µA4**|
|21 mA|–0.3|VREF – 0.2 VREF + 0.2|VREF – 0.2 VREF + 0.2|3.6|0.5|VCCI – 0.9|21|21|109|103|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
**==> picture [131 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
VTT<br>SSTL3<br>Class II 25<br>Test Point<br>25<br>30 pF<br>**----- End of picture text -----**<br>
_**Figure 2-133 •**_ **AC Loading**
_**Table 2-166 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|**VTT (typ.) (V)**|**CLOAD (pF)**|
|---|---|---|---|---|---|
|VREF – 0.2|VREF + 0.2|1.5|1.5|1.485|30|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-167 •**_ **SSTL3- Class II**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V**
|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~a ~~|0.66<br> ~~a ~~|2.07<br> ~~a~~|0.04<br>~~a~~|1.25|0.43<br>~~ee~~|2.10<br>~~ee ~~|1.67<br> ~~ee~~|~~ee~~|~~ee ~~|4.34<br> ~~ee~~|3.91<br>~~ee~~|ns|
|–1<br>~~a ~~|0.56<br> ~~a~~|1.76|0.04<br>~~ee~~|1.06<br>~~ee~~|0.36<br>~~ee~~|1.79<br>~~ee ~~|1.42<br> ~~ee~~|~~ee~~||3.69|3.32<br>~~eee~~|ns<br>~~eee~~|
|–2<br>~~a~~|0.49<br>~~ee~~|1.54<br>~~ee~~|0.03<br>~~ee~~|0.93<br>~~ee~~|0.32<br>~~ee~~|1.57<br>~~ee~~|1.25<br>~~ee~~|~~ee~~|~~ee~~|3.24<br>~~ee~~|2.92<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**Revision 8**
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_Device Architecture_
## _**Differential I/O Characteristics**_
Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer software when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with these standards.
## _**LVDS**_
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-134. The building blocks of the LVDS transmitter–receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different.
**==> picture [439 x 87] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bourns Part Number: CAT16-LV4F12<br>FPGA FPGA<br>OUTBUF_LVDS P P<br>165 ZO = 50 <br>+ INBUF_LVDS<br>140 100 <br>–<br>165 ZO = 50 <br>N N<br>**----- End of picture text -----**<br>
_**Figure 2-134 •**_ **LVDS Circuit Diagram and Board-Level Implementation**
_**Table 2-168 •**_ **Minimum and Maximum DC Input and Output Levels**
|**DC Parameter**<br>~~es~~<br>~~es~~|**Description**<br>~~nD~~|**Min.**<br>~~I~~|**Typ.**<br>~~(~~<br>~~(OO~~|**Max.**<br>~~I~~|**Units**|
|---|---|---|---|---|---|
|VCCI<br>~~es~~<br>~~es~~<br>~~es~~|Supply Voltage<br>~~nD~~<br>~~nn~~|2.375<br>~~I~~<br>~~(~~|2.5<br>~~(~~<br>~~(OO~~<br>~~(~~|2.625<br>~~I~~|V|
|VOL<br>~~es~~<br>~~es~~<br>~~es~~|Output Low Voltage<br>~~nD ~~<br>~~nn~~<br>~~nD~~|0.9<br> ~~I ~~<br>~~(~~<br>~~I~~|1.075<br> ~~(OO~~<br>~~(~~<br>~~(OO~~|1.25<br>~~I~~<br>~~I~~|V|
|VOH<br>~~es~~<br>~~es~~<br>~~es~~|Input High Voltage<br>~~nn~~<br>~~nD~~<br>~~nn~~|1.25<br>~~(~~<br>~~I~~<br>~~(~~|1.425<br>~~(~~<br>~~(OO~~<br>~~(~~|1.6<br>~~I~~|V|
|IOL 1<br>~~es~~<br>~~es~~<br>~~es~~|Output Low Voltage<br>~~nD ~~<br>~~nn~~<br>~~nD~~|0.65<br> ~~I ~~<br>~~(~~<br>~~I (~~|0.91<br> ~~(OO~~<br>~~(~~<br>~~(~~|1.16<br>~~I~~|mA|
|IOH 1<br>~~es~~<br>~~es~~<br>~~ee~~|Output High Voltage<br>~~nn~~<br>~~nD~~<br>~~nD~~|0.65<br>~~(~~<br>~~I (~~<br>~~(~~|0.91<br>~~(~~<br>~~(~~<br>~~(~~|1.16|mA|
|VI<br>~~es~~<br>~~ee~~<br>~~es~~|Input Voltage<br>~~nD ~~<br>~~nD~~<br>~~nD~~|0<br> ~~I (~~<br>~~(~~<br>~~I (~~|~~(~~<br>~~(~~<br>~~(~~|2.925|V|
|IIL 2,3<br>~~ee~~<br>~~es~~<br>~~ee~~|Input Low Voltage<br>~~nD~~<br>~~nD~~<br>~~nD~~|~~(~~<br>~~I (~~<br>~~(~~|~~(~~<br>~~(~~<br>~~(~~|10|A|
|IIH 2,4<br>~~es~~<br>~~ee~~<br>~~es~~|Input High Voltage<br>~~nD ~~<br>~~nD~~<br>~~nD~~|~~I (~~<br>~~(~~<br>~~I~~|~~(~~<br>~~(~~<br>~~(OO~~|10<br>~~I~~|A|
|VODIFF<br>~~ee~~<br>~~es~~<br>~~es~~|Differential Output Voltage<br>~~nD~~<br>~~nD~~<br>~~nn~~|250<br>~~(~~<br>~~I~~<br>~~(~~|350<br>~~(~~<br>~~(OO~~<br>~~(~~|450<br>~~I~~|mV|
|VOCM<br>~~es~~<br>~~es~~<br>~~es~~|Output Common Mode Voltage<br>~~nD ~~<br>~~nn~~<br>~~nD~~|1.125<br> ~~I ~~<br>~~(~~<br>~~I~~|1.25<br> ~~(OO~~<br>~~(~~<br>~~(OO~~|1.375<br>~~I~~<br>~~I~~|V|
|VICM<br>~~es~~<br>~~es~~<br>~~es~~|Input Common Mode Voltage<br>~~nn~~<br>~~nD~~<br>~~nD~~|0.05<br>~~(~~<br>~~I~~<br>~~(~~|1.25<br>~~(~~<br>~~(OO~~<br>~~(~~|2.35<br>~~I~~|V|
|VIDIFF<br>~~es~~<br>~~es~~|Input Differential Voltage<br>~~nD ~~<br>~~nD~~|100<br> ~~I ~~<br>~~(~~|350<br> ~~(OO~~<br>~~(~~|~~I~~|mV|
_Notes:_
_1. IOL/IOH defined by VODIFF/(Resistor Network)_
_2. Currents are measured at 85°C junction temperature._
_3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
**2-209**
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_Fusion Family of Mixed Signal FPGAs_
_**Table 2-169 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**VREF (typ.) (V)**|
|---|---|---|---|
|1.075|1.325|Cross point|–|
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
## _**Table 2-170 •**_ **LVDS**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os**
|**Speed Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**Units**|
|---|---|---|---|---|---|
|Std.|0.66|2.10|0.04|1.82|ns|
|–1|0.56|1.79|0.04|1.55|ns|
|–2|0.49|1.57|0.03|1.36|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
## _**BLVDS/M-LVDS**_
Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations can contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by BLVDS and M-LVDS to accommodate the loading. The driver requires series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. These configurations can be implemented using TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-135. The input and output buffer delays are available in the LVDS section in Table 2-171.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case industrial operating conditions at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5").
**==> picture [437 x 103] intentionally omitted <==**
**----- Start of picture text -----**<br>
Receiver Transceiver Driver Receiver Transceiver<br>EN EN D EN EN EN BIBUF_LVDS<br>R T R T<br>+ - + - + - + - + -<br>x x<br>RS RS RS RS RS RS RS RS RS RS<br>Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub ...<br>Z0 Z0 Z0 Z0 Z0 Z0<br>RT Z0 Z0 Z0 Z0 Z0 Z0 RT<br>**----- End of picture text -----**<br>
_**Figure 2-135 •**_ **BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers**
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_Device Architecture_
## _**LVPECL**_
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-136. The building blocks of the LVPECL transmitter–receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different.
**==> picture [458 x 92] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bourns Part Number: CAT16-PC4F12<br>FPGA FPGA<br>OUTBUF_LVPECL P P<br>100 ZO = 50 <br>+ INBUF_LVPECL<br>187 W 100 <br>–<br>oe —map<br>o> xh 100 : ZO = 50 x]<br>N N<br>**----- End of picture text -----**<br>
_**Figure 2-136 •**_ **LVPECL Circuit Diagram and Board-Level Implementation**
_**Table 2-171 •**_ **Minimum and Maximum DC Input and Output Levels**
|~~ee~~|~~ns~~||||||||
|---|---|---|---|---|---|---|---|---|
|**DC Parameter**<br>~~ee~~|**Description**<br>~~ns~~|**Min.**<br>**Max.**||**Min.**<br>**Max.**||**Min.**<br>**Max.**||**Units**|
|VCCI<br>~~ee~~<br>~~a~~<br>~~ee~~|Supply Voltage<br>~~ns~~<br>~~nn~~<br>~~nD~~|3.0<br>~~nn~~<br>~~IDI~~||3.3<br>~~I(~~||3.6<br>~~(~~||V|
|VOL<br>~~ee~~<br>~~a~~|Output Low Voltage<br>~~nD~~<br>~~ns~~|0.96<br>~~ID~~<br>~~IID~~|1.27<br>~~I~~<br>~~I~~|1.06<br>~~I~~<br>~~I (D~~|1.43<br>~~(~~<br>~~(D~~|1.30<br>~~(~~<br>~~(~~|1.57<br>~~(~~<br>~~(~~|V|
|VOH<br>~~ee~~<br>~~a~~<br>~~ee~~|Output High Voltage<br>~~nD ~~<br>~~ns~~<br>~~nD~~|1.8<br> ~~ID ~~<br>~~IID~~<br>~~RID~~|2.11<br> ~~I ~~<br>~~I~~<br>~~I~~|1.92<br> ~~I ~~<br>~~I (D~~|2.28<br> ~~(~~<br>~~(D~~|2.13<br>~~(~~<br>~~(~~|2.41<br>~~(~~<br>~~(~~|V|
|VIL, VIH<br>~~a~~<br>~~ee~~<br>~~a~~|Input Low, Input High Voltages<br>~~ns ~~<br>~~nD~~<br>~~ns~~|0<br> ~~IID ~~<br>~~RID~~<br>~~IID~~|3.6<br> ~~I~~<br>~~I~~<br>~~I~~|0<br>~~I (D~~<br>~~I (D~~|3.6<br>~~(D~~<br>~~(D~~|0<br>~~(~~<br>~~(~~|3.6<br>~~(~~<br>~~(~~|V|
|VODIFF<br>~~ee~~<br>~~a~~<br>~~ee~~|Differential Output Voltage<br>~~nD ~~<br>~~ns~~<br>~~nD~~|0.625<br> ~~RID ~~<br>~~IID~~<br>~~RID~~|0.97<br> ~~I~~<br>~~I~~<br>~~I~~|0.625<br>~~I (D~~|0.97<br>~~(D~~|0.625<br>~~(~~|0.97<br>~~(~~|V|
|VOCM<br>~~a~~<br>~~ee~~<br>~~a~~|Output Common Mode Voltage<br>~~ns ~~<br>~~nD~~<br>~~ns~~|1.762<br> ~~IID ~~<br>~~RID~~<br>~~IID~~|1.98<br> ~~I~~<br>~~I~~<br>~~I~~|1.762<br>~~I (D~~<br>~~I (D~~|1.98<br>~~(D~~<br>~~(D~~|1.762<br>~~(~~<br>~~(~~|1.98<br>~~(~~<br>~~(~~|V|
|VICM<br>~~ee~~<br>~~a~~<br>~~ee~~|Input Common Mode Voltage<br>~~nD ~~<br>~~ns~~<br>~~nD PN~~|1.01<br> ~~RID ~~<br>~~IID~~<br>~~PN~~|2.57<br> ~~I~~<br>~~I~~<br>~~I~~|1.01<br>~~I (D~~<br>~~(D~~|2.57<br>~~(D~~<br>~~(D~~|1.01<br>~~(~~<br>~~(~~|2.57<br>~~(~~<br>~~(~~|V|
|VIDIFF<br>~~a~~<br>~~ee~~|Input Differential Voltage<br>~~ns ~~<br>~~nD PN~~|300<br> ~~IID ~~<br>~~PN~~|~~I~~<br>~~I~~|300<br>~~I (D~~<br>~~(D~~|~~(D~~<br>~~(D~~|300<br>~~(~~<br>~~(~~|~~(~~<br>~~(~~|mV|
_**Table 2-172 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
_Note: *Measuring point = Vtrip. See Table 2-90 on page 2-166 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-173 •**_ **LVPECL**
## **Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os**
|**Applicable to Pro I/Os**|**Applicable to Pro I/Os**|||||
|---|---|---|---|---|---|
|**Speed Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**Units**|
|Std.|0.66|2.14|0.04|1.63|ns|
|–1|0.56|1.82|0.04|1.39|ns|
|–2|0.49|1.60|0.03|1.22|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
**2-211**
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## _**I/O Register Specifications**_
_**Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset**_
**==> picture [459 x 342] intentionally omitted <==**
**----- Start of picture text -----**<br>
Preset L<br>X X<br>D<br>DOUT<br>Data_out<br>PRE Y F PRE<br>E Core<br>Data X D Q X Array X D Q X<br>C<br>DFN1E1P1 G DFN1E1P1<br>E X E X<br>Enable X<br>B EOUT<br>H<br>X<br>CLK X I<br>A X<br>J PRE<br>X D Q<br>K DFN1E1P1<br>Data Input I/O Register with: X E<br> Active High Enable<br> Active High Preset<br> Positive Edge Triggered<br>Data Output Register and<br>Enable Output Register with:<br>Active High Enable<br>Active High Preset<br>Postive Edge Triggered<br>CLKBUF INBUF INBUF<br>CLK Enable D_Enable<br>Pad Out<br>INBUF<br>INBUF TRIBUF<br>INBUF<br>CLKBUF<br>**----- End of picture text -----**<br>
_**Figure 2-137 •**_ **Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset**
**Revision 8**
**2-212**
_Device Architecture_
_**Table 2-174 •**_ **Parameter Definitions and Measuring Nodes**
|**Parameter**<br>**Name**<br>~~a~~|**Parameter Definition**|**Measuring Nodes**<br>**(from, to)***|
|---|---|---|
|tOCLKQ<br>~~a~~|Clock-to-Q of the Output Data Register|H, DOUT|
|tOSUD<br>~~aI~~<br>~~ee~~|Data Setup Time for the Output Data Register|F, H|
|tOHD<br>~~ee~~<br>~~es~~|Data Hold Time for the Output Data Register|F, H|
|tOSUE<br>~~ee~~<br>~~es~~|Enable Setup Time for the Output Data Register|G, H|
|tOHE<br>~~es~~<br>~~a~~|Enable Hold Time for the Output Data Register|G, H|
|tOPRE2Q<br>~~a~~|Asynchronous Preset-to-Q of the Output Data Register|L,DOUT|
|tOREMPRE<br>~~a~~|Asynchronous Preset Removal Time for the Output Data Register|L, H|
|tORECPRE<br>~~I~~<br>~~ee~~|Asynchronous Preset Recovery Time for the Output Data Register|L, H|
|tOECLKQ<br>~~ee~~<br>~~es~~|Clock-to-Q of the Output Enable Register|H, EOUT|
|tOESUD<br>~~ee~~<br>~~es~~|Data Setup Time for the Output Enable Register|J, H|
|tOEHD<br>~~es~~<br>~~a~~|Data Hold Time for the Output Enable Register|J, H|
|tOESUE<br>~~a~~|Enable Setup Time for the Output Enable Register|K, H|
|tOEHE<br>~~a~~<br>~~ee~~|Enable Hold Time for the Output Enable Register|K, H|
|tOEPRE2Q<br>~~ee~~|Asynchronous Preset-to-Q of the Output Enable Register|I, EOUT|
|tOEREMPRE<br>~~ee~~<br>~~a~~<br>~~es~~|Asynchronous Preset Removal Time for the Output Enable Register|I, H|
|tOERECPRE<br>~~es~~|Asynchronous Preset Recovery Time for the Output Enable Register|I, H|
|tICLKQ<br>~~es~~<br>~~a~~|Clock-to-Q of the Input Data Register|A, E|
|tISUD<br>~~a~~|Data Setup Time for the Input Data Register|C, A|
|tIHD<br>~~a~~<br>~~a~~|Data Hold Time for the Input Data Register|C, A|
|tISUE<br>~~a~~|Enable Setup Time for the Input Data Register|B, A|
|tIHE<br>~~aa~~<br>~~es~~|Enable Hold Time for the Input Data Register|B, A|
|tIPRE2Q<br>~~es~~|Asynchronous Preset-to-Q of the Input Data Register|D, E|
|tIREMPRE<br>~~es~~<br>~~a~~|Asynchronous Preset Removal Time for the Input Data Register|D, A|
|tIRECPRE<br>~~a~~|Asynchronous Preset Recovery Time for the Input Data Register|D, A|
_Note: *See Figure 2-137 on page 2-212 for more information._
**2-213**
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## _**Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear**_
**==> picture [444 x 320] intentionally omitted <==**
**----- Start of picture text -----**<br>
DOUT<br>Y Core Data_out FF<br>Data D Q Ar ray D Q<br>CC DFN1E1C1 EE DFN1E1C1<br>- GG<br>E E EOUT<br>Enable<br>BB CLR CLR<br>LL<br>HH<br>CLK<br>AA<br>JJ<br>CLR D Q<br>DD<br>DFN1E1C1<br>KK<br>E<br>Data Input I/O Register with CLR<br> Active High Enable<br> Active High Clear He<br> Positive Edge Triggered Data Output Register and<br>Enable Output Register with<br> Active High Enable<br> Active High Clear<br>mA<br> Positive Edge Triggered<br>INBUF INBUF CLKBUF<br>Enable D_Enable CLK<br>Pad Out<br>INBUF TRIBUF<br>INBUF<br>CLKBUF<br>INBUF<br>**----- End of picture text -----**<br>
_**Figure 2-138 •**_ **Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear**
**Revision 8**
**2-214**
_Device Architecture_
_**Table 2-175 •**_ **Parameter Definitions and Measuring Nodes**
|**Parameter Name**|**Parameter Definition**|**Measuring Nodes**<br>**(from, to)***|
|---|---|---|
|tOCLKQ<br>~~De~~|Clock-to-Q of the Output Data Register<br>~~De~~|HH, DOUT<br>~~De~~|
|tOSUD<br>~~De~~|Data Setup Time for the Output Data Register<br>~~De~~|FF, HH<br>~~De~~|
|tOHD<br>~~a~~|Data Hold Time for the Output Data Register|FF, HH|
|tOSUE<br>~~a~~|Enable Setup Time for the Output Data Register|GG, HH|
|tOHE<br>~~a~~|Enable Hold Time for the Output Data Register|GG, HH|
|tOCLR2Q<br>~~a~~|Asynchronous Clear-to-Q of the Output Data Register|LL, DOUT|
|tOREMCLR<br>~~a ee~~|Asynchronous Clear Removal Time for the Output Data Register<br>~~ee~~|LL, HH<br>~~ee~~|
|tORECCLR<br>~~De~~|Asynchronous Clear Recovery Time for the Output Data Register<br>~~De~~|LL, HH<br>~~De~~|
|tOECLKQ<br>~~a~~|Clock-to-Q of the Output Enable Register|HH, EOUT|
|tOESUD<br>~~a~~|Data Setup Time for the Output Enable Register|JJ, HH|
|tOEHD<br>~~a~~|Data Hold Time for the Output Enable Register|JJ, HH|
|tOESUE<br>~~a~~|Enable Setup Time for the Output Enable Register|KK, HH|
|tOEHE<br>~~a~~<br>~~VR~~|Enable Hold Time for the Output Enable Register<br>~~ee~~|KK, HH<br>~~ee~~|
|tOECLR2Q<br><br>~~VR~~|Asynchronous Clear-to-Q of the Output Enable Register<br>~~ee~~|II, EOUT<br>~~ee~~|
|tOEREMCLR<br><br>~~VRa~~|Asynchronous Clear Removal Time for the Output Enable Register<br>~~ee~~|II, HH<br>~~ee~~|
|tOERECCLR<br>~~a~~|Asynchronous Clear Recovery Time for the Output Enable Register|II, HH|
|tICLKQ<br>~~a~~|Clock-to-Q of the Input Data Register|AA, EE|
|tISUD<br>~~a~~|Data Setup Time for the Input Data Register|CC, AA|
|tIHD<br>~~a~~|Data Hold Time for the Input Data Register<br>~~ee~~|CC, AA<br>~~ee~~|
|tISUE<br>~~VD~~|Enable Setup Time for the Input Data Register<br>~~VD~~|BB, AA<br>~~VD~~|
|tIHE<br>~~a~~|Enable Hold Time for the Input Data Register|BB, AA|
|tICLR2Q<br>~~a~~|Asynchronous Clear-to-Q of the Input Data Register|DD, EE|
|tIREMCLR<br>~~a~~|Asynchronous Clear Removal Time for the Input Data Register|DD, AA|
|tIRECCLR<br>~~a~~|Asynchronous Clear Recovery Time for the Input Data Register|DD, AA|
_Note: *See Figure 2-138 on page 2-214 for more information._
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_**Input Register**_
|tICKMPWH<br>tICKMPWL|
|---|
|CLK<br>Data<br>50%<br>tISUD<br>tIHD<br>50%<br>50%<br>1<br>0<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>~~[ES~~<br>a<br>~~a~~|
|Enable<br>50%<br>tIHE<br>tIRECPRE<br>tIREMPRE<br>tIWPRE|
|Preset<br>tISUE<br>tIRECCLR<br>tIREMCLR<br>tIWCLR<br>50%<br>50%<br>50%|
|50%<br>Clear<br>50%<br>50%|
|Out_1<br>tIPRE2Q<br>tICLR2Q<br>50%<br>50%<br>50%|
|tICLKQ|
|**_Figure 2-139 •_Input Register Timing Diagram**|
|**_Timing Characteristics_**|
|**_Table 2-176 •_Input Data Register Propagation Delays**|
|**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**|
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std.**<br>**Units**<br>~~a~~|
|tICLKQ<br>Clock-to-Q of the Input Data Register<br>0.24<br>0.27<br>0.32<br>ns<br>tISUD<br>Data Setup Time for the Input Data Register<br>0.26<br>0.30<br>0.35<br>ns<br>~~a~~|
|tIHD<br>Data Hold Time for the Input Data Register<br>0.00<br>0.00<br>0.00<br>ns<br>tISUE<br>Enable Setup Time for the Input Data Register<br>0.37<br>0.42<br>0.50<br>ns<br>~~a~~|
|tIHE<br>Enable Hold Time for the Input Data Register<br>0.00<br>0.00<br>0.00<br>ns<br>~~a~~<br>~~eG~~|
|tICLR2Q<br>Asynchronous Clear-to-Q of the Input Data Register<br>0.45<br>0.52<br>0.61<br>ns<br>~~a ee~~|
|tIPRE2Q<br>Asynchronous Preset-to-Q of the Input Data Register<br>0.45<br>0.52<br>0.61<br>ns<br>tIREMCLR<br>Asynchronous Clear Removal Time for the Input Data Register<br>0.00<br>0.00<br>0.00<br>ns<br>~~a~~|
|tIRECCLR<br>Asynchronous Clear Recovery Time for the Input Data Register<br>0.22<br>0.25<br>0.30<br>ns<br>tIREMPRE<br>Asynchronous Preset Removal Time for the Input Data Register<br>0.00<br>0.00<br>0.00<br>ns<br>~~a~~|
|tIRECPRE<br>Asynchronous Preset Recovery Time for the Input Data Register<br>0.22<br>0.25<br>0.30<br>ns<br>tIWCLR<br>Asynchronous Clear Minimum Pulse Width for the Input Data Register<br>0.22<br>0.25<br>0.30<br>ns<br>~~a~~|
|tIWPRE<br>Asynchronous Preset Minimum Pulse Width for the Input Data Register<br>0.22<br>0.25<br>0.30<br>ns<br>tICKMPWH<br>Clock Minimum Pulse Width High for the Input Data Register<br>0.36<br>0.41<br>0.48<br>ns<br>tICKMPWL<br>Clock Minimum Pulse Width Low for the Input Data Register<br>0.32<br>0.37<br>0.43<br>ns<br>~~re~~|
|_Note:_<br>_For the derating values at specific junction temperature and voltage supply levels, refer toTable 3-7 on_|
|_page 3-9._|
_**Figure 2-139 •**_ **Input Register Timing Diagram**
_**Table 2-176 •**_ **Input Data Register Propagation Delays**
**Revision 8**
**2-216**
_Device Architecture_
_**Output Register**_
**==> picture [443 x 247] intentionally omitted <==**
**----- Start of picture text -----**<br>
tOCKMPWH tOCKMPWL<br>50% 50% 50% 50% 50% 50% 50%<br>CLK<br>tOSUD tOHD<br>Data_out 1 P 50% 0 50% MU<br>— k E RL K) a<br>Enable 50% tOHE tOWPRE tORECPRE tOREMPRE<br>50% 50% 50%<br>Preset tOSUE<br>tOWCLR tORECCLR tOREMCLR<br>50% 50% 50%<br>Clear<br>tOPRE2Q<br>DOUT 50% 50% tOCLR2Q 50%<br>tOCLKQ<br>**----- End of picture text -----**<br>
_**Figure 2-140 •**_ **Output Register Timing Diagram**
## _**Timing Characteristics**_
_**Table 2-177 •**_ **Output Data Register Propagation Delays**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Parameter**<br>~~es~~<br>~~es~~|**Description**<br>~~nN~~|**–2**<br>~~nN~~<br>~~I~~|**–1**<br>~~nN~~<br>~~I~~|**Std.**<br>~~nN~~<br>~~I~~|**Units**<br>~~nN~~|
|---|---|---|---|---|---|
|tOCLKQ<br>~~es~~<br>~~a nN~~<br>~~es~~|Clock-to-Q of the Output Data Register<br>~~nN~~<br>~~nN~~|0.59<br>~~nN~~<br>~~nN~~<br>~~I~~|0.67<br>~~nN~~<br>~~nN~~<br>~~I~~|0.79<br>~~nN~~<br>~~nN~~<br>~~I~~|ns<br>~~nN~~<br>~~nN~~|
|tOSUD<br>~~es~~<br>~~es~~|Data Setup Time for the Output Data Register|0.31<br>~~I~~<br>~~I~~|0.36<br>~~I~~<br>~~I~~|0.42<br>~~I~~<br>~~I~~|ns|
|tOHD<br>~~es~~<br>~~a nN~~<br>~~es~~|Data Hold Time for the Output Data Register<br>~~nN~~|0.00<br>~~I ~~<br>~~nN~~<br>~~I~~|0.00<br> ~~I ~~<br>~~nN~~<br>~~I~~|0.00<br> ~~I~~<br>~~nN~~<br>~~I~~|ns<br>~~nN~~|
|tOSUE<br>~~es~~<br>~~es~~|Enable Setup Time for the Output Data Register|0.44<br>~~I~~<br>~~I~~|0.50<br>~~I~~<br>~~I~~|0.59<br>~~I~~<br>~~I~~|ns|
|tOHE<br>~~es~~<br>~~a nN~~<br>~~es~~|Enable Hold Time for the Output Data Register<br>~~nN~~|0.00<br>~~I ~~<br>~~nN~~<br>~~I~~|0.00<br> ~~I ~~<br>~~nN~~<br>~~I~~|0.00<br> ~~I~~<br>~~nN~~<br>~~I~~|ns<br>~~nN~~|
|tOCLR2Q<br>~~es~~<br>~~es~~|Asynchronous Clear-to-Q of the Output Data Register|0.80<br>~~I~~<br>~~I~~|0.91<br>~~I~~<br>~~I~~|1.07<br>~~I~~<br>~~I~~|ns|
|tOPRE2Q<br>~~es~~<br>~~a nN~~<br>~~es~~|Asynchronous Preset-to-Q of the Output Data Register<br>~~nN~~|0.80<br>~~I ~~<br>~~nN~~<br>~~I~~|0.91<br> ~~I ~~<br>~~nN~~<br>~~I~~|1.07<br> ~~I~~<br>~~nN~~<br>~~I~~|ns<br>~~nN~~|
|tOREMCLR<br>~~es~~<br>~~es~~|Asynchronous Clear Removal Time for the Output Data Register|0.00<br>~~I~~<br>~~I~~|0.00<br>~~I~~<br>~~I~~|0.00<br>~~I~~<br>~~I~~|ns|
|tORECCLR<br>~~es~~<br>~~a nN~~<br>~~es~~|Asynchronous Clear Recovery Time for the Output Data Register<br>~~nN~~|0.22<br>~~I ~~<br>~~nN~~<br>~~I~~|0.25<br> ~~I ~~<br>~~nN~~<br>~~I~~|0.30<br> ~~I~~<br>~~nN~~<br>~~I~~|ns<br>~~nN~~|
|tOREMPRE<br>~~es~~<br>~~es~~|Asynchronous Preset Removal Time for the Output Data Register|0.00<br>~~I~~<br>~~I~~|0.00<br>~~I~~<br>~~I~~|0.00<br>~~I~~<br>~~I~~|ns|
|tORECPRE<br>~~es~~<br>~~a nN~~<br>~~es~~|Asynchronous Preset Recovery Time for the Output Data Register<br>~~nN~~|0.22<br>~~I ~~<br>~~nN~~<br>~~I~~|0.25<br> ~~I ~~<br>~~nN~~<br>~~I~~|0.30<br> ~~I~~<br>~~nN~~<br>~~I~~|ns<br>~~nN~~|
|tOWCLR<br>~~es~~<br>~~a~~|Asynchronous Clear Minimum Pulse Width for the Output Data Register|0.22<br>~~I~~<br>~~ee~~|0.25<br>~~I~~|0.30<br>~~I~~<br>~~ee~~|ns<br>~~ee~~|
|tOWPRE<br>~~es~~<br>~~a~~<br>~~a~~|Asynchronous Preset Minimum Pulse Width for the Output Data<br>Register<br>~~ee~~|0.22<br>~~I ~~<br>~~ee~~<br>~~ee~~|0.25<br> ~~I ~~<br>~~ee~~|0.30<br> ~~I~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|tOCKMPWH<br>~~a~~|Clock Minimum Pulse Width High for the Output Data Register|0.36<br>~~ee~~|0.41<br>~~I~~|0.48<br>~~ee~~|ns<br>~~ee~~|
|tOCKMPWL<br>~~a GO~~|Clock Minimum Pulse Width Low for the Output Data Register<br>~~GO~~|0.32<br>~~GO~~|0.37<br>~~GO~~<br>~~I~~|0.43<br>~~GO~~|ns<br>~~GO~~|
**2-217**
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_**Output Enable Register**_
|tOECKMPWH tOECKMPWL|
|---|
|50%<br>Preset<br>Clear<br>EOUT<br>CLK<br>D_Enable<br>Enable<br>tOESUE<br>50%<br>50%<br>tOESUDtOEHD<br>50%<br>50%<br>tOECLKQ<br>1<br>0<br>tOEHE<br>tOERECPRE<br>tOEREMPRE<br>tOERECCLR<br>tOEREMCLR<br>tOEWCLR<br>tOEWPRE<br>tOEPRE2Q<br>tOECLR2Q<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>~~ee~~<br>SH q~~t|~~<br>7<br>\<br>~~a~~|
||
|**_Figure 2-141 •_Output Enable Register Timing Diagram**|
|**_Timing Characteristics_**|
|**_Table 2-178 •_Output Enable Register Propagation Delays**|
|**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**|
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std.**<br>**Units**<br>tOECLKQ<br>Clock-to-Q of the Output Enable Register<br>0.44<br>0.51<br>0.59<br>ns<br>tOESUD<br>Data Setup Time for the Output Enable Register<br>0.31<br>0.36<br>0.42<br>ns<br>~~esI~~<br>~~(~~<br>~~————————————————~~|
|tOEHD<br>Data Hold Time for the Output Enable Register<br>0.00<br>0.00<br>0.00<br>ns<br>tOESUE<br>Enable Setup Time for the Output Enable Register<br>0.44<br>0.50<br>0.58<br>ns<br>~~————————————————~~|
|tOEHE<br>Enable Hold Time for the Output Enable Register<br>0.00<br>0.00<br>0.00<br>ns<br>tOECLR2Q<br>Asynchronous Clear-to-Q of the Output Enable Register<br>0.67<br>0.76<br>0.89<br>ns<br>~~————————————————~~|
|tOEPRE2Q<br>Asynchronous Preset-to-Q of the Output Enable Register<br>0.67<br>0.76<br>0.89<br>ns<br>tOEREMCLR<br>Asynchronous Clear Removal Time for the Output Enable Register<br>0.00<br>0.00<br>0.00<br>ns<br>~~————————————————~~|
|tOERECCLR<br>Asynchronous Clear Recovery Time for the Output Enable Register<br>0.22<br>0.25<br>0.30<br>ns<br>tOEREMPRE<br>Asynchronous Preset Removal Time for the Output Enable Register<br>0.00<br>0.00<br>0.00<br>ns<br>tOERECPRE<br>Asynchronous Preset Recovery Time for the Output Enable Register<br>0.22<br>0.25<br>0.30<br>ns<br>tOEWCLR<br>Asynchronous Clear Minimum Pulse Width for the Output Enable<br>Register<br>0.22<br>0.25<br>0.30<br>ns<br>tOEWPRE<br>Asynchronous Preset Minimum Pulse Width for the Output Enable<br>Register<br>0.22<br>0.25<br>0.30<br>ns<br>tOECKMPWH<br>Clock Minimum Pulse Width High for the Output Enable Register<br>0.36<br>0.41<br>0.48<br>ns<br>tOECKMPWL<br>Clock Minimum Pulse Width Low for the Output Enable Register<br>0.32<br>0.37<br>0.43<br>ns<br>~~———————————————~~<br>~~a ee~~<br>~~e~~~~**e**~~<br>~~a ee~~<br>~~ee~~<br>~~e~~<br>~~———————————~~|
_**Figure 2-141 •**_ **Output Enable Register Timing Diagram**
_**Table 2-178 •**_ **Output Enable Register Propagation Delays**
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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## _**DDR Module Specifications**_
## _**Input DDR Module**_
**==> picture [294 x 234] intentionally omitted <==**
**----- Start of picture text -----**<br>
Input DDR<br>A<br>D<br>Data Out_QF<br>(to core)<br>INBUF<br>FF1<br>B E<br>Out_QR<br>CLK<br>(to core)<br>CLKBUF<br>FF2<br>C<br>CL R<br>INBUF DDR_IN<br>**----- End of picture text -----**<br>
_**Figure 2-142 •**_ **Input DDR Timing Model**
## _**Table 2-179 •**_ **Parameter Definitions**
|**Parameter Name**|**Parameter Definition**|**Measuring Nodes (from, to)**|
|---|---|---|
|tDDRICLKQ1|Clock-to-Out Out_QR|B, D|
|tDDRICLKQ2|Clock-to-Out Out_QF|B, E|
|tDDRISUD|Data Setup Time of DDR Input|A, B|
|tDDRIHD|Data Hold Time of DDR Input|A, B|
|tDDRICLR2Q1|Clear-to-Out Out_QR|C, D|
|tDDRICLR2Q2|Clear-to-Out Out_QF|C, E|
|tDDRIREMCLR|Clear Removal|C, B|
|tDDRIRECCLR|Clear Recovery|C, B|
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**==> picture [438 x 173] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>tDDRISUD tDDRIHD<br>Data 1 2 3 4 5 6 7 8 9<br>tDDRIRECCLR<br>CLR tDDRIREMCLR<br>tDDRICLKQ1<br>tDDRICLR2Q1<br>Out_QF 2 4 6<br>tee pee<br>tDDRICLR2Q2 tDDRICLKQ2<br>Out_QR 3 5 7<br>XXX) < xKixD<br>**----- End of picture text -----**<br>
_**Figure 2-143 •**_ **Input DDR Timing Diagram**
## _**Timing Characteristics**_
_**Table 2-180 •**_ **Input DDR Propagation Delays**
|~~a~~||~~ee Ge~~<br>|~~Ge~~<br>|||
|---|---|---|---|---|---|
|**Parameter**<br>~~a es~~<br>~~a~~<br>~~a~~|**Description**<br>~~es~~<br><br>|**–2**<br>~~es~~<br>~~ee Ge~~<br><br>~~ee es~~<br>|**–1**<br>~~es~~<br>~~Ge~~<br><br>~~es~~<br>|**Std.**<br>~~es~~<br><br>~~ee~~<br>|**Units**<br>~~es~~<br><br>|
|tDDRICLKQ1<br>~~a ~~<br>~~a~~<br>~~a~~|Clock-to-Out Out_QR for Input DDR<br> ~~es~~<br><br>|0.39<br>~~ee Ge~~<br>~~es~~<br>~~ee es~~<br><br>~~ee~~<br>|0.44<br>~~Ge~~<br>~~es~~<br>~~es~~<br><br>~~ee~~<br>|0.52<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tDDRICLKQ2<br>~~a ~~<br>~~a~~<br>~~a~~|Clock-to-Out Out_QF for Input DDR<br> ~~es~~<br><br>|0.27<br>~~ee es~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.31<br>~~es ~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.37<br> ~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tDDRISUD<br>~~a ~~<br>~~a~~<br>~~a~~|Data Setup for Input DDR<br> ~~es~~<br><br>|0.28<br>~~ee ~~<br>~~es~~<br>~~ee~~<br><br>~~ee ee~~<br>|0.32<br> ~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.38<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>|ns<br>~~es~~<br><br>|
|tDDRIHD<br>~~a ~~<br>~~a~~<br>~~a~~|Data Hold for Input DDR<br> ~~es~~<br><br>|0.00<br>~~ee ~~<br>~~es~~<br>~~ee ee~~<br><br>~~ee~~<br>|0.00<br> ~~ee ~~<br>~~es~~<br>~~ee~~<br><br>~~es~~<br>|0.00<br> ~~ee~~<br>~~es~~<br><br>~~es~~<br>|ns<br>~~es~~<br><br>|
|tDDRICLR2Q1<br>~~a ~~<br>~~a~~<br>~~a~~|Asynchronous Clear-to-Out Out_QR for Input DDR<br> ~~es~~<br><br>|0.57<br>~~ee ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee Ge~~<br>|0.65<br>~~ee~~<br>~~es~~<br>~~es~~<br><br>~~Ge~~<br>|0.76<br>~~es~~<br>~~es~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tDDRICLR2Q2<br>~~a~~<br>~~a~~<br>~~a~~|Asynchronous Clear-to-Out Out_QF for Input DDR<br>~~a~~<br><br>|0.46<br>~~ee ~~<br>~~a~~<br>~~ee Ge~~<br><br>~~ee es~~<br>|0.53<br> ~~es ~~<br>~~a~~<br>~~Ge~~<br><br>~~es~~<br>|0.62<br> ~~es~~<br>~~a~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~a~~<br><br>|
|tDDRIREMCLR<br>~~a ~~<br>~~a~~<br>~~a~~|Asynchronous Clear Removal Time for Input DDR<br> ~~es~~<br><br>|0.00<br>~~ee Ge~~<br>~~es~~<br>~~ee es~~<br><br>~~ee~~<br>|0.00<br>~~Ge~~<br>~~es~~<br>~~es~~<br><br>~~ee~~<br>|0.00<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tDDRIRECCLR<br>~~a ~~<br>~~a~~<br>~~a~~|Asynchronous Clear Recovery Time for Input DDR<br> ~~es~~<br><br>|0.22<br>~~ee es~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.25<br>~~es ~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.30<br> ~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tDDRIWCLR<br>~~a ~~<br>~~a~~<br>~~a~~|Asynchronous Clear Minimum Pulse Width for Input DDR<br> ~~es~~<br><br>|0.22<br>~~ee ~~<br>~~es~~<br>~~ee~~<br><br>~~ee ee~~<br>|0.25<br> ~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.30<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>|ns<br>~~es~~<br><br>|
|tDDRICKMPWH<br>~~a ~~<br>~~a~~<br>~~a~~|Clock Minimum Pulse Width High for Input DDR<br> ~~es~~<br><br>|0.36<br>~~ee ~~<br>~~es~~<br>~~ee ee~~<br><br>~~ee~~<br>|0.41<br> ~~ee ~~<br>~~es~~<br>~~ee~~<br><br>~~es~~<br>|0.48<br> ~~ee~~<br>~~es~~<br><br>~~es~~<br>|ns<br>~~es~~<br><br>|
|tDDRICKMPWL<br>~~a ~~<br>~~a~~|Clock Minimum Pulse Width Low for Input DDR<br> ~~es~~<br>|0.32<br>~~ee ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~|0.37<br>~~ee~~<br>~~es~~<br>~~es~~<br><br>~~Ge~~|0.43<br>~~es~~<br>~~es~~<br><br>~~es~~|ns<br>~~es~~<br>|
|FDDRIMAX<br>~~a~~|Maximum Frequency for Input DDR<br>~~es~~|1404<br>~~ee ~~<br>~~es~~<br>~~ee~~|1232<br> ~~es ~~<br>~~es~~<br>~~Ge~~|1048<br> ~~es~~<br>~~es~~<br>~~es~~|MHz<br>~~es~~|
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## _**Output DDR**_
**==> picture [353 x 218] intentionally omitted <==**
**----- Start of picture text -----**<br>
A<br>Data_F<br>(from core)<br>FF1<br>Out<br>B<br>CLK 0<br>CLKBUF E<br>C<br>OUTBUF<br>Data_R D 1<br>(from core)<br>FF2<br>B<br>CLR<br>INBUF<br>C<br>DDR_OUT<br>**----- End of picture text -----**<br>
_**Figure 2-144 •**_ **Output DDR Timing Model**
_**Table 2-181 •**_ **Parameter Definitions**
|**Parameter Name**|**Parameter Definition**|**Measuring Nodes (From, To)**|
|---|---|---|
|tDDROCLKQ|Clock-to-Out|B, E|
|tDDROCLR2Q|Asynchronous Clear-to-Out|C, E|
|tDDROREMCLR|Clear Removal|C, B|
|tDDRORECCLR|Clear Recovery|C, B|
|tDDROSUD1|Data Setup Data_F|A, B|
|tDDROSUD2|Data Setup Data_R|D, B|
|tDDROHD1|Data Hold Data_F|A, B|
|tDDROHD2|Data Hold Data_R|D, B|
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**==> picture [447 x 179] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK<br>tDDROSUD2 tDDROHD2<br>Data_F 1 2 3 4 5<br>tDDROSUD1 tDDROHD1<br>Data_R 6 7 8 9 10 11<br>C GeeGe, t G DDRORECCLR e<br>CLR tDDROREMCLR<br>w tDDROCLR2Q oo tDDROCLKQ ;<br>Out 7 2 8 3 9 4 10<br>XX) xX xX xX xX _xX_ xX)<br>**----- End of picture text -----**<br>
_**Figure 2-145 •**_ **Output DDR Timing Diagram**
_**Timing Characteristics**_
_**Table 2-182 •**_ **Output DDR Propagation Delays**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|~~ee~~||||||
|---|---|---|---|---|---|
|**Parameter**<br>~~ee~~<br>~~ee~~|**Description**|**–2**|**–1**|**Std.**|**Units**|
|tDDROCLKQ<br>~~ee~~<br>~~ee~~<br>~~ee~~|Clock-to-Out of DDR for Output DDR|0.70|0.80|0.94|ns|
|tDDROSUD1<br>~~ee~~<br>~~ee~~<br>~~ee~~|Data_F Data Setup for Output DDR|0.38|0.43|0.51|ns|
|tDDROSUD2<br>~~ee~~<br>~~ee~~<br>~~ee~~|Data_R Data Setup for Output DDR|0.38|0.43|0.51|ns|
|tDDROHD1<br>~~ee~~<br>~~ee~~|Data_F Data Hold for Output DDR|0.00|0.00|0.00|ns|
|tDDROHD2<br>~~ee~~<br>~~a~~<br>~~ee~~|Data_R Data Hold for Output DDR|0.00|0.00|0.00|ns|
|tDDROCLR2Q<br>~~ee~~<br>~~ee~~|Asynchronous Clear-to-Out for Output DDR|0.80|0.91|1.07|ns|
|tDDROREMCLR<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Clear Removal Time for Output DDR|0.00|0.00|0.00|ns|
|tDDRORECCLR<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Clear Recovery Time for Output DDR|0.22|0.25|0.30|ns|
|tDDROWCLR1<br>~~ee~~<br>~~ee~~|Asynchronous Clear Minimum Pulse Width for Output DDR|0.22|0.25|0.30|ns|
|tDDROCKMPWH<br>~~ee~~<br>~~a~~|Clock Minimum Pulse Width High for the Output DDR|0.36|0.41|0.48|ns|
|tDDROCKMPWL<br>~~a~~|Clock Minimum Pulse Width Low for the Output DDR|0.32|0.37|0.43|ns|
|FDDOMAX<br>~~a~~|Maximum Frequency for the Output DDR|1404|1232|1048|MHz|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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## **Pin Descriptions**
## **Supply Pins**
## **GND Ground**
Ground supply voltage to the core, I/O outputs, and I/O logic.
## **GNDQ Ground (quiet)**
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ needs to always be connected on the board to GND. Note: In FG256, FG484, and FG676 packages, GNDQ and GND pins are connected within the package and are labeled as GND pins in the respective package pin assignment tables.
## **ADCGNDREF Analog Reference Ground**
Analog ground reference used by the ADC. This pad should be connected to a quiet analog ground.
## **GNDA Ground (analog)**
Quiet ground supply voltage to the Analog Block of Fusion devices. The use of a separate analog ground helps isolate the analog functionality of the Fusion device from any digital switching noise. A 0.2 V maximum differential voltage between GND and GNDA/GNDQ should apply to system implementation.
## **GNDAQ Ground (analog quiet)**
Quiet ground supply voltage to the analog I/O of Fusion devices. The use of a separate analog ground helps isolate the analog functionality of the Fusion device from any digital switching noise. A 0.2 V maximum differential voltage between GND and GNDA/GNDQ should apply to system implementation. Note: In FG256, FG484, and FG676 packages, GNDAQ and GNDA pins are connected within the package and are labeled as GNDA pins in the respective package pin assignment tables.
## **GNDNVM Flash Memory Ground**
Ground supply used by the Fusion device's flash memory block module(s).
## **GNDOSC Oscillator Ground**
Ground supply for both integrated RC oscillator and crystal oscillator circuit.
**VCC15A Analog Power Supply (1.5 V)**
1.5 V clean analog power supply input for use by the 1.5 V portion of the analog circuitry.
**VCC33A Analog Power Supply (3.3 V)**
3.3 V clean analog power supply input for use by the 3.3 V portion of the analog circuitry. **VCC33N Negative 3.3 V Output**
This is the –3.3 V output from the voltage converter. A 2.2 µF capacitor must be connected from this pin to ground.
**VCC33PMP Analog Power Supply (3.3 V)**
3.3 V clean analog power supply input for use by the analog charge pump. To avoid high current draw, VCC33PMP should be powered up simultaneously with or after VCC33A.
## **VCCNVM Flash Memory Block Power Supply (1.5 V)**
1.5 V power supply input used by the Fusion device's flash memory block module(s). To avoid high current draw, VCC should be powered up before or simultaneously with VCCNVM.
## **VCCOSC Oscillator Power Supply (3.3 V)**
Power supply for both integrated RC oscillator and crystal oscillator circuit. The internal 100 MHz oscillator, powered by the VCCOSC pin, is needed for device programming, operation of the VDDN33 pump, and eNVM operation. VCCOSC is off only when VCCA is off. VCCOSC must be powered whenever the Fusion device needs to function.
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## **VCC Core Supply Voltage**
Supply voltage to the FPGA core, nominally 1.5 V. VCC is also required for powering the JTAG state machine, in addition to VJTAG. Even when a Fusion device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the Fusion device.
## **VCCIBx I/O Supply Voltage**
Supply voltage to the bank's I/O output buffers and I/O logic. B _x_ is the I/O bank number. There are either four (AFS090 and AFS250) or five (AFS600 and AFS1500) I/O banks on the Fusion devices plus a dedicated VJTAG bank.
Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND.
## **VCCPLA/B PLL Supply Voltage**
Supply voltage to analog PLL, nominally 1.5 V, where A and B refer to the PLL. AFS090 and AFS250 each have a single PLL. The AFS600 and AFS1500 devices each have two PLLs. Microsemi recommends tying VCCPLX to VCC and using proper filtering circuits to decouple VCC noise from PLL. If unused, VCCPLA/B should be tied to GND.
## **VCOMPLA/B Ground for West and East PLL**
VCOMPLA is the ground of the west PLL (CCC location F) and VCOMPLB is the ground of the east PLL (CCC location C).
## **VJTAG JTAG Supply Voltage**
Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a Fusion device is in a JTAG chain of interconnected boards and it is desired to power down the board containing the Fusion device, this may be done provided both VJTAG and VCC to the Fusion part remain powered; otherwise, JTAG signals will not be able to transition the Fusion device, even in bypass mode.
## **VPUMP Programming Supply Voltage**
Fusion devices support single-voltage ISP programming of the configuration flash and FlashROM. For programming, VPUMP should be in the 3.3 V +/-5% range. During normal device operation, VPUMP can be left floating or can be tied to any voltage between 0 V and 3.6 V.
When the VPUMP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
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## **User-Defined Supply Pins**
## **VREF I/O Voltage Reference**
Reference voltage for I/O minibanks. Both AFS600 and AFS1500 (north bank only) support Microsemi Pro I/O. These I/O banks support voltage reference standard I/O. The VREF pins are configured by the user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated as the voltage reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its minibank.
## **VAREF**
## **Analog Reference Voltage**
The Fusion device can be configured to generate a 2.56 V internal reference voltage that can be used by the ADC. While using the internal reference, the reference voltage is output on the VAREF pin for use as a system reference. If a different reference voltage is required, it can be supplied by an external source and applied to this pin. The valid range of values that can be supplied to the ADC is 1.0 V to 3.3 V. When VAREF is internally generated by the Fusion device, a bypass capacitor must be connected from this pin to ground. The value of the bypass capacitor should be between 3.3 µF and 22 µF, which is based on the needs of the individual designs. The choice of the capacitor value has an impact on the settling time it takes the VAREF signal to reach the required specification of 2.56 V to initiate valid conversions by the ADC. If the lower capacitor value is chosen, the settling time required for VAREF to achieve 2.56 V will be shorter than when selecting the larger capacitor value. The above range of capacitor values supports the accuracy specification of the ADC, which is detailed in the datasheet. Designers choosing the smaller capacitor value will not obtain as much margin in the accuracy as that achieved with a larger capacitor value. Depending on the capacitor value selected in the Analog System Builder, a tool in Libero SoC, an automatic delay circuit will be generated using logic tiles available within the FPGA to ensure that VAREF has achieved the 2.56 V value. Microsemi recommends customers use 10 µF as the value of the bypass capacitor. Designers choosing to use an external VAREF need to ensure that a stable and clean VAREF source is supplied to the VAREF pin before initiating conversions by the ADC. Designers should also make sure that the ADCRESET signal is deasserted before initiating valid conversions.[2]
If the user connects VAREF to external 3.3 V on their board, the internal VAREF driving OpAmp tries to bring the pin down to the nominal 2.56 V until the device is programmed and up/functional. Under this scenario, it is recommended to connect an external 3.3 V supply through a ~1 KOhm resistor to limit current, along with placing a 10-100nF capacitor between VAREF and GNDA.
## **User Pins**
## **I/O User Input/Output**
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. Unused I/O pins are configured as inputs with pull-up resistors.
During programming, I/Os become tristated and weakly pulled up to VCCI. With the VCCI and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os get instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
- Output buffer is disabled (with tristate value of high impedance)
- Input buffer is disabled (with tristate value of high impedance)
- Weak pull-up is programmed
## **A** _**xy**_
## **Analog Input/Output**
Analog I/O pin, where _x_ is the analog pad type (C = current pad, G = Gate driver pad, T = Temperature pad, V = Voltage pad) and _y_ is the Analog Quad number (0 to 9). There is a minimum 1 M to ground on AV, AC, and AT. This pin can be left floating when it is unused.
> _2. The ADC is functional with an external reference down to 1V, however to meet the performance parameters highlighted in the datasheet refer to the VAREF specification in Table 3-2 on page 3-3._
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## **ATRTN** _**x**_
## **Temperature Monitor Return**
_AT returns_ are the returns for the temperature sensors. The cathode terminal of the external diodes should be connected to these pins. There is one analog return pin for every two Analog Quads. The _x_ in the ATRTN _x_ designator indicates the quad pairing ( _x_ = 0 for AQ1 and AQ2, _x_ = 1 for AQ2 and AQ3, .., _x_ = 4 for AQ8 and AQ9). The signals that drive these pins are called out as ATRETURN _xy_ in the software (where _x_ and _y_ refer to the quads that share the return signal). ATRTN is internally connected to ground. It can be left floating when it is unused. The maximum capacitance allowed across the AT pins is 500 pF.
## **GL Globals**
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as Pro I/Os since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on page 2-22.
Refer to the "User I/O Naming Convention" section on page 2-158 for a description of naming of global pins.
## **JTAG Pins**
Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the Fusion part must be supplied to allow JTAG signals to transition the Fusion device.
Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the VJTAG pin together with the TRST pin could be tied to GND.
## **TCK Test Clock**
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pullup/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND or VJTAG through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 2-183 for more information.
_**Table 2-183 •**_ **Recommended Tie-Off Values for the TCK and TRST Pins**
|**VJTAG**|**Tie-Off Resistance2, 3**|
|---|---|
|VJTAG at 3.3 V|200to 1 k|
|VJTAG at 2.5 V|200to 1 k|
|VJTAG at 1.8 V|500to 1 k|
|VJTAG at 1.5 V|500to 1 k|
_Notes:_
_1. Equivalent parallel resistance if more than one device is on JTAG chain._
_2. The TCK pin can be pulled up/down._
_3. The TRST pin can only be pulled down._
## **TDI**
## **Test Data Input**
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin.
## **TDO**
## **Test Data Output**
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
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## **TMS**
## **Test Mode Select**
The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin.
## **TRST Boundary Scan Reset Pin**
The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pulldown resistor could be included to ensure the TAP is held in reset mode. The resistor values must be chosen from Table 2-183 and must satisfy the parallel resistance value requirement. The values in Table 2-183 correspond to the resistor recommended when a single device is used and to the equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
## **Special Function Pins**
## **NC No Connect**
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
## **DC Don't Connect**
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
## **NCAP Negative Capacitor**
Negative Capacitor is where the negative terminal of the charge pump capacitor is connected. A capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP.
## **PCAP Positive Capacitor**
_Positive Capacitor_ is where the positive terminal of the charge pump capacitor is connected. A capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP.
## **PUB Push Button**
_Push button_ is the connection for the external momentary switch used to turn on the 1.5 V voltage regulator and can be floating if not used.
**PTBASE Pass Transistor Base**
_Pass Transistor Base_ is the control signal of the voltage regulator. This pin should be connected to the base of the external pass transistor used with the 1.5 V internal voltage regulator and can be floating if not used.
## **PTEM Pass Transistor Emitter**
_Pass Transistor Emitter_ is the feedback input of the voltage regulator.
This pin should be connected to the emitter of the external pass transistor used with the 1.5 V internal voltage regulator and can be floating if not used.
## **XTAL1 Crystal Oscillator Circuit Input**
Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network, or external clock input. When using an external crystal or ceramic oscillator, external capacitors are also recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value).
If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected. In the case where the Crystal Oscillator block is not used, the XTAL1 pin should be connected to GND and the XTAL2 pin should be left floating.
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## **XTAL2**
## **Crystal Oscillator Circuit Input**
Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network, or external clock input. When using an external crystal or ceramic oscillator, external capacitors are also recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value).
If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected. In the case where the Crystal Oscillator block is not used, the XTAL1 pin should be connected to GND and the XTAL2 pin should be left floating.
## **Security**
Fusion devices have a built-in 128-bit AES decryption core. The decryption core facilitates highly secure, in-system programming of the FPGA core array fabric and the FlashROM. The FlashROM and the FPGA core fabric can be programmed independently from each other, allowing the FlashROM to be updated without the need for change to the FPGA core fabric. The AES master key is stored in on-chip nonvolatile memory (flash). The AES master key can be preloaded into parts in a security-protected programming environment (such as the Microsemi in-house programming center), and then “blank” parts can be shipped to an untrusted programming or manufacturing center for final personalization with an AESencrypted bitstream. Late stage product changes or personalization can be implemented easily and with high level security by simply sending a STAPL file with AES-encrypted data. Highly secure remote field updates over public networks (such as the Internet) are possible by sending and programming a STAPL file with AES-encrypted data. For more information, refer to the _Fusion Security_ application note.
## _**128-Bit AES Decryption**_
The 128-bit AES standard (FIPS-197) block cipher is the National Institute of Standards and Technology (NIST) replacement for DES (Data Encryption Standard FIPS46-2). AES has been designed to protect sensitive government information well into the 21st century. It replaces the aging DES, which NIST adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect sensitive, unclassified information. The 128-bit AES standard has 3.4 × 10[38] possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text using exhaustive techniques. Keys are stored (protected with security) in Fusion devices in nonvolatile flash memory. All programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. All programming verification is performed on-chip, ensuring that the contents of Fusion devices remain as secure as possible.
AES decryption can also be used on the 1,024-bit FlashROM to allow for remote updates of the FlashROM contents. This allows for easy support of subscription model products and protects them with measures designed to provide the highest level of security available. See the application note _Fusion Security_ for more details.
## _**AES for Flash Memory**_
AES decryption can also be used on the flash memory blocks. This provides the best available security during update of the flash memory blocks. During runtime, the encrypted data can be clocked in via the JTAG interface. The data can be passed through the internal AES decryption engine, and the decrypted data can then be stored in the flash memory block.
## **Programming**
Programming can be performed using various programming tools, such as Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Microsemi).
The user can generate STP programming files from the Designer software and can use these files to program a device.
Fusion devices can be programmed in-system. During programming, VCCOSC is needed in order to power the internal 100 MHz oscillator. This oscillator is used as a source for the 20 MHz oscillator that is used to drive the charge pump for programming.
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## _**ISP**_
Fusion devices support IEEE 1532 ISP via JTAG and require a single VPUMP voltage of 3.3 V during programming. In addition, programming via a microcontroller in a target system can be achieved. Refer to the standard or the “In-System Programming (ISP) of Microsemi's Low Power Flash Devices Using FlashPro4/3/3X” chapter of the _Fusion FPGA Fabric User’s Guide_ for more details.
## _**JTAG IEEE 1532**_
## _**Programming with IEEE 1532**_
Fusion devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a Fusion device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping the global IO_EN signal deactivated, which also has the effect of disabling the input buffers. Consequently, the SAMPLE instruction will have no effect while the Fusion device is in this unprogrammed state—different behavior from that of the ProASIC[PLUS] ® device family. This is done because SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be a noninvasive instruction. Refer to the standard or the “In-System Programming (ISP) of Microsemi's Low Power Flash Devices Using FlashPro4/3/3X” chapter of the _Fusion FPGA Fabric User’s Guide_ for more details.
## _**Boundary Scan**_
Fusion devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is composed of the test access port (TAP) controller, test data registers, and instruction register (Figure 2- 146 on page 2-230). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-185 on page 2-230).
Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" section on page 2-226 for pull-up/-down recommendations for TDO and TCK pins. The TAP controller is a 4-bit state machine (16 states) that operates as shown in Figure 2-146 on page 2-230. The 1s and 0s represent the values that must be present on TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state.
_**Table 2-184 •**_ **TRST and TCK Pull-Down Recommendations**
|**VJTAG**|**Tie-Off Resistance***|
|---|---|
|VJTAG at 3.3 V|200to 1 k|
|VJTAG at 2.5 V|200to 1 k|
|VJTAG at 1.8 V|500to 1 k|
|VJTAG at 1.5 V|500to 1 k|
_Note: *Equivalent parallel resistance if more than one device is on JTAG chain._
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain High for five TCK cycles. The TRST pin can also be used to asynchronously place the TAP controller in the TestLogic-Reset state.
Fusion devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin.
The serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are
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connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O.
**==> picture [359 x 300] intentionally omitted <==**
**----- Start of picture text -----**<br>
I/O I/O I/O I/O I/O<br>Test Data<br>7 Registers<br>Bypass Register |<br>TAP Instruction Device<br>Controller Register Logic<br>I/O I/O I/O I/O I/O<br>TDI<br>I/O<br>TCK<br>I/O<br>TMS<br>I/O<br>TRST<br>I/O<br>TDO<br>**----- End of picture text -----**<br>
_**Figure 2-146 •**_ **Boundary Scan Chain in Fusion**
_**Table 2-185 •**_ **Boundary Scan Opcodes**
|**_Table 2-185 •_Boundary Scan Opcodes**||
|---|---|
||**Hex Opcode**|
|EXTEST|00|
|HIGHZ|07|
|USERCODE|0E|
|SAMPLE/PRELOAD|01|
|IDCODE|0F|
|CLAMP|05|
|BYPASS|FF|
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## _**IEEE 1532 Characteristics**_
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/Os" section on page 2-132 for more details.
## _**Timing Characteristics**_
_**Table 2-186 •**_ **JTAG 1532**
**Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|~~es~~||||||
|---|---|---|---|---|---|
|**Parameter**<br>~~es~~|**Description**<br>|**–2**<br>|**–1**<br>|**Std.**<br>|**Units**<br>|
|tDISU<br>~~esa~~|Test Data Input Setup Time<br>~~a~~<br>~~a~~|0.50<br>~~a~~<br>~~a~~|0.57<br>~~a~~<br>~~a~~|0.67<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tDIHD<br>~~a~~|Test Data Input Hold Time<br>~~a~~<br>~~a~~|1.00<br>~~a~~<br>~~a~~|1.13<br>~~a~~<br>~~a~~|1.33<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tTMSSU<br>~~a~~|Test Mode Select Setup Time<br>~~a~~<br>~~a~~|0.50<br>~~a~~<br>~~a~~|0.57<br>~~a~~<br>~~a~~|0.67<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tTMDHD<br>~~a~~<br>~~Vs~~|Test Mode Select Hold Time<br>~~a~~|1.00<br>~~a~~|1.13<br>~~a~~|1.33<br>~~a~~|ns<br>~~a~~|
|tTCK2Q<br>~~Vs~~|Clock to Q (data out)|6.00|6.80|8.00|ns|
|tRSTB2Q<br>~~Vs~~<br>~~a~~|Reset to Q (data out)|20.00|22.67|26.67|ns|
|FTCKMAX<br>~~a~~|TCK Maximum Frequency<br>~~a~~|25.00<br>~~a~~|22.00<br>~~a~~|19.00<br>~~a~~|MHz<br>~~a~~|
|tTRSTREM<br>~~a~~|ResetB Removal Time<br>~~a~~<br>~~a~~|0.00<br>~~a~~<br>~~a~~|0.00<br>~~a~~<br>~~a~~|0.00<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tTRSTREC<br>~~a~~|ResetB Recovery Time<br>~~a~~<br>~~a~~|0.20<br>~~a~~<br>~~a~~|0.23<br>~~a~~<br>~~a~~|0.27<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tTRSTMPW<br>~~a~~|ResetB Minimum Pulse|TBD|TBD|TBD|ns|
_Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9._
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## **3 – DC and Power Characteristics**
## **General Specifications**
## **Operating Conditions**
Stresses beyond those listed in Table 3-1 may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating ranges specified in Table 3-2 on page 3-3.
_**Table 3-1 •**_ **Absolute Maximum Ratings**
|**Symbol**<br>~~a es~~|**Parameter**<br>~~es~~|**Commercial**<br>~~es~~|**Industrial**<br>~~es~~|**Units**<br>~~es~~|
|---|---|---|---|---|
|VCC<br>~~a es~~<br>~~a~~|DC core supply voltage<br>~~es~~<br>~~es~~|–0.3 to 1.65<br>~~es~~|–0.3 to 1.65<br>~~es~~|V<br>~~es~~|
|VJTAG<br>~~a~~|JTAG DC voltage<br>~~es~~|–0.3 to 3.75|–0.3 to 3.75|V|
|VPUMP<br>~~a~~<br>~~a~~|Programming voltage<br>~~es~~|–0.3 to 3.75|–0.3 to 3.75|V|
|VCCPLL<br>~~a~~|Analog power supply (PLL)<br>|–0.3 to 1.65|–0.3 to 1.65|V|
|VCCI<br>~~rr~~|DC I/O output buffer supply voltage<br>~~rr~~|–0.3 to 3.75<br>~~rn~~|–0.3 to 3.75<br>~~rn~~|V<br>~~rn~~|
|VI<br>~~rr~~<br>~~ee~~|I/O input voltage 1<br>~~rr~~<br>~~i~~|–0.3 V to 3.6 V (when I/O hot insertion mode is<br>enabled)<br>–0.3 V to (VCCI + 1 V) or 3.6 V, whichever<br>voltage is lower (when I/O hot-insertion mode is<br>disabled)<br>~~rn~~||V<br>~~rn~~|
|VCC33A<br>~~ee~~|+3.3 V power supply<br>~~i~~|–0.3 to 3.75 2|–0.3 to 3.75 2|V|
|VCC33PMP<br>~~ee~~<br>~~a es~~|+3.3 V power supply<br>~~i~~<br>~~es~~|–0.3 to 3.75 2<br>~~es~~|–0.3 to 3.75 2<br>~~es~~|V<br>~~es~~|
|VAREF<br>~~a es~~<br>~~a~~|Voltage reference for ADC<br>~~es~~<br>~~es~~|–0.3 to 3.75<br>~~es~~|–0.3 to 3.75<br>~~es~~|V<br>~~es~~|
|VCC15A<br>~~a~~|Digital power supply for the analog system<br>~~es~~|–0.3 to 1.65|–0.3 to 1.65|V|
|VCCNVM<br>~~a~~<br>~~a~~|Embedded flash power supply<br>~~es~~|–0.3 to 1.65|–0.3 to 1.65|V|
|VCCOSC<br>~~a a~~|Oscillator power supply<br>~~a~~|–0.3 to 3.75|–0.3 to 3.75|V|
## _Notes:_
_1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4._
_2. Analog data not valid beyond 3.65 V._
_3. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad._
_4. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits refer to Table 3-2 on page 3-3._
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_**Table 3-1 •**_ **Absolute Maximum Ratings (continued)**
|**Symbol**<br>~~a~~|**Parameter**<br>|**Commercial**<br>|**Industrial**<br>|**Units**<br>|
|---|---|---|---|---|
|AV, AC<br>~~Se~~<br>~~__——~~|Unpowered,<br>ADC<br>reset<br>asserted<br>or<br>unconfigured<br>~~Se~~|–11.0 to 12.6<br>~~Se~~|–11.0 to 12.0<br>~~ee~~|V<br>~~ee~~|
||Analog input (+16 V to +2 V prescaler range)<br>~~Se~~|–0.4 to 12.6<br>~~Se~~|–0.4 to 12.0<br>~~ee~~|V<br>~~ee~~|
||Analog input (+1 V to +0.125 V prescaler<br>range)<br>~~Se~~|–0.4 to 3.75<br>~~Se~~|–0.4 to 3.75<br>~~ee~~|V<br>~~ee~~|
||Analog input (–16 V to –2 V prescaler range)<br>~~Se~~<br>~~ee~~<br>~~__——~~|–11.0 to 0.4<br>~~Se ~~<br>~~ee~~<br>~~__——~~|–11.0 to 0.4<br> ~~ee~~<br>~~ee~~<br>~~__——~~|V<br>~~ee~~<br>~~__——~~|
|~~__——~~|Analog input (–1 V to –0.125 V prescaler<br>range)<br>~~ee~~<br>~~__——~~|–3.75 to 0.4<br>~~ee~~<br>~~__——~~|–3.75 to 0.4<br>~~ee~~<br>~~__——~~|V<br>~~__——~~|
||Analog input (direct input to ADC)<br>~~ee~~<br>~~__——~~|–0.4 to 3.75<br>~~ee~~<br>~~__——~~|–0.4 to 3.75<br>~~ee~~<br>~~__——~~|V<br>~~__——~~|
||Digital input<br>~~__——~~<br>~~ee~~|–0.4 to 12.6<br>~~__——~~<br>~~ee~~|–0.4 to 12.0<br>~~__——~~<br>~~ee~~|V<br>~~__——~~|
|AG<br>~~__——~~<br>~~See~~|Unpowered,<br>ADC<br>reset<br>asserted<br>or<br>unconfigured<br>~~__——~~<br>~~ee~~<br>~~See~~|–11.0 to 12.6<br>~~__——~~<br>~~ee~~<br>~~See~~|–11.0 to 12.0<br>~~__——~~<br>~~ee~~<br>~~ee~~|V<br>~~__——~~<br>~~ee~~|
||Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA)<br>~~ee~~<br>~~See~~|–0.4 to 12.6<br>~~ee~~<br>~~See~~|–0.4 to 12.0<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
||Low Current Mode (–1 µA, –3 µA, –10 µA, –30<br>µA)<br>~~See~~|–11.0 to 0.4<br>~~See~~|–11.0 to 0.4<br>~~ee~~|V<br>~~ee~~|
||High Current Mode 3<br>~~See~~<br>~~ee~~|–11.0 to 12.6<br>~~See ~~<br>~~ee~~|–11.0 to 12.0<br> ~~ee~~<br>~~ee~~|V<br>~~ee~~|
|AT|Unpowered,<br>ADC<br>reset<br>asserted<br>or<br>unconfigured<br>~~ee~~|–0.4 to 16.0<br>~~ee~~<br>~~ee~~|–0.4 to 15.0<br>~~ee~~|V|
||Analog input (+16 V, 4 V prescaler range)<br>~~ee~~<br>~~es~~|–0.4 to 16.0<br>~~ee~~<br>~~es~~<br>~~ee~~|–0.4 to 15.0<br>~~ee~~<br>~~es~~|V<br>~~es~~|
||Analog input (direct input to ADC)<br>~~ee~~|–0.4 to 3.75<br>~~ee~~<br>~~ee~~|–0.4 to 3.75<br>~~ee~~|V<br>~~ee~~|
||Digital input<br>~~es~~|–0.4 to 16.0<br>~~es~~|–0.4 to 15.0<br>~~es~~|V<br>~~es~~|
|TSTG<br>4<br>~~a~~|Storage temperature|–65 to +150||°C|
|TJ<br>4<br>~~a~~|Junction temperature|+125||°C|
_Notes:_
_1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4._
_2. Analog data not valid beyond 3.65 V._
_3. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad._
_4. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits refer to Table 3-2 on page 3-3._
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_**Table 3-2 •**_ **Recommended Operating Conditions**[1]
|**Symbol**<br>~~a~~|**Parameter**2<br>~~eG~~|**Parameter**2<br>~~eG~~|**Commercial**<br>~~eG~~|**Industrial**<br>~~eG~~|**Units**<br>~~eG~~|
|---|---|---|---|---|---|
|TJ<br>~~a~~|Junction temperature||0 to +85|–40 to +100|°C|
|VCC<br>~~a~~|1.5 V DC core supply voltage||1.425 to 1.575|1.425 to 1.575|V|
|VJTAG<br>~~a~~<br>~~eee~~|JTAG DC voltage<br>~~Qe~~<br>~~eee~~||1.4 to 3.6<br>~~Qe~~<br>~~eee~~|1.4 to 3.6<br>~~Qe~~<br>~~eee~~|V<br>~~Qe~~<br>~~eee~~|
|VPUMP<br>~~eee~~<br>~~a~~|Programming voltage<br>~~eee~~<br>|Programming mode3<br>~~eee~~|3.15 to 3.45<br>~~eee~~<br>~~ee~~|3.15 to 3.45<br>~~eee~~|V<br>~~eee~~|
|||Operation4<br>~~eee~~<br>~~es~~|0 to 3.6<br>~~eee~~<br>~~es~~<br>~~ee~~|0 to 3.6<br>~~eee~~<br>~~es~~|V<br>~~eee~~<br>~~es~~|
|VCCPLL<br>~~eee~~<br>~~aa~~|Analog power supply (PLL)<br>~~eee~~<br>~~a~~||1.425 to 1.575<br>~~eee~~<br>~~ee~~|1.425 to 1.575<br>~~eee~~|V<br>~~eee~~|
|VCCI<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~aa~~|1.5 V DC supply voltage<br>~~a~~<br>~~a~~||1.425 to 1.575|1.425 to 1.575|V|
||1.8 V DC supply voltage<br>~~a~~<br>~~a~~<br>~~a~~||1.7 to 1.9|1.7 to 1.9|V|
||2.5 V DC supply voltage<br>~~a~~<br>~~a~~<br>~~a~~||2.3 to 2.7|2.3 to 2.7|V|
||3.3 V DC supply voltage<br>~~a~~<br>~~a~~<br>~~a~~||3.0 to 3.6|3.0 to 3.6|V|
||LVDS differential I/O<br>~~a~~<br>~~aa~~||2.375 to 2.625|2.375 to 2.625|V|
||LVPECL differential I/O<br>~~aa~~||3.0 to 3.6|3.0 to 3.6|V|
|VCC33A<br>~~a~~<br>~~a~~|+3.3 V power supply<br>~~a~~<br>~~a~~||2.97 to 3.63|2.97 to 3.63|V|
|VCC33PMP <br>~~a~~|+3.3 V power supply<br>~~a~~||2.97 to 3.63|2.97 to 3.63|V|
|VAREF<br>~~a~~|Voltage reference for ADC<br>~~a~~||2.527 to 2.593|2.527 to 2.593|V|
|VCC15A 5<br>~~a~~|Digital power supply for the analog system<br>~~a~~||1.425 to 1.575|1.425 to 1.575|V|
|VCCNVM<br>~~a~~|Embedded flash power supply<br>~~a~~||1.425 to 1.575|1.425 to 1.575|V|
|VCCOSC<br>~~aa~~|Oscillator power supply<br>~~aa~~||2.97 to 3.63|2.97 to 3.63|V|
|AV, AC 6<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Unpowered, ADC reset asserted or unconfigured<br>~~a~~<br>~~a~~||–10.5 to 12.0|–10.5 to 11.6|V|
||Analog input (+16 V to +2 V prescaler range)<br>~~a~~<br>~~a~~<br>~~a~~||–0.3 to 12.0|–0.3 to 11.6|V|
||Analog input (+1 V to + 0.125 V prescaler range)<br>~~a~~<br>~~a~~<br>~~a~~||–0.3 to 3.6|–0.3 to 3.6|V|
||Analog input (–16 V to –2 V prescaler range)<br>~~a~~<br>~~a~~<br>~~a~~||–10.5 to 0.3|–10.5 to 0.3|V|
||Analog input (–1 V to –0.125 V prescaler range)<br>~~a~~<br>~~a~~<br>~~a~~||–3.6 to 0.3|–3.6 to 0.3|V|
||Analog input (direct input to ADC)<br>~~a~~<br>~~a~~<br>~~a~~||–0.3 to 3.6|–0.3 to 3.6|V|
||Digital input<br>~~a~~<br>~~a~~<br>~~a~~||–0.3 to 12.0|–0.3 to 11.6|V|
|AG 6<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Unpowered, ADC reset asserted or unconfigured<br>~~a~~<br>~~a~~<br>~~a~~||–10.5 to 12.0|–10.5 to 11.6|V|
||Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA)<br>~~a~~<br>~~a~~<br>~~a~~||–0.3 to 12.0|–0.3 to 11.6|V|
||Low Current Mode (–1 µA, –3 µA, –10 µA, –30 µA)<br>~~a~~<br>~~a~~<br>~~a~~||–10.5 to 0.3|–10.5 to 0.3|V|
||High Current Mode 7<br>~~a~~<br>~~a~~<br>~~a~~||–10.5 to 12.0|–10.5 to 11.6|V|
|AT 6<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Unpowered, ADC reset asserted or unconfigured<br>~~a~~<br>~~a~~<br>~~a~~||–0.3 to 15.5|–0.3 to 14.5|V|
||Analog input (+16 V, +4 V prescaler range)<br>~~a~~<br>~~a~~<br>~~a~~||–0.3 to 15.5<br>|–0.3 to 14.5<br>|V<br>|
||Analog input (direct input to ADC)<br>~~a~~<br>~~a~~||–0.3 to 3.6<br>|–0.3 to 3.6<br>|V<br>|
||Digital input<br>~~aee~~||–0.3 to 15.5<br>~~ee~~|–0.3 to 14.5<br>~~ee~~|V<br>~~ee~~|
_Notes:_
_1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-85 on page 2-157._
_2. All parameters representing voltages are measured with respect to GND unless otherwise specified._
_3. The programming temperature range supported is Tambient = 0°C to 85°C._
_4. VPUMP can be left floating during normal operation (not programming mode)._
_5. Violating the VCC15A recommended voltage supply during an embedded flash program cycle can corrupt the page being programmed._
_6. The input voltage may overshoot by up to 500 mV above the Recommended Maximum (150 mV in Direct mode), provided the duration of the overshoot is less than 50% of the operating lifetime of the device._
_7. The AG pad should also conform to the limits as specified in Table 2-48 on page 2-114._
**3-3**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 3-3 •**_ **Input Resistance of Analog Pads**
|**Pads**|**Pad Configuration**|**Prescaler Range**|**Input Resistance to Ground**|
|---|---|---|---|
|AV, AC|Analog Input (direct input to ADC)|–|2 k(typical)|
|||–|> 10 M|
||Analog Input (positive prescaler)|+16 V to +2 V|1 M(typical)|
|||+1 V to +0.125 V|> 10 M|
||Analog Input (negative prescaler)|–16 V to –2 V|1 M(typical)|
|||–1 V to –0.125 V|> 10 M|
||Digital input|+16 V to +2 V|1 M(typical)|
||Current monitor|+16 V to +2 V|1 M(typical)|
|||–16 V to –2 V|1 M(typical)|
|AT|Analog Input (direct input to ADC)|–|1 M(typical)|
||Analog Input (positive prescaler)|+16 V, +4 V|1 M(typical)|
||Digital input|+16 V, +4 V|1 M(typical)|
||Temperature monitor|+16 V, +4 V|> 10 M|
_**Table 3-4 •**_ **Overshoot and Undershoot Limits[1]**
|**VCCI**|**Average VCCI–GND Overshoot or Undershoot**<br>**Duration as a Percentage of Clock Cycle2**|**Maximum Overshoot/**<br>**Undershoot2**|
|---|---|---|
|2.7 V or less|10%|1.4 V|
||5%|1.49 V|
|3.0 V|10%|1.1 V|
||5%|1.19 V|
|3.3 V|10%|0.79 V|
||5%|0.88 V|
|3.6 V|10%|0.45 V|
||5%|0.54 V|
_Notes:_
_1. Based on reliability requirements at a junction temperature of 85°C._
_2. The duration is allowed at one cycle out of six clock cycle. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V._
**Revision 8**
**3-4**
_DC and Power Characteristics_
_**Table 3-5 •**_ **FPGA Programming, Storage, and Operating Limits**
|**Product**<br>**Grade**|**Storage**<br>**Temperature**|**Element**|**Grade Programming**<br>**Cycles**|**Retention**|
|---|---|---|---|---|
|Commercial|Min. TJ= 0°C<br>Max. TJ= 85°C|FPGA/FlashROM|500|20 years|
|||Embedded Flash|< 1,000|20 years|
||||< 10,000|10 years|
||||< 15,000|5 years|
|Industrial|Min. TJ= –40°C<br>Max. TJ= 100°C|FPGA/FlashROM|500|20 years|
|||Embedded Flash|< 1,000|20 years|
||||< 10,000|10 years|
||||< 15,000|5 years|
## **I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)**
Sophisticated power-up management circuitry is designed into every Fusion device. These circuits ensure easy transition from the powered off state to the powered up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 3-1 on page 3-6.
There are five regions to consider during power-up.
Fusion I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 3-1).
2. VCCI > VCC – 0.75 V (typical).
3. Chip is in the operating mode.
**VCCI Trip Point:**
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
**VCC Trip Point:**
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
- During programming, I/Os become tristated and weakly pulled up to VCCI.
- JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
## _**Internal Power-Up Activation Sequence**_
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
## _**PLL Behavior at Brownout Condition**_
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 3-1 on page 3-6 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost.
**3-5**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
**==> picture [454 x 345] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCC = VCCI + VT<br>Where VT can be from 0.58 V to 0.9 V (typically 0.75 V)<br>VCC<br>VCC = 1.575 V<br>Region 4: I/O Region 5: I/O buffers are ON<br>Region 1: I/O Buffers are OFF buffers are ON. and power supplies are within<br>I/Os are functional specification.<br>(except differential inputs)<br> but slower because VCCI is I/Os meet the entire datasheet<br>below specification. For the and timer specifications for<br>same reason, input buffers do not speed, VIH / VIL, VOH VOL, etc.<br> meet VIH / VIL levels, and output<br>buffers do not meet VOH / VOL levels.<br>VCC = 1.425 V<br>Region 2: I/O buffers are ON.<br>Region 3: I/O buffers are ON.<br>I/Os are functional (except differential inputs)<br>I/Os are functional; I/O DC<br>but slower because VCCI / VCC are below<br>specifications are met,<br>specification. For the same reason, input but I/Os are slower because<br>buffers do not meet VIH / VIL levels, and<br>the VCC is below specification<br> output buffers do not meet VOH / VOL levels.<br>Activation trip point:<br>Va = 0.85 V ± 0.25 V<br>Deactivation trip point:<br>Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF<br>{ t<br>VCCI<br>Activation trip point: Min VCCI datasheet specification<br>Va = 0.9 V ±0.3 V voltage at a selected I/O<br>Deactivation trip point: standard; i.e., 1.425 V or 1.7 V<br>Vd = 0.8 V ± 0.3 V or 2.3 V or 3.0 V<br>**----- End of picture text -----**<br>
_**Figure 3-1 •**_ **I/O State as a Function of VCCI and VCC Voltage Levels**
**Revision 8**
**3-6**
_DC and Power Characteristics_
## **Thermal Characteristics**
## _**Introduction**_
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's junction temperature to be higher than the ambient, case, or board temperatures. EQ 1 through EQ 3 give the relationship between thermal resistance, temperature gradient, and power.
**==> picture [236 x 66] intentionally omitted <==**
**==> picture [237 x 34] intentionally omitted <==**
**==> picture [23 x 9] intentionally omitted <==**
where
- JA = Junction-to-air thermal resistance
- JB = Junction-to-board thermal resistance
- JC = Junction-to-case thermal resistance
- TJ = Junction temperature
- TA = Ambient temperature
- TB = Board temperature (measured 1.0 mm away from the package edge)
- TC = Case temperature
- P = Total power dissipated by the device
_**Table 3-6 •**_ **Package Thermal Resistance**
|**Product**<br>~~—~~<br>~~**e**e~~|**JA**<br>~~—~~<br>~~ee~~<br>~~eeseee~~|**JA**<br>~~—~~<br>~~ee~~<br>~~eeseee~~|**JA**<br>~~—~~<br>~~ee~~<br>~~eeseee~~|**JC**<br>~~eee~~|**JB**|**Units**|
|---|---|---|---|---|---|---|
||**Still Air**<br>~~—~~<br>~~ee~~|**1.0 m/s**<br>~~ees~~|**2.5 m/s**<br>~~eee~~||||
|AFS090-QN108<br>~~—~~<br>~~**e**e~~|34.5<br>~~—~~<br>~~ee~~|30.0<br>~~ees ~~<br>~~e~~|27.7<br> ~~eee~~<br>~~e~~|8.1<br>~~eee~~<br>~~e~~|16.7<br>~~e~~|°C/W<br>~~e~~|
|AFS090-QN180<br>~~a~~|33.3|27.6|25.7|9.2|21.2|°C/W|
|AFS250-QN180<br>~~ee~~<br>~~a~~|32.2<br>~~ee~~<br>~~ee~~|26.5<br>~~ee~~|24.7<br>~~ee~~|5.7<br>~~ee~~|15.0<br>~~ee~~|°C/W<br>~~ee~~|
|AFS250-PQ2081<br>~~a~~|42.1<br>~~ee~~|38.4|37|20.5|36.3|°C/W|
|AFS600-PQ2081<br>~~a~~<br>~~ee~~<br>~~a~~|23.9<br>~~ee~~<br>~~ee~~<br>~~ee~~|21.3<br>~~ee~~|20.48<br>~~ee~~|6.1<br>~~ee~~|16.5<br>~~ee~~|°C/W<br>~~ee~~|
|AFS090-FG256<br>~~a~~|37.7<br>~~ee~~|33.9|32.2|11.5|29.7|°C/W|
|AFS250-FG256<br>~~a~~<br>~~ee~~<br>~~a~~|33.7<br>~~ee~~<br>~~ee~~<br>~~ee~~|30.0<br>~~ee~~|28.3<br>~~ee~~|9.3<br>~~ee~~|24.8<br>~~ee~~|°C/W<br>~~ee~~|
|AFS600-FG256<br>~~a~~|28.9<br>~~ee~~|25.2|23.5|6.8|19.9|°C/W|
|AFS1500-FG256<br>~~a~~<br>~~ee~~<br>~~a~~|23.3<br>~~ee~~<br>~~ee~~<br>~~ee~~|19.6<br>~~ee~~|18.0<br>~~ee~~|4.3<br>~~ee~~|14.2<br>~~ee~~|°C/W<br>~~ee~~|
|AFS600-FG484<br>~~a~~|21.8<br>~~ee~~|18.2|16.7|7.7|16.8|°C/W|
|AFS1500-FG484<br>~~a~~<br>~~ee~~|21.6<br>~~ee~~<br>~~ee~~|16.8<br>~~ee~~|15.2<br>~~ee~~|5.6<br>~~ee~~|14.9<br>~~ee~~|°C/W<br>~~ee~~|
|AFS1500-FG676<br>~~Pe~~|TBD<br>~~Pe~~|TBD<br>~~Pe~~|TBD<br>~~Pe~~|TBD<br>~~Pe~~|TBD<br>~~Pe~~|°C/W<br>~~Pe~~|
_1. The package PQ208 is discontinued.For more information, see PDN 1407: Specific Part / Package Combinations._
**3-7**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Theta-JA**_
Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with caution but is useful for comparing the thermal performance of one package to another.
A sample calculation showing the maximum power dissipation allowed for the AFS600-FG484 package under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:
T – T Maximum Power Allowed = --------------------------------------------J(MAX) A(MAX) JA
_EQ 4_
where
- JA = 19.00°C/W (taken from Table 3-6 on page 3-7). TA = 75.00°C
Maximum Power Allowed = 100.00°C ----------------------------------------------------– 75.00°C = 1.3 W 19.00°C/W _EQ 5_
The power consumption of a device can be calculated using the Microsemi power calculator. The device's power consumption must be lower than the calculated maximum power dissipation by the package. If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must be increased.
## _**Theta-JB**_
Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.
## _**Theta-JC**_
Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the surface of the chip to the top or bottom surface of the package. It is applicable for packages used with external heat sinks. Constant temperature is applied to the surface in consideration and acts as a boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration.
## _**Calculation for Heat Sink**_
For example, in a design implemented in an AFS600-FG484 package with 2.5 m/s airflow, the power consumption value using the power calculator is 3.00 W. The user-dependent Ta and Tj are given as follows:
TJ = 100.00°C
TA = 70.00°C
From the datasheet:
JA = 17.00°C/W
JC = 8.28°C/W
**==> picture [161 x 24] intentionally omitted <==**
_EQ 6_
**Revision 8**
**3-8**
_DC and Power Characteristics_
The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the airflow where the device is mounted should be increased. The design's total junction-to-air thermal resistance requirement can be estimated by EQ 7:
**==> picture [199 x 21] intentionally omitted <==**
**==> picture [23 x 9] intentionally omitted <==**
Determining the heat sink's thermal performance proceeds as follows:
**==> picture [266 x 31] intentionally omitted <==**
where
- JA = 0.37°C/W
- = Thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer
- SA = Thermal resistance of the heat sink in °C/W
**==> picture [266 x 28] intentionally omitted <==**
**==> picture [221 x 10] intentionally omitted <==**
A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat sinks is a function of airflow. The heat sink performance can be significantly improved with increased airflow.
Carefully estimating thermal resistance is important in the long-term reliability of an Microsemi FPGA. Design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device.
Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard (JESD-51) and assumptions made in building the model. It may not be realized in actual application and therefore should be used with a degree of caution. Junction-to-case thermal resistance assumes that all power is dissipated through the case.
## _**Temperature and Voltage Derating Factors**_
_**Table 3-7 •**_ **Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)**
|**(normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)**|**(normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)J = 70°C, Worst-Case VCC = 1.425 V) = 70°C, Worst-Case VCC = 1.425 V)**|**(normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)J = 70°C, Worst-Case VCC = 1.425 V) = 70°C, Worst-Case VCC = 1.425 V)**|**(normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)J = 70°C, Worst-Case VCC = 1.425 V) = 70°C, Worst-Case VCC = 1.425 V)**|**(normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)J = 70°C, Worst-Case VCC = 1.425 V) = 70°C, Worst-Case VCC = 1.425 V)**|**(normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)J = 70°C, Worst-Case VCC = 1.425 V) = 70°C, Worst-Case VCC = 1.425 V)**|**(normalized to TJ = 70°C, Worst-Case VCC = 1.425 V)J = 70°C, Worst-Case VCC = 1.425 V) = 70°C, Worst-Case VCC = 1.425 V)**|
|---|---|---|---|---|---|---|
|**Array Voltage**<br>**VCC (V)**|**Junction Temperature (°C)**||||||
||**–40°C**|**0°C**|**25°C**|**70°C**|**85°C**|**100°C**|
|1.425|0.88|0.93|0.95|1.00|1.02|1.05|
|1.500|0.83|0.88|0.90|0.95|0.96|0.99|
|1.575|0.80|0.85|0.87|0.91|0.93|0.96|
**3-9**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Calculating Power Dissipation**
## **Quiescent Supply Current**
_**Table 3-8 •**_ **AFS1500 Quiescent Supply Current Characteristics**
|~~ee~~|~~ee~~|~~rere~~|~~Gers~~|~~tn~~|~~ts~~|~~ee~~||
|---|---|---|---|---|---|---|---|
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~rere~~|Temp.<br>~~Gers~~<br>~~PT~~|Min.<br>~~tn~~<br>~~PTTT~~|Typ.<br>~~ts~~<br>~~TT~~|Max.<br>~~ee~~<br>~~TT~~|Unit<br>~~TT~~|
|ICC1<br>~~ee~~|1.5 V quiescent current<br>~~ee~~|Operational standby4,<br>VCC = 1.575 V<br>~~rere ~~<br>~~PF~~<br>~~ee~~|TJ= 25°C<br> ~~Gers~~<br>~~PT~~<br>~~PF~~|~~tn ~~<br>~~PTTT~~<br>|20<br> ~~ts ~~<br>~~TT~~<br>|40<br> ~~ee~~<br>~~TT~~<br>|mA<br>~~TT~~<br>|
||||TJ= 85°C<br>~~PT~~<br>~~PFTt~~<br>~~ee~~|~~PT TT~~<br>~~Tt~~|32<br>~~TT~~<br>~~Tt~~|65<br>~~TT~~<br>~~Tt~~|mA<br>~~TT~~<br>~~Tt~~|
||||TJ= 100°C<br>~~PF~~<br>~~ee~~<br>~~ee~~|~~ee~~|59<br><br>~~ee~~|120<br><br>~~ee~~|mA<br><br>~~ee~~|
|||Standby mode5or Sleep mode6,<br>VCC = 0 V<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~PT~~|~~ee~~<br>~~PTTT~~|0<br>~~ee~~<br>~~TT~~|0<br>~~ee~~<br>~~TT~~|µA<br>~~ee~~<br>~~TT~~|
|ICC332|3.3 V analog supplies<br>current|Operational standby4,<br>VCC33 = 3.63 V|TJ= 25°C<br>~~ee~~<br>~~PT~~<br>~~FT~~|~~PTTT~~<br>~~FTTT~~|9.8<br>~~TT~~<br>~~TT~~|13<br>~~TT~~<br>~~TT~~|mA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~PT~~<br>~~FT~~<br>~~PT~~|~~PT TT~~<br>~~FTTT~~<br>~~PTTE~~|10.7<br>~~TT~~<br>~~TT~~<br>~~TE~~|14<br>~~TT~~<br>~~TT~~<br>~~TE~~|mA<br>~~TT~~<br>~~TT~~<br>~~TE~~|
||||TJ= 100°C<br>~~FT~~<br>~~PT~~|~~FT TT~~<br>~~PTTE~~|10.8<br>~~TT~~<br>~~TE~~|15<br>~~TT~~<br>~~TE~~|mA<br>~~TT~~<br>~~TE~~|
|||Operational standby, only Analog<br>Quad and –3.3 V output ON,<br>VCC33 = 3.63 V<br>~~PF~~|TJ= 25°C<br>~~PT~~<br>~~PTT~~|~~PT TE~~<br>~~PTT~~|0.31<br>~~TE~~<br>~~PTT~~|2<br>~~TE~~<br>~~PTT~~|mA<br>~~TE~~<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~<br>~~PF~~|~~PTT~~<br>|0.35<br>~~PTT~~<br>|2<br>~~PTT~~<br>|mA<br>~~PTT~~<br>|
||||TJ= 100°C<br>~~PFTt~~|~~Tt~~|0.45<br>~~Tt~~|2<br>~~Tt~~|mA<br>~~Tt~~|
|||Standby mode5, VCC33 = 3.63 V<br>~~PF~~|TJ= 25°C<br>~~PF~~<br>~~ee~~<br>~~PT~~|~~ee~~<br>~~PTTT~~|2.9<br><br>~~ee~~<br>~~TT~~|3.6<br><br>~~ee~~<br>~~TT~~|mA<br><br>~~ee~~<br>~~TT~~|
||||TJ= 85°C<br>~~PT~~<br>~~PT~~|~~PTTT~~<br>~~PTTE~~|2.9<br>~~TT~~<br>~~TE~~|4<br>~~TT~~<br>~~TE~~|mA<br>~~TT~~<br>~~TE~~|
||||TJ= 100°C<br>~~PT~~<br>~~PT~~|~~PT TT~~<br>~~PTTE~~|3.3<br>~~TT~~<br>~~TE~~|6<br>~~TT~~<br>~~TE~~|mA<br>~~TT~~<br>~~TE~~|
|||Sleep mode6, VCC33 = 3.63 V|TJ= 25°C<br>~~PT~~<br>~~PTT~~|~~PT TE~~<br>~~PTT~~|17<br>~~TE~~<br>~~PTT~~|19<br>~~TE~~<br>~~PTT~~|µA<br>~~TE~~<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|18<br>~~PTT~~|20<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~a~~|~~PTT~~<br>~~ee~~|24<br>~~PTT~~<br>~~ee~~|25<br>~~PTT~~<br>~~eee~~|µA<br>~~PTT~~<br>~~eee~~|
|ICCI3|I/O quiescent current|Operational standby4,<br>Standby mode, and Sleep Mode6,<br>VCCIx = 3.63 V<br>~~PF~~|TJ= 25°C<br>~~a~~<br>~~PT~~|~~ee~~<br>~~PTTT~~|417<br>~~ee~~<br>~~TT~~|649<br>~~eee~~<br>~~TT~~|µA<br>~~eee~~<br>~~TT~~|
||||TJ= 85°C<br>~~a~~<br>~~PT~~<br>~~PF~~|~~ee~~<br>~~PTTT~~<br>|417<br>~~ee~~<br>~~TT~~<br>|649<br>~~eee~~<br>~~TT~~<br>|µA<br>~~eee~~<br>~~TT~~<br>|
||||TJ= 100°C<br>~~PT~~<br>~~PFTt~~|~~PT TT~~<br>~~Tt~~|417<br>~~TT~~<br>~~Tt~~|649<br>~~TT~~<br>~~Tt~~|µA<br>~~TT~~<br>~~Tt~~|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC and ICC15A._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V._
**Revision 8**
**3-10**
_DC and Power Characteristics_
_**Table 3-8 •**_ **AFS1500 Quiescent Supply Current Characteristics (continued)**
|~~ee~~|~~ee~~|~~es~~|~~reer~~|~~teen~~|~~te~~|~~en~~||
|---|---|---|---|---|---|---|---|
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~es~~|Temp.<br>~~reer~~|Min.<br>~~teen~~|Typ.<br>~~te~~|Max.<br>~~en~~|Unit|
|IJTAG<br>~~ee~~|JTAG I/O quiescent<br>current<br>~~ee~~|Operational standby4,<br>VJTAG = 3.63 V<br>~~es ~~<br>~~ee~~|TJ= 25°C<br> ~~reer~~<br>~~PTT~~|~~teen ~~<br>~~PTT~~<br>~~ee~~|80<br> ~~te~~<br>~~PTT~~<br>~~ee~~|100<br>~~en~~<br>~~PTT~~<br>~~eee~~|µA<br>~~PTT~~<br>~~eee~~|
||||TJ= 85°C<br>~~ee~~<br>~~ae~~|~~ee~~<br>~~ee~~|80<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~eee~~|µA<br>~~ee~~<br>~~eee~~|
||||TJ= 100°C<br>~~ee~~<br>~~ae~~|~~ee ~~<br>~~ee~~|80<br> ~~ee ~~<br>~~ee~~|100<br> ~~eee~~<br>~~ee~~|µA<br>~~eee~~<br>~~ee~~|
|||Standby mode5or Sleep mode6,<br>VJTAG = 0 V<br>~~ee~~|~~ee~~<br>~~ae~~|~~ee~~|0<br>~~ee~~|0<br>~~ee~~|µA<br>~~ee~~|
|IPP|Programming supply<br>current|Non-programming mode,<br>VPUMP = 3.63 V<br>~~es~~|TJ= 25°C<br>~~ae~~<br>~~PTT~~|~~PTT~~|39<br>~~PTT~~|80<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~<br>~~ee~~|~~PTT~~|40<br>~~PTT~~|80<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~es~~<br>~~ee~~|~~es~~|40<br>~~es~~|80<br>~~es~~|µA<br>~~es~~|
|||Standby mode5or Sleep mode6,<br>VPUMP = 0 V<br>~~es~~|~~es~~<br>~~ee~~|~~es~~|0<br>~~es~~|0<br>~~es~~|µA<br>~~es~~|
|ICCNVM|Embedded NVM<br>current|Reset asserted, VCCNVM= 1.575 V|TJ= 25°C<br>~~ee~~<br>~~PTT~~|~~PTT~~|50<br>~~PTT~~|150<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ=85°C<br>~~PTT~~|~~PTT~~|50<br>~~PTT~~|150<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~|~~PTT~~|50<br>~~PTT~~|150<br>~~PTT~~|µA<br>~~PTT~~|
|ICCPLL|1.5 V PLL quiescent<br>current|Operational standby<br>, VCCPLL = 1.575 V|TJ= 25°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~ee~~<br>~~FT~~|130<br>~~PTT~~<br>~~ee~~<br>|200<br>~~PTT~~<br>~~eee~~<br>|µA<br>~~PTT~~<br>~~eee~~<br>|
||||TJ= 85°C<br>~~re~~<br>~~FT~~|~~re~~<br>~~ee~~<br>~~FT~~|130<br>~~re~~<br>~~ee~~<br>|200<br>~~re~~<br>~~eee~~<br>|µA<br>~~re~~<br>~~eee~~<br>|
||||TJ= 100°C<br>~~FT~~|~~ee~~<br>~~FT TT~~|130<br>~~ee~~<br>~~TT~~|200<br>~~eee~~<br>~~TT~~|µA<br>~~eee~~<br>~~TT~~|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC and ICC15A._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V._
**3-11**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 3-9 •**_ **AFS600 Quiescent Supply Current Characteristics**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~Mees~~|**Temp.**<br>~~Mees~~<br>~~Gs~~|**Min**<br>~~Mees~~<br>~~tir~~|**Typ**<br>~~Mees~~<br>~~i~~|**Max**<br>~~Mees~~<br>~~i~~|**Unit**<br>~~Mees~~|
|---|---|---|---|---|---|---|---|
|ICC1<br>~~ee~~|1.5 V quiescent current<br>~~ee~~|Operational standby4,<br>VCC = 1.575 V<br>~~Mees~~<br>~~e~~|TJ= 25°C<br>~~Mees~~<br>~~Gs ~~<br>~~PTT~~<br>~~FT~~|~~Mees~~<br> ~~tir ~~<br>~~PTT~~<br>~~FTTT~~|13<br>~~Mees~~<br> ~~i ~~<br>~~PTT~~<br>~~TT~~|25<br>~~Mees~~<br> ~~i~~<br>~~PTT~~<br>~~TT~~|mA<br>~~Mees~~<br>~~PTT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~e~~|~~FTTT~~|20<br>~~TT~~|45<br>~~TT~~|mA<br>~~TT~~|
||||TJ=100°C<br>~~FT~~<br>~~e~~~~**e**~~<br>~~e~~|~~FT TT~~<br>~~**e**~~|25<br>~~TT~~<br>~~**e**~~|75<br>~~TT~~<br>~~**e**~~|mA<br>~~TT~~<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VCC = 0 V<br>~~e~~|~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
|ICC332|3.3 V analog supplies<br>current|Operational standby4,<br>VCC33 = 3.63 V|TJ= 25°C<br>~~e~~<br>~~PTT~~|~~PTT~~|9.8<br>~~PTT~~|13<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|10.7<br>~~PTT~~|14<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|10.8<br>~~PTT~~<br>~~TT~~|15<br>~~PTT~~<br>~~TT~~|mA<br>~~PTT~~<br>~~TT~~|
|||Operational standby,<br>only Analog Quad and –3.3 V<br>output ON, VCC33 = 3.63 V|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|0.31<br>~~TT~~<br>~~TT~~|2<br>~~TT~~<br>~~TT~~|mA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~|~~FT TT~~<br>~~FTTT~~|0.35<br>~~TT~~<br>~~TT~~|2<br>~~TT~~<br>~~TT~~|mA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~PTT~~|~~FT TT~~<br>~~PTT~~|0.45<br>~~TT~~<br>~~PTT~~|2<br>~~TT~~<br>~~PTT~~|mA<br>~~TT~~<br>~~PTT~~|
|||Standby mode5,<br>VCC33 = 3.63 V|TJ= 25°C<br>~~PTT~~|~~PTT~~|2.8<br>~~PTT~~|3.6<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|2.9<br>~~PTT~~|4<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|3.5<br>~~PTT~~<br>~~TT~~|6<br>~~PTT~~<br>~~TT~~|mA<br>~~PTT~~<br>~~TT~~|
|||Sleep mode6, VCC33= 3.63 V|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|17<br>~~TT~~<br>~~TT~~|19<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~|~~FT TT~~<br>~~FTTT~~|18<br>~~TT~~<br>~~TT~~|20<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~PTT~~|~~FT TT~~<br>~~PTT~~|24<br>~~TT~~<br>~~PTT~~|25<br>~~TT~~<br>~~PTT~~|µA<br>~~TT~~<br>~~PTT~~|
|ICCI3|I/O quiescent current|Operational standby4,<br>VCCIx = 3.63 V|TJ= 25°C<br>~~PTT~~|~~PTT~~|417<br>~~PTT~~|648<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|417<br>~~PTT~~|648<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|417<br>~~PTT~~<br>~~TT~~|649<br>~~PTT~~<br>~~TT~~|µA<br>~~PTT~~<br>~~TT~~|
|IJTAG|JTAG I/O quiescent current|Operational standby4,<br>VJTAG = 3.63 V<br>~~e~~|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|80<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~<br>~~e~~|~~FT TT~~<br>~~FTTT~~|80<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~e~~~~**e**~~<br>~~e~~|~~FT TT~~<br>~~**e**~~|80<br>~~TT~~<br>~~**e**~~|100<br>~~TT~~<br>~~**e**~~|µA<br>~~TT~~<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VJTAG = 0 V<br>~~e~~|~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC and ICC15A._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V._
**Revision 8**
**3-12**
_DC and Power Characteristics_
_**Table 3-9 •**_ **AFS600 Quiescent Supply Current Characteristics (continued)**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~Mees~~|**Temp.**<br>~~Mees~~<br>~~Gs~~|**Min**<br>~~Mees~~<br>~~tir~~|**Typ**<br>~~Mees~~<br>~~i~~|**Max**<br>~~Mees~~<br>~~i~~|**Unit**<br>~~Mees~~|
|---|---|---|---|---|---|---|---|
|IPP<br>~~ee~~|Programming supply<br>current<br>~~ee~~|Non-programming mode,<br>VPUMP = 3.63 V<br>~~Mees~~<br>~~e~~|TJ= 25°C<br>~~Mees~~<br>~~Gs ~~<br>~~PTT~~<br>~~FT~~|~~Mees~~<br> ~~tir ~~<br>~~PTT~~<br>~~FTTT~~|36<br>~~Mees~~<br> ~~i ~~<br>~~PTT~~<br>~~TT~~|80<br>~~Mees~~<br> ~~i~~<br>~~PTT~~<br>~~TT~~|µA<br>~~Mees~~<br>~~PTT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~e~~|~~FTTT~~|36<br>~~TT~~|80<br>~~TT~~|µA<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~e~~~~**e**~~<br>~~e~~|~~FT TT~~<br>~~**e**~~|36<br>~~TT~~<br>~~**e**~~|80<br>~~TT~~<br>~~**e**~~|µA<br>~~TT~~<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VPUMP = 0 V<br>~~e~~|~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
|ICCNVM|Embedded NVM current|Reset asserted,<br>VCCNVM = 1.575 V|TJ= 25°C<br>~~e~~<br>~~PTT~~|~~PTT~~|22<br>~~PTT~~|80<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|24<br>~~PTT~~|80<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|25<br>~~PTT~~<br>~~TT~~|80<br>~~PTT~~<br>~~TT~~|µA<br>~~PTT~~<br>~~TT~~|
|ICCPLL|1.5 V PLL quiescent current|Operational standby,<br>VCCPLL = 1.575 V<br>~~PF~~|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|130<br>~~TT~~<br>~~TT~~|200<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~<br>~~PF~~|~~FT TT~~<br>~~FTTT~~<br>|130<br>~~TT~~<br>~~TT~~<br>|200<br>~~TT~~<br>~~TT~~<br>|µA<br>~~TT~~<br>~~TT~~<br>|
||||TJ= 100°C<br>~~FT~~<br>~~PFTT~~|~~FT TT~~<br>~~TT~~|130<br>~~TT~~<br>~~TT~~|200<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC and ICC15A._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V._
**3-13**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 3-10 •**_ **AFS250 Quiescent Supply Current Characteristics**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~Mees~~|**Temp.**<br>~~Mees~~<br>~~Gs~~|**Min**<br>~~Mees~~<br>~~tir~~|**Typ**<br>~~Mees~~<br>~~i~~|**Max**<br>~~Mees~~<br>~~i~~|**Unit**<br>~~Mees~~|
|---|---|---|---|---|---|---|---|
|ICC1<br>~~ee~~|1.5 V quiescent current<br>~~ee~~|Operational standby4,<br>VCC = 1.575 V<br>~~Mees~~<br>~~e~~|TJ= 25°C<br>~~Mees~~<br>~~Gs ~~<br>~~PTT~~<br>~~FT~~|~~Mees~~<br> ~~tir ~~<br>~~PTT~~<br>~~FTTT~~|4.8<br>~~Mees~~<br> ~~i ~~<br>~~PTT~~<br>~~TT~~|10<br>~~Mees~~<br> ~~i~~<br>~~PTT~~<br>~~TT~~|mA<br>~~Mees~~<br>~~PTT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~e~~|~~FTTT~~|8.2<br>~~TT~~|30<br>~~TT~~|mA<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~e~~~~**e**~~<br>~~e~~|~~FT TT~~<br>~~**e**~~|15<br>~~TT~~<br>~~**e**~~|50<br>~~TT~~<br>~~**e**~~|mA<br>~~TT~~<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VCC = 0 V<br>~~e~~|~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
|ICC332|3.3 V analog supplies<br>current|Operational standby4,<br>VCC33 = 3.63 V|TJ= 25°C<br>~~e~~<br>~~PTT~~|~~PTT~~|9.8<br>~~PTT~~|13<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|9.8<br>~~PTT~~|14<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|10.8<br>~~PTT~~<br>~~TT~~|15<br>~~PTT~~<br>~~TT~~|mA<br>~~PTT~~<br>~~TT~~|
|||Operational standby, only<br>Analog Quad and –3.3 V<br>output ON, VCC33 = 3.63 V|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|0.29<br>~~TT~~<br>~~TT~~|2<br>~~TT~~<br>~~TT~~|mA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~|~~FT TT~~<br>~~FTTT~~|0.31<br>~~TT~~<br>~~TT~~|2<br>~~TT~~<br>~~TT~~|mA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~PTT~~|~~FT TT~~<br>~~PTT~~|0.45<br>~~TT~~<br>~~PTT~~|2<br>~~TT~~<br>~~PTT~~|mA<br>~~TT~~<br>~~PTT~~|
|||Standby mode5, VCC33 = 3.63V T|, VCC33 = 3.63V TJ= 25°C<br>~~PTT~~|~~PTT~~|2.9<br>~~PTT~~|3.0<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|2.9<br>~~PTT~~|3.1<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|3.5<br>~~PTT~~<br>~~TT~~|6<br>~~PTT~~<br>~~TT~~|mA<br>~~PTT~~<br>~~TT~~|
|||Sleep mode6, VCC33 = 3.63 V|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|19<br>~~TT~~<br>~~TT~~|18<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~|~~FT TT~~<br>~~FTTT~~|19<br>~~TT~~<br>~~TT~~|20<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~PTT~~|~~FT TT~~<br>~~PTT~~|24<br>~~TT~~<br>~~PTT~~|25<br>~~TT~~<br>~~PTT~~|µA<br>~~TT~~<br>~~PTT~~|
|ICCI3|I/O quiescent current|Operational standby6,<br>VCCIx = 3.63 V|TJ= 25°C<br>~~PTT~~|~~PTT~~|266<br>~~PTT~~|437<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|266<br>~~PTT~~|437<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|266<br>~~PTT~~<br>~~TT~~|437<br>~~PTT~~<br>~~TT~~|µA<br>~~PTT~~<br>~~TT~~|
|IJTAG|JTAG I/O quiescent current|Operational standby4,<br>VJTAG = 3.63 V<br>~~e~~|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|80<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~<br>~~e~~|~~FT TT~~<br>~~FTTT~~|80<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~e~~~~**e**~~<br>~~e~~|~~FT TT~~<br>~~**e**~~|80<br>~~TT~~<br>~~**e**~~|100<br>~~TT~~<br>~~**e**~~|µA<br>~~TT~~<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VJTAG = 0 V<br>~~e~~|~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, and ICCI2._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTA G = VPUMP = 0 V._
**Revision 8**
**3-14**
_DC and Power Characteristics_
_**Table 3-10 •**_ **AFS250 Quiescent Supply Current Characteristics (continued)**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~Mees~~|**Temp.**<br>~~Mees~~<br>~~Gs~~|**Min**<br>~~Mees~~<br>~~tir~~|**Typ**<br>~~Mees~~<br>~~i~~|**Max**<br>~~Mees~~<br>~~i~~|**Unit**<br>~~Mees~~|
|---|---|---|---|---|---|---|---|
|IPP<br>~~ee~~|Programming supply<br>current<br>~~ee~~|Non-programming mode,<br>VPUMP = 3.63 V<br>~~Mees~~<br>~~e~~|TJ= 25°C<br>~~Mees~~<br>~~Gs ~~<br>~~PTT~~<br>~~FT~~|~~Mees~~<br> ~~tir ~~<br>~~PTT~~<br>~~FTTT~~|37<br>~~Mees~~<br> ~~i ~~<br>~~PTT~~<br>~~TT~~|80<br>~~Mees~~<br> ~~i~~<br>~~PTT~~<br>~~TT~~|µA<br>~~Mees~~<br>~~PTT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~e~~|~~FTTT~~|37<br>~~TT~~|80<br>~~TT~~|µA<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~e~~~~**e**~~<br>~~e~~|~~FT TT~~<br>~~**e**~~|80<br>~~TT~~<br>~~**e**~~|100<br>~~TT~~<br>~~**e**~~|µA<br>~~TT~~<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VPUMP = 0 V<br>~~e~~|~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
|ICCNVM|Embedded NVM current|Reset asserted,<br>VCCNVM = 1.575 V|TJ= 25°C<br>~~e~~<br>~~PTT~~|~~PTT~~|10<br>~~PTT~~|40<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|14<br>~~PTT~~|40<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|14<br>~~PTT~~<br>~~TT~~|40<br>~~PTT~~<br>~~TT~~|µA<br>~~PTT~~<br>~~TT~~|
|ICCPLL|1.5 V PLL quiescent current|Operational standby,<br>VCCPLL = 1.575 V<br>~~PF~~|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|65<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~<br>~~PF~~|~~FT TT~~<br>~~FTTT~~<br>|65<br>~~TT~~<br>~~TT~~<br>|100<br>~~TT~~<br>~~TT~~<br>|µA<br>~~TT~~<br>~~TT~~<br>|
||||TJ= 100°C<br>~~FT~~<br>~~PFTT~~|~~FT TT~~<br>~~TT~~|65<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, and ICCI2._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTA G = VPUMP = 0 V._
**3-15**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 3-11 •**_ **AFS090 Quiescent Supply Current Characteristics**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~Mees~~|**Temp.**<br>~~Mees~~<br>~~Gs~~|**Min**<br>~~Mees~~<br>~~tir~~|**Typ**<br>~~Mees~~<br>~~i~~|**Max**<br>~~Mees~~<br>~~i~~|**Unit**<br>~~Mees~~|
|---|---|---|---|---|---|---|---|
|ICC1<br>~~ee~~|1.5 V quiescent current<br>~~ee~~|Operational standby4,<br>VCC = 1.575 V<br>~~Mees~~<br>~~e~~|TJ= 25°C<br>~~Mees~~<br>~~Gs ~~<br>~~PTT~~<br>~~FT~~|~~Mees~~<br> ~~tir ~~<br>~~PTT~~<br>~~FTTT~~|5<br>~~Mees~~<br> ~~i ~~<br>~~PTT~~<br>~~TT~~|7.5<br>~~Mees~~<br> ~~i~~<br>~~PTT~~<br>~~TT~~|mA<br>~~Mees~~<br>~~PTT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~e~~|~~FTTT~~|6.5<br>~~TT~~|20<br>~~TT~~|mA<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~e~~~~**e**~~<br>~~e~~|~~FT TT~~<br>~~**e**~~|14<br>~~TT~~<br>~~**e**~~|48<br>~~TT~~<br>~~**e**~~|mA<br>~~TT~~<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VCC= 0 V<br>~~e~~|~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
|ICC332|3.3 V analog supplies<br>current|Operational standby4,<br>VCC33 = 3.63 V|TJ= 25°C<br>~~e~~<br>~~PTT~~|~~PTT~~|9.8<br>~~PTT~~|12<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|9.8<br>~~PTT~~|12<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|10.7<br>~~PTT~~<br>~~TT~~|15<br>~~PTT~~<br>~~TT~~|mA<br>~~PTT~~<br>~~TT~~|
|||Operational standby, only<br>Analog Quad and –3.3 V<br>output ON, VCC33 = 3.63 V|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|0.30<br>~~TT~~<br>~~TT~~|2<br>~~TT~~<br>~~TT~~|mA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~|~~FT TT~~<br>~~FTTT~~|0.30<br>~~TT~~<br>~~TT~~|2<br>~~TT~~<br>~~TT~~|mA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~PTT~~|~~FT TT~~<br>~~PTT~~|0.45<br>~~TT~~<br>~~PTT~~|2<br>~~TT~~<br>~~PTT~~|mA<br>~~TT~~<br>~~PTT~~|
|||Standby mode5,<br>VCC33 = 3.63 V|TJ= 25°C<br>~~PTT~~|~~PTT~~|2.9<br>~~PTT~~|2.9<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|2.9<br>~~PTT~~|3.0<br>~~PTT~~|mA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|3.5<br>~~PTT~~<br>~~TT~~|6<br>~~PTT~~<br>~~TT~~|mA<br>~~PTT~~<br>~~TT~~|
|||Sleep mode6, VCC33 = 3.63 V|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|17<br>~~TT~~<br>~~TT~~|18<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~|~~FT TT~~<br>~~FTTT~~|18<br>~~TT~~<br>~~TT~~|20<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~PTT~~|~~FT TT~~<br>~~PTT~~|24<br>~~TT~~<br>~~PTT~~|25<br>~~TT~~<br>~~PTT~~|µA<br>~~TT~~<br>~~PTT~~|
|ICCI3|I/O quiescent current|Operational standby6,<br>VCCIx = 3.63 V|TJ= 25°C<br>~~PTT~~|~~PTT~~|260<br>~~PTT~~|437<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 85°C<br>~~PTT~~|~~PTT~~|260<br>~~PTT~~|437<br>~~PTT~~|µA<br>~~PTT~~|
||||TJ= 100°C<br>~~PTT~~<br>~~FT~~|~~PTT~~<br>~~FTTT~~|260<br>~~PTT~~<br>~~TT~~|437<br>~~PTT~~<br>~~TT~~|µA<br>~~PTT~~<br>~~TT~~|
|IJTAG|JTAG I/O quiescent current <br>~~po~~|Operational standby4,<br>VJTAG = 3.63 V<br>~~ee~~<br>~~po~~|TJ= 25°C<br>~~FT~~<br>~~FT~~|~~FTTT~~<br>~~FTTT~~|80<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 85°C<br>~~FT~~<br>~~FT~~<br>~~ee~~|~~FT TT~~<br>~~FTTT~~|80<br>~~TT~~<br>~~TT~~|100<br>~~TT~~<br>~~TT~~|µA<br>~~TT~~<br>~~TT~~|
||||TJ= 100°C<br>~~FT~~<br>~~ee~~<br>~~ee~~|~~FT TT~~<br>~~ee~~|80<br>~~TT~~<br>~~ee~~|100<br>~~TT~~<br>~~ee~~|µA<br>~~TT~~<br>~~ee~~|
|||Standby mode5or Sleep<br>mode6, VJTAG = 0 V<br>~~ee~~<br>~~po~~|~~ee~~<br>~~ee~~|~~ee~~|0<br>~~ee~~|0<br>~~ee~~|µA<br>~~ee~~|
|IPP|Programming supply<br>current<br>~~po~~|Non-programming mode,<br>VPUMP = 3.63 V<br>~~po~~<br>~~e~~|TJ= 25°C<br>~~ee~~||37|80|µA|
||||TJ= 85°C<br>~~ee~~<br>~~epee~~<br>~~e~~|~~epee~~|37<br>~~epee~~|80<br>~~epee~~|µA<br>~~epee~~|
||||TJ= 100°C<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|~~**e**~~|80<br>~~**e**~~|100<br>~~**e**~~|µA<br>~~**e**~~|
|||Standby mode5or Sleep<br>mode6, VPUMP = 0 V<br>~~po~~<br>~~e~~|~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|~~**e**~~|0<br>~~**e**~~|0<br>~~**e**~~|µA<br>~~**e**~~|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, and ICCI2._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V._
**Revision 8**
**3-16**
_DC and Power Characteristics_
_**Table 3-11 •**_ **AFS090 Quiescent Supply Current Characteristics (continued)**
|**Parameter**|**Description**|**Conditions**|**Temp.**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|ICCNVM|Embedded NVM current|Reset asserted,<br>VCCNVM = 1.575 V|TJ= 25°C||10|40|µA|
||||TJ= 85°C||14|40|µA|
||||TJ= 100°C||14|40|µA|
|ICCPLL|1.5 V PLL quiescent current|Operational standby,<br>VCCPLL = 1.575 V|TJ= 25°C||65|100|µA|
||||TJ= 85°C||65|100|µA|
||||TJ= 100°C||65|100|µA|
_Notes:_
_1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM._
_2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC._
_3. ICCI includes all ICCI0, ICCI1, and ICCI2._
_4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON._
_5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V._
_6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V._
**3-17**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Power per I/O Pin**
_**Table 3-12 •**_ **Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings**
||**VCCI (V)**|**Static Power**<br>**PDC7 (mW)1**|**Dynamic Power**<br>**PAC9 (µW/MHz)2**|
|---|---|---|---|
|**Applicable to Pro I/O Banks**<br>~~ee~~||||
|**Single-Ended**||||
|3.3 V LVTTL/LVCMOS<br>~~ee~~|3.3<br>~~ee~~|–<br>~~ee~~|17.39<br>~~ee~~|
|3.3 V LVTTL/LVCMOS – Schmitt trigger<br>~~ee~~<br>~~Rn~~|3.3<br>~~ee~~<br>~~Rn~~|–<br>~~ee~~<br>~~Rn~~|25.51<br>~~ee~~<br>~~Rn~~|
|2.5 V LVCMOS<br>~~Rn~~<br>~~Re~~|2.5<br>~~Rn~~<br>~~Re~~|–<br>~~Rn~~<br>~~Re~~|5.76<br>~~Rn~~<br>~~Re~~|
|2.5 V LVCMOS – Schmitt trigger<br>~~Re~~<br>~~ee~~<br>~~DR~~|2.5<br>~~Re~~<br>~~ee~~<br>|–<br>~~Re~~<br>~~ee~~<br>|7.16<br>~~Re~~<br>~~ee~~<br>|
|1.8 V LVCMOS<br>~~ee~~<br>~~DR~~|1.8<br>~~ee~~<br>|–<br>~~ee~~<br>|2.72<br>~~ee~~<br>|
|1.8 V LVCMOS – Schmitt trigger<br>~~DRa~~|1.8<br>~~a~~|–<br>~~a~~|2.80<br>~~a~~|
|1.5 V LVCMOS (JESD8-11)<br>~~ee~~|1.5<br>~~ee~~|–<br>~~ee~~|2.08<br>~~ee~~|
|1.5 V LVCMOS (JESD8-11) – Schmitt trigger<br>~~ee~~<br>~~Rn~~<br>~~a~~|1.5<br>~~ee~~<br>~~Rn~~|–<br>~~ee~~<br>~~Rn~~|2.00<br>~~ee~~<br>~~Rn~~|
|3.3 V PCI<br>~~Rn~~<br>~~a~~<br>~~**a**~~|3.3<br>~~Rn~~<br>|–<br>~~Rn~~<br>|18.82<br>~~Rn~~<br>|
|3.3 V PCI – Schmitt trigger<br>~~a~~<br>~~**a**~~|3.3<br>|–<br>|20.12<br>|
|3.3 V PCI-X<br>~~**a**a~~|3.3<br>|–<br>|18.82<br>|
|3.3 V PCI-X – Schmitt trigger<br>~~a~~|3.3<br>|–<br>|20.12<br>|
|**Voltage-Referenced**<br>~~a~~<br>~~ee~~||||
|3.3 V GTL<br>~~es~~|3.3<br>~~es~~<br>~~ee~~<br>~~es~~|2.90<br>~~es~~|8.23<br>~~es~~|
|2.5 V GTL<br>~~es~~|2.5<br>~~ee~~<br>~~es~~<br>~~es~~|2.13<br>~~es~~|4.78<br>~~es~~|
|3.3 V GTL+<br>~~eG~~|3.3<br>~~es~~<br>~~eG~~|2.81<br>~~eG~~|4.14<br>~~eG~~|
|2.5 V GTL+<br>~~es~~|2.5<br>~~es~~|2.57<br>~~es~~|3.71<br>~~es~~|
|HSTL (I)<br>~~es~~|1.5<br>~~es~~|0.17<br>~~es~~|2.03<br>~~es~~|
|HSTL (II)<br>~~es~~|1.5<br>~~es~~<br>~~ee~~|0.17<br>~~es~~|2.03<br>~~es~~|
|SSTL2 (I)<br>~~es~~|2.5<br>~~es~~<br>~~ee~~<br>~~es~~|1.38<br>~~es~~|4.48<br>~~es~~|
|SSTL2 (II)<br>~~es~~|2.5<br>~~ee~~<br>~~es~~<br>~~es~~|1.38<br>~~es~~|4.48<br>~~es~~|
|SSTL3 (I)<br>~~eG~~|3.3<br>~~es~~<br>~~eG~~|3.21<br>~~eG~~|9.26<br>~~eG~~|
|SSTL3 (II)<br>~~ss~~<br>~~ee~~|3.3<br>~~ss~~<br>|3.21<br>~~ss~~<br>|9.26<br>~~ss~~<br>|
|**Differential**<br>~~ee~~||||
|LVDS<br>~~eees~~|2.5<br>~~es~~<br>~~ee~~|2.26<br>~~es~~|1.50<br>~~es~~|
|LVPECL<br>~~es~~|3.3<br>~~es~~<br>~~ee~~|5.71<br>~~es~~|2.17<br>~~es~~|
_Notes:_
_1. PDC7 is the static power (where applicable) measured on VCCI._
_2. PAC9 is the total dynamic power measured on VCC and VCCI._
**Revision 8**
**3-18**
_DC and Power Characteristics_
_**Table 3-12 •**_ **Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings (continued)**
||**VCCI (V)**|**Static Power**<br>**PDC7 (mW)1**|**Dynamic Power**<br>**PAC9 (µW/MHz)2**|
|---|---|---|---|
|**Applicable to Advanced I/O Banks**||||
|**Single-Ended**<br>~~Ce~~||||
|3.3 V LVTTL/LVCMOS<br>~~Rs~~|3.3<br>~~Rs~~|–<br>~~Rs~~|16.69<br>~~Rs~~|
|2.5 V LVCMOS<br>~~es~~|2.5<br>~~es~~|–<br>~~es~~|5.12<br>~~es~~|
|1.8 V LVCMOS<br>~~es~~|1.8<br>~~es~~<br>~~ee~~|–<br>~~es~~|2.13<br>~~es~~|
|1.5 V LVCMOS (JESD8-11)<br>~~es~~|1.5<br>~~es~~<br>~~ee~~<br>~~es~~|–<br>~~es~~|1.45<br>~~es~~|
|3.3 V PCI<br>~~es~~|3.3<br>~~ee~~<br>~~es~~<br>~~es~~|–<br>~~es~~|18.11<br>~~es~~|
|3.3 V PCI-X|3.3<br>~~es~~|–|18.11|
|**Differential**<br>~~eo~~||||
|LVDS<br>~~es~~|2.5<br>~~es~~|2.26<br>~~es~~|1.20<br>~~es~~|
|LVPECL<br>~~es~~<br>~~eo~~|3.3<br>~~es~~<br>|5.72<br>~~es~~<br>|1.87<br>~~es~~<br>|
|**Applicable to Standard I/O Banks**<br>~~eo~~||||
|3.3 V LVTTL/LVCMOS<br>~~eoes~~|3.3<br>~~es~~|–<br>~~es~~|16.79<br>~~es~~|
|2.5 V LVCMOS<br>~~sO~~|2.5<br>~~sO~~|–<br>~~sO~~|5.19<br>~~sO~~|
|1.8 V LVCMOS<br>~~es~~|1.8<br>~~es~~|–<br>~~es~~|2.18<br>~~es~~|
|1.5 V LVCMOS (JESD8-11)<br>~~es~~|1.5<br>~~es~~|–<br>~~es~~|1.52<br>~~es~~|
_Notes:_
_1. PDC7 is the static power (where applicable) measured on VCCI._
_2. PAC9 is the total dynamic power measured on VCC and VCCI._
**3-19**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
_**Table 3-13 •**_ **Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings[1]**
||**CLOAD (pF)**|**VCCI (V)**|**Static Power**<br>**PDC8 (mW)2**|**Dynamic Power**<br>**PAC10 (µW/MHz)3**|
|---|---|---|---|---|
|**Applicable to Pro I/O Banks**|||||
|**Single-Ended**<br>~~ee~~|||||
|3.3 V LVTTL/LVCMOS<br>~~ss~~|35<br>~~ss~~|3.3<br>~~ss~~|–<br>~~ss~~|474.70<br>~~ss~~|
|2.5 V LVCMOS<br>~~es~~|35<br>~~es~~<br>~~es~~|2.5<br>~~es~~|–<br>~~es~~|270.73<br>~~es~~|
|1.8 V LVCMOS<br>~~ee~~|35<br>~~ee~~<br>~~es~~<br>~~es~~|1.8<br>~~ee~~|–<br>~~ee~~|151.78<br>~~ee~~|
|1.5 V LVCMOS (JESD8-11)<br>~~ee~~|35<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|1.5<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|104.55<br>~~ee~~|
|3.3 V PCI<br>~~ee~~|10<br>~~es~~<br>~~ee~~<br>~~es~~|3.3<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|204.61<br>~~ee~~|
|3.3 V PCI-X<br>~~ss~~|10<br>~~es ~~<br>~~ss~~|3.3<br> ~~ee~~<br>~~ss~~|–<br>~~ss~~|204.61<br>~~ss~~|
|**Voltage-Referenced**<br>~~eo~~<br>~~es~~|||||
|3.3 V GTL<br>~~ee~~|10<br>~~ee~~<br>~~es~~<br>~~es~~|3.3<br>~~ee~~|–<br>~~ee~~|24.08<br>~~ee~~|
|2.5 V GTL<br>~~ee~~|10<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|2.5<br>~~ee~~|–<br>~~ee~~|13.52<br>~~ee~~|
|3.3 V GTL+<br>~~ee~~|10<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|3.3<br>~~ee~~|–<br>~~ee~~|24.10<br>~~ee~~|
|2.5 V GTL+<br>~~ee~~|10<br>~~es~~<br>~~ee~~<br>~~es~~|2.5<br>~~ee~~|–<br>~~ee~~|13.54<br>~~ee~~|
|HSTL (I)<br>~~ss~~|20<br>~~es~~<br>~~ss~~<br>~~es~~|1.5<br>~~ss~~<br>~~es~~|7.08<br>~~ss~~|26.22<br>~~ss~~|
|HSTL (II)<br>~~es~~|20<br>~~es~~<br>~~es~~|1.5<br>~~es~~<br>~~es~~|13.88<br>~~es~~|27.22<br>~~es~~|
|SSTL2 (I)<br>~~es~~|30<br>~~es~~<br>~~es~~<br>~~es~~|2.5<br>~~es~~<br>~~es~~|16.69<br>~~es~~|105.56<br>~~es~~|
|SSTL2 (II)<br>~~ee~~|30<br>~~ee~~<br>~~es~~<br>~~es~~|2.5<br>~~ee~~|25.91<br>~~ee~~|116.60<br>~~ee~~|
|SSTL3 (I)<br>~~ee~~<br>~~eo~~|30<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>|3.3<br>~~ee~~<br>|26.02<br>~~ee~~<br>|114.87<br>~~ee~~<br>|
|SSTL3 (II)<br>~~re~~<br>~~eo~~|30<br>~~es~~<br>~~re~~<br>~~es~~<br>|3.3<br>~~re~~<br>|42.21<br>~~re~~<br>|131.76<br>~~re~~<br>|
|**Differential**<br>~~es~~<br>~~eo~~<br>~~es~~|||||
|LVDS<br>~~eoes~~|–<br>~~es~~<br>~~es~~<br>~~es~~|2.5<br>~~es~~<br>~~es~~|7.70<br>~~es~~|89.62<br>~~es~~|
|LVPECL<br>~~ee~~|–<br>~~es~~<br>~~ee~~|3.3<br>~~es~~<br>~~ee~~|19.42<br>~~ee~~|168.02<br>~~ee~~|
|**Applicable to Advanced I/O Banks**|||||
|**Single-Ended**<br>~~DR~~|||||
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~DR~~<br>~~Fa~~|35<br>~~eG~~|3.3<br>~~eG~~|–|468.67|
|2.5 V LVCMOS<br>~~DR~~<br>~~Fa~~<br>~~Pe~~|35<br>~~eG~~<br>~~GG~~|2.5<br>~~eG~~<br>~~GG~~|–<br>~~GG~~|267.48|
|1.8 V LVCMOS<br>~~Fa~~<br>~~Pe~~|35<br>~~eG~~<br>~~GG~~|1.8<br>~~eG~~<br>~~GG~~|–<br>~~GG~~|149.46|
|1.5 V LVCMOS (JESD8-11)<br>~~Pe ~~<br>~~Rs~~<br>~~Ps~~|35<br> ~~GG~~<br>~~Rs~~<br>~~eG~~|1.5<br>~~GG~~<br>~~Rs~~<br>~~eG~~|–<br>~~GG~~<br>~~Rs~~|103.12<br>~~Rs~~|
|3.3 V PCI<br>~~Ps~~<br>~~DR~~|10<br>~~eG~~|3.3<br>~~eG~~|–|201.02|
|3.3 V PCI-X<br>~~Ps ~~<br>~~DR~~|10<br> ~~eG~~|3.3<br>~~eG~~|–|201.02|
## _Notes:_
_1. Dynamic power consumption is given for standard load and software-default drive strength and output slew._
_2. PDC8 is the static power (where applicable) measured on VCCI._
_3. PAC10 is the total dynamic power measured on VCC and VCCI._
**Revision 8**
**3-20**
_DC and Power Characteristics_
_**Table 3-13 •**_ **Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings[1] (continued)**
||**CLOAD (pF)**|**VCCI (V)**|**Static Power**<br>**PDC8 (mW)2**|**Dynamic Power**<br>**PAC10 (µW/MHz)3**|
|---|---|---|---|---|
|**Differential**|||||
|LVDS|–|2.5|7.74|88.92|
|LVPECL|–|3.3|19.54|166.52|
|**Applicable to Standard I/O Banks**|||||
|**Single-Ended**|||||
|3.3 V LVTTL / 3.3 V LVCMOS|35|3.3|–|431.08|
|2.5 V LVCMOS|35|2.5|–|247.36|
|1.8 V LVCMOS|35|1.8|–|128.46|
|1.5 V LVCMOS (JESD8-11)|35|1.5|–|89.46|
_Notes:_
_1. Dynamic power consumption is given for standard load and software-default drive strength and output slew._
_2. PDC8 is the static power (where applicable) measured on VCCI._
_3. PAC10 is the total dynamic power measured on VCC and VCCI._
**3-21**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Dynamic Power Consumption of Various Internal Resources**
_**Table 3-14 •**_ **Different Components Contributing to the Dynamic Power Consumption in Fusion Devices**
|**Parameter**<br>~~a~~|**Definition**<br>~~ee~~|**Power Supply**<br>~~a~~<br>ee<br>|**Power Supply**<br>~~a~~<br>ee<br>|**Device-Specific**<br>**Dynamic Contributions**<br>~~**eeee**~~eeee|**Device-Specific**<br>**Dynamic Contributions**<br>~~**eeee**~~eeee|**Device-Specific**<br>**Dynamic Contributions**<br>~~**eeee**~~eeee|**Device-Specific**<br>**Dynamic Contributions**<br>~~**eeee**~~eeee|**Units**<br>ee<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Name**<br>~~a~~<br>~~ee~~|**Setting**<br>ee<br>~~ee~~|**AFS1500**<br>~~**ee**~~|**AFS600**<br>~~**ee**~~|**AFS250**<br>ee|**AFS090**<br>ee<br>~~ee~~||
|PAC1<br>~~a ~~<br>~~fo~~|Clock contribution of a Global<br>Rib<br> ~~ee~~<br>~~fo~~<br>~~et~~|VCC<br>~~a~~<br>~~ee~~<br>~~et~~|1.5 V<br>ee <br>~~ee~~<br>~~et~~|14.5<br> ~~**ee**~~ <br>~~et~~|12.8<br> ~~**ee**~~|11<br> ee|11<br> ee<br>~~ee~~|µW/MHz<br>ee<br>~~ee~~|
|PAC2<br> <br>~~fo~~<br>~~a~~|Clock contribution of a Global<br>Spine<br> ~~ee ~~<br>~~fo~~<br>~~et~~<br>~~ee~~|VCC<br> ~~ee~~<br>~~et~~<br>~~ee~~|1.5 V<br>~~ee~~<br>~~et~~<br>~~ee~~|2.5<br>~~et~~<br>~~eee~~|1.9<br>~~eee~~|1.6<br>~~eee~~|0.8<br>~~ee~~<br>~~eee~~|µW/MHz<br>~~ee~~<br>~~eee~~|
|PAC3<br>~~fo~~<br>~~a~~<br>~~a~~|Clock contribution of a VersaTile<br>row<br>~~fo~~<br>~~et~~<br>~~ee~~<br>~~ee~~|VCC<br>~~et~~<br>~~ee~~<br>~~ee~~|1.5 V<br>~~et~~<br>~~ee~~<br>~~ee~~|0.81<br>~~et~~<br>~~eee~~<br>~~ee~~||||µW/MHz<br>~~eee~~<br>~~ee~~|
|PAC4<br>~~a~~<br>~~a~~<br>~~AE~~|Clock contribution of a VersaTile<br>used as a sequential module<br>~~ee~~<br>~~ee~~<br>~~AEEE~~|VCC<br>~~ee~~<br>~~ee~~<br>~~EE~~|1.5 V<br>~~ee~~<br>~~ee~~<br>~~EE~~|0.11<br>~~eee~~<br>~~ee~~<br>~~oo~~||||µW/MHz<br>~~eee~~<br>~~ee~~<br>~~oo~~|
|PAC5<br>~~a ~~<br>~~AE~~|First contribution of a VersaTile<br>used as a sequential module<br> ~~ee ~~<br>~~AEEE~~|VCC<br> ~~ee~~<br>~~EE~~|1.5 V<br>~~ee~~<br>~~EE~~|0.07<br>~~ee ~~<br>~~oo~~||||µW/MHz<br> ~~ee~~<br>~~oo~~|
|PAC6<br>~~AE~~<br>~~a~~|Second<br>contribution<br>of<br>a<br>VersaTile used as a sequential<br>module<br>~~AEEE~~<br>~~ee~~|VCC<br>~~EE~~<br>~~ee~~|1.5 V<br>~~EE~~<br>~~ee~~|0.29<br>~~oo~~<br>||||µW/MHz<br>~~oo~~<br>|
|PAC7<br>~~AE~~<br>~~a~~|Contribution of a VersaTile used<br>as a combinatorial module<br>~~AE EE~~<br>~~ee~~|VCC<br>~~EE~~<br>~~ee~~|1.5 V<br>~~EE~~<br>~~eeeee~~|0.29<br>~~oo~~<br>~~eee~~||||µW/MHz<br>~~oo~~<br>~~eee~~|
|PAC8<br>~~a ~~<br>~~ee~~<br>~~ee~~|Average contribution of a routing<br>net<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|VCC<br> ~~ee~~<br>~~ee~~<br>~~eee~~|1.5 V<br>~~ee~~<br>~~ee~~<br>~~eee~~|0.70<br><br>~~ee~~<br>~~eee~~||||µW/MHz<br><br>~~ee~~<br>~~eee~~|
|PAC9<br>~~ee~~|Contribution of an I/O input pin<br>(standard dependent)<br>~~ee~~|VCCI<br>~~eee~~|SeeTable 3-12 on page 3-18<br>~~eee~~||||||
|PAC10<br>~~ee~~<br>~~a~~|Contribution of an I/O output pin<br>(standard dependent)<br>~~ee ~~<br>~~eee~~|VCCI<br> ~~eee~~<br>~~eee~~|SeeTable 3-13 on page 3-20<br>~~eee~~<br>~~eee~~||||||
|PAC11<br>~~eee~~<br>~~es~~|Average contribution of a RAM<br>block during a read operation<br>~~eee~~|VCC<br>~~eee~~<br>~~ee~~|1.5 V<br>~~eee~~<br>~~ee~~|25<br>~~eee~~<br>~~eee~~||||µW/MHz<br>~~eee~~<br>~~eee~~|
|PAC12<br>~~ee~~<br>~~es~~<br>~~AE~~|Average contribution of a RAM<br>block during a write operation<br>~~ee~~<br>~~tn~~<br>~~AE~~|VCC<br>~~ee~~<br>~~ee~~<br>~~Ge~~<br>|1.5 V<br>~~ee~~<br>~~ee~~<br>~~Gs~~<br>|30<br>~~ee~~<br>~~eee~~<br>~~Gn~~||||µW/MHz<br>~~ee~~<br>~~eee~~|
|PAC13<br>~~es~~<br>~~AE~~|Dynamic Contribution for PLL<br>~~tn~~<br>~~AE~~|VCC<br>~~ee~~<br>~~Ge~~<br>|1.5 V<br>~~ee~~<br>~~Gs~~<br>|2.6<br>~~eee~~<br>~~Gn~~||||µW/MHz<br>~~eee~~|
|PAC15<br>~~es~~<br>~~AE~~|Contribution of NVM block during<br>a read operation (F < 33MHz)<br>~~tn~~<br>~~AEEE~~|VCC<br>~~ee~~<br>~~Ge~~<br>~~EE~~|1.5 V<br>~~ee~~<br>~~Gs~~<br>~~EE~~|358<br>~~eee~~<br>~~Gn~~<br>~~oo~~||||µW/MHz<br>~~eee~~<br>~~oo~~|
|PAC16<br>~~AE~~|1st contribution of NVM block<br>during a read operation (F > 33<br>MHz)<br>~~tn~~<br>~~AE EE~~|VCC<br>~~Ge~~<br>~~EE~~|1.5 V<br>~~Gs~~<br>~~EE~~|12.88<br>~~Gn~~<br>~~oo~~||||mW<br>~~oo~~|
|PAC17<br>~~AE~~<br>~~pp~~|2nd contribution of NVM block<br>during a read operation (F > 33<br>MHz)<br>~~tn~~<br>~~AE ~~<br>~~pp~~|VCC<br>~~Ge~~<br><br>~~pp~~|1.5 V<br>~~Gs~~<br><br>~~pp~~|4.8<br>~~Gn~~<br>~~pp~~||||µW/MHz<br>~~pp~~|
|PAC18<br>~~pp~~<br>~~a~~|Crystal Oscillator contribution<br>~~pp~~<br>|VCC33A<br>~~pp~~<br>Gr**e**s|3.3 V<br>~~pp~~<br>ts|0.63<br>~~pp~~<br>~~Ge~~||||mW<br>~~pp~~|
|PAC19<br>~~rs~~<br>~~a~~|RC Oscillator contribution<br>~~rs~~<br>~~ee~~|VCC33A<br>~~rs~~<br>Gr**e**s|3.3 V<br>~~rs~~<br>ts<br>~~e~~|3.3<br>~~rs~~<br>~~Ge~~<br>~~ee~~||||mW<br>~~rs~~<br>~~ee~~<br>~~ee~~|
|PAC20<br>~~a ~~|Analog Block dynamic power<br>contribution of ADC<br> ~~ee~~|VCC<br>Gr**e**s|1.5 V<br> ts<br>~~e~~|3<br>~~Ge~~<br>~~ee~~||||mW<br>~~ee~~<br>~~ee~~|
**Revision 8**
**3-22**
_DC and Power Characteristics_
## **Static Power Consumption of Various Internal Resources**
_**Table 3-15 •**_ **Different Components Contributing to the Static Power Consumption in Fusion Devices**
|**Parameter**<br>~~ee~~|**Definition**<br>~~ee~~|**Power**<br>**Supply**<br>~~ee~~|~~ee~~<br>~~a~~|**Device-Specific Static Contributions**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~|**Device-Specific Static Contributions**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~|**Device-Specific Static Contributions**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~|**Device-Specific Static Contributions**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~|**Units**<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
||||~~ee~~<br>~~a~~|**AFS1500 **<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|**AFS600**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**AFS250**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**AFS090**<br>~~ee~~<br>~~ee~~<br>~~ee~~||
|PDC1<br>~~ee~~|Core static power contribution in<br>operating mode<br>~~ee~~|VCC<br>~~ee~~|1.5 V<br>~~a~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|7.5<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.50<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.00<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mW<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PDC2<br>~~ee~~<br>~~a~~|Device static power contribution in<br>standby mode<br>~~ee~~|VCC33A<br>~~ee~~<br>~~ee~~|3.3 V<br>~~ee~~<br>~~ee ee~~|0.66<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||||mW<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PDC3<br>~~ee~~<br>~~a~~|Device static power contribution in<br>sleep mode<br>~~ee~~<br>~~ee~~|VCC33A<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.3 V<br>~~ee~~<br>~~ee ee~~|0.03<br>~~ee~~<br>~~ee~~<br>~~ee~~||||mW<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PDC4<br>~~a~~<br>~~ee~~|NVM static power contribution<br>~~ee~~<br>~~ee~~|VCC<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.5 V<br>~~ee ee~~<br>~~ee~~|1.19<br>~~ee~~<br>~~ee~~||||mW<br>~~ee~~<br>~~ee~~|
|PDC5<br>~~ee~~<br>~~a~~|Analog<br>Block<br>static<br>power<br>contribution of ADC<br>~~ee ~~<br>~~ee~~<br>~~ee~~|VCC33A<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.3 V<br>~~ee~~<br>~~ee~~|8.25<br>~~ee~~<br>~~ee~~||||mW<br>~~ee~~<br>~~ee~~|
|PDC6<br>~~ee~~<br>~~a~~|Analog<br>Block<br>static<br>power<br>contribution per Quad<br>~~ee~~<br>~~ee~~|VCC33A<br>~~ee~~<br>~~ee~~|3.3 V<br>~~ee~~<br>~~ee~~|3.3<br>~~ee~~<br>~~ee~~||||mW<br>~~ee~~<br>~~ee~~|
|PDC7<br>~~a~~<br>~~ee~~<br>~~a~~|Static contribution per input pin –<br>standard dependent contribution<br>~~ee~~<br>~~ee~~<br>~~a~~|VCCI<br>~~ee~~<br>~~ee~~|SeeTable 3-12 on page 3-18<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||||||
|PDC8<br>~~a~~<br>~~Rs~~|Static contribution per input pin –<br>standard dependent contribution<br>~~a~~<br>~~ee~~|VCCI<br>~~eG~~|SeeTable 3-13 on page 3-20<br>~~ee~~<br>~~eG~~||||||
|PDC9<br>~~a~~<br>~~Rs~~|Static contribution for PLL<br>~~a~~<br>~~ee~~|VCC<br>~~eG~~|1.5 V<br>~~eG~~|2.55<br>~~ee~~<br>~~eG~~||||mW<br>~~ee~~|
## **Power Calculation Methodology**
This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.
The power calculation methodology described below uses the following variables:
- The number of PLLs as well as the number and the frequency of each output clock generated
- The number of combinatorial and sequential cells used in the design
- The internal clock frequencies
- The number and the standard of I/O pins used in the design
- The number of RAM blocks used in the design
- The number of NVM blocks used in the design
- The number of Analog Quads used in the design
- Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-16 on page 3-27.
- Enable rates of output buffers—guidelines are provided for typical applications in Table 3-17 on page 3-27.
- Read rate and write rate to the RAM—guidelines are provided for typical applications in Table 3-17 on page 3-27.
- Read rate to the NVM blocks
The calculation should be repeated for each clock domain defined in the design.
**3-23**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Methodology**_
## _**Total Power Consumption—PTOTAL**_
## _**Operating Mode, Standby Mode, and Sleep Mode**_
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
## _**Total Static Power Consumption—PSTAT**_
## _**Operating Mode**_
PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5+ (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) + (NPLLS * PDC9)
NNVM-BLOCKS is the number of NVM blocks available in the device.
NQUADS is the number of Analog Quads used in the design.
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
NPLLS is the number of PLLs available in the device.
## _**Standby Mode**_
PSTAT = PDC2
## _**Sleep Mode**_
PSTAT = PDC3
## _**Total Dynamic Power Consumption—PDYN**_
## _**Operating Mode**_
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC-OSC + PAB
## _**Standby Mode**_
PDYN = PXTL-OSC
## _**Sleep Mode**_
PDYN = 0 W
## _**Global Clock Dynamic Contribution—PCLOCK**_
## _**Operating Mode**_
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the “Spine Architecture” section of the Global Resources chapter in the _Fusion and Extended Temperature Fusion FPGA Fabric User's Guide_ .
NROW is the number of VersaTile rows used in the design—guidelines are provided in the “Spine Architecture” section of the Global Resources chapter in the _Fusion and Extended Temperature Fusion FPGA Fabric User's Guide_ .
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
## _**Standby Mode and Sleep Mode**_
PCLOCK = 0 W
## _**Sequential Cells Dynamic Contribution—PS-CELL**_
## _**Operating Mode**_
**Revision 8**
**3-24**
_DC and Power Characteristics_
PS-CELL = NS-CELL * (PAC5 + (1 / 2) * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27. FCLK is the global clock signal frequency.
## _**Standby Mode and Sleep Mode**_
PS-CELL = 0 W
## _**Combinatorial Cells Dynamic Contribution—PC-CELL**_
## _**Operating Mode**_
PC-CELL = NC-CELL* (1 / 2) * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27. FCLK is the global clock signal frequency.
## _**Standby Mode and Sleep Mode**_
PC-CELL = 0 W
Routing Net Dynamic Contribution—PNET
## _**Operating Mode**_
PNET = (NS-CELL + NC-CELL) * (1 / 2) * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27. FCLK is the global clock signal frequency.
## _**Standby Mode and Sleep Mode**_
PNET = 0 W
## _**I/O Input Buffer Dynamic Contribution—PINPUTS**_
## _**Operating Mode**_
PINPUTS = NINPUTS * (2 / 2) * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 3-16 on page 3-27.
FCLK is the global clock signal frequency.
## _**Standby Mode and Sleep Mode**_
PINPUTS = 0 W
## _**I/O Output Buffer Dynamic Contribution—POUTPUTS**_
## _**Operating Mode**_
POUTPUTS = NOUTPUTS * (2 / 2) * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 3-16 on page 3-27.
1 is the I/O buffer enable rate—guidelines are provided in Table 3-17 on page 3-27.
FCLK is the global clock signal frequency.
## _**Standby Mode and Sleep Mode**_
POUTPUTS = 0 W
**3-25**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**RAM Dynamic Contribution—PMEMORY**_
## _**Operating Mode**_
PMEMORY = (NBLOCKS * PAC11 * 2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * 3 * FWRITE-CLOCK)
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations—guidelines are provided in Table 3-17 on page 3-27.
3 the RAM enable rate for write operations—guidelines are provided in Table 3-17 on page 3-27.
FWRITE-CLOCK is the memory write clock frequency.
## _**Standby Mode and Sleep Mode**_
PMEMORY = 0 W
## _**PLL/CCC Dynamic Contribution—PPLL**_
## _**Operating Mode**_
PPLL = PAC13 * FCLKOUT
FCLKIN is the input clock frequency.
FCLKOUT is the output clock frequency.[1]
## _**Standby Mode and Sleep Mode**_
PPLL = 0 W
## _**Nonvolatile Memory Dynamic Contribution—PNVM**_
## _**Operating Mode**_
The NVM dynamic power consumption is a piecewise linear function of frequency.
PNVM = NNVM-BLOCKS * 4 * PAC15 * FREAD-NVM when FREAD-NVM 33 MHz,
PNVM = NNVM-BLOCKS * 4 *(PAC16 + PAC17 * FREAD-NVM when FREAD-NVM > 33 MHz
NNVM-BLOCKS is the number of NVM blocks used in the design (2 inAFS600).
4 is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state).
FREAD-NVM is the NVM read clock frequency.
## _**Standby Mode and Sleep Mode**_
PNVM = 0 W
## _**Crystal Oscillator Dynamic Contribution—PXTL-OSC**_
## _**Operating Mode**_
PXTL-OSC = PAC18
## _**Standby Mode**_
PXTL-OSC = PAC18
## _**Sleep Mode**_
PXTL-OSC = 0 W
> _1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula output clock by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution._
**Revision 8**
**3-26**
_DC and Power Characteristics_
## _**RC Oscillator Dynamic Contribution—PRC-OSC**_
## _**Operating Mode**_
PRC-OSC = PAC19
## _**Standby Mode and Sleep Mode**_
PRC-OSC = 0 W
## _**Analog System Dynamic Contribution—PAB**_
## _**Operating Mode**_
PAB = PAC20
## _**Standby Mode and Sleep Mode**_
PAB = 0 W
## _**Guidelines**_
## _**Toggle Rate Definition**_
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some examples:
- The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock frequency.
- The average toggle rate of an 8-bit counter is 25%:
- Bit 0 (LSB) = 100%
- Bit 1 = 50%
- Bit 2 = 25%
-
- …
- Bit 7 (MSB) = 0.78125%
- Average toggle rate = (100% + 50% + 25% + 12.5% +. . . 0.78125%) / 8.
## _**Enable Rate Definition**_
Output enable rate is the average percentage of time during which tristate outputs are enabled. When non-tristate output buffers are used, the enable rate should be 100%.
_**Table 3-16 •**_ **Toggle Rate Guidelines Recommended for Power Calculation**
|**Component**|**Definition**|**Guideline**|
|---|---|---|
|1|Toggle rate of VersaTile outputs|10%|
|2|I/O buffer toggle rate|10%|
_**Table 3-17 •**_ **Enable Rate Guidelines Recommended for Power Calculation**
|**Component**|**Definition**|**Guideline**|
|---|---|---|
|1|I/O output buffer enable rate|100%|
|2|RAM enable rate for read operations|12.5%|
|3|RAM enable rate for write operations|12.5%|
|4|NVM enable rate for read operations|0%|
**3-27**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**Example of Power Calculation**_
This example considers a shift register with 5,000 storage tiles, including a counter and memory that stores analog information. The shift register is clocked at 50 MHz and stores and reads information from a RAM.
The device used is a commercial AFS600 device operating in typical conditions.
The calculation below uses the power calculation methodology previously presented and shows how to determine the dynamic and static power consumption of resources used in the application.
Also included in the example is the calculation of power consumption in operating, standby, and sleep modes to illustrate the benefit of power-saving modes.
## _**Global Clock Contribution—PCLOCK**_
FCLK = 50 MHz Number of sequential VersaTiles: NS-CELL = 5,000 Estimated number of Spines: NSPINES = 5 Estimated number of Rows: NROW = 313
## _**Operating Mode**_
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
PCLOCK = (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50
PCLOCK = 41.28 mW
## _**Standby Mode and Sleep Mode**_
PCLOCK = 0 W
## _**Logic—Sequential Cells, Combinational Cells, and Routing Net Contributions—PS-CELL,**_
## _**PC-CELL, and PNET**_
FCLK = 50 MHz Number of sequential VersaTiles: NS-CELL = 5,000 Number of combinatorial VersaTiles: NC-CELL = 6,000 Estimated toggle rate of VersaTile outputs: 1 = 0.1 (10%)
## _**Operating Mode**_
PS-CELL = NS-CELL * (PAC5+ (1 / 2) * PAC6) * FCLK PS-CELL = 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50 PS-CELL = 21.13 mW
PC-CELL = NC-CELL* (1 / 2) * PAC7 * FCLK PC-CELL = 6,000 * (0.1 / 2) * 0.00029 * 50 PC-CELL = 4.35 mW PNET = (NS-CELL + NC-CELL) * (1 / 2) * PAC8 * FCLK PNET = (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50 PNET = 19.25 mW
PLOGIC = PS-CELL + PC-CELL + PNET PLOGIC = 21.13 mW + 4.35 mW + 19.25 mW PLOGIC = 44.73 mW
## _**Standby Mode and Sleep Mode**_
**Revision 8**
**3-28**
_DC and Power Characteristics_
PS-CELL = 0 W PC-CELL = 0 W PNET = 0 W PLOGIC = 0 W
## _**I/O Input and Output Buffer Contribution—PI/O**_
This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA–capable, configured with high output slew and driving a 35 pF output load.
FCLK = 50 MHz Number of input pins used: NINPUTS = 30 Number of output pins used: NOUTPUTS = 40 Estimated I/O buffer toggle rate: 2 = 0.1 (10%) Estimated IO buffer enable rate: 1 = 1 (100%)
## _**Operating Mode**_
PINPUTS = NINPUTS * (2 / 2) * PAC9 * FCLK PINPUTS = 30 * (0.1 / 2) * 0.01739 * 50 PINPUTS = 1.30 mW
POUTPUTS = NOUTPUTS * (2 / 2) * 1 * PAC10 * FCLK POUTPUTS = 40 * (0.1 / 2) * 1 * 0.4747 * 50 POUTPUTS = 47.47 mW
PI/O = PINPUTS + POUTPUTS PI/O = 1.30 mW + 47.47 mW PI/O = 48.77 mW
## _**Standby Mode and Sleep Mode**_
PINPUTS = 0 W POUTPUTS = 0 W
PI/O = 0 W
## _**RAM Contribution—PMEMORY**_
Frequency of Read Clock: FREAD-CLOCK = 10 MHz Frequency of Write Clock: FWRITE-CLOCK = 10 MHz Number of RAM blocks: NBLOCKS = 20 Estimated RAM Read Enable Rate: 2 = 0.125 (12.5%) Estimated RAM Write Enable Rate: 3 = 0.125 (12.5%)
## _**Operating Mode**_
PMEMORY = (NBLOCKS * PAC11 * 2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * 3 * FWRITE-CLOCK) PMEMORY = (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10) PMEMORY = 1.38 mW
## _**Standby Mode and Sleep Mode**_
PMEMORY = 0 W
**3-29**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## _**PLL/CCC Contribution—PPLL**_
PLL is not used in this application. PPLL = 0 W
_**Nonvolatile Memory—PNVM**_
Nonvolatile memory is not used in this application. PNVM = 0 W
## _**Crystal Oscillator—PXTL-OSC**_
The application utilizes standby mode. The crystal oscillator is assumed to be active.
## _**Operating Mode**_
PXTL-OSC = PAC18 PXTL-OSC = 0.63 mW
## _**Standby Mode**_
PXTL-OSC = PAC18 PXTL-OSC = 0.63 mW
## _**Sleep Mode**_
PXTL-OSC = 0 W
## _**RC Oscillator—PRC-OSC**_
## _**Operating Mode**_
PRC-OSC = PAC19 PRC-OSC = 3.30 mW
## _**Standby Mode and Sleep Mode**_
PRC-OSC = 0 W
## _**Analog System—PAB**_
Number of Quads used: NQUADS = 4
## _**Operating Mode**_
PAB = PAC20 PAB = 3.00 mW
## _**Standby Mode and Sleep Mode**_
PAB = 0 W
## _**Total Dynamic Power Consumption—PDYN**_
## _**Operating Mode**_
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC-OSC + PAB
PDYN = 41.28 mW + 21.1 mW + 4.35 mW + 19.25 mW + 1.30 mW + 47.47 mW + 1.38 mW + 0 + 0 + 0.63 mW + 3.30 mW + 3.00 mW
PDYN = 143.06 mW
## _**Standby Mode**_
PDYN = PXTL-OSC
PDYN = 0.63 mW
## _**Sleep Mode**_
PDYN = 0 W
**Revision 8**
**3-30**
_DC and Power Characteristics_
## _**Total Static Power Consumption—PSTAT**_
Number of Quads used: NQUADS = 4
Number of NVM blocks available (AFS600): NNVM-BLOCKS = 2 Number of input pins used: NINPUTS = 30
Number of output pins used: NOUTPUTS = 40
## _**Operating Mode**_
PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5 + (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8)
PSTAT = 7.50 mW + (2 * 1.19 mW) + 8.25 mW + (4 * 3.30 mW) + (30 * 0.00) + (40 * 0.00)
PSTAT = 31.33 mW
## _**Standby Mode**_
PSTAT = PDC2
PSTAT = 0.03 mW
## _**Sleep Mode**_
PSTAT = PDC3
PSTAT = 0.03 mW
## _**Total Power Consumption—PTOTAL**_
In operating mode, the total power consumption of the device is 174.39 mW:
PTOTAL = PSTAT + PDYN
PTOTAL = 143.06 mW + 31.33 mW
PTOTAL = 174.39 mW
In standby mode, the total power consumption of the device is limited to 0.66 mW:
PTOTAL = PSTAT + PDYN
PTOTAL = 0.03 mW + 0.63 mW
PTOTAL = 0.66 mW
In sleep mode, the total power consumption of the device drops as low as 0.03 mW:
PTOTAL = PSTAT + PDYN
PTOTAL = 0.03 mW
**3-31**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Power Consumption**
_**Table 3-18 •**_ **Power Consumption**
|**_Table 3-18 •_Power Consumption**<br>~~es~~|**Power Consumption**||||||
|---|---|---|---|---|---|---|
|**Parameter**<br>~~es~~<br>~~CO~~|**Description**<br>|**Condition**|**Min.**|**Typical**|**Max.**|**Units**|
|**Crystal Oscillator**<br>~~es~~<br>~~COaee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|||||||
|ISTBXTAL<br>~~COa~~<br>~~Pf~~|Standby Current of Crystal<br>Oscillator<br>~~ee~~<br>~~Pf~~|~~ee~~<br>~~es~~<br>~~a~~<br>|~~ee~~<br>~~ee~~<br>~~a~~<br>|10<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~<br>|µA<br>~~ee~~<br>|
|IDYNXTAL<br>~~a ~~<br>~~Pf~~|Operating Current<br> ~~ee~~<br>~~Pf ~~|RC<br>~~ee~~<br>~~es~~<br>~~a~~<br>~~ESE~~|~~ee~~<br>~~ee~~<br>~~a~~<br>~~ESE~~|0.6<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ESE~~|~~ee~~<br>~~ee~~<br>~~ESE~~|mA<br>~~ee~~<br>~~ESE~~|
|||0.032–0.2<br>~~es ~~<br>~~a~~<br>~~ESE~~|~~ee~~<br>~~a~~<br>~~ESE~~|0.19<br>~~ee ~~<br>~~ee~~<br>~~ESE~~|~~ee~~<br>~~ee~~<br>~~ESE~~|mA<br>~~ESE~~|
|||0.2–2.0<br>~~a~~<br>~~ESE~~<br>~~es~~|~~a~~<br>~~ESE~~|0.6<br>~~ee~~<br>~~ESE~~<br>~~ee~~|~~ee~~<br>~~ESE~~<br>~~ee~~|mA<br>~~ESE~~|
|||2.0–20.0<br>~~a~~<br> ~~ESE~~<br>~~es~~|~~a~~<br>~~ESE~~|0.6<br>~~ee~~<br>~~ESE~~<br>~~ee~~|~~ee~~<br>~~ESE~~<br>~~ee~~|mA<br>~~ESE~~|
|**RC Oscillator**<br>~~a a~~<br>~~ee~~<br>~~Pf ~~<br>~~es~~<br>~~ee ee~~<br>~~CO~~<br>~~Rs~~|||||||
|IDYNRC<br>~~Rs~~|Operating Current|||1||mA|
|**ACM**<br>~~Rs~~<br>~~Ce~~<br>~~aeeeeee ee~~|||||||
|~~a~~<br>~~a~~|Operating<br>Current<br>(fixed<br>clock)<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|200<br>~~ee ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|µA/MHz<br>~~ee~~<br>~~ee~~|
|~~a ~~<br>~~a~~|Operating<br>Current<br>(user<br>clock)<br> ~~ee ~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~ee~~<br>~~ee~~|30<br>~~ee ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|**NVM System**<br>~~a~~<br>~~ee ee ee ee~~<br>~~eeeeee~~~~**e**e~~<br>|~~|Ef~~|||||||
|| ~~|~~<br>~~a~~|NVM Array Operating Power<br>~~|~~<br>~~a~~|Idle<br>~~ee~~<br>~~Ef~~|~~ee~~<br>~~Ef~~|795<br>~~ee~~<br>~~Ef~~|~~**e**e~~<br>~~Ef~~|µA|
|||Read<br>operation<br>~~ee~~<br>~~Ef~~|~~ee~~<br>~~Ef~~|See<br>Table 3-15 on<br>page 3-23.<br>~~ee~~<br>~~Ef~~|~~**e**e~~<br>~~Ef~~|See<br>Table 3-15 on<br>page 3-23.|
|||Erase<br>~~ee~~<br>~~Ef~~<br>~~a~~|~~ee~~<br>~~Ef~~<br>ee|900<br>~~ee~~<br>~~Ef~~<br>~~ee~~|~~**e**e~~<br>~~Ef~~<br>ee|µA|
|||Write<br>~~ee ~~<br>~~Ef~~<br>~~a~~<br>~~ee~~|~~ee ~~<br>~~Ef~~<br>ee<br>~~ee~~|900<br> ~~ee ~~<br>~~Ef~~<br>~~ee~~<br>~~ee~~|~~**e**e~~<br>~~Ef~~<br>ee|µA|
|PNVMCTRL<br> ~~|~~<br>~~a ~~|NVM<br>Controller<br>Operating<br>Power<br>~~| ~~<br> ~~a~~|~~Ef~~<br>~~a~~ <br>~~ee~~|~~Ef~~<br> ee<br>~~ee~~|20<br>~~Ef~~<br>~~ee~~ <br>~~ee~~|~~Ef~~<br> ee|µW/MHz|
**Revision 8**
**3-32**
## **4 – Package Pin Assignments**
## **QN108**
**==> picture [344 x 325] intentionally omitted <==**
**----- Start of picture text -----**<br>
A44 A56<br>B41 B52<br>Pin A1 Mark<br>A43 3 IO OOOOOOOUOOY G A1<br>B40 F HUOOOOOOOOOOOYER B1<br>oO Oo Oo Oo<br>Oo Oo Oo Oo<br>oO Oo Oo Oo<br>oO Oo Oo Oo<br>Oo oO Oo Oo<br>oO Oo Oo Oo<br>oO Oo Oo Oo<br>oO oO Oo Oo<br>Oo Oo Oo Oo<br>oO Oo Oo Oo<br>Oo Oo<br>OF =o B13<br>A14<br>B27 S H pooooooooOoooOgS<br>A29 A poooooooooood!Gg<br>B26 B14<br>A28 A15<br>**----- End of picture text -----**<br>
_Note: The die attach paddle center of the package is tied to ground (GND)._
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**Revision 8**
**4-1**
_Package Pin Assignments_
|**QN108**<br>**Pin Number**<br>**AFS090 Function**<br>A1<br>NC<br>A2<br>GNDQ<br>A3<br>GAA2/IO52PDB3V0<br>A4<br>GND<br>A5<br>GFA1/IO47PDB3V0<br>A6<br>GEB1/IO45PDB3V0<br>A7<br>VCCOSC<br>A8<br>XTAL2<br>A9<br>GEA1/IO44PPB3V0<br>A10<br>GEA0/IO44NPB3V0<br>A11<br>GEB2/IO42PDB3V0<br>A12<br>VCCNVM<br>A13<br>VCC15A<br>A14<br>PCAP<br>A39<br>GND<br>A40<br>GCB1/IO35PDB1V0<br>A41<br>GCB2/IO33PDB1V0<br>A42<br>GBA2/IO31PDB1V0<br>A43<br>NC<br>A44<br>GBA1/IO30RSB0V0<br>A45<br>GBB1/IO28RSB0V0<br>A46<br>GND<br>A47<br>VCC<br>A48<br>GBC1/IO26RSB0V0<br>A49<br>IO21RSB0V0<br>A50<br>IO19RSB0V0<br>A51<br>IO09RSB0V0<br>A52<br>GAC0/IO04RSB0V0<br>**QN108**<br>**Pin Number**<br>**AFS090 Function**<br>~~re ~~i**e**<br>~~s~~<br>~~a so~~<br>~~es~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ae~~<br>~~ee ~~i<br>~~eses~~<br>~~a so es en~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~es~~<br>~~ss~~<br>~~a ee ~~i<br>~~eses se~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~es~~<br>~~ss~~<br>~~a ee ~~i<br>~~eses se~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~es~~<br>~~ss~~<br>~~a ee ~~i<br>~~esss~~<br>~~ae~~<br>~~ee ~~be ~~es es ~~Os<br>~~a ee ~~ie~~es~~<br>~~ss~~|**QN108**<br>**Pin Number**<br>**AFS090 Function**<br>A1<br>NC<br>A2<br>GNDQ<br>A3<br>GAA2/IO52PDB3V0<br>A4<br>GND<br>A5<br>GFA1/IO47PDB3V0<br>A6<br>GEB1/IO45PDB3V0<br>A7<br>VCCOSC<br>A8<br>XTAL2<br>A9<br>GEA1/IO44PPB3V0<br>A10<br>GEA0/IO44NPB3V0<br>A11<br>GEB2/IO42PDB3V0<br>A12<br>VCCNVM<br>A13<br>VCC15A<br>A14<br>PCAP<br>A39<br>GND<br>A40<br>GCB1/IO35PDB1V0<br>A41<br>GCB2/IO33PDB1V0<br>A42<br>GBA2/IO31PDB1V0<br>A43<br>NC<br>A44<br>GBA1/IO30RSB0V0<br>A45<br>GBB1/IO28RSB0V0<br>A46<br>GND<br>A47<br>VCC<br>A48<br>GBC1/IO26RSB0V0<br>A49<br>IO21RSB0V0<br>A50<br>IO19RSB0V0<br>A51<br>IO09RSB0V0<br>A52<br>GAC0/IO04RSB0V0<br>**QN108**<br>**Pin Number**<br>**AFS090 Function**<br>~~re ~~i**e**<br>~~s~~<br>~~a so~~<br>~~es~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ae~~<br>~~ee ~~i<br>~~eses~~<br>~~a so es en~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~es~~<br>~~ss~~<br>~~a ee ~~i<br>~~eses se~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~es~~<br>~~ss~~<br>~~a ee ~~i<br>~~eses se~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~es~~<br>~~ss~~<br>~~a ee ~~i<br>~~esss~~<br>~~ae~~<br>~~ee ~~be ~~es es ~~Os<br>~~a ee ~~ie~~es~~<br>~~ss~~|B21<br>AC2<br>B22<br>ATRTN1<br>B23<br>AG3<br>B24<br>AV3<br>B25<br>VCC33A<br>B26<br>VAREF<br>B27<br>PUB<br>B28<br>VCC33A<br>B29<br>PTBASE<br>B30<br>VCCNVM<br>B31<br>VCC<br>B32<br>TDI<br>B33<br>TDO<br>B34<br>VJTAG<br>**QN108**<br>**Pin Number**<br>**AFS090 Function**<br>~~se~~<br>~~se~~|
|---|---|---|
|A15<br>NC<br>A53<br>VCCIB0||B35<br>GDC0/IO38NDB1V|
|A16<br>GNDA<br>A17<br>AV0<br>A18<br>AG0<br>A19<br>ATRTN0<br>A20<br>AT1<br>A21<br>AC1<br>A22<br>AV2<br>A23<br>AG2<br>A24<br>AT2<br>A25<br>AT3<br>A26<br>AC3<br>A27<br>GNDAQ<br>A28<br>ADCGNDREF<br>A29<br>NC<br>A30<br>GNDA<br>A31<br>PTEM<br>A32<br>GNDNVM<br>A54<br>GND<br>A55<br>GAB0/IO02RSB0V0<br>A56<br>GAA0/IO00RSB0V0<br>B1<br>VCOMPLA<br>B2<br>VCCIB3<br>B3<br>GAB2/IO52NDB3V0<br>B4<br>VCCIB3<br>B5<br>GFA0/IO47NDB3V0<br>B6<br>GEB0/IO45NDB3V0<br>B7<br>XTAL1<br>B8<br>GNDOSC<br>B9<br>GEC2/IO43PSB3V0<br>B10<br>GEA2/IO42NDB3V0<br>B11<br>VCC<br>B12<br>GNDNVM<br>B13<br>NCAP<br>B14<br>VCC33PMP<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~eeee~~<br>~~a Ca~~<br>9~~OC~~<br>~~a~~<br>~~a~~<br>~~es~~<br>~~a~~<br>~~a~~<br>~~es~~<br>~~a~~<br>~~a~~<br>~~es~~<br>~~a~~<br>~~a~~<br>~~es~~<br>~~a~~||0<br>B36<br>VCCIB1<br>B37<br>GCB0/IO35NDB1V0<br>B38<br>GCC2/IO33NDB1V<br>0<br>B39<br>GBB2/IO31NDB1V0<br>B40<br>VCCIB1<br>B41<br>GNDQ<br>B42<br>GBA0/IO29RSB0V0<br>B43<br>VCCIB0<br>B44<br>GBB0/IO27RSB0V0<br>B45<br>GBC0/IO25RSB0V0<br>B46<br>IO20RSB0V0<br>B47<br>IO10RSB0V0<br>B48<br>GAC1/IO05RSB0V0<br>B49<br>GAB1/IO03RSB0V0<br>B50<br>VCC<br>B51<br>GAA1/IO01RSB0V0<br>~~J~~<br>~~a~~|
|A33<br>VPUMP<br>A34<br>TCK<br>A35<br>TMS<br>A36<br>TRST<br>A37<br>GDB1/IO39PSB1V0<br>A38<br>GDC1/IO38PDB1V0<br>B15<br>VCC33N<br>B16<br>GNDAQ<br>B17<br>AC0<br>B18<br>AT0<br>B19<br>AG1<br>B20<br>AV1<br>B52<br>VCCPLA<br>~~aee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~<br>~~**es**~~<br>~~ae~~|||
**4-2**
**Revision 8**
_Package Pin Assignments_
## **QN180**
**==> picture [387 x 348] intentionally omitted <==**
**----- Start of picture text -----**<br>
A49 A64<br>B46 B60<br>C43 C56<br>Pin A1 Mark<br>D4 a SAMOOOOOOOOOOOOOOe roe E D1<br>A48 B45C42 aCor MOOOOOOOOOOO0 =Se C1 B1 A1<br>Og O90<br>O7,u Ou<br>O_o Ou<br>O,u O70<br>Ou Ou<br>Ondo Ou<br>Ou O70<br>Ou Ou<br>Ondo Ou<br>OU OU<br>O7,u Ou<br>Ou O70<br>C29 C14<br>B31 = g al 4 et B15<br>A33 A16<br>| MOOOOOOOOOOOOG] Ez<br>D3 D2<br>i an fn ooo oooh<br>"Yt GIO OOOO OOOO OOOO i<br>Optional Corner<br>Pad (4X) C28 C15<br>B30 B16<br>A32 A17<br>**----- End of picture text -----**<br>
_Note: The die attach paddle center of the package is tied to ground (GND)._
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-3**
**Revision 8**
_Package Pin Assignments_
|**QN180**<br>**QN180**<br>~~es~~|
|---|
|**Pin Number**<br>**AFS090 Function**<br>**AFS250 Function**<br>A1<br>GNDQ<br>GNDQ<br>A37<br>VPUMP<br>VPUMP<br>**Pin Number**<br>**AFS090 Function**<br>**AFS250 Function**<br>~~aPe0~~|
|A2<br>VCCIB3<br>VCCIB3<br>A38<br>TDI<br>TDI<br>~~Re0~~|
|A3<br>GAB2/IO52NDB3V0<br>IO74NDB3V0<br>A39<br>TDO<br>TDO<br>~~ee0~~|
|A4<br>GFA2/IO51NDB3V0<br>IO71NDB3V0<br>A40<br>VJTAG<br>VJTAG<br>~~a~~|
|A5<br>GFC2/IO50NDB3V0<br>IO69NPB3V0<br>A6<br>VCCIB3<br>VCCIB3<br>A7<br>GFA1/IO47PPB3V0<br>GFB1/IO67PPB3V0<br>A8<br>GEB0/IO45NDB3V0<br>NC<br>A41<br>GDB1/IO39PPB1V0 GDA1/IO54PPB1V0<br>A42<br>GDC1/IO38PDB1V0 GDB1/IO53PDB1V0<br>A43<br>VCC<br>VCC<br>A44<br>GCB0/IO35NPB1V0 GCB0/IO48NPB1V0<br>~~a~~<br>~~a~~~~**ee**~~ 2<br>~~aRe0~~|
|A9<br>XTAL1<br>XTAL1<br>A45<br>GCC1/IO34PDB1V0 GCC1/IO47PDB1V0<br>~~ee0~~|
|A10<br>GNDOSC<br>GNDOSC<br>A46<br>VCCIB1<br>VCCIB1<br>~~a~~|
|A11<br>GEC2/IO43PPB3V0 GEA1/IO61PPB3V0<br>A12<br>IO43NPB3V0<br>GEA0/IO61NPB3V0<br>A13<br>NC<br>VCCIB3<br>A14<br>GNDNVM<br>GNDNVM<br>A15<br>PCAP<br>PCAP<br>A16<br>VCC33PMP<br>VCC33PMP<br>A47<br>GBC2/IO32PPB1V0 GBB2/IO41PPB1V0<br>A48<br>VCCIB1<br>VCCIB1<br>A49<br>NC<br>NC<br>A50<br>GBA0/IO29RSB0V0 GBB1/IO37RSB0V0<br>A51<br>VCCIB0<br>VCCIB0<br>A52<br>GBB0/IO27RSB0V0 GBC0/IO34RSB0V0<br>~~a~~<br>~~aee~~ 2<br>~~aFe0~~<br>~~ee0~~<br>~~a~~|
|A17<br>NC<br>NC<br>A18<br>AV0<br>AV0<br>A19<br>AG0<br>AG0<br>A20<br>ATRTN0<br>ATRTN0<br>A21<br>AG1<br>AG1<br>A22<br>AC1<br>AC1<br>A53<br>GBC1/IO26RSB0V0<br>IO33RSB0V0<br>A54<br>IO24RSB0V0<br>IO29RSB0V0<br>A55<br>IO21RSB0V0<br>IO26RSB0V0<br>A56<br>VCCIB0<br>VCCIB0<br>A57<br>IO15RSB0V0<br>IO21RSB0V0<br>A58<br>IO10RSB0V0<br>IO13RSB0V0<br>~~a~~<br>~~a~~<br>~~**ee**~~ 2<br>~~aPe0~~<br>~~ee0~~<br>~~a~~|
|A23<br>AV2<br>AV2<br>A24<br>AT2<br>AT2<br>A25<br>AT3<br>AT3<br>A26<br>AC3<br>AC3<br>A27<br>AV4<br>AV4<br>A28<br>AC4<br>AC4<br>A59<br>IO07RSB0V0<br>IO10RSB0V0<br>A60<br>GAC0/IO04RSB0V0<br>IO06RSB0V0<br>A61<br>GAB1/IO03RSB0V0 GAC1/IO05RSB0V0<br>A62<br>VCC<br>VCC<br>A63<br>GAA1/IO01RSB0V0 GAB0/IO02RSB0V0<br>A64<br>NC<br>NC<br>~~a~~<br>~~a~~<br>~~**ee**~~ 2<br>~~aPe0~~<br>~~ee0~~<br>~~a~~|
|A29<br>AT4<br>AT4<br>A30<br>NC<br>AG5<br>A31<br>NC<br>AV5<br>A32<br>ADCGNDREF<br>ADCGNDREF<br>B1<br>VCOMPLA<br>VCOMPLA<br>B2<br>GAA2/IO52PDB3V0 GAC2/IO74PDB3V0<br>B3<br>GAC2/IO51PDB3V0 GFA2/IO71PDB3V0<br>B4<br>GFB2/IO50PDB3V0<br>GFB2/IO70PSB3V0<br>~~a~~<br>~~a~~<br>~~**ee**~~ 2<br>~~aPe0~~|
|A33<br>VCC33A<br>VCC33A<br>B5<br>VCC<br>VCC<br>~~Pe0~~|
|A34<br>GNDA<br>GNDA<br>B6<br>GFC0/IO49NDB3V0 GFC0/IO68NDB3V0<br>~~a~~|
|A35<br>PTBASE<br>PTBASE<br>B7<br>GEB1/IO45PDB3V0<br>NC<br>~~a~~|
|A36<br>VCCNVM<br>VCCNVM<br>B8<br>VCCOSC<br>VCCOSC<br>~~a~~|
**4-4**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**QN180**<br>~~0~~|||**QN180**||
|---|---|---|---|---|
|**Pin Number**<br>**AFS090 Function**<br>**AFS250 Function**<br>~~a~~<br>~~se~~||**Pin Number**|**AFS090 Function**|**AFS250 Function**|
|B9<br>XTAL2<br>XTAL2<br>B45<br>GBA2/IO31PDB1V0 GBA2/IO40PDB1V0<br>~~Pe0~~|||||
|B10<br>GEA0/IO44NDB3V0 GFA0/IO66NDB3V0<br>B46<br>GNDQ<br>GNDQ<br>~~Re0~~|||||
|B11<br>GEB2/IO42PDB3V0<br>IO60NDB3V0<br>B47<br>GBA1/IO30RSB0V0 GBA0/IO38RSB0V0<br>~~ee0~~|||||
|B12<br>VCC<br>VCC<br>~~0~~||B48|GBB1/IO28RSB0V0|GBC1/IO35RSB0V0|
|B13<br>VCCNVM<br>VCCNVM<br>~~a~~<br>~~0~~||B49|VCC|VCC|
|B14<br>VCC15A<br>VCC15A<br>~~a~~||B50|GBC0/IO25RSB0V0|IO31RSB0V0|
|B15<br>NCAP<br>NCAP<br>~~a ee~~||B51|IO23RSB0V0|IO28RSB0V0|
|B16<br>VCC33N<br>VCC33N<br>B52<br>IO20RSB0V0<br>IO25RSB0V0<br>~~Re0~~|||||
|B17<br>GNDAQ<br>GNDAQ<br>B53<br>VCC<br>VCC<br>~~ee0~~|||||
|B18<br>AC0<br>AC0<br>~~0~~||B54|IO11RSB0V0|IO14RSB0V0|
|B19<br>AT0<br>AT0<br>~~a~~<br>~~0~~||B55|IO08RSB0V0|IO11RSB0V0|
|B20<br>AT1<br>AT1<br>~~a~~||B56|GAC1/IO05RSB0V0|IO08RSB0V0|
|B21<br>AV1<br>AV1<br>B57<br>VCCIB0<br>VCCIB0<br>~~aee~~|||||
|B22<br>AC2<br>AC2<br>B23<br>ATRTN1<br>ATRTN1<br>B24<br>AG3<br>AG3<br>B58<br>GAB0/IO02RSB0V0 GAC0/IO04RSB0V0<br>B59<br>GAA0/IO00RSB0V0 GAA1/IO01RSB0V0<br>B60<br>VCCPLA<br>VCCPLA<br>~~Fe0~~<br>~~ee~~<br>~~0~~<br>~~0~~|||||
|B25<br>AV3<br>AV3<br>~~a~~<br>~~0~~||C1|NC|NC|
|B26<br>AG4<br>AG4<br>~~a~~||C2|NC|VCCIB3|
|B27<br>ATRTN2<br>ATRTN2<br>~~a ee~~||C3|GND|GND|
|B28<br>NC<br>AC5<br>B29<br>VCC33A<br>VCC33A<br>B30<br>VAREF<br>VAREF<br>C4<br>NC<br>GFC2/IO69PPB3V0<br>C5<br>GFC1/IO49PDB3V0 GFC1/IO68PDB3V0<br>C6<br>GFA0/IO47NPB3V0<br>GFB0/IO67NPB3V0<br>~~Pe0~~<br>~~ee~~<br>~~0~~<br>~~0~~|||||
|B31<br>PUB<br>PUB<br>~~a~~<br>~~0~~||C7|VCCIB3|NC|
|B32<br>PTEM<br>PTEM<br>~~a~~||C8|GND|GND|
|B33<br>GNDNVM<br>GNDNVM<br>~~a ee~~||C9|GEA1/IO44PDB3V0|GFA1/IO66PDB3V0|
|B34<br>VCC<br>VCC<br>B35<br>TCK<br>TCK<br>B36<br>TMS<br>TMS<br>C10<br>GEA2/IO42NDB3V0 GEC2/IO60PDB3V0<br>C11<br>NC<br>GEA2/IO58PSB3V0<br>C12<br>NC<br>NC<br>~~Pe0~~<br>~~ee~~<br>~~0~~<br>~~0~~|||||
|B37<br>TRST<br>TRST<br>~~a~~<br>~~0~~||C13|GND|GND|
|B38<br>GDB2/IO41PSB1V0 GDA2/IO55PSB1V0<br>~~a~~||C14|NC|NC|
|B39<br>GDC0/IO38NDB1V0 GDB0/IO53NDB1V0<br>~~a ee~~||C15|NC|NC|
|B40<br>VCCIB1<br>VCCIB1<br>C16<br>GNDA<br>GNDA<br>~~Pe0~~|||||
|B41<br>GCA1/IO36PDB1V0 GCA1/IO49PDB1V0<br>C17<br>NC<br>NC<br>~~Pe0~~|||||
|B42<br>GCC0/IO34NDB1V0 GCC0/IO47NDB1V0<br>~~0~~||C18|NC|NC|
|B43<br>GCB2/IO33PSB1V0 GBC2/IO42PSB1V0<br>~~a~~||C19|NC|NC|
|B44<br>VCC<br>VCC<br>~~a~~||C20|NC|NC|
**Revision 8**
**4-5**
_Package Pin Assignments_
|**QN180**<br>~~rree~~|**QN180**<br>~~rree~~|**QN180**<br>~~rree~~|
|---|---|---|
|**Pin Number**<br>~~rr~~<br>~~ee~~|**AFS090 Function**<br>~~ee~~<br>~~ee~~|**AFS250 Function**<br>~~ee~~<br>~~ee~~|
|C21<br>~~rr~~<br>~~ee~~<br>~~ee~~|AG2<br>~~ee~~<br>~~ee~~<br>~~ee~~|AG2<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C22<br>~~ee~~<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C23<br>~~ee~~<br>~~ee~~<br>~~rr~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C24<br>~~ee~~<br>~~rr~~<br>~~rs~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C25<br>~~rr ~~<br>~~rs~~<br>~~rr~~|NC<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|AT5<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C26<br>~~rs~~<br>~~rr~~<br>~~rs~~|GNDAQ<br>~~ee~~<br>~~ee~~<br>~~ee~~|GNDAQ<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C27<br>~~rr ~~<br>~~rs~~<br>~~ee~~|NC<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|NC<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C28<br>~~rs ~~<br>~~ee~~<br>~~ee~~|NC<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|NC<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C29<br>~~ee~~<br>~~ee~~<br>~~rr~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C30<br>~~ee~~<br>~~rr~~<br>~~rs~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C31<br>~~rr ~~<br>~~rs~~<br>~~rr~~|GND<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C32<br>~~rs~~<br>~~rr~~|NC<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~|
|C33<br>~~rr ~~<br>~~a ~~<br>~~ee~~|NC<br> ~~ee ~~<br> ~~ee~~<br>~~ee~~|NC<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C34<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~|
|C35<br>~~ee~~<br>~~ee~~<br>~~rr~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C36<br>~~ee~~<br>~~rr~~<br>~~rs~~|GDB0/IO39NPB1V0 <br>~~ee~~<br>~~ee~~<br>~~ee~~|GDA0/IO54NPB1V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C37<br>~~rr ~~<br>~~rs~~<br>~~rr~~|GDA1/IO37NSB1V0 <br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GDC0/IO52NSB1V0<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C38<br>~~rs~~<br>~~rr~~<br>~~rs~~|GCA0/IO36NDB1V0 <br>~~ee~~<br>~~ee~~<br>~~ee~~|GCA0/IO49NDB1V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C39<br>~~rr ~~<br>~~rs~~<br>~~ee~~|GCB1/IO35PPB1V0 <br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GCB1/IO48PPB1V0<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C40<br>~~rs ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C41<br>~~ee~~<br>~~ee~~<br>~~rr~~|GCA2/IO32NPB1V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|IO41NPB1V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C42<br>~~ee~~<br>~~rr~~<br>~~rs~~|GBB2/IO31NDB1V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|IO40NDB1V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C43<br>~~rr ~~<br>~~rs~~<br>~~rr~~|NC<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|NC<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C44<br>~~rs~~<br>~~rr~~<br>~~rs~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|GBA1/IO39RSB0V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C45<br>~~rr ~~<br>~~rs~~<br>~~ee~~|NC<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GBB0/IO36RSB0V0<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C46<br>~~rs ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C47<br>~~ee~~<br>~~ee~~<br>~~rr~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|IO30RSB0V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C48<br>~~ee~~<br>~~rr~~<br>~~rs~~|IO22RSB0V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|IO27RSB0V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C49<br>~~rr ~~<br>~~rs~~<br>~~rr~~|GND<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C50<br>~~rs~~<br>~~rr~~<br>~~rs~~|IO13RSB0V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|IO16RSB0V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C51<br>~~rr ~~<br>~~rs~~<br>~~ee~~|IO09RSB0V0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|IO12RSB0V0<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C52<br>~~rs ~~<br>~~ee~~<br>~~ee~~|IO06RSB0V0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|IO09RSB0V0<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C53<br>~~ee~~<br>~~ee~~<br>~~rr~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C54<br>~~ee~~<br>~~rr~~<br>~~rr~~|NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|GAB1/IO03RSB0V0<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C55<br>~~rr ~~<br>~~rr~~<br>~~a~~|NC<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GAA0/IO00RSB0V0<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|C56<br>~~rr~~<br>~~a~~|NC<br>~~ee~~<br>~~ee~~|NC<br>~~ee~~<br>~~ee~~|
|**QN180**|**QN180**|**QN180**|
|---|---|---|
|**Pin Number**|**AFS090 Function**|**AFS250 Function**|
|D1|NC|NC|
|D2|NC|NC|
|D3|NC|NC|
|D4|NC|NC|
**4-6**
**Revision 8**
_Package Pin Assignments_
## **PQ208**
**==> picture [191 x 167] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 [208]<br>208-Pin PQFP<br>**----- End of picture text -----**<br>
## _**Note**_
1. Package PQ208 is discontinued.
2. For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-7**
**Revision 8**
_Package Pin Assignments_
|**PQ208**<br>**Pin**<br>**Number**<br>**AFS250 Function**<br>**AFS600 Function**<br>1<br>VCCPLA<br>VCCPLA<br>2<br>VCOMPLA<br>VCOMPLA<br>3<br>GNDQ<br>GAA2/IO85PDB4V0<br>4<br>VCCIB3<br>IO85NDB4V0<br>5<br>GAA2/IO76PDB3V0<br>GAB2/IO84PDB4V0<br>6<br>IO76NDB3V0<br>IO84NDB4V0<br>7<br>GAB2/IO75PDB3V0 GAC2/IO83PDB4V0<br>8<br>IO75NDB3V0<br>IO83NDB4V0<br>9<br>NC<br>IO77PDB4V0<br>10<br>NC<br>IO77NDB4V0<br>11<br>VCC<br>IO76PDB4V0<br>12<br>GND<br>IO76NDB4V0<br>13<br>VCCIB3<br>VCC<br>14<br>IO72PDB3V0<br>GND<br>15<br>IO72NDB3V0<br>VCCIB4<br>16<br>GFA2/IO71PDB3V0<br>GFA2/IO75PDB4V0<br>17<br>IO71NDB3V0<br>IO75NDB4V0<br>18<br>GFB2/IO70PDB3V0<br>GFC2/IO73PDB4V0<br>19<br>IO70NDB3V0<br>IO73NDB4V0<br>20<br>GFC2/IO69PDB3V0<br>VCCOSC<br>21<br>IO69NDB3V0<br>XTAL1<br>22<br>VCC<br>XTAL2<br>23<br>GND<br>GNDOSC<br>24<br>VCCIB3<br>GFC1/IO72PDB4V0<br>25<br>GFC1/IO68PDB3V0 GFC0/IO72NDB4V0<br>26<br>GFC0/IO68NDB3V0<br>GFB1/IO71PDB4V0<br>27<br>GFB1/IO67PDB3V0<br>GFB0/IO71NDB4V0<br>28<br>GFB0/IO67NDB3V0<br>GFA1/IO70PDB4V0<br>29<br>VCCOSC<br>GFA0/IO70NDB4V0<br>30<br>XTAL1<br>IO69PDB4V0<br>31<br>XTAL2<br>IO69NDB4V0<br>32<br>GNDOSC<br>VCC<br>33<br>GEB1/IO62PDB3V0<br>GND<br>38<br>IO60NDB3V0<br>GEB0/IO62NDB4V0<br>39<br>GND<br>GEA1/IO61PDB4V0<br>40<br>VCCIB3<br>GEA0/IO61NDB4V0<br>41<br>GEB2/IO59PDB3V0 GEC2/IO60PDB4V0<br>42<br>IO59NDB3V0<br>IO60NDB4V0<br>43<br>GEA2/IO58PDB3V0<br>VCCIB4<br>44<br>IO58NDB3V0<br>GNDQ<br>45<br>VCC<br>VCC<br>45<br>VCC<br>VCC<br>46<br>VCCNVM<br>VCCNVM<br>47<br>GNDNVM<br>GNDNVM<br>48<br>GND<br>GND<br>49<br>VCC15A<br>VCC15A<br>50<br>PCAP<br>PCAP<br>51<br>NCAP<br>NCAP<br>52<br>VCC33PMP<br>VCC33PMP<br>53<br>VCC33N<br>VCC33N<br>54<br>GNDA<br>GNDA<br>55<br>GNDAQ<br>GNDAQ<br>56<br>NC<br>AV0<br>57<br>NC<br>AC0<br>58<br>NC<br>AG0<br>59<br>NC<br>AT0<br>60<br>NC<br>ATRTN0<br>61<br>NC<br>AT1<br>62<br>NC<br>AG1<br>63<br>NC<br>AC1<br>64<br>NC<br>AV1<br>65<br>AV0<br>AV2<br>66<br>AC0<br>AC2<br>67<br>AG0<br>AG2<br>68<br>AT0<br>AT2<br>69<br>ATRTN0<br>ATRTN1<br>**PQ208**<br>**Pin**<br>**Number**<br>**AFS250 Function**<br>**AFS600 Function**<br>~~eoes0~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~eoes0~~<br>~~Rs~~<br>~~s~~<br>~~eoes0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~|
|---|
|34<br>GEB0/IO62NDB3V0<br>VCCIB4<br>70<br>AT1<br>AT3<br>~~0~~|
|35<br>GEA1/IO61PDB3V0 GEC1/IO63PDB4V0<br>71<br>AG1<br>AG3|
|36<br>GEA0/IO61NDB3V0 GEC0/IO63NDB4V0<br>37<br>GEC2/IO60PDB3V0 GEB1/IO62PDB4V0<br>72<br>AC1<br>AC3<br>73<br>AV1<br>AV3<br>~~Rs0~~<br>~~es~~<br>~~ee0~~|
**4-8**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**PQ208**<br>**PQ208**<br>~~oo~~|
|---|
|**Pin**<br>**Pin**|
|74<br>AV2<br>AV4<br>75<br>AC2<br>AC4<br>76<br>AG2<br>AG4<br>77<br>AT2<br>AT4<br>78<br>ATRTN1<br>ATRTN2<br>79<br>AT3<br>AT5<br>80<br>AG3<br>AG5<br>81<br>AC3<br>AC5<br>82<br>AV3<br>AV5<br>83<br>AV4<br>AV6<br>84<br>AC4<br>AC6<br>85<br>AG4<br>AG6<br>86<br>AT4<br>AT6<br>87<br>ATRTN2<br>ATRTN3<br>88<br>AT5<br>AT7<br>89<br>AG5<br>AG7<br>90<br>AC5<br>AC7<br>91<br>AV5<br>AV7<br>92<br>NC<br>AV8<br>93<br>NC<br>AC8<br>94<br>NC<br>AG8<br>95<br>NC<br>AT8<br>96<br>NC<br>ATRTN4<br>97<br>NC<br>AT9<br>98<br>NC<br>AG9<br>99<br>NC<br>AC9<br>100<br>NC<br>AV9<br>101<br>GNDAQ<br>GNDAQ<br>102<br>VCC33A<br>VCC33A<br>103<br>ADCGNDREF<br>ADCGNDREF<br>104<br>VAREF<br>VAREF<br>105<br>PUB<br>PUB<br>106<br>VCC33A<br>VCC33A<br>107<br>GNDA<br>GNDA<br>108<br>PTEM<br>PTEM<br>109<br>PTBASE<br>PTBASE<br>110<br>GNDNVM<br>GNDNVM<br>**Number**<br>**AFS250 Function**<br>**AFS600 Function**<br>111<br>VCCNVM<br>VCCNVM<br>112<br>VCC<br>VCC<br>112<br>VCC<br>VCC<br>113<br>VPUMP<br>VPUMP<br>114<br>GNDQ<br>NC<br>115<br>VCCIB1<br>TCK<br>116<br>TCK<br>TDI<br>117<br>TDI<br>TMS<br>118<br>TMS<br>TDO<br>119<br>TDO<br>TRST<br>120<br>TRST<br>VJTAG<br>121<br>VJTAG<br>IO57NDB2V0<br>122<br>IO57NDB1V0<br>GDC2/IO57PDB2V0<br>123<br>GDC2/IO57PDB1V0<br>IO56NDB2V0<br>124<br>IO56NDB1V0<br>GDB2/IO56PDB2V0<br>125<br>GDB2/IO56PDB1V0<br>IO55NDB2V0<br>126<br>VCCIB1<br>GDA2/IO55PDB2V0<br>127<br>GND<br>GDA0/IO54NDB2V0<br>128<br>IO55NDB1V0<br>GDA1/IO54PDB2V0<br>129<br>GDA2/IO55PDB1V0<br>VCCIB2<br>130<br>GDA0/IO54NDB1V0<br>GND<br>131<br>GDA1/IO54PDB1V0<br>VCC<br>132<br>GDB0/IO53NDB1V0 GCA0/IO45NDB2V0<br>133<br>GDB1/IO53PDB1V0 GCA1/IO45PDB2V0<br>134<br>GDC0/IO52NDB1V0 GCB0/IO44NDB2V0<br>135<br>GDC1/IO52PDB1V0 GCB1/IO44PDB2V0<br>136<br>IO51NSB1V0<br>GCC0/IO43NDB2V<br>0<br>137<br>VCCIB1<br>GCC1/IO43PDB2V0<br>138<br>GND<br>IO42NDB2V0<br>139<br>VCC<br>IO42PDB2V0<br>140<br>IO50NDB1V0<br>IO41NDB2V0<br>141<br>IO50PDB1V0<br>GCC2/IO41PDB2V0<br>142<br>GCA0/IO49NDB1V0<br>VCCIB2<br>143<br>GCA1/IO49PDB1V0<br>GND<br>144<br>GCB0/IO48NDB1V0<br>VCC<br>145<br>GCB1/IO48PDB1V0<br>IO40NDB2V0<br>146<br>GCC0/IO47NDB1V0 GCB2/IO40PDB2V0<br>**Number**<br>**AFS250 Function**<br>**AFS600 Function**<br>~~Oa|~~<br>~~ooo | O_O EiCieT~~<br>~~ETE) |~~<br>~~EEE Ei~~<br>~~ooo |EET~~<br>~~ooo | O_O EiCieT~~<br>~~ETE) |~~<br>~~EEE Ei~~<br>~~ooo |EET~~<br>~~ooo | O_O EiCieT~~<br>~~ETE) |~~<br>~~EEE Ei~~<br>~~ooo |EET~~<br>~~oo |§ ZOEET~~<br>~~Ca|~~<br>~~ooo |EET~~<br>~~oo |§ ZOEET~~<br>~~Ca|~~<br>~~ooo |EET~~<br>~~ooo | O_O EiCieT~~<br>~~ETE) |~~<br>~~EEE Ei~~<br>~~ooo |EET~~<br>~~ooo | O_O EiCieT~~<br>~~ETE) |~~<br>~~EEE Ei~~<br>~~ooo |EET~~<br>~~ooo | O_O EiCieT~~<br>~~ETE) |~~<br>~~EEE Ei~~<br>~~ooo |EET~~<br>~~ooo | O_O EiCieT~~<br>~~rs a~~<br>~~So~~<br>~~———~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~pf~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~pf~~<br>~~pf fd~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~pf~~<br>~~NE|es~~<br>~~ee~~<br>~~ee~~|
**Revision 8**
**4-9**
_Package Pin Assignments_
|**PQ208**<br>**PQ208**<br>~~a~~|
|---|
|**Pin**<br>**Pin**|
|**Number**<br>**AFS250 Function**<br>**AFS600 Function**<br>**Number**<br>**AFS250 Function**<br>**AFS600 Function**|
|147<br>GCC1/IO47PDB1V0<br>IO39NDB2V0<br>148<br>IO42NDB1V0<br>GCA2/IO39PDB2V0<br>149<br>GBC2/IO42PDB1V0<br>IO31NDB2V0<br>150<br>VCCIB1<br>GBB2/IO31PDB2V0<br>151<br>GND<br>IO30NDB2V0<br>152<br>VCC<br>GBA2/IO30PDB2V0<br>153<br>IO41NDB1V0<br>VCCIB2<br>154<br>GBB2/IO41PDB1V0<br>GNDQ<br>155<br>IO40NDB1V0<br>VCOMPLB<br>156<br>GBA2/IO40PDB1V0<br>VCCPLB<br>157<br>GBA1/IO39RSB0V0<br>VCCIB1<br>158<br>GBA0/IO38RSB0V0<br>GNDQ<br>159<br>GBB1/IO37RSB0V0<br>GBB1/IO27PPB1V1<br>160<br>GBB0/IO36RSB0V0<br>GBA1/IO28PPB1V1<br>161<br>GBC1/IO35RSB0V0 GBB0/IO27NPB1V1<br>162<br>VCCIB0<br>GBA0/IO28NPB1V1<br>163<br>GND<br>VCCIB1<br>164<br>VCC<br>GND<br>165<br>GBC0/IO34RSB0V0<br>VCC<br>166<br>IO33RSB0V0<br>GBC1/IO26PDB1V1<br>167<br>IO32RSB0V0<br>GBC0/IO26NDB1V1<br>168<br>IO31RSB0V0<br>IO24PPB1V1<br>169<br>IO30RSB0V0<br>IO23PPB1V1<br>170<br>IO29RSB0V0<br>IO24NPB1V1<br>171<br>IO28RSB0V0<br>IO23NPB1V1<br>172<br>IO27RSB0V0<br>IO22PPB1V0<br>173<br>IO26RSB0V0<br>IO21PPB1V0<br>174<br>IO25RSB0V0<br>IO22NPB1V0<br>175<br>VCCIB0<br>IO21NPB1V0<br>176<br>GND<br>IO20PSB1V0<br>177<br>VCC<br>IO19PSB1V0<br>178<br>IO24RSB0V0<br>IO14NSB0V1<br>179<br>IO23RSB0V0<br>IO12PDB0V1<br>180<br>IO22RSB0V0<br>IO12NDB0V1<br>181<br>IO21RSB0V0<br>VCCIB0<br>182<br>IO20RSB0V0<br>GND<br>183<br>IO19RSB0V0<br>VCC<br>184<br>IO18RSB0V0<br>IO10PPB0V1<br>185<br>IO17RSB0V0<br>IO09PPB0V1<br>186<br>IO16RSB0V0<br>IO10NPB0V1<br>187<br>IO15RSB0V0<br>IO09NPB0V1<br>188<br>VCCIB0<br>IO08PPB0V1<br>189<br>GND<br>IO07PPB0V1<br>190<br>VCC<br>IO08NPB0V1<br>191<br>IO14RSB0V0<br>IO07NPB0V1<br>192<br>IO13RSB0V0<br>IO06PPB0V0<br>193<br>IO12RSB0V0<br>IO05PPB0V0<br>194<br>IO11RSB0V0<br>IO06NPB0V0<br>195<br>IO10RSB0V0<br>IO04PPB0V0<br>196<br>IO09RSB0V0<br>IO05NPB0V0<br>197<br>IO08RSB0V0<br>IO04NPB0V0<br>198<br>IO07RSB0V0<br>GAC1/IO03PDB0V0<br>199<br>IO06RSB0V0<br>GAC0/IO03NDB0V0<br>200<br>GAC1/IO05RSB0V0<br>VCCIB0<br>201<br>VCCIB0<br>GND<br>202<br>GND<br>VCC<br>203<br>VCC<br>GAB1/IO02PDB0V0<br>204<br>GAC0/IO04RSB0V0 GAB0/IO02NDB0V0<br>205<br>GAB1/IO03RSB0V0<br>GAA1/IO01PDB0V0<br>206<br>GAB0/IO02RSB0V0 GAA0/IO01NDB0V0<br>207<br>GAA1/IO01RSB0V0<br>GNDQ<br>208<br>GAA0/IO00RSB0V0<br>VCCIB0<br>~~es0~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~eoes0~~<br>~~Rs~~<br>~~s~~<br>~~eoes0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~s~~<br>~~se ~~0<br>~~Rs0~~<br>~~Rs~~<br>~~esee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~esee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~esee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~eeee~~|
**4-10**
**Revision 8**
_Package Pin Assignments_
## **FG256**
|A1 Ball Pad Corner||
|---|---|
|1<br>3<br>5<br>7<br>9<br>11<br>13<br>15<br>2<br>4<br>6<br>8<br>10<br>12<br>14<br>16||
|OCOOCCDDDD000O000000"%<br>OOOOQOQOCOOQOOCOO0O0C0O|B<br>A|
|OOQOOQOQOQOOQOOCO0O0O00O0|C|
|OOOQOQOQOOQOOOCO0O0O00O|D|
|OOOQOOQOQOOQOOCO0O0O00O|E|
|OOOQOQOQOQOOOOCOO0O0C0O|F|
|OOOOQOOCOOOOCOO0O0C0O|G|
|OTOTOTOTOLOTOIOLOLOOIOLOLOIOre|H|
|OTOTOTOTOLOTOIOLOLOOIOLOLOIOXS|J|
|OOOQOQOQOQOQOQOQOOQOO0O00O0|K|
|OTOTOTOTOLOTOIOLOLOOIOLOLOIOrSe|L|
|OOOQOQOQOQOQOQOQOOQOO0O00O|M|
|OOOOQOOCQOOOOCO0O0O0C0O|N|
|OOOQOQOQOCQOOOOCOO0O0C0O|P|
|OOOQOQOQOQOOQOOCOO0O0C0O|R|
|OOOQOOQOQOQOQOOO0O0O00O0|T|
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-11**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|
|---|---|---|---|---|
|**Pin Number**<br>~~a~~<br>~~a~~|**AFS090 Function**<br>~~es~~|**AFS250 Function**|**AFS600 Function**|**AFS1500 Function**|
|A1<br>~~a~~<br>~~a~~|GND<br>~~es~~|GND|GND|GND|
|A2<br>~~aa~~<br>~~a~~|VCCIB0<br>~~es~~<br>|VCCIB0<br>|VCCIB0<br>|VCCIB0<br>|
|A3<br>~~a~~<br>~~a~~|GAB0/IO02RSB0V0<br>~~es~~<br>|GAA0/IO00RSB0V0<br>|GAA0/IO01NDB0V0<br>|GAA0/IO01NDB0V0<br>|
|A4<br>~~a~~|GAB1/IO03RSB0V0<br>~~es~~<br>|GAA1/IO01RSB0V0<br>|GAA1/IO01PDB0V0<br>|GAA1/IO01PDB0V0<br>|
|A5<br>~~aGe~~|GND<br>~~es~~<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|A6<br>~~a ~~<br>~~a~~|IO07RSB0V0<br> ~~se~~<br>|IO11RSB0V0<br>~~se~~<br>|IO10PDB0V1<br>~~se~~<br>|IO07PDB0V1<br>~~se~~<br>|
|A7<br>~~a~~|IO10RSB0V0<br>|IO14RSB0V0<br>|IO12PDB0V1<br>|IO13PDB0V2<br>|
|A8<br>~~aGe~~|IO11RSB0V0<br>~~Ge~~|IO15RSB0V0<br>~~Ge~~|IO12NDB0V1<br>~~Ge~~|IO13NDB0V2<br>~~Ge~~|
|A9<br>~~a ~~<br>~~a~~|IO16RSB0V0<br> ~~se~~<br>|IO24RSB0V0<br>~~se~~<br>|IO22NDB1V0<br>~~se~~<br>|IO24NDB1V0<br>~~se~~<br>|
|A10<br>~~a~~|IO17RSB0V0<br>|IO25RSB0V0<br>|IO22PDB1V0<br>|IO24PDB1V0<br>|
|A11<br>~~aGe~~|IO18RSB0V0<br>~~Ge~~|IO26RSB0V0<br>~~Ge~~|IO24NDB1V1<br>~~Ge~~|IO29NDB1V1<br>~~Ge~~|
|A12<br>~~a se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|
|A13<br>~~Ge~~|GBC0/IO25RSB0V0<br>~~Ge~~|GBA0/IO38RSB0V0<br>~~Ge~~|GBA0/IO28NDB1V1<br>~~Ge~~|GBA0/IO42NDB1V2<br>~~Ge~~|
|A14<br>~~Ge~~|GBA0/IO29RSB0V0<br>~~Ge~~|IO32RSB0V0<br>~~Ge~~|IO29NDB1V1<br>~~Ge~~|IO43NDB1V2<br>~~Ge~~|
|A15<br>~~a se~~|VCCIB0<br>~~se~~|VCCIB0<br>~~se~~|VCCIB1<br>~~se~~|VCCIB1<br>~~se~~|
|A16<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|B1<br>~~Ge~~|VCOMPLA<br>~~Ge~~|VCOMPLA<br>~~Ge~~|VCOMPLA<br>~~Ge~~|VCOMPLA<br>~~Ge~~|
|B2<br>~~a se~~|VCCPLA<br>~~se~~|VCCPLA<br>~~se~~|VCCPLA<br>~~se~~|VCCPLA<br>~~se~~|
|B3<br>~~Ge~~|GAA0/IO00RSB0V0<br>~~Ge~~|IO07RSB0V0<br>~~Ge~~|IO00NDB0V0<br>~~Ge~~|IO00NDB0V0<br>~~Ge~~|
|B4<br>~~Ge~~|GAA1/IO01RSB0V0<br>~~Ge~~|IO06RSB0V0<br>~~Ge~~|IO00PDB0V0<br>~~Ge~~|IO00PDB0V0<br>~~Ge~~|
|B5<br>~~a se~~|NC<br>~~se~~|GAB1/IO03RSB0V0<br>~~se~~|GAB1/IO02PPB0V0<br>~~se~~|GAB1/IO02PPB0V0<br>~~se~~|
|B6<br>~~Ge~~|IO06RSB0V0<br>~~Ge~~|IO10RSB0V0<br>~~Ge~~|IO10NDB0V1<br>~~Ge~~|IO07NDB0V1<br>~~Ge~~|
|B7<br>~~Ge~~|VCCIB0<br>~~Ge~~|VCCIB0<br>~~Ge~~|VCCIB0<br>~~Ge~~|VCCIB0<br>~~Ge~~|
|B8<br>~~a se~~|IO12RSB0V0<br>~~se~~|IO16RSB0V0<br>~~se~~|IO18NDB1V0<br>~~se~~|IO22NDB1V0<br>~~se~~|
|B9<br>~~Ge~~|IO13RSB0V0<br>~~Ge~~|IO17RSB0V0<br>~~Ge~~|IO18PDB1V0<br>~~Ge~~|IO22PDB1V0<br>~~Ge~~|
|B10<br>~~Ge~~|VCCIB0<br>~~Ge~~|VCCIB0<br>~~Ge~~|VCCIB1<br>~~Ge~~|VCCIB1<br>~~Ge~~|
|B11<br>~~a se~~|IO19RSB0V0<br>~~se~~|IO27RSB0V0<br>~~se~~|IO24PDB1V1<br>~~se~~|IO29PDB1V1<br>~~se~~|
|B12<br>~~Ge~~|GBB0/IO27RSB0V0<br>~~Ge~~|GBC0/IO34RSB0V0<br>~~Ge~~|GBC0/IO26NPB1V1<br>~~Ge~~|GBC0/IO40NPB1V2<br>~~Ge~~|
|B13<br>~~Ge~~|GBC1/IO26RSB0V0<br>~~Ge~~|GBA1/IO39RSB0V0<br>~~Ge~~|GBA1/IO28PDB1V1<br>~~Ge~~|GBA1/IO42PDB1V2<br>~~Ge~~|
|B14<br>~~a se~~|GBA1/IO30RSB0V0<br>~~se~~|IO33RSB0V0<br>~~se~~|IO29PDB1V1<br>~~se~~|IO43PDB1V2<br>~~se~~|
|B15<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|VCCPLB<br>~~Ge~~|VCCPLB<br>~~Ge~~|
|B16<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|VCOMPLB<br>~~Ge~~|VCOMPLB<br>~~Ge~~|
|C1<br>~~a se~~|VCCIB3<br>~~se~~|V**CCI**B3<br>~~se~~|VCCIB4<br>~~se~~|VCCIB4<br>~~se~~|
|C2<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|C3<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB4<br>~~Ge~~|VCCIB4<br>~~Ge~~|
|C4<br>~~a~~|NC|NC|VCCIB0|VCCIB0|
|C5<br>~~a~~|VCCIB0|VCCIB0|VCCIB0|VCCIB0|
|C6<br>~~a~~|GAC1/IO05RSB0V0<br>~~se~~|GAC1/IO05RSB0V0<br>~~se~~|GAC1/IO03PDB0V0|GAC1/IO03PDB0V0|
**Revision 8**
**4-12**
_Package Pin Assignments_
|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|
|---|---|---|---|---|
|**Pin Number**<br>~~a~~<br>~~a~~|**AFS090 Function**<br>~~es~~|**AFS250 Function**|**AFS600 Function**|**AFS1500 Function**|
|C7<br>~~a~~<br>~~a~~|IO09RSB0V0<br>~~es~~|IO12RSB0V0|IO06NDB0V0|IO09NDB0V1|
|C8<br>~~aa~~<br>~~a~~|IO14RSB0V0<br>~~es~~<br>|IO22RSB0V0<br>|IO16PDB1V0<br>|IO23PDB1V0<br>|
|C9<br>~~a~~<br>~~a~~|IO15RSB0V0<br>~~es~~<br>|IO23RSB0V0<br>|IO16NDB1V0<br>|IO23NDB1V0<br>|
|C10<br>~~a~~|IO22RSB0V0<br>~~es~~<br>|IO30RSB0V0<br>|IO25NDB1V1<br>|IO31NDB1V1<br>|
|C11<br>~~aGe~~|IO20RSB0V0<br>~~es~~<br>~~Ge~~|IO31RSB0V0<br>~~Ge~~|IO25PDB1V1<br>~~Ge~~|IO31PDB1V1<br>~~Ge~~|
|C12<br>~~a ~~<br>~~a~~|VCCIB0<br> ~~se~~<br>|VCCIB0<br>~~se~~<br>|VCCIB1<br>~~se~~<br>|VCCIB1<br>~~se~~<br>|
|C13<br>~~a~~|GBB1/IO28RSB0V0<br>|GBC1/IO35RSB0V0<br>|GBC1/IO26PPB1V1<br>|GBC1/IO40PPB1V2<br>|
|C14<br>~~aGe~~|VCCIB1<br>~~Ge~~|VCCIB1<br>~~Ge~~|VCCIB2<br>~~Ge~~|VCCIB2<br>~~Ge~~|
|C15<br>~~a ~~<br>~~a~~|GND<br> ~~se~~<br>|GND<br>~~se~~<br>|GND<br>~~se~~<br>|GND<br>~~se~~<br>|
|C16<br>~~a~~|VCCIB1<br>|VCCIB1<br>|VCCIB2<br>|VCCIB2<br>|
|D1<br>~~aGe~~|GFC2/IO50NPB3V0<br>~~Ge~~|IO75NDB3V0<br>~~Ge~~|IO84NDB4V0<br>~~Ge~~|IO124NDB4V0<br>~~Ge~~|
|D2<br>~~a se~~|GFA2/IO51NDB3V0<br>~~se~~|GAB2/IO75PDB3V0<br>~~se~~|GAB2/IO84PDB4V0<br>~~se~~|GAB2/IO124PDB4V0<br>~~se~~|
|D3<br>~~Ge~~|GAC2/IO51PDB3V0<br>~~Ge~~|IO76NDB3V0<br>~~Ge~~|IO85NDB4V0<br>~~Ge~~|IO125NDB4V0<br>~~Ge~~|
|D4<br>~~Ge~~|GAA2/IO52PDB3V0<br>~~Ge~~|GAA2/IO76PDB3V0<br>~~Ge~~|GAA2/IO85PDB4V0<br>~~Ge~~|GAA2/IO125PDB4V0<br>~~Ge~~|
|D5<br>~~a se~~|GAB2/IO52NDB3V0<br>~~se~~|GAB0/IO02RSB0V0<br>~~se~~|GAB0/IO02NPB0V0<br>~~se~~|GAB0/IO02NPB0V0<br>~~se~~|
|D6<br>~~Ge~~|GAC0/IO04RSB0V0<br>~~Ge~~|GAC0/IO04RSB0V0<br>~~Ge~~|GAC0/IO03NDB0V0<br>~~Ge~~|GAC0/IO03NDB0V0<br>~~Ge~~|
|D7<br>~~Ge~~|IO08RSB0V0<br>~~Ge~~|IO13RSB0V0<br>~~Ge~~|IO06PDB0V0<br>~~Ge~~|IO09PDB0V1<br>~~Ge~~|
|D8<br>~~a se~~|NC<br>~~se~~|IO20RSB0V0<br>~~se~~|IO14NDB0V1<br>~~se~~|IO15NDB0V2<br>~~se~~|
|D9<br>~~Ge~~|NC<br>~~Ge~~|IO21RSB0V0<br>~~Ge~~|IO14PDB0V1<br>~~Ge~~|IO15PDB0V2<br>~~Ge~~|
|D10<br>~~Ge~~|IO21RSB0V0<br>~~Ge~~|IO28RSB0V0<br>~~Ge~~|IO23PDB1V1<br>~~Ge~~|IO37PDB1V2<br>~~Ge~~|
|D11<br>~~a se~~|IO23RSB0V0<br>~~se~~|GBB0/IO36RSB0V0<br>~~se~~|GBB0/IO27NDB1V1<br>~~se~~|GBB0/IO41NDB1V2<br>~~se~~|
|D12<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|VCCIB1<br>~~Ge~~|VCCIB1<br>~~Ge~~|
|D13<br>~~Ge~~|GBA2/IO31PDB1V0<br>~~Ge~~|GBA2/IO40PDB1V0<br>~~Ge~~|GBA2/IO30PDB2V0<br>~~Ge~~|GBA2/IO44PDB2V0<br>~~Ge~~|
|D14<br>~~a se~~|GBB2/IO31NDB1V0<br>~~se~~|IO40NDB1V0<br>~~se~~|IO30NDB2V0<br>~~se~~|IO44NDB2V0<br>~~se~~|
|D15<br>~~Ge~~|GBC2/IO32PDB1V0<br>~~Ge~~|GBB2/IO41PDB1V0<br>~~Ge~~|GBB2/IO31PDB2V0<br>~~Ge~~|GBB2/IO45PDB2V0<br>~~Ge~~|
|D16<br>~~Ge~~|GCA2/IO32NDB1V0<br>~~Ge~~|IO41NDB1V0<br>~~Ge~~|IO31NDB2V0<br>~~Ge~~|IO45NDB2V0<br>~~Ge~~|
|E1<br>~~a se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|
|E2<br>~~Ge~~|GFB0/IO48NPB3V0<br>~~Ge~~|IO73NDB3V0<br>~~Ge~~|IO81NDB4V0<br>~~Ge~~|IO118NDB4V0<br>~~Ge~~|
|E3<br>~~Ge~~|GFB2/IO50PPB3V0<br>~~Ge~~|IO73PDB3V0<br>~~Ge~~|IO81PDB4V0<br>~~Ge~~|IO118PDB4V0<br>~~Ge~~|
|E4<br>~~a se~~|VCCIB3<br>~~se~~|VCCIB3<br>~~se~~|VCCIB4<br>~~se~~|VCCIB4<br>~~se~~|
|E5<br>~~Ge~~|NC<br>~~Ge~~|IO74NPB3V0<br>~~Ge~~|IO83NPB4V0<br>~~Ge~~|IO123NPB4V0<br>~~Ge~~|
|E6<br>~~Ge~~|NC<br>~~Ge~~|IO08RSB0V0<br>~~Ge~~|IO04NPB0V0<br>~~Ge~~|IO05NPB0V1<br>~~Ge~~|
|E7<br>~~a se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|
|E8<br>~~Ge~~|NC<br>~~Ge~~|IO18RSB0V0<br>~~Ge~~|IO08PDB0V1<br>~~Ge~~|IO11PDB0V1<br>~~Ge~~|
|E9<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|IO20NDB1V0<br>~~Ge~~|IO27NDB1V1<br>~~Ge~~|
|E10<br>~~a~~|GND|GND|GND|GND|
|E11<br>~~a~~|IO24RSB0V0|GBB1/IO37RSB0V0|GBB1/IO27PDB1V1|GBB1/IO41PDB1V2|
|E12<br>~~a~~|NC<br>~~se~~|IO50PPB1V0<br>~~se~~|IO33PSB2V0|IO48PSB2V0|
**4-13**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|
|---|---|---|---|---|
|**Pin Number**<br>~~a~~<br>~~a~~|**AFS090 Function**<br>~~es~~|**AFS250 Function**|**AFS600 Function**|**AFS1500 Function**|
|E13<br>~~a~~<br>~~a~~|VCCIB1<br>~~es~~|VCCIB1|VCCIB2|VCCIB2|
|E14<br>~~aa~~<br>~~a~~|GCC2/IO33NDB1V0<br>~~es~~<br>|IO42NDB1V0<br>|IO32NDB2V0<br>|IO46NDB2V0<br>|
|E15<br>~~a~~<br>~~a~~|GCB2/IO33PDB1V0<br>~~es~~<br>|GBC2/IO42PDB1V0<br>|GBC2/IO32PDB2V0<br>|GBC2/IO46PDB2V0<br>|
|E16<br>~~a~~|GND<br>~~es~~<br>|GND<br>|GND<br>|GND<br>|
|F1<br>~~aGe~~|NC<br>~~es~~<br>~~Ge~~|NC<br>~~Ge~~|IO79NDB4V0<br>~~Ge~~|IO111NDB4V0<br>~~Ge~~|
|F2<br>~~a ~~<br>~~a~~|NC<br> ~~se~~<br>|NC<br>~~se~~<br>|IO79PDB4V0<br>~~se~~<br>|IO111PDB4V0<br>~~se~~<br>|
|F3<br>~~a~~|GFB1/IO48PPB3V0<br>|IO72NDB3V0<br>|IO76NDB4V0<br>|IO112NDB4V0<br>|
|F4<br>~~aGe~~|GFC0/IO49NDB3V0<br>~~Ge~~|IO72PDB3V0<br>~~Ge~~|IO76PDB4V0<br>~~Ge~~|IO112PDB4V0<br>~~Ge~~|
|F5<br>~~a ~~<br>~~a~~|NC<br> ~~se~~<br>|NC<br>~~se~~<br>|IO82PSB4V0<br>~~se~~<br>|IO120PSB4V0<br>~~se~~<br>|
|F6<br>~~a~~|GFC1/IO49PDB3V0<br>|GAC2/IO74PPB3V0<br>|GAC2/IO83PPB4V0<br>|GAC2/IO123PPB4V0<br>|
|F7<br>~~aGe~~|NC<br>~~Ge~~|IO09RSB0V0<br>~~Ge~~|IO04PPB0V0<br>~~Ge~~|IO05PPB0V1<br>~~Ge~~|
|F8<br>~~a se~~|NC<br>~~se~~|IO19RSB0V0<br>~~se~~|IO08NDB0V1<br>~~se~~|IO11NDB0V1<br>~~se~~|
|F9<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|IO20PDB1V0<br>~~Ge~~|IO27PDB1V1<br>~~Ge~~|
|F10<br>~~Ge~~|NC<br>~~Ge~~|IO29RSB0V0<br>~~Ge~~|IO23NDB1V1<br>~~Ge~~|IO37NDB1V2<br>~~Ge~~|
|F11<br>~~a se~~|NC<br>~~se~~|IO43NDB1V0<br>~~se~~|IO36NDB2V0<br>~~se~~|IO50NDB2V0<br>~~se~~|
|F12<br>~~Ge~~|NC<br>~~Ge~~|IO43PDB1V0<br>~~Ge~~|IO36PDB2V0<br>~~Ge~~|IO50PDB2V0<br>~~Ge~~|
|F13<br>~~Ge~~|NC<br>~~Ge~~|IO44NDB1V0<br>~~Ge~~|IO39NDB2V0<br>~~Ge~~|IO59NDB2V0<br>~~Ge~~|
|F14<br>~~a se~~|NC<br>~~se~~|GCA2/IO44PDB1V0<br>~~se~~|GCA2/IO39PDB2V0<br>~~se~~|GCA2/IO59PDB2V0<br>~~se~~|
|F15<br>~~Ge~~|GCC1/IO34PDB1V0<br>~~Ge~~|GCB2/IO45PDB1V0<br>~~Ge~~|GCB2/IO40PDB2V0<br>~~Ge~~|GCB2/IO60PDB2V0<br>~~Ge~~|
|F16<br>~~Ge~~|GCC0/IO34NDB1V0<br>~~Ge~~|IO45NDB1V0<br>~~Ge~~|IO40NDB2V0<br>~~Ge~~|IO60NDB2V0<br>~~Ge~~|
|G1<br>~~a se~~|GEC0/IO46NPB3V0<br>~~se~~|IO70NPB3V0<br>~~se~~|IO74NPB4V0<br>~~se~~|IO109NPB4V0<br>~~se~~|
|G2<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB4<br>~~Ge~~|VCCIB4<br>~~Ge~~|
|G3<br>~~Ge~~|GEC1/IO46PPB3V0<br>~~Ge~~|GFB2/IO70PPB3V0<br>~~Ge~~|GFB2/IO74PPB4V0<br>~~Ge~~|GFB2/IO109PPB4V0<br>~~Ge~~|
|G4<br>~~a se~~|GFA1/IO47PDB3V0<br>~~se~~|GFA2/IO71PDB3V0<br>~~se~~|GFA2/IO75PDB4V0<br>~~se~~|GFA2/IO110PDB4V0<br>~~se~~|
|G5<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|G6<br>~~Ge~~|GFA0/IO47NDB3V0<br>~~Ge~~|IO71NDB3V0<br>~~Ge~~|IO75NDB4V0<br>~~Ge~~|IO110NDB4V0<br>~~Ge~~|
|G7<br>~~a se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|
|G8<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|
|G9<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|G10<br>~~a se~~|VCC<br>~~se~~|VCC<br>~~se~~|VCC<br>~~se~~|VCC<br>~~se~~|
|G11<br>~~Ge~~|GDA1/IO37NDB1V0<br>~~Ge~~|GCC0/IO47NDB1V0<br>~~Ge~~|GCC0/IO43NDB2V0<br>~~Ge~~|GCC0/IO62NDB2V0<br>~~Ge~~|
|G12<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|G13<br>~~a se~~|IO37PDB1V0<br>~~se~~|GCC1/IO47PDB1V0<br>~~se~~|GCC1/IO43PDB2V0<br>~~se~~|GCC1/IO62PDB2V0<br>~~se~~|
|G14<br>~~Ge~~|GCB0/IO35NPB1V0<br>~~Ge~~|IO46NPB1V0<br>~~Ge~~|IO41NPB2V0<br>~~Ge~~|IO61NPB2V0<br>~~Ge~~|
|G15<br>~~Ge~~|VCCIB1<br>~~Ge~~|VCCIB1<br>~~Ge~~|VCCIB2<br>~~Ge~~|VCCIB2<br>~~Ge~~|
|G16<br>~~a~~|GCB1/IO35PPB1V0|GCC2/IO46PPB1V0|GCC2/IO41PPB2V0|GCC2/IO61PPB2V0|
|H1<br>~~a~~|GEB1/IO45PDB3V0|GFC2/IO69PDB3V0|GFC2/IO73PDB4V0|GFC2/IO108PDB4V0|
|H2<br>~~a~~|GEB0/IO45NDB3V0<br>~~se~~|IO69NDB3V0<br>~~se~~|IO73NDB4V0|IO108NDB4V0|
**Revision 8**
**4-14**
_Package Pin Assignments_
|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|
|---|---|---|---|---|
|**Pin Number**<br>~~a~~<br>~~a~~|**AFS090 Function**<br>~~es~~|**AFS250 Function**|**AFS600 Function**|**AFS1500 Function**|
|H3<br>~~a~~<br>~~a~~|XTAL2<br>~~es~~|XTAL2|XTAL2|XTAL2|
|H4<br>~~aa~~<br>~~a~~|XTAL1<br>~~es~~<br>|XTAL1<br>|XTAL1<br>|XTAL1<br>|
|H5<br>~~a~~<br>~~a~~|GNDOSC<br>~~es~~<br>|GNDOSC<br>|GNDOSC<br>|GNDOSC<br>|
|H6<br>~~a~~|VCCOSC<br>~~es~~<br>|VCCOSC<br>|VCCOSC<br>|VCCOSC<br>|
|H7<br>~~aGe~~|VCC<br>~~es~~<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|
|H8<br>~~a ~~<br>~~a~~|GND<br> ~~se~~<br>|GND<br>~~se~~<br>|GND<br>~~se~~<br>|GND<br>~~se~~<br>|
|H9<br>~~a~~|VCC<br>|VCC<br>|VCC<br>|VCC<br>|
|H10<br>~~aGe~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|H11<br>~~a ~~<br>~~a~~|GDC0/IO38NDB1V0<br> ~~se~~<br>|IO51NDB1V0<br>~~se~~<br>|IO47NDB2V0<br>~~se~~<br>|IO69NDB2V0<br>~~se~~<br>|
|H12<br>~~a~~|GDC1/IO38PDB1V0<br>|IO51PDB1V0<br>|IO47PDB2V0<br>|IO69PDB2V0<br>|
|H13<br>~~aGe~~|GDB1/IO39PDB1V0<br>~~Ge~~|GCA1/IO49PDB1V0<br>~~Ge~~|GCA1/IO45PDB2V0<br>~~Ge~~|GCA1/IO64PDB2V0<br>~~Ge~~|
|H14<br>~~a se~~|GDB0/IO39NDB1V0<br>~~se~~|GCA0/IO49NDB1V0<br>~~se~~|GCA0/IO45NDB2V0<br>~~se~~|GCA0/IO64NDB2V0<br>~~se~~|
|H15<br>~~Ge~~|GCA0/IO36NDB1V0<br>~~Ge~~|GCB0/IO48NDB1V0<br>~~Ge~~|GCB0/IO44NDB2V0<br>~~Ge~~|GCB0/IO63NDB2V0<br>~~Ge~~|
|H16<br>~~Ge~~|GCA1/IO36PDB1V0<br>~~Ge~~|GCB1/IO48PDB1V0<br>~~Ge~~|GCB1/IO44PDB2V0<br>~~Ge~~|GCB1/IO63PDB2V0<br>~~Ge~~|
|J1<br>~~a se~~|GEA0/IO44NDB3V0<br>~~se~~|GFA0/IO66NDB3V0<br>~~se~~|GFA0/IO70NDB4V0<br>~~se~~|GFA0/IO105NDB4V0<br>~~se~~|
|J2<br>~~Ge~~|GEA1/IO44PDB3V0<br>~~Ge~~|GFA1/IO66PDB3V0<br>~~Ge~~|GFA1/IO70PDB4V0<br>~~Ge~~|GFA1/IO105PDB4V0<br>~~Ge~~|
|J3<br>~~Ge~~|IO43NDB3V0<br>~~Ge~~|GFB0/IO67NDB3V0<br>~~Ge~~|GFB0/IO71NDB4V0<br>~~Ge~~|GFB0/IO106NDB4V0<br>~~Ge~~|
|J4<br>~~a se~~|GEC2/IO43PDB3V0<br>~~se~~|GFB1/IO67PDB3V0<br>~~se~~|GFB1/IO71PDB4V0<br>~~se~~|GFB1/IO106PDB4V0<br>~~se~~|
|J5<br>~~Ge~~|NC<br>~~Ge~~|GFC0/IO68NDB3V0<br>~~Ge~~|GFC0/IO72NDB4V0<br>~~Ge~~|GFC0/IO107NDB4V0<br>~~Ge~~|
|J6<br>~~Ge~~|NC<br>~~Ge~~|GFC1/IO68PDB3V0<br>~~Ge~~|GFC1/IO72PDB4V0<br>~~Ge~~|GFC1/IO107PDB4V0<br>~~Ge~~|
|J7<br>~~a se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|GND<br>~~se~~|
|J8<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|VCC<br>~~Ge~~|
|J9<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|J10<br>~~a se~~|VCC<br>~~se~~|VCC<br>~~se~~|VCC<br>~~se~~|VCC<br>~~se~~|
|J11<br>~~Ge~~|GDC2/IO41NPB1V0<br>~~Ge~~|IO56NPB1V0<br>~~Ge~~|IO56NPB2V0<br>~~Ge~~|IO83NPB2V0<br>~~Ge~~|
|J12<br>~~Ge~~|NC<br>~~Ge~~|GDB0/IO53NPB1V0<br>~~Ge~~|GDB0/IO53NPB2V0<br>~~Ge~~|GDB0/IO80NPB2V0<br>~~Ge~~|
|J13<br>~~a se~~|NC<br>~~se~~|GDA1/IO54PDB1V0<br>~~se~~|GDA1/IO54PDB2V0<br>~~se~~|GDA1/IO81PDB2V0<br>~~se~~|
|J14<br>~~Ge~~|GDA0/IO40PDB1V0<br>~~Ge~~|GDC1/IO52PPB1V0<br>~~Ge~~|GDC1/IO52PPB2V0<br>~~Ge~~|GDC1/IO79PPB2V0<br>~~Ge~~|
|J15<br>~~Ge~~|NC<br>~~Ge~~|IO50NPB1V0<br>~~Ge~~|IO51NSB2V0<br>~~Ge~~|IO77NSB2V0<br>~~Ge~~|
|J16<br>~~a se~~|GDA2/IO40NDB1V0<br>~~se~~|GDC0/IO52NPB1V0<br>~~se~~|GDC0/IO52NPB2V0<br>~~se~~|GDC0/IO79NPB2V0<br>~~se~~|
|K1<br>~~Ge~~|NC<br>~~Ge~~|IO65NPB3V0<br>~~Ge~~|IO67NPB4V0<br>~~Ge~~|IO92NPB4V0<br>~~Ge~~|
|K2<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB4<br>~~Ge~~|VCCIB4<br>~~Ge~~|
|K3<br>~~a se~~|NC<br>~~se~~|IO65PPB3V0<br>~~se~~|IO67PPB4V0<br>~~se~~|IO92PPB4V0<br>~~se~~|
|K4<br>~~Ge~~|NC<br>~~Ge~~|IO64PDB3V0<br>~~Ge~~|IO65PDB4V0<br>~~Ge~~|IO96PDB4V0<br>~~Ge~~|
|K5<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|K6<br>~~a~~|NC|IO64NDB3V0|IO65NDB4V0|IO96NDB4V0|
|K7<br>~~a~~|VCC|VCC|VCC|VCC|
|K8<br>~~a~~|GND<br>~~se~~|GND<br>~~se~~|GND|GND|
**4-15**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|
|---|---|---|---|---|
|**Pin Number**<br>~~a~~<br>~~a~~|**AFS090 Function**<br>~~es~~|**AFS250 Function**|**AFS600 Function**|**AFS1500 Function**|
|K9<br>~~a~~<br>~~a~~|VCC<br>~~es~~|VCC|VCC|VCC|
|K10<br>~~aa~~<br>~~a~~|GND<br>~~es~~<br>|GND<br>|GND<br>|GND<br>|
|K11<br>~~a~~<br>~~a~~|NC<br>~~es~~<br>|GDC2/IO57PPB1V0<br>|GDC2/IO57PPB2V0<br>|GDC2/IO84PPB2V0<br>|
|K12<br>~~a~~|GND<br>~~es~~<br>|GND<br>|GND<br>|GND<br>|
|K13<br>~~aGe~~|NC<br>~~es~~<br>~~Ge~~|GDA0/IO54NDB1V0<br>~~Ge~~|GDA0/IO54NDB2V0<br>~~Ge~~|GDA0/IO81NDB2V0<br>~~Ge~~|
|K14<br>~~a ~~<br>~~a~~|NC<br> ~~se~~<br>|GDA2/IO55PPB1V0<br>~~se~~<br>|GDA2/IO55PPB2V0<br>~~se~~<br>|GDA2/IO82PPB2V0<br>~~se~~<br>|
|K15<br>~~a~~|VCCIB1<br>|VCCIB1<br>|VCCIB2<br>|VCCIB2<br>|
|K16<br>~~aGe~~|NC<br>~~Ge~~|GDB1/IO53PPB1V0<br>~~Ge~~|GDB1/IO53PPB2V0<br>~~Ge~~|GDB1/IO80PPB2V0<br>~~Ge~~|
|L1<br>~~a ~~<br>~~a~~|NC<br> ~~se~~<br>|GEC1/IO63PDB3V0<br>~~se~~<br>|GEC1/IO63PDB4V0<br>~~se~~<br>|GEC1/IO90PDB4V0<br>~~se~~<br>|
|L2<br>~~a~~|NC<br>|GEC0/IO63NDB3V0<br>|GEC0/IO63NDB4V0<br>|GEC0/IO90NDB4V0<br>|
|L3<br>~~aGe~~|NC<br>~~Ge~~|GEB1/IO62PDB3V0<br>~~Ge~~|GEB1/IO62PDB4V0<br>~~Ge~~|GEB1/IO89PDB4V0<br>~~Ge~~|
|L4<br>~~a se~~|NC<br>~~se~~|GEB0/IO62NDB3V0<br>~~se~~|GEB0/IO62NDB4V0<br>~~se~~|GEB0/IO89NDB4V0<br>~~se~~|
|L5<br>~~Ge~~|NC<br>~~Ge~~|IO60NDB3V0<br>~~Ge~~|IO60NDB4V0<br>~~Ge~~|IO87NDB4V0<br>~~Ge~~|
|L6<br>~~Ge~~|NC<br>~~Ge~~|GEC2/IO60PDB3V0<br>~~Ge~~|GEC2/IO60PDB4V0<br>~~Ge~~|GEC2/IO87PDB4V0<br>~~Ge~~|
|L7<br>~~a se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|
|L8<br>~~Ge~~|AC0<br>~~Ge~~|AC0<br>~~Ge~~|AC2<br>~~Ge~~|AC2<br>~~Ge~~|
|L9<br>~~Ge~~|AV2<br>~~Ge~~|AV2<br>~~Ge~~|AV4<br>~~Ge~~|AV4<br>~~Ge~~|
|L10<br>~~a se~~|AC3<br>~~se~~|AC3<br>~~se~~|AC5<br>~~se~~|AC5<br>~~se~~|
|L11<br>~~Ge~~|PTEM<br>~~Ge~~|PTEM<br>~~Ge~~|PTEM<br>~~Ge~~|PTEM<br>~~Ge~~|
|L12<br>~~Ge~~|TDO<br>~~Ge~~|TDO<br>~~Ge~~|TDO<br>~~Ge~~|TDO<br>~~Ge~~|
|L13<br>~~a se~~|VJTAG<br>~~se~~|VJTAG<br>~~se~~|VJTAG<br>~~se~~|VJTAG<br>~~se~~|
|L14<br>~~Ge~~|NC<br>~~Ge~~|IO57NPB1V0<br>~~Ge~~|IO57NPB2V0<br>~~Ge~~|IO84NPB2V0<br>~~Ge~~|
|L15<br>~~Ge~~|GDB2/IO41PPB1V0<br>~~Ge~~|GDB2/IO56PPB1V0<br>~~Ge~~|GDB2/IO56PPB2V0<br>~~Ge~~|GDB2/IO83PPB2V0<br>~~Ge~~|
|L16<br>~~a se~~|NC<br>~~se~~|IO55NPB1V0<br>~~se~~|IO55NPB2V0<br>~~se~~|IO82NPB2V0<br>~~se~~|
|M1<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|M2<br>~~Ge~~|NC<br>~~Ge~~|GEA1/IO61PDB3V0<br>~~Ge~~|GEA1/IO61PDB4V0<br>~~Ge~~|GEA1/IO88PDB4V0<br>~~Ge~~|
|M3<br>~~a se~~|NC<br>~~se~~|GEA0/IO61NDB3V0<br>~~se~~|GEA0/IO61NDB4V0<br>~~se~~|GEA0/IO88NDB4V0<br>~~se~~|
|M4<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB4<br>~~Ge~~|VCCIB4<br>~~Ge~~|
|M5<br>~~Ge~~|NC<br>~~Ge~~|IO58NPB3V0<br>~~Ge~~|IO58NPB4V0<br>~~Ge~~|IO85NPB4V0<br>~~Ge~~|
|M6<br>~~a se~~|NC<br>~~se~~|NC<br>~~se~~|AV0<br>~~se~~|AV0<br>~~se~~|
|M7<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AC1<br>~~Ge~~|AC1<br>~~Ge~~|
|M8<br>~~Ge~~|AG1<br>~~Ge~~|AG1<br>~~Ge~~|AG3<br>~~Ge~~|AG3<br>~~Ge~~|
|M9<br>~~a se~~|AC2<br>~~se~~|AC2<br>~~se~~|AC4<br>~~se~~|AC4<br>~~se~~|
|M10<br>~~Ge~~|AC4<br>~~Ge~~|AC4<br>~~Ge~~|AC6<br>~~Ge~~|AC6<br>~~Ge~~|
|M11<br>~~Ge~~|NC<br>~~Ge~~|AG5<br>~~Ge~~|AG7<br>~~Ge~~|AG7<br>~~Ge~~|
|M12<br>~~a~~|VPUMP|VPUMP|VPUMP|VPUMP|
|M13<br>~~a~~|VCCIB1|VCCIB1|VCCIB2|VCCIB2|
|M14<br>~~a~~|TMS<br>~~se~~|TMS<br>~~se~~|TMS|TMS|
**Revision 8**
**4-16**
_Package Pin Assignments_
|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|
|---|---|---|---|---|
|**Pin Number**<br>~~a~~<br>~~a~~|**AFS090 Function**<br>~~es~~|**AFS250 Function**|**AFS600 Function**|**AFS1500 Function**|
|M15<br>~~a~~<br>~~a~~|TRST<br>~~es~~|TRST|TRST|TRST|
|M16<br>~~aa~~<br>~~a~~|GND<br>~~es~~<br>|GND<br>|GND<br>|GND<br>|
|N1<br>~~a~~<br>~~a~~|GEB2/IO42PDB3V0<br>~~es~~<br>|GEB2/IO59PDB3V0<br>|GEB2/IO59PDB4V0<br>|GEB2/IO86PDB4V0<br>|
|N2<br>~~a~~|GEA2/IO42NDB3V0<br>~~es~~<br>|IO59NDB3V0<br>|IO59NDB4V0<br>|IO86NDB4V0<br>|
|N3<br>~~aGe~~|NC<br>~~es~~<br>~~Ge~~|GEA2/IO58PPB3V0<br>~~Ge~~|GEA2/IO58PPB4V0<br>~~Ge~~|GEA2/IO85PPB4V0<br>~~Ge~~|
|N4<br>~~a ~~<br>~~a~~|VCC33PMP<br> ~~se~~<br>|VCC33PMP<br>~~se~~<br>|VCC33PMP<br>~~se~~<br>|VCC33PMP<br>~~se~~<br>|
|N5<br>~~a~~|VCC15A<br>|VCC15A<br>|VCC15A<br>|VCC15A<br>|
|N6<br>~~aGe~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AG0<br>~~Ge~~|AG0<br>~~Ge~~|
|N7<br>~~a ~~<br>~~a~~|AC1<br> ~~se~~<br>|AC1<br>~~se~~<br>|AC3<br>~~se~~<br>|AC3<br>~~se~~<br>|
|N8<br>~~a~~|AG3<br>|AG3<br>|AG5<br>|AG5<br>|
|N9<br>~~aGe~~|AV3<br>~~Ge~~|AV3<br>~~Ge~~|AV5<br>~~Ge~~|AV5<br>~~Ge~~|
|N10<br>~~a se~~|AG4<br>~~se~~|AG4<br>~~se~~|AG6<br>~~se~~|AG6<br>~~se~~|
|N11<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AC8<br>~~Ge~~|AC8<br>~~Ge~~|
|N12<br>~~Ge~~|GNDA<br>~~Ge~~|GNDA<br>~~Ge~~|GNDA<br>~~Ge~~|GNDA<br>~~Ge~~|
|N13<br>~~a se~~|VCC33A<br>~~se~~|VCC33A<br>~~se~~|VCC33A<br>~~se~~|VCC33A<br>~~se~~|
|N14<br>~~Ge~~|VCCNVM<br>~~Ge~~|VCCNVM<br>~~Ge~~|VCCNVM<br>~~Ge~~|VCCNVM<br>~~Ge~~|
|N15<br>~~Ge~~|TCK<br>~~Ge~~|TCK<br>~~Ge~~|TCK<br>~~Ge~~|TCK<br>~~Ge~~|
|N16<br>~~a se~~|TDI<br>~~se~~|TDI<br>~~se~~|TDI<br>~~se~~|TDI<br>~~se~~|
|P1<br>~~Ge~~|VCCNVM<br>~~Ge~~|VCCNVM<br>~~Ge~~|VCCNVM<br>~~Ge~~|VCCNVM<br>~~Ge~~|
|P2<br>~~Ge~~|GNDNVM<br>~~Ge~~|GNDNVM<br>~~Ge~~|GNDNVM<br>~~Ge~~|GNDNVM<br>~~Ge~~|
|P3<br>~~a se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|
|P4<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AC0<br>~~Ge~~|AC0<br>~~Ge~~|
|P5<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AG1<br>~~Ge~~|AG1<br>~~Ge~~|
|P6<br>~~a se~~|NC<br>~~se~~|NC<br>~~se~~|AV1<br>~~se~~|AV1<br>~~se~~|
|P7<br>~~Ge~~|AG0<br>~~Ge~~|AG0<br>~~Ge~~|AG2<br>~~Ge~~|AG2<br>~~Ge~~|
|P8<br>~~Ge~~|AG2<br>~~Ge~~|AG2<br>~~Ge~~|AG4<br>~~Ge~~|AG4<br>~~Ge~~|
|P9<br>~~a se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|GNDA<br>~~se~~|
|P10<br>~~Ge~~|NC<br>~~Ge~~|AC5<br>~~Ge~~|AC7<br>~~Ge~~|AC7<br>~~Ge~~|
|P11<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AV8<br>~~Ge~~|AV8<br>~~Ge~~|
|P12<br>~~a se~~|NC<br>~~se~~|NC<br>~~se~~|AG8<br>~~se~~|AG8<br>~~se~~|
|P13<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AV9<br>~~Ge~~|AV9<br>~~Ge~~|
|P14<br>~~Ge~~|ADCGNDREF<br>~~Ge~~|ADCGNDREF<br>~~Ge~~|ADCGNDREF<br>~~Ge~~|ADCGNDREF<br>~~Ge~~|
|P15<br>~~a se~~|PTBASE<br>~~se~~|PTBASE<br>~~se~~|PTBASE<br>~~se~~|PTBASE<br>~~se~~|
|P16<br>~~Ge~~|GNDNVM<br>~~Ge~~|GNDNVM<br>~~Ge~~|GNDNVM<br>~~Ge~~|GNDNVM<br>~~Ge~~|
|R1<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB3<br>~~Ge~~|VCCIB4<br>~~Ge~~|VCCIB4<br>~~Ge~~|
|R2<br>~~a~~|PCAP|PCAP|PCAP|PCAP|
|R3<br>~~a~~|NC|NC|AT1|AT1|
|R4<br>~~a~~|NC<br>~~se~~|NC<br>~~se~~|AT0|AT0|
**4-17**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|**FG256**<br>~~ee~~<br>~~a~~<br>~~es~~|
|---|---|---|---|---|
|**Pin Number**<br>~~a~~<br>~~a~~|**AFS090 Function**<br>~~es~~|**AFS250 Function**|**AFS600 Function**|**AFS1500 Function**|
|R5<br>~~a~~<br>~~a~~|AV0<br>~~es~~|AV0|AV2|AV2|
|R6<br>~~aa~~<br>~~a~~|AT0<br>~~es~~<br>|AT0<br>|AT2<br>|AT2<br>|
|R7<br>~~a~~<br>~~a~~|AV1<br>~~es~~<br>|AV1<br>|AV3<br>|AV3<br>|
|R8<br>~~a~~|AT3<br>~~es~~<br>|AT3<br>|AT5<br>|AT5<br>|
|R9<br>~~aGe~~|AV4<br>~~es~~<br>~~Ge~~|AV4<br>~~Ge~~|AV6<br>~~Ge~~|AV6<br>~~Ge~~|
|R10<br>~~a ~~<br>~~a~~|NC<br> ~~se~~<br>|AT5<br>~~se~~<br>|AT7<br>~~se~~<br>|AT7<br>~~se~~<br>|
|R11<br>~~a~~|NC<br>|AV5<br>|AV7<br>|AV7<br>|
|R12<br>~~aGe~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AT9<br>~~Ge~~|AT9<br>~~Ge~~|
|R13<br>~~a ~~<br>~~a~~|NC<br> ~~se~~<br>|NC<br>~~se~~<br>|AG9<br>~~se~~<br>|AG9<br>~~se~~<br>|
|R14<br>~~a~~|NC<br>|NC<br>|AC9<br>|AC9<br>|
|R15<br>~~aGe~~|PUB<br>~~Ge~~|PUB<br>~~Ge~~|PUB<br>~~Ge~~|PUB<br>~~Ge~~|
|R16<br>~~a se~~|VCCIB1<br>~~se~~|VCCIB1<br>~~se~~|VCCIB2<br>~~se~~|VCCIB2<br>~~se~~|
|T1<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
|T2<br>~~Ge~~|NCAP<br>~~Ge~~|NCAP<br>~~Ge~~|NCAP<br>~~Ge~~|NCAP<br>~~Ge~~|
|T3<br>~~a se~~|VCC33N<br>~~se~~|VCC33N<br>~~se~~|VCC33N<br>~~se~~|VCC33N<br>~~se~~|
|T4<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|ATRTN0<br>~~Ge~~|ATRTN0<br>~~Ge~~|
|T5<br>~~Ge~~|AT1<br>~~Ge~~|AT1<br>~~Ge~~|AT3<br>~~Ge~~|AT3<br>~~Ge~~|
|T6<br>~~a se~~|ATRTN0<br>~~se~~|ATRTN0<br>~~se~~|ATRTN1<br>~~se~~|ATRTN1<br>~~se~~|
|T7<br>~~Ge~~|AT2<br>~~Ge~~|AT2<br>~~Ge~~|AT4<br>~~Ge~~|AT4<br>~~Ge~~|
|T8<br>~~Ge~~|ATRTN1<br>~~Ge~~|ATRTN1<br>~~Ge~~|ATRTN2<br>~~Ge~~|ATRTN2<br>~~Ge~~|
|T9<br>~~a se~~|AT4<br>~~se~~|AT4<br>~~se~~|AT6<br>~~se~~|AT6<br>~~se~~|
|T10<br>~~Ge~~|ATRTN2<br>~~Ge~~|ATRTN2<br>~~Ge~~|ATRTN3<br>~~Ge~~|ATRTN3<br>~~Ge~~|
|T11<br>~~Ge~~|NC<br>~~Ge~~|NC<br>~~Ge~~|AT8<br>~~Ge~~|AT8<br>~~Ge~~|
|T12<br>~~a se~~|NC<br>~~se~~|NC<br>~~se~~|ATRTN4<br>~~se~~|ATRTN4<br>~~se~~|
|T13<br>~~Ge~~|GNDA<br>~~Ge~~|GNDA<br>~~Ge~~|GNDA<br>~~Ge~~|GNDA<br>~~Ge~~|
|T14<br>~~Ge~~|VCC33A<br>~~Ge~~|VCC33A<br>~~Ge~~|VCC33A<br>~~Ge~~|VCC33A<br>~~Ge~~|
|T15<br>~~a se~~|VAREF<br>~~se~~|VAREF<br>~~se~~|VAREF<br>~~se~~|VAREF<br>~~se~~|
|T16<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|GND<br>~~Ge~~|
**Revision 8**
**4-18**
_Package Pin Assignments_
## **FG484**
|**A1 Ball Pad Corner**|**A1 Ball Pad Corner**|
|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14<br>15<br>16<br>17<br>18<br>19<br>20<br>21<br>22||
|(ORORORORORORORORORORORORORORORORORORORORONO|A|
|(ORORORORORORORORORORORORORORORORORORORORONO)|B|
|(ORORORORORORORORORORORORORORORORORORORORONO)|C|
|(OROROROROROROROROROROROROROROROROROROROROXO)|D|
|(ORORORORORORORORORORORORORORORORORORORORONO)|E|
|(ORORORORORORORORORORORORORORORORORORORORONC)|F|
|ORORORORORORORORORORORORORORORORORORORORONO|G|
|(ORORORORORORORORORORORORORORORORORORORORONO|H|
|(ORORORORORORORORORORORORORORORORORORORORONC)|J|
|(OROROROROROROROROROROROROROROROROROROROROC|K|
|(ORORORORORORORORORORORORORORORORORORORORONO|L|
|ORORORORORORORORORORORORORORORORORORORORONO)|M|
|(ORORORORORORORORORORORORORORORORORORORORONC)|N|
|(OROROROROROROROROROROROROROROROROROROROROXC|P|
|ORORORORORORORORORORORORORORORORORORORORONC)|R|
|(ORORORORORORORORORORORORORORORORORORORORONO|T|
|(OROROROROROROROROROROROROROROROROROROROROXC)|U|
|(ORORORORORORORORORORORORORORORORORORORORONO|V|
|(ORORORORORORORORORORORORORORORORORORORORORO|W|
|(ORORORORORORORORORORORORORORORORORORORORONO|Y|
|(ORORORORORORORORORORORORORORORORORORORORONC)|AA|
|(OROROROROROROROROROROROROROROROROROROROHOXO)|AB|
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-19**
**Revision 8**
_Package Pin Assignments_
|**FG484**<br>**FG484**<br>~~ee~~|
|---|
|**Pin**<br>**Pin**|
|**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**|
|A1<br>GND<br>GND<br>A2<br>VCC<br>NC<br>A3<br>GAA1/IO01PDB0V0<br>GAA1/IO01PDB0V0<br>A4<br>GAB0/IO02NDB0V0<br>GAB0/IO02NDB0V0<br>AA14<br>AG7<br>AG7<br>AA15<br>AG8<br>AG8<br>AA16<br>GNDA<br>GNDA<br>AA17<br>AG9<br>AG9<br>~~ee0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|A5<br>GAB1/IO02PDB0V0<br>GAB1/IO02PDB0V0<br>AA18<br>VAREF<br>VAREF<br>~~a 0~~|
|A6<br>IO07NDB0V1<br>IO07NDB0V1<br>AA19<br>VCCIB2<br>VCCIB2<br>~~ee~~|
|A7<br>IO07PDB0V1<br>IO07PDB0V1<br>A8<br>IO10PDB0V1<br>IO09PDB0V1<br>A9<br>IO14NDB0V1<br>IO13NDB0V2<br>A10<br>IO14PDB0V1<br>IO13PDB0V2<br>AA20<br>PTEM<br>PTEM<br>AA21<br>GND<br>GND<br>AA22<br>VCC<br>NC<br>AB1<br>GND<br>GND<br>~~0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|A11<br>IO17PDB1V0<br>IO24PDB1V0<br>AB2<br>VCC<br>NC<br>~~a~~<br>~~0~~|
|A12<br>IO18PDB1V0<br>IO26PDB1V0<br>AB3<br>NC<br>IO94NSB4V0<br>~~a~~|
|A13<br>IO19NDB1V0<br>IO27NDB1V1<br>A14<br>IO19PDB1V0<br>IO27PDB1V1<br>A15<br>IO24NDB1V1<br>IO35NDB1V2<br>A16<br>IO24PDB1V1<br>IO35PDB1V2<br>A17<br>GBC0/IO26NDB1V1<br>GBC0/IO40NDB1V2<br>AB4<br>GND<br>GND<br>AB5<br>VCC33N<br>VCC33N<br>AB6<br>AT0<br>AT0<br>AB7<br>ATRTN0<br>ATRTN0<br>AB8<br>AT1<br>AT1<br>~~a~~<br>~~0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|A18<br>GBA0/IO28NDB1V1<br>GBA0/IO42NDB1V2<br>A19<br>IO29NDB1V1<br>IO43NDB1V2<br>A20<br>IO29PDB1V1<br>IO43PDB1V2<br>A21<br>VCC<br>NC<br>A22<br>GND<br>GND<br>AA1<br>VCC<br>NC<br>AB9<br>AT2<br>AT2<br>AB10<br>ATRTN1<br>ATRTN1<br>AB11<br>AT3<br>AT3<br>AB12<br>AT6<br>AT6<br>AB13<br>ATRTN3<br>ATRTN3<br>AB14<br>AT7<br>AT7<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|AA2<br>GND<br>GND<br>AA3<br>VCCIB4<br>VCCIB4<br>AA4<br>VCCIB4<br>VCCIB4<br>AA5<br>PCAP<br>PCAP<br>AA6<br>AG0<br>AG0<br>AA7<br>GNDA<br>GNDA<br>AB15<br>AT8<br>AT8<br>AB16<br>ATRTN4<br>ATRTN4<br>AB17<br>AT9<br>AT9<br>AB18<br>VCC33A<br>VCC33A<br>AB19<br>GND<br>GND<br>AB20<br>NC<br>IO76NPB2V0<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|AA8<br>AG1<br>AG1<br>AB21<br>VCC<br>NC<br>~~ee~~|
|AA9<br>AG2<br>AG2<br>AA10<br>GNDA<br>GNDA<br>AA11<br>AG3<br>AG3<br>AA12<br>AG6<br>AG6<br>AA13<br>GNDA<br>GNDA<br>AB22<br>GND<br>GND<br>B1<br>VCC<br>NC<br>B2<br>GND<br>GND<br>B3<br>GAA0/IO01NDB0V0<br>GAA0/IO01NDB0V0<br>B4<br>GND<br>GND<br>~~a 0~~<br>~~Ce~~<br>~~0~~<br>~~Fs0~~<br>~~Fs0~~<br>~~a De~~<br>~~0~~|
**4-20**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG484**<br>~~ee~~|||**FG484**||
|---|---|---|---|---|
|**Pin**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>**Pin**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>~~eeee~~|||||
|B5<br>IO05NDB0V0<br>IO04NDB0V0<br>B6<br>IO05PDB0V0<br>IO04PDB0V0<br>B7<br>GND<br>GND<br>~~ee~~<br>~~Ha De~~<br>~~a~~||C18<br>C19<br>C20|VCCIB1<br>VCOMPLB<br>GBA2/IO30PDB2V0|VCCIB1<br>VCOMPLB<br>GBA2/IO44PDB2V0|
|B8<br>IO10NDB0V1<br>IO09NDB0V1<br>~~a~~<br>~~ee~~||C21|NC|IO48PSB2V0|
|B9<br>IO13PDB0V1<br>IO11PDB0V1<br>~~ee~~<br>~~a~~||C22|GBB2/IO31PDB2V0|GBB2/IO45PDB2V0<br>~~|~~|
|B10<br>GND<br>GND||D1|IO82NDB4V0|IO121NDB4V0|
|B11<br>IO17NDB1V0<br>IO24NDB1V0<br>B12<br>IO18NDB1V0<br>IO26NDB1V0<br>B13<br>GND<br>GND<br>~~Ha De~~<br>~~a~~||D2<br>D3<br>D4|GND<br>IO83NDB4V0<br>GAC2/IO83PDB4V0|GND<br>IO123NDB4V0<br>GAC2/IO123PDB4V0|
|B14<br>IO21NDB1V0<br>IO31NDB1V1<br>~~a~~<br>~~ee~~||D5|GAA2/IO85PDB4V0|GAA2/IO125PDB4V0|
|B15<br>IO21PDB1V0<br>IO31PDB1V1<br>~~a~~<br>~~ee~~||D6|GAC0/IO03NDB0V0|GAC0/IO03NDB0V0<br>~~|~~|
|B16<br>GND<br>GND||D7|GAC1/IO03PDB0V0|GAC1/IO03PDB0V0|
|B17<br>GBC1/IO26PDB1V1<br>GBC1/IO40PDB1V2<br>B18<br>GBA1/IO28PDB1V1<br>GBA1/IO42PDB1V2<br>B19<br>GND<br>GND<br>~~a ~~<br>~~Fa De~~<br>~~a~~|9|D8<br>D9<br>D10|IO09NDB0V1<br>IO09PDB0V1<br>IO11NDB0V1|IO10NDB0V1<br>IO10PDB0V1<br>IO14NDB0V2|
|B20<br>VCCPLB<br>VCCPLB<br>D11<br>IO16NDB1V0<br>IO23NDB1V0<br>~~a~~<br>~~eeee~~|||||
|B21<br>GND<br>GND<br>~~a~~<br>~~ee~~||D12|IO16PDB1V0|IO23PDB1V0<br>~~|~~|
|B22<br>VCC<br>NC||D13|NC|IO32NPB1V1|
|C1<br>IO82PDB4V0<br>IO121PDB4V0<br>C2<br>NC<br>IO122PSB4V0<br>C3<br>IO00NDB0V0<br>IO00NDB0V0<br>~~ee ~~<br>~~Fa De~~<br>~~a~~|9|D14<br>D15<br>D16|IO23NDB1V1<br>IO23PDB1V1<br>IO25PDB1V1|IO34NDB1V1<br>IO34PDB1V1<br>IO37PDB1V2|
|C4<br>IO00PDB0V0<br>IO00PDB0V0<br>D17<br>GBB1/IO27PDB1V1<br>GBB1/IO41PDB1V2<br>~~a~~<br>~~eeee~~|||||
|C5<br>VCCIB0<br>VCCIB0<br>~~ee~~<br>~~a~~||D18|VCCIB2|VCCIB2<br>~~|~~|
|C6<br>IO06NDB0V0<br>IO05NDB0V1||D19|NC|IO47PPB2V0|
|C7<br>IO06PDB0V0<br>IO05PDB0V1<br>C8<br>VCCIB0<br>VCCIB0<br>C9<br>IO13NDB0V1<br>IO11NDB0V1<br>D20<br>IO30NDB2V0<br>IO44NDB2V0<br>D21<br>GND<br>GND<br>D22<br>IO31NDB2V0<br>IO45NDB2V0<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~|||||
|C10<br>IO11PDB0V1<br>IO14PDB0V2<br>C11<br>VCCIB0<br>VCCIB0<br>C12<br>VCCIB1<br>VCCIB1<br>~~ee ~~<br>~~**a**~~|0|E1<br>E2<br>E3|IO81NDB4V0<br>IO81PDB4V0<br>VCCIB4|IO120NDB4V0<br>IO120PDB4V0<br>VCCIB4|
|C13<br>IO20NDB1V0<br>IO29NDB1V1<br>C14<br>IO20PDB1V0<br>IO29PDB1V1<br>C15<br>VCCIB1<br>VCCIB1<br>E4<br>GAB2/IO84PDB4V0<br>GAB2/IO124PDB4V0<br>E5<br>IO85NDB4V0<br>IO125NDB4V0<br>E6<br>GND<br>GND<br>~~Ce0~~<br>~~a~~<br>~~Fs0~~|||||
|C16<br>IO25NDB1V1<br>IO37NDB1V2<br>C17<br>GBB0/IO27NDB1V1<br>GBB0/IO41NDB1V2<br>~~ee~~<br>~~**a**~~|9|E7<br>E8<br>~~ee~~|VCCIB0<br>NC|VCCIB0<br>IO08NDB0V1|
**Revision 8**
**4-21**
_Package Pin Assignments_
|**FG484**<br>**FG484**<br>~~ee~~|
|---|
|**Pin**<br>**Pin**|
|**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**|
|E9<br>NC<br>IO08PDB0V1<br>E10<br>GND<br>GND<br>E11<br>IO15NDB1V0<br>IO22NDB1V0<br>E12<br>IO15PDB1V0<br>IO22PDB1V0<br>F22<br>IO35PDB2V0<br>IO51PDB2V0<br>G1<br>IO77PDB4V0<br>IO115PDB4V0<br>G2<br>GND<br>GND<br>G3<br>IO78NDB4V0<br>IO116NDB4V0<br>~~ee0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|E13<br>GND<br>GND<br>G4<br>IO78PDB4V0<br>IO116PDB4V0<br>~~a 0~~|
|E14<br>NC<br>IO32PPB1V1<br>G5<br>VCCIB4<br>VCCIB4<br>~~ee~~|
|E15<br>NC<br>IO36NPB1V2<br>E16<br>VCCIB1<br>VCCIB1<br>E17<br>GND<br>GND<br>E18<br>NC<br>IO47NPB2V0<br>G6<br>NC<br>IO117PDB4V0<br>G7<br>VCCIB4<br>VCCIB4<br>G8<br>GND<br>GND<br>G9<br>IO04NDB0V0<br>IO06NDB0V1<br>~~0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|E19<br>IO33PDB2V0<br>IO49PDB2V0<br>G10<br>IO04PDB0V0<br>IO06PDB0V1<br>~~a~~<br>~~0~~|
|E20<br>VCCIB2<br>VCCIB2<br>G11<br>IO12NDB0V1<br>IO16NDB0V2<br>~~a~~|
|E21<br>IO32NDB2V0<br>IO46NDB2V0<br>E22<br>GBC2/IO32PDB2V0<br>GBC2/IO46PDB2V0<br>F1<br>IO80NDB4V0<br>IO118NDB4V0<br>F2<br>IO80PDB4V0<br>IO118PDB4V0<br>F3<br>NC<br>IO119NSB4V0<br>G12<br>IO12PDB0V1<br>IO16PDB0V2<br>G13<br>NC<br>IO28NDB1V1<br>G14<br>NC<br>IO28PDB1V1<br>G15<br>GND<br>GND<br>G16<br>NC<br>IO38PPB1V2<br>~~a~~<br>~~0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|F4<br>IO84NDB4V0<br>IO124NDB4V0<br>F5<br>GND<br>GND<br>F6<br>VCOMPLA<br>VCOMPLA<br>F7<br>VCCPLA<br>VCCPLA<br>F8<br>VCCIB0<br>VCCIB0<br>F9<br>IO08NDB0V1<br>IO12NDB0V1<br>G17<br>NC<br>IO53PDB2V0<br>G18<br>VCCIB2<br>VCCIB2<br>G19<br>IO36PDB2V0<br>IO52PDB2V0<br>G20<br>IO36NDB2V0<br>IO52NDB2V0<br>G21<br>GND<br>GND<br>G22<br>IO35NDB2V0<br>IO51NDB2V0<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|F10<br>IO08PDB0V1<br>IO12PDB0V1<br>F11<br>VCCIB0<br>VCCIB0<br>F12<br>VCCIB1<br>VCCIB1<br>F13<br>IO22NDB1V0<br>IO30NDB1V1<br>F14<br>IO22PDB1V0<br>IO30PDB1V1<br>F15<br>VCCIB1<br>VCCIB1<br>H1<br>IO77NDB4V0<br>IO115NDB4V0<br>H2<br>IO76PDB4V0<br>IO113PDB4V0<br>H3<br>VCCIB4<br>VCCIB4<br>H4<br>IO79NDB4V0<br>IO114NDB4V0<br>H5<br>IO79PDB4V0<br>IO114PDB4V0<br>H6<br>NC<br>IO117NDB4V0<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|F16<br>NC<br>IO36PPB1V2<br>H7<br>GND<br>GND<br>~~ee~~|
|F17<br>NC<br>IO38NPB1V2<br>F18<br>GND<br>GND<br>F19<br>IO33NDB2V0<br>IO49NDB2V0<br>F20<br>IO34PDB2V0<br>IO50PDB2V0<br>F21<br>IO34NDB2V0<br>IO50NDB2V0<br>H8<br>VCC<br>VCC<br>H9<br>VCCIB0<br>VCCIB0<br>H10<br>GND<br>GND<br>H11<br>VCCIB0<br>VCCIB0<br>H12<br>VCCIB1<br>VCCIB1<br>~~a 0~~<br>~~Ce~~<br>~~0~~<br>~~Fs0~~<br>~~Fs0~~<br>~~a De~~<br>~~0~~|
**4-22**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG484**<br>~~ee~~|||**FG484**||
|---|---|---|---|---|
|**Pin**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>**Pin**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>~~eeee~~|||||
|H13<br>GND<br>GND<br>H14<br>VCCIB1<br>VCCIB1<br>H15<br>GND<br>GND<br>~~ee~~<br>~~Ha De~~<br>~~a~~||K4<br>K5<br>K6|IO75NDB4V0<br>GND<br>NC|IO110NDB4V0<br>GND<br>IO104NDB4V0|
|H16<br>GND<br>GND<br>~~a~~<br>~~ee~~||K7|NC|IO111NDB4V0|
|H17<br>NC<br>IO53NDB2V0<br>~~ee~~<br>~~a~~||K8|GND|GND<br>~~|~~|
|H18<br>IO38PDB2V0<br>IO57PDB2V0||K9|VCC|VCC|
|H19<br>GCA2/IO39PDB2V0<br>GCA2/IO59PDB2V0<br>H20<br>VCCIB2<br>VCCIB2<br>H21<br>IO37NDB2V0<br>IO54NDB2V0<br>~~Ha De~~<br>~~a~~||K10<br>K11<br>K12|GND<br>VCC<br>GND|GND<br>VCC<br>GND|
|H22<br>IO37PDB2V0<br>IO54PDB2V0<br>~~a~~<br>~~ee~~||K13|VCC|VCC|
|J1<br>NC<br>IO112PPB4V0<br>~~a~~<br>~~ee~~||K14|GND|GND<br>~~|~~|
|J2<br>IO76NDB4V0<br>IO113NDB4V0||K15|GND|GND|
|J3<br>GFB2/IO74PDB4V0<br>GFB2/IO109PDB4V0<br>J4<br>GFA2/IO75PDB4V0<br>GFA2/IO110PDB4V0<br>J5<br>NC<br>IO112NPB4V0<br>~~a ~~<br>~~Fa De~~<br>~~a~~|9|K16<br>K17<br>K18|IO40NDB2V0<br>NC<br>GND|IO60NDB2V0<br>IO58PDB2V0<br>GND|
|J6<br>NC<br>IO104PDB4V0<br>K19<br>NC<br>IO68NPB2V0<br>~~a~~<br>~~eeee~~|||||
|J7<br>NC<br>IO111PDB4V0<br>~~a~~<br>~~ee~~||K20|IO41NDB2V0|IO61NDB2V0<br>~~|~~|
|J8<br>VCCIB4<br>VCCIB4||K21|GND|GND|
|J9<br>GND<br>GND<br>J10<br>VCC<br>VCC<br>J11<br>GND<br>GND<br>~~ee ~~<br>~~Fa De~~<br>~~a~~|9|K22<br>L1<br>L2|IO42NDB2V0<br>IO73NDB4V0<br>VCCOSC|IO56NDB2V0<br>IO108NDB4V0<br>VCCOSC|
|J12<br>VCC<br>VCC<br>L3<br>VCCIB4<br>VCCIB4<br>~~a~~<br>~~eeee~~|||||
|J13<br>GND<br>GND<br>~~ee~~<br>~~a~~||L4|XTAL2|XTAL2<br>~~|~~|
|J14<br>VCC<br>VCC||L5|GFC1/IO72PDB4V0|GFC1/IO107PDB4V0|
|J15<br>VCCIB2<br>VCCIB2<br>J16<br>GCB2/IO40PDB2V0<br>GCB2/IO60PDB2V0<br>J17<br>NC<br>IO58NDB2V0<br>L6<br>VCCIB4<br>VCCIB4<br>L7<br>GFB1/IO71PDB4V0<br>GFB1/IO106PDB4V0<br>L8<br>VCCIB4<br>VCCIB4<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~|||||
|J18<br>IO38NDB2V0<br>IO57NDB2V0<br>J19<br>IO39NDB2V0<br>IO59NDB2V0<br>J20<br>GCC2/IO41PDB2V0<br>GCC2/IO61PDB2V0<br>~~ee ~~<br>~~**a**~~|0|L9<br>L10<br>L11|GND<br>VCC<br>GND|GND<br>VCC<br>GND|
|J21<br>NC<br>IO55PSB2V0<br>J22<br>IO42PDB2V0<br>IO56PDB2V0<br>K1<br>GFC2/IO73PDB4V0<br>GFC2/IO108PDB4V0<br>L12<br>VCC<br>VCC<br>L13<br>GND<br>GND<br>L14<br>VCC<br>VCC<br>~~Ce0~~<br>~~a~~<br>~~Fs0~~|||||
|K2<br>GND<br>GND<br>K3<br>IO74NDB4V0<br>IO109NDB4V0<br>~~ee~~<br>~~**a**~~|9|L15<br>L16<br>~~ee~~|VCCIB2<br>IO48PDB2V0|VCCIB2<br>IO70PDB2V0|
**Revision 8**
**4-23**
_Package Pin Assignments_
|**FG484**<br>**FG484**<br>~~ee~~|
|---|
|**Pin**<br>**Pin**|
|**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**|
|L17<br>VCCIB2<br>VCCIB2<br>L18<br>IO46PDB2V0<br>IO69PDB2V0<br>L19<br>GCA1/IO45PDB2V0<br>GCA1/IO64PDB2V0<br>L20<br>VCCIB2<br>VCCIB2<br>N8<br>GND<br>GND<br>N9<br>GND<br>GND<br>N10<br>VCC<br>VCC<br>N11<br>GND<br>GND<br>~~ee0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|L21<br>GCC0/IO43NDB2V0<br>GCC0/IO62NDB2V0<br>N12<br>VCC<br>VCC<br>~~a 0~~|
|L22<br>GCC1/IO43PDB2V0<br>GCC1/IO62PDB2V0<br>N13<br>GND<br>GND<br>~~ee~~|
|M1<br>NC<br>IO103PDB4V0<br>M2<br>XTAL1<br>XTAL1<br>M3<br>VCCIB4<br>VCCIB4<br>M4<br>GNDOSC<br>GNDOSC<br>N14<br>VCC<br>VCC<br>N15<br>GND<br>GND<br>N16<br>GDB2/IO56PDB2V0<br>GDB2/IO83PDB2V0<br>N17<br>NC<br>IO78PDB2V0<br>~~0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|M5<br>GFC0/IO72NDB4V0<br>GFC0/IO107NDB4V0<br>N18<br>GND<br>GND<br>~~a~~<br>~~0~~|
|M6<br>VCCIB4<br>VCCIB4<br>N19<br>IO47NDB2V0<br>IO72NDB2V0<br>~~a~~|
|M7<br>GFB0/IO71NDB4V0<br>GFB0/IO106NDB4V0<br>M8<br>VCCIB4<br>VCCIB4<br>M9<br>VCC<br>VCC<br>M10<br>GND<br>GND<br>M11<br>VCC<br>VCC<br>N20<br>IO47PDB2V0<br>IO72PDB2V0<br>N21<br>GND<br>GND<br>N22<br>IO49PDB2V0<br>IO71PDB2V0<br>P1<br>GFA1/IO70PDB4V0<br>GFA1/IO105PDB4V0<br>P2<br>GFA0/IO70NDB4V0<br>GFA0/IO105NDB4V0<br>~~a~~<br>~~0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|M12<br>GND<br>GND<br>M13<br>VCC<br>VCC<br>M14<br>GND<br>GND<br>M15<br>VCCIB2<br>VCCIB2<br>M16<br>IO48NDB2V0<br>IO70NDB2V0<br>M17<br>VCCIB2<br>VCCIB2<br>P3<br>IO68NDB4V0<br>IO101NDB4V0<br>P4<br>IO65PDB4V0<br>IO96PDB4V0<br>P5<br>IO65NDB4V0<br>IO96NDB4V0<br>P6<br>NC<br>IO99NDB4V0<br>P7<br>NC<br>IO97NDB4V0<br>P8<br>VCCIB4<br>VCCIB4<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|M18<br>IO46NDB2V0<br>IO69NDB2V0<br>M19<br>GCA0/IO45NDB2V0<br>GCA0/IO64NDB2V0<br>M20<br>VCCIB2<br>VCCIB2<br>M21<br>GCB0/IO44NDB2V0<br>GCB0/IO63NDB2V0<br>M22<br>GCB1/IO44PDB2V0<br>GCB1/IO63PDB2V0<br>N1<br>NC<br>IO103NDB4V0<br>P9<br>VCC<br>VCC<br>P10<br>GND<br>GND<br>P11<br>VCC<br>VCC<br>P12<br>GND<br>GND<br>P13<br>VCC<br>VCC<br>P14<br>GND<br>GND<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|N2<br>GND<br>GND<br>P15<br>VCCIB2<br>VCCIB2<br>~~ee~~|
|N3<br>IO68PDB4V0<br>IO101PDB4V0<br>N4<br>NC<br>IO100NPB4V0<br>N5<br>GND<br>GND<br>N6<br>NC<br>IO99PDB4V0<br>N7<br>NC<br>IO97PDB4V0<br>P16<br>IO56NDB2V0<br>IO83NDB2V0<br>P17<br>NC<br>IO78NDB2V0<br>P18<br>GDA1/IO54PDB2V0<br>GDA1/IO81PDB2V0<br>P19<br>GDB1/IO53PDB2V0<br>GDB1/IO80PDB2V0<br>P20<br>IO51NDB2V0<br>IO73NDB2V0<br>~~a 0~~<br>~~Ce~~<br>~~0~~<br>~~Fs0~~<br>~~Fs0~~<br>~~a De~~<br>~~0~~|
**4-24**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG484**<br>~~ee~~|||**FG484**||
|---|---|---|---|---|
|**Pin**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>**Pin**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>~~eeee~~|||||
|P21<br>IO51PDB2V0<br>IO73PDB2V0<br>P22<br>IO49NDB2V0<br>IO71NDB2V0<br>R1<br>IO69PDB4V0<br>IO102PDB4V0<br>~~ee~~<br>~~Ha De~~<br>~~a~~||T12<br>T13<br>T14|AV5<br>AC5<br>NC|AV5<br>AC5<br>NC|
|R2<br>IO69NDB4V0<br>IO102NDB4V0<br>~~a~~<br>~~ee~~||T15|GNDA|GNDA|
|R3<br>VCCIB4<br>VCCIB4<br>~~ee~~<br>~~a~~||T16|NC|IO77PPB2V0<br>~~|~~|
|R4<br>IO64PDB4V0<br>IO91PDB4V0||T17|NC|IO74PDB2V0|
|R5<br>IO64NDB4V0<br>IO91NDB4V0<br>R6<br>NC<br>IO92PDB4V0<br>R7<br>GND<br>GND<br>~~Ha De~~<br>~~a~~||T18<br>T19<br>T20|VCCIB2<br>IO55NDB2V0<br>GDA2/IO55PDB2V0|VCCIB2<br>IO82NDB2V0<br>GDA2/IO82PDB2V0|
|R8<br>GND<br>GND<br>~~a~~<br>~~ee~~||T21|GND|GND|
|R9<br>VCC33A<br>VCC33A<br>~~a~~<br>~~ee~~||T22|GDC1/IO52PDB2V0|GDC1/IO79PDB2V0<br>~~|~~|
|R10<br>GNDA<br>GNDA||U1|IO67PDB4V0|IO98PDB4V0|
|R11<br>VCC33A<br>VCC33A<br>R12<br>GNDA<br>GNDA<br>R13<br>VCC33A<br>VCC33A<br>~~a ~~<br>~~Fa De~~<br>~~a~~|9|U2<br>U3<br>U4|IO67NDB4V0<br>GEC1/IO63PDB4V0<br>GEC0/IO63NDB4V0|IO98NDB4V0<br>GEC1/IO90PDB4V0<br>GEC0/IO90NDB4V0|
|R14<br>GNDA<br>GNDA<br>U5<br>GND<br>GND<br>~~a~~<br>~~eeee~~|||||
|R15<br>VCC<br>VCC<br>~~a~~<br>~~ee~~||U6|VCCNVM|VCCNVM<br>~~|~~|
|R16<br>GND<br>GND||U7|VCCIB4|VCCIB4|
|R17<br>NC<br>IO74NDB2V0<br>R18<br>GDA0/IO54NDB2V0<br>GDA0/IO81NDB2V0<br>R19<br>GDB0/IO53NDB2V0<br>GDB0/IO80NDB2V0<br>~~ee ~~<br>~~Fa De~~<br>~~a~~|9|U8<br>U9<br>U10|VCC15A<br>GNDA<br>AC4|VCC15A<br>GNDA<br>AC4|
|R20<br>VCCIB2<br>VCCIB2<br>U11<br>VCC33A<br>VCC33A<br>~~a~~<br>~~eeee~~|||||
|R21<br>IO50NDB2V0<br>IO75NDB2V0<br>~~ee~~<br>~~a~~||U12|GNDA|GNDA<br>~~|~~|
|R22<br>IO50PDB2V0<br>IO75PDB2V0||U13|AG5|AG5|
|T1<br>NC<br>IO100PPB4V0<br>T2<br>GND<br>GND<br>T3<br>IO66PDB4V0<br>IO95PDB4V0<br>U14<br>GNDA<br>GNDA<br>U15<br>PUB<br>PUB<br>U16<br>VCCIB2<br>VCCIB2<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~|||||
|T4<br>IO66NDB4V0<br>IO95NDB4V0<br>T5<br>VCCIB4<br>VCCIB4<br>T6<br>NC<br>IO92NDB4V0<br>~~ee ~~<br>~~**a**~~|0|U17<br>U18<br>U19|TDI<br>GND<br>IO57NDB2V0|TDI<br>GND<br>IO84NDB2V0|
|T7<br>GNDNVM<br>GNDNVM<br>T8<br>GNDA<br>GNDA<br>T9<br>NC<br>NC<br>U20<br>GDC2/IO57PDB2V0<br>GDC2/IO84PDB2V0<br>U21<br>NC<br>IO77NPB2V0<br>U22<br>GDC0/IO52NDB2V0<br>GDC0/IO79NDB2V0<br>~~Ce0~~<br>~~a~~<br>~~Fs0~~|||||
|T10<br>AV4<br>AV4<br>T11<br>NC<br>NC<br>~~ee~~<br>~~**a**~~|9|V1<br>V2<br>~~ee~~|GEB1/IO62PDB4V0<br>GEB0/IO62NDB4V0|GEB1/IO89PDB4V0<br>GEB0/IO89NDB4V0|
**Revision 8**
**4-25**
_Package Pin Assignments_
|**FG484**<br>**FG484**<br>~~ee~~|
|---|
|**Pin**<br>**Pin**|
|**Number**<br>**AFS600 Function**<br>**AFS1500 Function**<br>**Number**<br>**AFS600 Function**<br>**AFS1500 Function**|
|V3<br>VCCIB4<br>VCCIB4<br>V4<br>GEA1/IO61PDB4V0<br>GEA1/IO88PDB4V0<br>V5<br>GEA0/IO61NDB4V0<br>GEA0/IO88NDB4V0<br>V6<br>GND<br>GND<br>W16<br>GNDA<br>GNDA<br>W17<br>AV9<br>AV9<br>W18<br>VCCIB2<br>VCCIB2<br>W19<br>NC<br>IO68PPB2V0<br>~~ee0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|V7<br>VCC33PMP<br>VCC33PMP<br>W20<br>TCK<br>TCK<br>~~a 0~~|
|V8<br>NC<br>NC<br>W21<br>GND<br>GND<br>~~ee~~|
|V9<br>VCC33A<br>VCC33A<br>V10<br>AG4<br>AG4<br>V11<br>AT4<br>AT4<br>V12<br>ATRTN2<br>ATRTN2<br>W22<br>NC<br>IO76PPB2V0<br>Y1<br>GEC2/IO60PDB4V0<br>GEC2/IO87PDB4V0<br>Y2<br>IO60NDB4V0<br>IO87NDB4V0<br>Y3<br>GEA2/IO58PDB4V0<br>GEA2/IO85PDB4V0<br>~~0~~<br>~~Ha De~~<br>~~FR ss ~~0<br>~~Vs0~~|
|V13<br>AT5<br>AT5<br>Y4<br>IO58NDB4V0<br>IO85NDB4V0<br>~~a~~<br>~~0~~|
|V14<br>VCC33A<br>VCC33A<br>Y5<br>NCAP<br>NCAP<br>~~a~~|
|V15<br>NC<br>NC<br>V16<br>VCC33A<br>VCC33A<br>V17<br>GND<br>GND<br>V18<br>TMS<br>TMS<br>V19<br>VJTAG<br>VJTAG<br>Y6<br>AC0<br>AC0<br>Y7<br>VCC33A<br>VCC33A<br>Y8<br>AC1<br>AC1<br>Y9<br>AC2<br>AC2<br>Y10<br>VCC33A<br>VCC33A<br>~~a~~<br>~~0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|V20<br>VCCIB2<br>VCCIB2<br>V21<br>TRST<br>TRST<br>V22<br>TDO<br>TDO<br>W1<br>NC<br>IO93PDB4V0<br>W2<br>GND<br>GND<br>W3<br>NC<br>IO93NDB4V0<br>Y11<br>AC3<br>AC3<br>Y12<br>AC6<br>AC6<br>Y13<br>VCC33A<br>VCC33A<br>Y14<br>AC7<br>AC7<br>Y15<br>AC8<br>AC8<br>Y16<br>VCC33A<br>VCC33A<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~a 0~~|
|W4<br>GEB2/IO59PDB4V0<br>GEB2/IO86PDB4V0<br>W5<br>IO59NDB4V0<br>IO86NDB4V0<br>W6<br>AV0<br>AV0<br>W7<br>GNDA<br>GNDA<br>W8<br>AV1<br>AV1<br>W9<br>AV2<br>AV2<br>W10<br>GNDA<br>GNDA<br>W11<br>AV3<br>AV3<br>W12<br>AV6<br>AV6<br>W13<br>GNDA<br>GNDA<br>W14<br>AV7<br>AV7<br>W15<br>AV8<br>AV8<br>Y17<br>AC9<br>AC9<br>Y18<br>ADCGNDREF<br>ADCGNDREF<br>Y19<br>PTBASE<br>PTBASE<br>Y20<br>GNDNVM<br>GNDNVM<br>Y21<br>VCCNVM<br>VCCNVM<br>Y22<br>VPUMP<br>VPUMP<br>~~ee~~<br>~~Ce0~~<br>~~Fa De~~<br>~~Fs0~~<br>~~A Ds ~~0<br>~~Fs0~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~<br>~~ee~~<br>~~eeeee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~<br>~~ee~~|
**4-26**
**Revision 8**
_Package Pin Assignments_
## **FG676**
|**A1 Ball Pad Corner**|**A1 Ball Pad Corner**|
|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14<br>15<br>16<br>17<br>18<br>19<br>20<br>21<br>22<br>23<br>24<br>25<br>26||
|OROROROROTOROROROROROROROHOROROROROROROROROROROROC|A|
|OROROROROTORORORORORORORORORORORORORORORORORORORORC)|B|
|OROROROROROROROROROROROROHORORORORORORORORORORORORC|C|
|OROROROROROROROROROROROROHORORORORORORORORORORORORC|D|
|OROROROROROROROROROROROROHORORORORORORORORORORORORC|E|
|OROROROROTORORORORORORORORORORORORORORORORORORORORC|F|
|OROROROROTOROROROROROROROHORORORORORORORORORORORORC|G|
|ORORORORORORORORORORORORORORORORORORORORORORORORORC|H|
|OROROROROROROROROROROROROROROROROROROROROROROTORORC)|J|
|ORORORORORORORORORORORORORORORORORORORORORORORORORO|K|
|ORORORORORORORORORORORORORORORORORORORORORORORORORC|L|
|OROTOROROROROROROROROROROROTOROROROROROROROROTORORO)|M|
|00000 0000 000 ~~oO~~ 0 OOOO DO00DD<br>ORORORORORO~~ROR~~ORORORORORO<br>OROROROROROROROROROTORONO|N<br>P|
|OROTOROROROROROROROROROROROTOROROROROROROROROTORONO)|R|
|ORORORORORORORORORORORORORORORORORORORORORORORORORO|T|
|OROROROROROROROROROROROROROROROROROROROROROROTORORC|U|
|OROROROROROROROROROROROROROR<br>ORO OROROROROROROTORORO)|V|
|ORORORORORORORORORORORORORORORORORORORORORORORORORO)|W|
|OROROROROROROROROROROROROROROROROROROROROROROTORORO)|Y|
|OROROROROROROROROROROROROROROROROROROROROROROTOROHO)|AA|
|OROROROROROROROROROROROROROROROROROROROROROROROROHO)|AB|
|OROROROROROROROROROROROROROROROROROROROROROROTOROHO)|AC|
|ORORORORORORORORORORORORORORORORORORORORORORORORORO)|AD|
|OROROROROROROROROROROROROROROROROROROROROROROROROHO)|AE|
|OROROROROROROROROROROROROROROROROROROROROROROROROHO)|AF|
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-27**
**Revision 8**
_Package Pin Assignments_
|**FG676**<br>**Pin Number**<br>**AFS1500 Function**<br>A1<br>NC<br>AA11<br>AV2<br>**FG676**<br>**Pin Number**<br>**AFS1500 Function**<br>~~ee eo~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||AB21<br>**Pin Number**|PTBASE<br>**FG676**<br>**AFS1500 Function**|
|---|---|---|---|
|A2<br>GND<br>AA12<br>GNDA<br>~~es~~<br>~~0~~||AB22|GNDNVM|
|A3<br>NC<br>A4<br>NC<br>A5<br>GND<br>A6<br>NC<br>A7<br>NC<br>A8<br>GND<br>AA13<br>AV3<br>AA14<br>AV6<br>AA15<br>GNDA<br>AA16<br>AV7<br>AA17<br>AV8<br>AA18<br>GNDA<br>~~ee0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~es~~<br>~~0~~||AB23<br>AB24<br>AB25<br>AB26<br>AC1<br>AC2|VCCNVM<br>VPUMP<br>NC<br>GND<br>NC<br>NC|
|A9<br>IO17NDB0V2<br>A10<br>IO17PDB0V2<br>A11<br>GND<br>A12<br>IO18NDB0V2<br>A13<br>IO18PDB0V2<br>A14<br>IO20NDB0V2<br>AA19<br>AV9<br>AA20<br>VCCIB2<br>AA21<br>IO68PPB2V0<br>AA22<br>TCK<br>AA23<br>GND<br>AA24<br>IO76PPB2V0<br>~~ee0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||AC3<br>AC4<br>AC5<br>AC6<br>AC7<br>AC8|NC<br>GND<br>VCCIB4<br>VCCIB4<br>PCAP<br>AG0|
|A15<br>IO20PDB0V2<br>A16<br>GND<br>A17<br>IO21PDB0V2<br>A18<br>IO21NDB0V2<br>A19<br>GND<br>A20<br>IO39NDB1V2<br>AA25<br>VCCIB2<br>AA26<br>NC<br>AB1<br>GND<br>AB2<br>NC<br>AB3<br>GEC2/IO87PDB4V0<br>AB4<br>IO87NDB4V0<br>AC9<br>GNDA<br>AC10<br>AG1<br>AC11<br>AG2<br>AC12<br>GNDA<br>AC13<br>AG3<br>AC14<br>AG6<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~<br>~~0~~||||
|A21<br>IO39PDB1V2<br>A22<br>GND<br>A23<br>NC<br>A24<br>NC<br>A25<br>GND<br>A26<br>NC<br>AB5<br>GEA2/IO85PDB4V0<br>AB6<br>IO85NDB4V0<br>AB7<br>NCAP<br>AB8<br>AC0<br>AB9<br>VCC33A<br>AB10<br>AC1<br>AC15<br>GNDA<br>AC16<br>AG7<br>AC17<br>AG8<br>AC18<br>GNDA<br>AC19<br>AG9<br>AC20<br>VAREF<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~<br>~~0~~||||
|AA1<br>NC<br>AA2<br>VCCIB4<br>AA3<br>IO93PDB4V0<br>AA4<br>GND<br>AA5<br>IO93NDB4V0<br>AA6<br>GEB2/IO86PDB4V0<br>AB11<br>AC2<br>AB12<br>VCC33A<br>AB13<br>AC3<br>AB14<br>AC6<br>AB15<br>VCC33A<br>AB16<br>AC7<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||AC21<br>AC22<br>AC23<br>AC24<br>AC25<br>AC26|VCCIB2<br>PTEM<br>GND<br>NC<br>NC<br>NC|
|AA7<br>IO86NDB4V0<br>AA8<br>AV0<br>AA9<br>GNDA<br>AA10<br>AV1<br>AB17<br>AC8<br>AB18<br>VCC33A<br>AB19<br>AC9<br>AB20<br>ADCGNDREF<br>~~0~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~||AD1<br>AD2<br>AD3<br>AD4|NC<br>NC<br>GND<br>NC|
**4-28**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG676**|||**FG676**||**FG676**|
|---|---|---|---|---|---|
|AD5<br>IO94NPB4V0<br>AD6<br>GND<br>**Pin Number**<br>**AFS1500 Function**<br>AE15<br>GNDA<br>AE16<br>NC<br>**Pin Number**<br>**AFS1500 Function**<br>~~a ee~~<br>~~a~~<br>~~eb0~~<br>~~ae~~||||~~ee~~|AF25<br>GND<br>AF26<br>NC<br>**Pin Number**<br>**AFS1500 Function**<br>~~ee~~<br>~~ee~~|
|AD7<br>VCC33N<br>~~re~~|||AE17<br>NC<br>~~ae~~||B1<br>GND<br>~~ee~~|
|AD8<br>AT0|||AE18<br>GNDA||B2<br>GND|
|AD9<br>ATRTN0<br>AD10<br>AT1<br>AD11<br>AT2<br>~~a~~<br>~~9~~<br>~~ee~~|||AE19<br>NC<br>AE20<br>NC<br>AE21<br>NC<br>~~ee~~||B3<br>NC<br>B4<br>NC<br>B5<br>NC|
|AD12<br>ATRTN1<br>~~ee~~|||AE22<br>NC<br>~~a~~||B6<br>VCCIB0<br>~~a~~|
|AD13<br>AT3|||AE23<br>NC||B7<br>NC|
|AD14<br>AT6<br>AD15<br>ATRTN3<br>AD16<br>AT7<br>AD17<br>AT8<br>AD18<br>ATRTN4<br>~~a~~<br>~~9~~<br>~~ee~~<br>~~a~~<br>~~9~~<br>~~a~~|||AE24<br>NC<br>AE25<br>GND<br>AE26<br>GND<br>AF1<br>NC<br>AF2<br>GND<br>~~ee~~<br>~~ee~~||B8<br>NC<br>B9<br>VCCIB0<br>B10<br>IO15NDB0V2<br>B11<br>IO15PDB0V2<br>B12<br>VCCIB0|
|AD19<br>AT9<br>~~a~~|||AF3<br>NC<br>~~ee~~||B13<br>IO19NDB0V2<br>~~ee~~|
|AD20<br>VCC33A|||AF4<br>NC||B14<br>IO19PDB0V2|
|AD21<br>GND|||AF5<br>NC||B15<br>VCCIB1|
|AD22<br>IO76NPB2V0<br>AD23<br>NC<br>AD24<br>GND<br>AD25<br>NC<br>~~a~~<br>~~a~~|||AF6<br>NC<br>AF7<br>NC<br>AF8<br>NC<br>AF9<br>VCC33A<br>B16<br>IO25NDB1V0<br>B17<br>IO25PDB1V0<br>B18<br>VCCIB1<br>B19<br>IO33NDB1V1<br>~~a~~<br>~~aa~~<br>~~a~~<br>~~ee~~|||
|AD26<br>NC|||AF10<br>NC||B20<br>IO33PDB1V1|
|AE1<br>GND<br>~~ee~~|||AF11<br>NC<br>~~ee~~||B21<br>VCCIB1<br>~~a~~|
|AE2<br>GND|||AF12<br>VCC33A||B22<br>NC|
|AE3<br>NC<br>AE4<br>NC<br>AE5<br>NC<br>~~a~~<br>~~ee 0~~<br>~~ae~~|~~0~~|AF13<br>NC<br>AF14<br>NC<br>AF15<br>VCC33A<br>~~00~~|||B23<br>NC<br>B24<br>NC<br>B25<br>GND|
|AE6<br>NC<br>AE7<br>NC<br>~~ee~~|||AF16<br>NC<br>AF17<br>NC<br>~~a~~<br>~~ee~~||B26<br>GND<br>C1<br>NC<br>~~a~~|
|AE8<br>NC<br>AE9<br>GNDA<br>AE10<br>NC<br>AE11<br>NC<br>AE12<br>GNDA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee 0~~<br>~~a~~<br>~~ee~~||AF18<br>VCC33A<br>AF19<br>NC<br>AF20<br>NC<br>AF21<br>NC<br>AF22<br>NC<br>9<br>~~ee~~<br>~~00~~|||C2<br>NC<br>C3<br>GND<br>C4<br>NC<br>C5<br>GAA1/IO01PDB0V0<br>C6<br>GAB0/IO02NDB0V0|
|AE13<br>NC<br>~~ee~~|||AF23<br>NC<br>~~ee~~||C7<br>GAB1/IO02PDB0V0<br>~~ee~~|
|AE14<br>NC<br>~~a~~<br>~~9~~|||AF24<br>NC<br>~~ee~~||C8<br>IO07NDB0V1|
**Revision 8**
**4-29**
_Package Pin Assignments_
|C9<br>IO07PDB0V1<br>**FG676**<br>**Pin Number**<br>**AFS1500 Function**<br>D19<br>GBC1/IO40PDB1V2<br>**FG676**<br>**Pin Number**<br>**AFS1500 Function**<br>~~ee eo~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||F3<br>**Pin Number**|IO121NDB4V0<br>**FG676**<br>**AFS1500 Function**|
|---|---|---|---|
|C10<br>IO09PDB0V1<br>D20<br>GBA1/IO42PDB1V2<br>~~es~~<br>~~0~~||F4|GND|
|C11<br>IO13NDB0V2<br>C12<br>IO13PDB0V2<br>C13<br>IO24PDB1V0<br>C14<br>IO26PDB1V0<br>C15<br>IO27NDB1V1<br>C16<br>IO27PDB1V1<br>D21<br>GND<br>D22<br>VCCPLB<br>D23<br>GND<br>D24<br>NC<br>D25<br>NC<br>D26<br>NC<br>~~ee0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~es~~<br>~~0~~||F5<br>F6<br>F7<br>F8<br>F9<br>F10|IO123NDB4V0<br>GAC2/IO123PDB4V0<br>GAA2/IO125PDB4V0<br>GAC0/IO03NDB0V0<br>GAC1/IO03PDB0V0<br>IO10NDB0V1|
|C17<br>IO35NDB1V2<br>C18<br>IO35PDB1V2<br>C19<br>GBC0/IO40NDB1V2<br>C20<br>GBA0/IO42NDB1V2<br>C21<br>IO43NDB1V2<br>C22<br>IO43PDB1V2<br>E1<br>GND<br>E2<br>IO122NPB4V0<br>E3<br>IO121PDB4V0<br>E4<br>IO122PPB4V0<br>E5<br>IO00NDB0V0<br>E6<br>IO00PDB0V0<br>~~ee0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||F11<br>F12<br>F13<br>F14<br>F15<br>F16|IO10PDB0V1<br>IO14NDB0V2<br>IO23NDB1V0<br>IO23PDB1V0<br>IO32NPB1V1<br>IO34NDB1V1|
|C23<br>NC<br>C24<br>GND<br>C25<br>NC<br>C26<br>NC<br>D1<br>NC<br>D2<br>NC<br>E7<br>VCCIB0<br>E8<br>IO05NDB0V1<br>E9<br>IO05PDB0V1<br>E10<br>VCCIB0<br>E11<br>IO11NDB0V1<br>E12<br>IO14PDB0V2<br>F17<br>IO34PDB1V1<br>F18<br>IO37PDB1V2<br>F19<br>GBB1/IO41PDB1V2<br>F20<br>VCCIB2<br>F21<br>IO47PPB2V0<br>F22<br>IO44NDB2V0<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~<br>~~0~~||||
|D3<br>NC<br>D4<br>GND<br>D5<br>GAA0/IO01NDB0V0<br>D6<br>GND<br>D7<br>IO04NDB0V0<br>D8<br>IO04PDB0V0<br>E13<br>VCCIB0<br>E14<br>VCCIB1<br>E15<br>IO29NDB1V1<br>E16<br>IO29PDB1V1<br>E17<br>VCCIB1<br>E18<br>IO37NDB1V2<br>F23<br>GND<br>F24<br>IO45NDB2V0<br>F25<br>VCCIB2<br>F26<br>NC<br>G1<br>NC<br>G2<br>IO119PPB4V0<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~<br>~~0~~||||
|D9<br>GND<br>D10<br>IO09NDB0V1<br>D11<br>IO11PDB0V1<br>D12<br>GND<br>D13<br>IO24NDB1V0<br>D14<br>IO26NDB1V0<br>E19<br>GBB0/IO41NDB1V2<br>E20<br>VCCIB1<br>E21<br>VCOMPLB<br>E22<br>GBA2/IO44PDB2V0<br>E23<br>IO48PPB2V0<br>E24<br>GBB2/IO45PDB2V0<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||G3<br>G4<br>G5<br>G6<br>G7<br>G8|IO120NDB4V0<br>IO120PDB4V0<br>VCCIB4<br>GAB2/IO124PDB4V0<br>IO125NDB4V0<br>GND|
|D15<br>GND<br>D16<br>IO31NDB1V1<br>D17<br>IO31PDB1V1<br>D18<br>GND<br>E25<br>NC<br>E26<br>GND<br>F1<br>NC<br>F2<br>VCCIB4<br>~~0~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~||G9<br>G10<br>G11<br>G12|VCCIB0<br>IO08NDB0V1<br>IO08PDB0V1<br>GND|
**4-30**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG676**|||**FG676**||**FG676**|
|---|---|---|---|---|---|
|G13<br>IO22NDB1V0<br>G14<br>IO22PDB1V0<br>**Pin Number**<br>**AFS1500 Function**<br>H23<br>IO50NDB2V0<br>H24<br>IO51PDB2V0<br>**Pin Number**<br>**AFS1500 Function**<br>~~a ee~~<br>~~a~~<br>~~eb0~~<br>~~ae~~||||~~ee~~|K7<br>IO114PDB4V0<br>K8<br>IO117NDB4V0<br>**Pin Number**<br>**AFS1500 Function**<br>~~ee~~<br>~~ee~~|
|G15<br>GND<br>~~re~~|||H25<br>NC<br>~~ae~~||K9<br>GND<br>~~ee~~|
|G16<br>IO32PPB1V1|||H26<br>GND||K10<br>VCC|
|G17<br>IO36NPB1V2<br>G18<br>VCCIB1<br>G19<br>GND<br>~~a~~<br>~~9~~<br>~~ee~~|||J1<br>NC<br>J2<br>VCCIB4<br>J3<br>IO115PDB4V0<br>~~ee~~||K11<br>VCCIB0<br>K12<br>GND<br>K13<br>VCCIB0|
|G20<br>IO47NPB2V0<br>~~ee~~|||J4<br>GND<br>~~a~~||K14<br>VCCIB1<br>~~a~~|
|G21<br>IO49PDB2V0|||J5<br>IO116NDB4V0||K15<br>GND|
|G22<br>VCCIB2<br>G23<br>IO46NDB2V0<br>G24<br>GBC2/IO46PDB2V0<br>G25<br>IO48NPB2V0<br>G26<br>NC<br>~~a~~<br>~~9~~<br>~~ee~~<br>~~a~~<br>~~9~~<br>~~a~~|||J6<br>IO116PDB4V0<br>J7<br>VCCIB4<br>J8<br>IO117PDB4V0<br>J9<br>VCCIB4<br>J10<br>GND<br>~~ee~~<br>~~ee~~||K16<br>VCCIB1<br>K17<br>GND<br>K18<br>GND<br>K19<br>IO53NDB2V0<br>K20<br>IO57PDB2V0|
|H1<br>GND<br>~~a~~|||J11<br>IO06NDB0V1<br>~~ee~~||K21<br>GCA2/IO59PDB2V0<br>~~ee~~|
|H2<br>NC|||J12<br>IO06PDB0V1||K22<br>VCCIB2|
|H3<br>IO118NDB4V0|||J13<br>IO16NDB0V2||K23<br>IO54NDB2V0|
|H4<br>IO118PDB4V0<br>H5<br>IO119NPB4V0<br>H6<br>IO124NDB4V0<br>H7<br>GND<br>~~a~~<br>~~a~~|||J14<br>IO16PDB0V2<br>J15<br>IO28NDB1V1<br>J16<br>IO28PDB1V1<br>J17<br>GND<br>K24<br>IO54PDB2V0<br>K25<br>NC<br>K26<br>NC<br>L1<br>GND<br>~~a~~<br>~~aa~~<br>~~a~~<br>~~ee~~|||
|H8<br>VCOMPLA|||J18<br>IO38PPB1V2||L2<br>NC|
|H9<br>VCCPLA<br>~~ee~~|||J19<br>IO53PDB2V0<br>~~ee~~||L3<br>IO112PPB4V0<br>~~a~~|
|H10<br>VCCIB0|||J20<br>VCCIB2||L4<br>IO113NDB4V0|
|H11<br>IO12NDB0V1<br>H12<br>IO12PDB0V1<br>H13<br>VCCIB0<br>~~a~~<br>~~ee 0~~<br>~~ae~~|~~0~~|J21<br>IO52PDB2V0<br>J22<br>IO52NDB2V0<br>J23<br>GND<br>~~00~~|||L5<br>GFB2/IO109PDB4V0<br>L6<br>GFA2/IO110PDB4V0<br>L7<br>IO112NPB4V0|
|H14<br>VCCIB1<br>H15<br>IO30NDB1V1<br>~~ee~~|||J24<br>IO51NDB2V0<br>J25<br>VCCIB2<br>~~a~~<br>~~ee~~||L8<br>IO104PDB4V0<br>L9<br>IO111PDB4V0<br>~~a~~|
|H16<br>IO30PDB1V1<br>H17<br>VCCIB1<br>H18<br>IO36PPB1V2<br>H19<br>IO38NPB1V2<br>H20<br>GND<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee 0~~<br>~~a~~<br>~~ee~~||J26<br>NC<br>K1<br>NC<br>K2<br>NC<br>K3<br>IO115NDB4V0<br>K4<br>IO113PDB4V0<br>9<br>~~ee~~<br>~~00~~|||L10<br>VCCIB4<br>L11<br>GND<br>L12<br>VCC<br>L13<br>GND<br>L14<br>VCC|
|H21<br>IO49NDB2V0<br>~~ee~~|||K5<br>VCCIB4<br>~~ee~~||L15<br>GND<br>~~ee~~|
|H22<br>IO50PDB2V0<br>~~a~~<br>~~9~~|||K6<br>IO114NDB4V0<br>~~ee~~||L16<br>VCC|
**Revision 8**
**4-31**
_Package Pin Assignments_
|L17<br>VCCIB2<br>**FG676**<br>**Pin Number**<br>**AFS1500 Function**<br>N1<br>NC<br>**FG676**<br>**Pin Number**<br>**AFS1500 Function**<br>~~ee eo~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||P11<br>**Pin Number**|VCC<br>**FG676**<br>**AFS1500 Function**|
|---|---|---|---|
|L18<br>GCB2/IO60PDB2V0<br>N2<br>NC<br>~~es~~<br>~~0~~||P12|GND|
|L19<br>IO58NDB2V0<br>L20<br>IO57NDB2V0<br>L21<br>IO59NDB2V0<br>L22<br>GCC2/IO61PDB2V0<br>L23<br>IO55PPB2V0<br>L24<br>IO56PDB2V0<br>N3<br>IO108NDB4V0<br>N4<br>VCCOSC<br>N5<br>VCCIB4<br>N6<br>XTAL2<br>N7<br>GFC1/IO107PDB4V0<br>N8<br>VCCIB4<br>~~ee0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~es~~<br>~~0~~||P13<br>P14<br>P15<br>P16<br>P17<br>P18|VCC<br>GND<br>VCC<br>GND<br>VCCIB2<br>IO70NDB2V0|
|L25<br>IO55NPB2V0<br>L26<br>GND<br>M1<br>NC<br>M2<br>VCCIB4<br>M3<br>GFC2/IO108PDB4V0<br>M4<br>GND<br>N9<br>GFB1/IO106PDB4V0<br>N10<br>VCCIB4<br>N11<br>GND<br>N12<br>VCC<br>N13<br>GND<br>N14<br>VCC<br>~~ee0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||P19<br>P20<br>P21<br>P22<br>P23<br>P24|VCCIB2<br>IO69NDB2V0<br>GCA0/IO64NDB2V0<br>VCCIB2<br>GCB0/IO63NDB2V0<br>GCB1/IO63PDB2V0|
|M5<br>IO109NDB4V0<br>M6<br>IO110NDB4V0<br>M7<br>GND<br>M8<br>IO104NDB4V0<br>M9<br>IO111NDB4V0<br>M10<br>GND<br>N15<br>GND<br>N16<br>VCC<br>N17<br>VCCIB2<br>N18<br>IO70PDB2V0<br>N19<br>VCCIB2<br>N20<br>IO69PDB2V0<br>P25<br>IO66NDB2V0<br>P26<br>IO67PDB2V0<br>R1<br>NC<br>R2<br>VCCIB4<br>R3<br>IO103NDB4V0<br>R4<br>GND<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~<br>~~0~~||||
|M11<br>V**CC**<br>M12<br>GND<br>M13<br>VCC<br>M14<br>GND<br>M15<br>VCC<br>M16<br>GND<br>N21<br>GCA1/IO64PDB2V0<br>N22<br>VCCIB2<br>N23<br>GCC0/IO62NDB2V0<br>N24<br>GCC1/IO62PDB2V0<br>N25<br>IO66PDB2V0<br>N26<br>IO65NDB2V0<br>R5<br>IO101PDB4V0<br>R6<br>IO100NPB4V0<br>R7<br>GND<br>R8<br>IO99PDB4V0<br>R9<br>IO97PDB4V0<br>R10<br>GND<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~<br>~~0~~||||
|M17<br>GND<br>M18<br>IO60NDB2V0<br>M19<br>IO58PDB2V0<br>M20<br>GND<br>M21<br>IO68NPB2V0<br>M22<br>IO61NDB2V0<br>P1<br>NC<br>P2<br>NC<br>P3<br>IO103PDB4V0<br>P4<br>XTAL1<br>P5<br>VCCIB4<br>P6<br>GNDOSC<br>~~a~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee2~~<br>~~a~~<br>~~ee ee~~<br>~~0~~||R11<br>R12<br>R13<br>R14<br>R15<br>R16|GND<br>VCC<br>GND<br>VCC<br>GND<br>VCC|
|M23<br>GND<br>M24<br>IO56NDB2V0<br>M25<br>VCCIB2<br>M26<br>IO65PDB2V0<br>P7<br>GFC0/IO107NDB4V0<br>P8<br>VCCIB4<br>P9<br>GFB0/IO106NDB4V0<br>P10<br>VCCIB4<br>~~0~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~||R17<br>R18<br>R19<br>R20|GND<br>GDB2/IO83PDB2V0<br>IO78PDB2V0<br>GND|
**4-32**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**FG676**|||**FG676**||**FG676**|
|---|---|---|---|---|---|
|R21<br>IO72NDB2V0<br>R22<br>IO72PDB2V0<br>**Pin Number**<br>**AFS1500 Function**<br>U5<br>VCCIB4<br>U6<br>IO91PDB4V0<br>**Pin Number**<br>**AFS1500 Function**<br>~~a ee~~<br>~~a~~<br>~~eb0~~<br>~~ae~~||||~~ee~~|V15<br>AC5<br>V16<br>NC<br>**Pin Number**<br>**AFS1500 Function**<br>~~ee~~<br>~~ee~~|
|R23<br>GND<br>~~re~~|||U7<br>IO91NDB4V0<br>~~ae~~||V17<br>GNDA<br>~~ee~~|
|R24<br>IO71PDB2V0|||U8<br>IO92PDB4V0||V18<br>IO77PPB2V0|
|R25<br>VCCIB2<br>R26<br>IO67NDB2V0<br>T1<br>GND<br>~~a~~<br>~~9~~<br>~~ee~~|||U9<br>GND<br>U10<br>GND<br>U11<br>VCC33A<br>~~ee~~||V19<br>IO74PDB2V0<br>V20<br>VCCIB2<br>V21<br>IO82NDB2V0|
|T2<br>NC<br>~~ee~~|||U12<br>GNDA<br>~~a~~||V22<br>GDA2/IO82PDB2V0<br>~~a~~|
|T3<br>GFA1/IO105PDB4V0|||U13<br>VCC33A||V23<br>GND|
|T4<br>GFA0/IO105NDB4V0<br>T5<br>IO101NDB4V0<br>T6<br>IO96PDB4V0<br>T7<br>IO96NDB4V0<br>T8<br>IO99NDB4V0<br>~~a~~<br>~~9~~<br>~~ee~~<br>~~a~~<br>~~9~~<br>~~a~~|||U14<br>GNDA<br>U15<br>VCC33A<br>U16<br>GNDA<br>U17<br>VCC<br>U18<br>GND<br>~~ee~~<br>~~ee~~||V24<br>GDC1/IO79PDB2V0<br>V25<br>VCCIB2<br>V26<br>NC<br>W1<br>GND<br>W2<br>IO94PPB4V0|
|T9<br>IO97NDB4V0<br>~~a~~|||U19<br>IO74NDB2V0<br>~~ee~~||W3<br>IO98PDB4V0<br>~~ee~~|
|T10<br>VCCIB4|||U20<br>GDA0/IO81NDB2V0||W4<br>IO98NDB4V0|
|T11<br>VCC|||U21<br>GDB0/IO80NDB2V0||W5<br>GEC1/IO90PDB4V0|
|T12<br>GND<br>T13<br>VCC<br>T14<br>GND<br>T15<br>VCC<br>~~a~~<br>~~a~~|||U22<br>VCCIB2<br>U23<br>IO75NDB2V0<br>U24<br>IO75PDB2V0<br>U25<br>NC<br>W6<br>GEC0/IO90NDB4V0<br>W7<br>GND<br>W8<br>VCCNVM<br>W9<br>VCCIB4<br>~~a~~<br>~~aa~~<br>~~a~~<br>~~ee~~|||
|T16<br>GND|||U26<br>NC||W10<br>VCC15A|
|T17<br>VCCIB2<br>~~ee~~|||V1<br>NC<br>~~ee~~||W11<br>GNDA<br>~~a~~|
|T18<br>IO83NDB2V0|||V2<br>VCCIB4||W12<br>AC4|
|T19<br>IO78NDB2V0<br>T20<br>GDA1/IO81PDB2V0<br>T21<br>GDB1/IO80PDB2V0<br>~~a~~<br>~~ee 0~~<br>~~ae~~|~~0~~|V3<br>IO100PPB4V0<br>V4<br>GND<br>V5<br>IO95PDB4V0<br>~~00~~|||W13<br>VCC33A<br>W14<br>GNDA<br>W15<br>AG5|
|T22<br>IO73NDB2V0<br>T23<br>IO73PDB2V0<br>~~ee~~|||V6<br>IO95NDB4V0<br>V7<br>VCCIB4<br>~~a~~<br>~~ee~~||W16<br>GNDA<br>W17<br>PUB<br>~~a~~|
|T24<br>IO71NDB2V0<br>T25<br>NC<br>T26<br>GND<br>U1<br>NC<br>U2<br>NC<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee 0~~<br>~~a~~<br>~~ee~~||V8<br>IO92NDB4V0<br>V9<br>GNDNVM<br>V10<br>GNDA<br>V11<br>NC<br>V12<br>AV4<br>9<br>~~ee~~<br>~~00~~|||W18<br>VCCIB2<br>W19<br>TDI<br>W20<br>GND<br>W21<br>IO84NDB2V0<br>W22<br>GDC2/IO84PDB2V0|
|U3<br>IO102PDB4V0<br>~~ee~~|||V13<br>NC<br>~~ee~~||W23<br>IO77NPB2V0<br>~~ee~~|
|U4<br>IO102NDB4V0<br>~~a~~<br>~~9~~|||V14<br>AV5<br>~~ee~~||W24<br>GDC0/IO79NDB2V0|
**Revision 8**
**4-33**
_Package Pin Assignments_
|**FG676**<br>~~po~~|**FG676**<br>~~po~~|
|---|---|
|**Pin Number**<br>~~a~~|**AFS1500 Function**<br>~~a~~|
|W25<br>~~a~~|NC<br>~~a~~|
|W26<br>~~a~~|GND<br>~~a~~|
|Y1<br>~~a~~|NC<br>~~a~~|
|Y2<br>~~a~~|NC<br>~~a~~|
|Y3<br>~~a~~|GEB1/IO89PDB4V0<br>~~a~~|
|Y4<br>~~a~~|GEB0/IO89NDB4V0<br>~~a~~|
|Y5<br>~~a~~|VCCIB4<br>~~a~~|
|Y6<br>~~a~~|GEA1/IO88PDB4V0<br>~~a~~|
|Y7<br>~~a~~|GEA0/IO88NDB4V0<br>~~a~~|
|Y8<br>~~a~~|GND<br>~~a~~|
|Y9<br>~~a~~|VCC33PMP<br>~~a~~|
|Y10<br>~~a~~|NC<br>~~a~~|
|Y11<br>~~a~~|VCC33A<br>~~a~~|
|Y12<br>~~a~~|AG4<br>~~a~~|
|Y13<br>~~a~~|AT4<br>~~a~~|
|Y14<br>~~a~~|ATRTN2<br>~~a~~|
|Y15<br>~~a~~|AT5<br>~~a~~|
|Y16<br>~~a~~|VCC33A<br>~~a~~|
|Y17<br>~~a~~|NC<br>~~a~~|
|Y18<br>~~a~~|VCC33A<br>~~a~~|
|Y19<br>~~a~~|GND<br>~~a~~|
|Y20<br>~~a~~|TMS<br>~~a~~|
|Y21<br>~~a~~|VJTAG<br>~~a~~|
|Y22<br>~~a~~|VCCIB2<br>~~a~~|
|Y23<br>~~a~~|TRST<br>~~a~~|
|Y24<br>~~a~~|TDO<br>~~a~~|
|Y25<br>~~a~~|NC<br>~~a~~|
|Y26<br>~~a~~|NC<br>~~a~~|
**4-34**
**Revision 8**
## **5 – Datasheet Information**
## **List of Changes**
The following table lists critical changes that were made in each revision of the Fusion datasheet.
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Revision 8<br>(May 2018)|In"Specifying I/O States During Programming", the version of the software, v9.0 is<br>removed to write Libero SoC, as Fusion family is supported in the Libero SoC (SAR<br>73296).|1-9|
||In tables,Table 2-78,Table 2-79andTable 2-80, “3” is edited to a tick mark, to show<br>the I/O standards with available drive and slew settings (SAR 70900).|2-152|
||The description for “LOCKREQUEST” is edited in"LOCKREQUEST" section(SAR<br>25423).|2-44|
||A note is added to explain data corruption in SRAM block, when setup and hold<br>requirements are violated on address inputs under"Clocking"(SAR 93618).|2-61|
||A note is added where ever it is applicable in the datasheet that the package PQ208<br>is discontinued (SAR 76873).||
||A note is added in"Package Pin Assignments"to direct the user to_PD3068:_<br>_Package Mechanical Drawings_(SAR 76874)|4-1|
|Revision 7<br>(May 2016)|Note added for discontinuance of PQ208 package to the"Package I/Os: Single-<br>/Double-Ended (Analog)" table,"Product Ordering Codes", and"Temperature Grade<br>Offerings" table(SAR).|1-II,1-III,<br>and1-IV|
||UpdatedFigure 2-42(SAR 61872).|2-51|
|Revision 6<br>(March 2014)|Note added for the discontinuance of QN108 and QN180 packages to the"Package<br>I/Os: Single-/Double-Ended (Analog)" tableand the"Temperature Grade Offerings"<br>table(SAR 55113, PDN 1306).|IIandIV|
||Updated details about page programming time in the"Program Operation" section<br>(SAR 49291).|2-46|
||ADC_START changed to ADCSTART in the"ADC Operation" section(SAR 44104).|2-104|
|Revision 5<br>(January 2014)|Calibrated offset values (AFS090, AFS250) of the external temperature monitor in<br>Table 2-49 • Analog Channel Specificationshave been updated (SAR 51464).|2-117|
||Specifications for the internal temperature monitor in<br>Table 2-49 • Analog Channel Specificationshave been updated (SAR 50870).|2-117|
**Revision 8**
**5-1**
_Fusion Family of Mixed Signal FPGAs_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Revision 4<br>(January 2013)|The"Product Ordering Codes" sectionhas been updated to mention “Y” as “Blank”<br>mentioning “Device Does Not Include License to Implement IP Based on the<br>Cryptography Research, Inc. (CRI) Patent Portfolio” (SAR 43177).|III|
||The note inTable 2-12 • Fusion CCC/PLL Specificationreferring the reader to<br>SmartGen was revised to refer instead to the online help associated with the core<br>(SAR 42563).|2-28|
||Table 2-49 • Analog Channel Specificationswas modified to update the uncalibrated<br>offset values (AFS250) of the external and internal temperature monitors (SAR<br>43134).|2-117|
||InTable 2-57 • Prescaler Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3),<br>changed the column heading from 'Full-Scale Voltage' to 'Full Scale Voltage in 10-Bit<br>Mode', and added and updated Notes as required (SAR 20812).|2-130|
||The values for the Speed Grade (-1 and Std.) for FDDRIMAX (Table 2-180 • Input<br>DDR Propagation Delays) and values for the Speed Grade (-2 and Std.) for<br>FDDOMAX (Table 2-182 • Output DDR Propagation Delays) had been inadvertently<br>interchanged. This has been rectified (SAR 38514).|2-220,<br>2-222|
||Added description about what happens if a user connects VAREF to an external 3.3<br>V on their board to the"VAREFAnalog Reference Voltage" section(SAR 35188).|2-225|
||Added a note toTable 3-2 • Recommended Operating Conditions1(SAR 43429):<br>The programming temperature range supported is Tambient= 0°C to 85°C.|3-3|
||Added the Package Thermal details for AFS600-PQ208 and AFS250-PQ208 to<br>Table 3-6 • Package Thermal Resistance(SAR 37816). Deleted the Die Size column<br>from the table (SAR 43503).|3-7|
||Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip<br>(SoC) throughout the document (SAR 42495).<br>Live at Power-Up (LAPU) has been replaced with’Instant On’.|NA|
|Revision 3<br>(August 2012)|Microblade U1AFS250 and U1AFS1500 devices were added to the product tables.|I–IV|
||A sentence pertaining to the analog I/Os was added to the"Specifying I/O States<br>During Programming" section(SAR 34831).|1-9|
**Revision 8**
**5-2**
_Datasheet Information_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Revision 3<br>(continued)|The"RC Oscillator" sectionwas revised to correct a sentence that did not<br>differentiate accuracy for commercial and industrial temperature ranges, which is<br>given inTable 2-9 • Electrical Characteristics of RC Oscillator(SAR 33722).|2-19|
||Figure 2-57 • FIFO ReadandFigure 2-58 • FIFO Writeare new (SAR 34840).|2-72|
||The first paragraph of the"Offset" sectionwas removed; it was intended to be<br>replaced by the paragraph following it (SAR 22647).|2-95|
||IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were corrected inTable 2-86 •<br>Summary of Maximum and Minimum DC Input and Output Levels Applicable to<br>Commercial and Industrial Conditions(SAR 39813).|2-164|
||The drive strength, IOL, and IOH for 3.3 V GTL and 2.5 V GTL were changed from<br>25 mA to 20 mA in the following tables (SAR 37373):<br>Table 2-86 • Summary of Maximum and Minimum DC Input and Output Levels<br>Applicable to Commercial and Industrial Conditions,<br>Table 2-92 • Summary of I/O Timing Characteristics – Software Default Settings<br>Table 2-96 • I/O Output Buffer Maximum Resistances 1<br>Table 2-138 • Minimum and Maximum DC Input and Output Levels<br>Table 2-141 • Minimum and Maximum DC Input and Output Levels|2-164<br>2-167<br>2-169<br>2-199<br>2-200|
||The following sentence was deleted from the"2.5 V LVCMOS" section(SAR 34800):<br>“It uses a 5 V–tolerant input buffer and push-pull output buffer.”|2-181|
||Corrected the inadvertent error in maximum values for LVPECL VIH and VIL and<br>revised them to “3.6” inTable 2-171 • Minimum and Maximum DC Input and Output<br>Levels, making these consistent withTable 3-1 • Absolute Maximum Ratings, and<br>Table 3-4 • Overshoot and Undershoot Limits1(SAR 37687).|2-211|
||The maximum frequency for global clock parameter was removed fromTable 2-5 •<br>AFS1500 Global Resource TimingthroughTable 2-8 • AFS090 Global Resource<br>Timingbecause a frequency on the global is only an indication of what the global<br>network can do. There are other limiters such as the SRAM, I/Os, and PLL.<br>SmartTime software should be used to determine the design frequency (SAR<br>36955).|2-16to<br>2-17|
|Revision 2<br>(March 2012)|The phrase “without debug” was removed from the"Soft ARM Cortex-M1 Fusion<br>Devices (M1)" section(SAR 21390).|I|
||The"In-System Programming (ISP) and Security" section,"Security" section,"Flash<br>Advantages" section, and"Security" sectionwere revised to clarify that although no<br>existing security measures can give an absolute guarantee, Microsemi FPGAs<br>implement the best security available in the industry (SAR 34679).|I,1-2,<br>2-228|
||The Y security option and Licensed DPA Logo was added to the"Product Ordering<br>Codes" section. The trademarked Licensed DPA Logo identifies that a product is<br>covered by a DPA counter-measures license from Cryptography Research (SAR<br>34721).|III|
||The"Specifying I/O States During Programming" sectionis new (SAR 34693).|1-9|
||The following information was added beforeFigure 2-17 • XTLOSC Macro:<br>In the case where the Crystal Oscillator block is not used, the XTAL1 pin should be<br>connected to GND and the XTAL2 pin should be left floating (SAR 24119).|2-20|
||Table 2-12 • Fusion CCC/PLL Specificationwas updated. A note was added<br>indicating that when the CCC/PLL core is generated by Microsemi core generator<br>software, not all delay values of the specified delay increments are available (SAR<br>34814).|2-28|
**5-3**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Revision 2<br>(continued)|A note was added toFigure 2-27 • Real-Time Counter System (not all the signals are<br>shown for the AB macro)stating that the user is only required to instantiate the<br>VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator<br>to be different from the default, or employ user logic to shut the voltage regulator off<br>(SAR 21773).|2-31|
||VPUMP was incorrectly represented as VPP in several places. This was corrected to<br>VPUMP in the"Standby and Sleep Mode Circuit Implementation" sectionand<br>Table 3-8 • AFS1500 Quiescent Supply Current CharacteristicsthroughTable 3-11 •<br>AFS090 Quiescent Supply Current Characteristics(21963).|2-32,3-10|
||Additional information was added to the Flash Memory Block"Write Operation"<br>section, including an explanation of the fact that a copy-page operation takes no less<br>than 55 cycles (SAR 26338).|2-45|
||The"FlashROM" sectionwas revised to refer toFigure 2-46 • FlashROM Timing<br>DiagramandTable 2-26 • FlashROM Access Timerather than stating 20 MHz as the<br>maximum FlashROM access clock and 10 ns as the time interval for D0 to become<br>valid or invalid (SAR 22105).|2-53,2-54|
||The following figures were deleted (SAR 29991). Reference was made to a new<br>application note,_Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-_<br>_Based cSoCs and FPGAs_,which covers these cases in detail (SAR 34862).<br>Figure 2-55 • Write Access after Write onto Same Address<br>Figure 2-56 • Read Access after Write onto Same Address<br>Figure 2-57 • Write Access after Read onto Same Address<br>The port names in the SRAM"Timing Waveforms","Timing Characteristics", SRAM<br>tables,Figure 2-55 • RAM Reset. Applicable to both RAM4K9 and RAM512x18., and<br>the FIFO"Timing Characteristics"tables were revised to ensure consistency with the<br>software names (SAR 35753).|2-63,<br>2-66,<br>2-65,2-75|
||In several places throughout the datasheet, GNDREF was corrected to<br>ADCGNDREF (SAR 20783):<br>Figure 2-64 • Analog Block Macro<br>Table 2-36 • Analog Block Pin Description<br>"ADC Operation" section|2-77<br>2-78<br>2-104|
||The following note was added belowFigure 2-78 • Timing Diagram for the<br>Temperature Monitor Strobe Signal:<br>When the IEEE 1149.1 Boundary Scan EXTEST instruction is executed, the AG pad<br>drive strength ceases and becomes a 1 µA sink into the Fusion device. (SAR<br>24796).|2-93|
||The"Analog-to-Digital Converter Block" sectionwas extensively revised,<br>reorganizing the information and adding the"ADC Theory of Operation" sectionand<br>"Acquisition Time or Sample Time Control" section. The"ADC Example" sectionwas<br>reworked and corrected (SAR 20577).|2-96|
||Table 2-49 • Analog Channel Specificationswas modified to include calibrated and<br>uncalibrated values for offset (AFS090 and AFS250) for the external and internal<br>temperature monitors. The"Offset" sectionwas revised accordingly and now<br>referencesTable 2-49 • Analog Channel Specifications(SARs 22647, 27015).|2-95,<br>2-117|
||The"Intra-Conversion" sectionand"Injected Conversion" sectionhad definitions<br>incorrectly interchanged and have been corrected.Figure 2-92 • Intra-Conversion<br>Timing DiagramandFigure 2-93 • Injected Conversion Timing Diagramwere also<br>incorrectly interchanged and have been replaced correctly. Reference in the figure<br>notes toEQ 10has been corrected toEQ 23(SAR 20547).|2-110,<br>2-113,<br>2-113|
**Revision 8**
**5-4**
_Datasheet Information_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Revision 2<br>(continued)|The prescalar range for the 'Analog Input (direct input to ADC)” configurations was<br>removed as inapplicable for direct inputs. The input resistance for direct inputs is<br>covered inTable 2-50 • ADC Characteristics in Direct Input Mode(SAR 31201).|2-120|
||The"Examples"for calibrating accuracy for ADC channels were revised and<br>corrected to make them consistent with terminology in the associated tables (SARs<br>36791, 36773).|2-124|
||A note was added toTable 2-56 • Analog Quad ACM Byte Assignmentand the<br>introductory text forTable 2-66 • Internal Temperature Monitor Control Truth Table,<br>stating that for the internal temperature monitor to function, Bit 0 of Byte 2 for all 10<br>Quads must be set (SAR 34418).|2-129,<br>2-131|
||tDOUTwas corrected to tDINinFigure 2-116 • Input Buffer Timing Model and Delays<br>(example)(SAR 37115).|2-161|
||The formulas in the table notes forTable 2-97 • I/O Weak Pull-Up/Pull-Down<br>Resistanceswere corrected (SAR 34751).|2-171|
||The AC Loading figures in the"Single-Ended I/O Characteristics" sectionwere<br>updated to match tables in the"Summary of I/O Timing Characteristics – Default I/O<br>Software Settings" section(SAR 34877).|2-175|
||The following notes were removed fromTable 2-168 • Minimum and Maximum DC<br>Input and Output Levels(SAR 34808):<br>±5%<br>Differential input voltage= ±350 mV|2-209|
||An incomplete, duplicate sentence was removed from the end of the"GNDAQ<br>Ground (analog quiet)"pin description (SAR 30185).|2-223|
||Information about configuration of unused I/Os was added to the"User Pins" section<br>(SAR 32642).|2-225|
||The following information was added to the pin description for"XTAL1 Crystal<br>Oscillator Circuit Input"and"XTAL2 Crystal Oscillator Circuit Input"(SAR 24119).|2-227|
||The input resistance to ground value inTable 3-3 • Input Resistance of Analog Pads<br>for Analog Input (direct input to ADC), was corrected from 1 M(typical) to 2 k<br>(typical) (SAR 34371).|3-4|
||The Storage Temperature column inTable 3-5 • FPGA Programming, Storage, and<br>Operating Limitsstated Min. TJtwice for commercial and industrial product grades<br>and has been corrected to Min. TJand Max. TJ(SAR 29416).|3-5|
||The reference to guidelines for global spines and VersaTile rows, given in the<br>"Global Clock Dynamic Contribution—PCLOCK" section, was corrected to the“Spine<br>Architecture” section of the Global Resources chapter in the_Fusion FPGA_<br>_Fabric User's Guide_(SAR 34741).|3-24|
||Package names used in the"Package Pin Assignments" sectionwere revised to<br>match standards given in_Package Mechanical Drawings_(SAR 36612).|4-1|
|July 2010|The versioning system for data-sheets has been changed. Datasheets are assigned<br>a revision number that increments each time the datasheet is revised. The"Fusion<br>Device Status" tableindicates the status for each device in the device family.|N/A|
**Revision 8**
**5-5**
_Fusion Family of Mixed Signal FPGAs_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|v2.0, Revision 1<br>(July 2009)|The MicroBlade and Fusion datasheets have been combined. Pigeon Point<br>information is new.<br>CoreMP7 support was removed since it is no longer offered.<br>–F was removed from the datasheet since it is no longer offered.<br>The operating temperature was changed from ambient to junction to better reflect<br>actual conditions of operations.<br>Commercial: 0°C to 85°C<br>Industrial: –40°C to 100°C<br>The version number category was changed from Preliminary to Production, which<br>means the datasheet contains information based on final characterization. The<br>version number changed from Preliminary v1.7 to v2.0.|N/A|
||The"Integrated Analog Blocks and Analog I/Os" sectionwas updated to include a<br>reference to the “Analog System Characteristics” section in the_Device Architecture_<br>chapter of the datasheet, which includesTable 2-46 • Analog Channel Specifications<br>and specific voltage data.|1-4|
||The phrase "Commercial-Case Conditions" in timing table titles was changed to<br>"Commercial Temperature Range Conditions."|N/A|
||The"Crystal Oscillator" sectionwas updated significantly. Please review carefully.|2-20|
||The"Real-Time Counter (part of AB macro)" sectionwas updated significantly.<br>Please review carefully.|2-33|
||There was a typo inTable 2-19 • Flash Memory Block Pin Namesfor the<br>ERASEPAGE description; it was the same as DISCARDPAGE. As as a result, the<br>ERASEPAGE description was updated.|2-40|
||The tFMAXCLKNVMparameter was updated inTable 2-25 • Flash Memory Block<br>Timing.|2-52|
||Table 2-31 • RAM4K9andTable 2-32 • RAM512X18were updated.|2-66|
||InTable 2-36 • Analog Block Pin Description, the Function description for PWRDWN<br>was changed from “Comparator power-down if 1"<br>to<br>“ADC comparator power-down if 1. When asserted, the ADC will stop functioning,<br>and the digital portion of the analog block will continue operating. This may result in<br>invalid status flags from the analog block. Therefore, Microsemi does not<br>recommend asserting the PWRDWN pin.”|2-78|
||Figure 2-75 • Gate Driver Examplewas updated.|2-91|
||The"ADC Operation" sectionwas updated. Please review carefully.|2-104|
||Figure 2-92 • Intra-Conversion Timing DiagramandFigure 2-93 • Injected<br>Conversion Timing Diagramare new.|2-113|
||The"Typical Performance Characteristics" sectionis new.|2-115|
||Table 2-49 • Analog Channel Specificationswas significantly updated.|2-117|
||Table 2-50 • ADC Characteristics in Direct Input Modewas significantly updated.|2-120|
||InTable 2-52 • Calibrated Analog Channel Accuracy 1,2,3, note 2 was updated.|2-123|
||InTable 2-53 • Analog Channel Accuracy: Monitoring Standard Positive Voltages,<br>note 1 was updated.|2-124|
||InTable 2-54 • ACM Address Decode Table for Analog Quad, bit 89 was removed.|2-126|
**Revision 8**
**5-6**
_Datasheet Information_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|v2.0, Revision 1<br>(continued)|The data in the 2.5 V LCMOS and LVCMOS 2.5 V / 5.0 V rows were updated in<br>Table 2-75 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance<br>Capabilities.|2-143|
||InTable 2-78 • Fusion Standard I/O Standards—OUT_DRIVE Settings, LVCMOS<br>1.5 V, for OUT_DRIVE 2, was changed from a dash to a check mark.|2-152|
||The"VCC15A Analog Power Supply (1.5 V)"definition was changed from “A 1.5 V<br>analog power supply input should be used to provide this input” to “1.5 V clean<br>analog power supply input for use by the 1.5 V portion of the analog circuitry.”|2-223|
||In the"VCC33PMP Analog Power Supply (3.3 V)"pin description, the following text<br>was changed from “VCC33PMP should be powered up before or simultaneously<br>with VCC33A” to “VCC33PMP should be powered up simultaneously with or after<br>VCC33A.”|2-223|
||The"VCCOSC Oscillator Power Supply (3.3 V)" sectionwas updated to include<br>information about when to power the pin.|2-223|
||In the"128-Bit AES Decryption" section, FIPS-192 was incorrect and changed to<br>FIPS-197.|2-228|
||The note inTable 2-84 • Fusion Standard and Advanced I/O Attributes vs. I/O<br>Standard Applicationswas updated.|2-156|
||For 1.5 V LVCMOS, the VIL and VIH parameters, 0.30 * VCCI was changed to 0.35 *<br>VCCI and 0.70 * VCCI was changed to 0.65 * VCCI inTable 2-86 • Summary of<br>Maximum and Minimum DC Input and Output Levels Applicable to Commercial and<br>Industrial Conditions,Table 2-87 • Summary of Maximum and Minimum DC Input<br>and Output Levels Applicable to Commercial and Industrial Conditions, and<br>Table 2-88 • Summary of Maximum and Minimum DC Input and Output Levels<br>Applicable to Commercial and Industrial Conditions.<br>InTable 2-87 • Summary of Maximum and Minimum DC Input and Output Levels<br>Applicable to Commercial and Industrial Conditions, the VIH max column was<br>updated.|2-164to<br>2-165|
||Table 2-89 • Summary of Maximum and Minimum DC Input Levels Applicable to<br>Commercial and Industrial Conditionswas updated to include notes 3 and 4. The<br>temperature ranges were also updated in notes 1 and 2.|2-165|
||The titles inTable 2-92 • Summary of I/O Timing Characteristics – Software Default<br>SettingstoTable 2-94 • Summary of I/O Timing Characteristics – Software Default<br>Settingswere updated to“VCCI = I/O Standard Dependent.”|2-167to<br>2-168|
||BelowTable 2-98 • I/O Short Currents IOSH/IOSL, the paragraph was updated to<br>change 110°C to 100°C and three months was changed to six months.|2-172|
||Table 2-99 • Short Current Event Duration before Failurewas updated to remove<br>110°C data.|2-174|
||InTable 2-101 • I/O Input Rise Time, Fall Time, and Related I/O Reliability,<br>LVTTL/LVCMOS rows were changed from 110°C to 100°C.|2-174|
||VCC33PMP was added toTable 3-1 • Absolute Maximum Ratings. In addition,<br>conditions for AV, AC, AG, and AT were also updated.|3-1|
||VCC33PMP was added toTable 3-2 • Recommended Operating Conditions1. In<br>addition, conditions for AV, AC, AG, and AT were also updated.|3-3|
||Table 3-5 • FPGA Programming, Storage, and Operating Limitswas updated to<br>include new data and the temperature ranges were changed. The notes were<br>removed from the table.|3-5|
**Revision 8**
**5-7**
_Fusion Family of Mixed Signal FPGAs_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|v2.0, Revision 1<br>(continued)|Table 3-6 • Package Thermal Resistancewas updated to include new data.|3-7|
||InEQ 4toEQ 6, the junction temperature was changed from 110°C to 100°C.|3-8to3-8|
||Table 3-8 • AFS1500 Quiescent Supply Current CharacteristicsthroughTable 3-11 •<br>AFS090 Quiescent Supply Current Characteristicsare new and have replaced the<br>Quiescent Supply Current Characteristics (IDDQ) table.|3-10to<br>3-16|
||InTable 3-14 • Different Components Contributing to the Dynamic Power<br>Consumption in Fusion Devices, the power supply for PAC9 and PAC10 were<br>changed from VMV/VCC to VCCI.|3-22|
||InTable 3-15 • Different Components Contributing to the Static Power Consumption<br>in Fusion Devices, the power supply for PDC7 and PDC8 were changed from<br>VMV/VCC to VCCI. PDC1 was updated from TBD to 18.|3-23|
||The"QN108" tablewas updated to remove the duplicates of pins B12 and B34.|4-2|
|Preliminary v1.7<br>(October 2008)|The version number category was changed from Advance to Preliminary, which<br>means the datasheet contains information based on simulation and/or initial<br>characterization. The information is believed to be correct, but changes are possible.||
||For the VIL and VIH parameters, 0.30 * VCCI was changed to 0.35 * VCCI and 0.70<br>* VCCI was changed to 0.65 * VCCI inTable 2-126 • Minimum and Maximum DC<br>Input and Output Levels.|2-193|
||The version number category was changed from Advance to Preliminary, which<br>means the datasheet contains information based on simulation and/or initial<br>characterization. The information is believed to be correct, but changes are possible.|N/A|
||The following updates were made toTable 2-141 • Minimum and Maximum DC Input<br>and Output Levels:<br>Temperature<br>Digital Output<br>213<br>00 1111 1101<br>283<br>01 0001 1011<br>358<br>01 0110 0110 – only the digital output was updated.<br>Temperature 358 remains in the temperature column.|2-200|
||In Advance v1.2, the"VAREFAnalog Reference Voltage"pin description was<br>significantly updated but the change was not noted in the change table.|2-225|
|Advance v1.6<br>(August 2008)|The title of the datasheet changed from Actel Programmable System Chips to Actel<br>Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip<br>were changed to mixed signal FPGA.|N/A|
||The references to the_Peripherals User’s Guide_in the"No-Glitch MUX (NGMUX)"<br>sectionand"Voltage Regulator Power Supply Monitor (VRPSM)" sectionwere<br>changed to_Fusion Handbook_.|2-32,2-42|
|Advance v1.5<br>(July 2008)|The following bullet was updated from High-Voltage Input Tolerance: ±12 V to High-<br>Voltage Input Tolerance: 10.5 V to 12 V.|I|
||The following bullet was updated from Programmable 1, 3, 10, 30 µA and 25 mA<br>Drive Strengths to Programmable 1, 3, 10, 30µA and 20 mA Drive Strengths.|I|
**Revision 8**
**5-8**
_Datasheet Information_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Advance v1.5<br>(continued)|This bullet was added to the “Integrated A/D Converter (ADC) and Analog I/O”<br>section: ADC Accuracy is Better than 1%|I|
||In the"Integrated Analog Blocks and Analog I/Os" section, ±4 LSB was changed to<br>0.72. The following sentence was deleted:<br>The input range for voltage signals is from –12 V to +12 V with full-scale output<br>values from 0.125 V to 16 V.<br>In addition, 2°C was changed to 3°C:<br>"One analog input in each quad can be connected to an external temperature<br>monitor diode and achieves detection accuracy of ±3ºC."<br>The following sentence was deleted:<br>The input range for voltage signals is from –12 V to +12 V with full-scale output<br>values from 0.125 V to 16 V.|1-4|
||The title of the datasheet changed from Actel Programmable System Chips to Actel<br>Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip<br>were changed to mixed signal FPGA.|N/A|
|Advance v1.4<br>(July 2008)|InTable 3-8 · Quiescent Supply Current Characteristics (IDDQ)1, footnote<br>references were updated for IDC2and IDC3.<br>Footnote 3 and 4 were updated and footnote 5 is new.|3-11|
|Advance v1.3<br>(July 2008)|The"ADC Description" sectionwas significantly updated. Please review carefully.|2-102|
|Advance v1.2<br>(May 2008)|Table 2-25 • Flash Memory Block Timingwas significantly updated.|2-55|
||The"VAREFAnalog Reference Voltage"pin description section was significantly<br>update. Please review it carefully.|2-226|
||Table 2-45 • ADC Interface Timingwas significantly updated.|2-110|
||Table 2-56 • Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1),<br>and AT (x = 3)was significantly updated.|2-131|
||The following sentence was deleted from the"Voltage Monitor" section:<br>The Analog Quad inputs are tolerant up to 12 V + 10%.|2-86|
||The"180-Pin QFN"figure was updated. D1 to D4 are new and the figure was<br>changed to bottom view. The note below the figure is new.|3-3|
|Advance v1.1<br>(May 2008)|The following text was incorrect and therefore deleted:<br>**VCC33A**<br>**Analog Power Filter**<br>Analog power pin for the analog power supply low-pass filter. An external 100 pF<br>capacitor should be connected between this pin and ground.<br>There is still a description of VCC33Aonpage 2-224.|2-204|
**5-9**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
**==> picture [468 x 649] intentionally omitted <==**
**----- Start of picture text -----**<br>
Revision Changes Table<br>ee<br>Advance v1.0 All Timing Characteristics tables were updated. For the Differential I/O Standards, N/A<br>(January 2008) the Standard I/O support tables are new.<br>Table 2-3 • Array Coordinates was updated to change the max x and y values 2-9<br>a<br>Table 2-12 • Fusion CCC/PLL Specification was updated. 2-31<br>Pe<br>A note was added to Table 2-16 · RTC ACM Memory Map. 2-37<br>A reference to the Peripheral’s User’s Guide was added to the "Voltage Regulator 2-42<br>Power Supply Monitor (VRPSM)" section.<br>ee In Table 2-25 • Flash Memory Block Timing, the commercial conditions were ee 2-55<br>updated.<br>In Table 2-26 • FlashROM Access Time, the commercial conditions were missing 2-58<br>and have been added below the title of the table.<br>In Table 2-36 • Analog Block Pin Description, the function description was updated 2-82<br>for the ADCRESET.<br>In the "Voltage Monitor" section, the following sentence originally had ± 10% and it 2-86<br>was changed to +10%.<br>The Analog Quad inputs are tolerant up to 12 V + 10%.<br>In addition, this statement was deleted from the datasheet:<br>Each I/O will draw power when connected to power (3 mA at 3 V).<br>The "Terminology" section is new. 2-88<br>The "Current Monitor" section was significantly updated. Figure 2-72 • Timing 2-90<br>Diagram for Current Monitor Strobe to Figure 2-74 • Negative Current Monitor and<br>Table 2-37 • Recommended Resistor for Different Current Range Measurement are<br>new.<br>Pt<br>The "ADC Description" section was updated to add the "Terminology" section. 2-93<br>In the "Gate Driver" section, 25 mA was changed to 20 mA and 1.5 MHz was 2-94<br>changed to 1.3 MHz. In addition, the following sentence was deleted:<br>The maximum AG pad switching frequency is 1.25 MHz.<br>pO<br>The "Temperature Monitor" section was updated to rewrite most of the text and add 2-96<br>Figure 2-78, Figure 2-79, and Table 2-38 • Temperature Data Format.<br>In Table 2-38 • Temperature Data Format, the temperature K column was changed 2-98<br>for 85°C from 538 to 358.<br>In Table 2-45 • ADC Interface Timing, "Typical-Case" was changed to "Worst-Case." 2-110<br>a<br>The "ADC Interface Timing" section is new. 2-110<br>a<br>Table 2-46 • Analog Channel Specifications was updated. 2-118<br>Pe<br>The "VCC15A Analog Power Supply (1.5 V)" section was updated. 2-224<br>The "VCCPLA/B PLL Supply Voltage" section is new. 2-225<br>In "VCCNVM Flash Memory Block Power Supply (1.5 V)" section, supply was 2-224<br>changed to supply input.<br>ee<br>The "VCCPLA/B PLL Supply Voltage" pin description was updated to include the 2-225<br>following statement:<br>Actel recommends tying VCCPLX to VCC and using proper filtering circuits to<br>decouple VCC noise from PLL.<br>The "VCOMPLA/B Ground for West and East PLL" section was updated. 2-225<br>Pe<br>**----- End of picture text -----**<br>
**Revision 8**
**5-10**
_Datasheet Information_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Advance 1.0<br>(continued)|InTable 2-47 • ADC Characteristics in Direct Input Mode, the commercial conditions<br>were updated and note 2 is new.|2-121|
||The VCC33ACAPsignal name was changed to"XTAL1 Crystal Oscillator Circuit<br>Input".|2-228|
||Table 2-48 • Uncalibrated Analog Channel Accuracy*is new.|2-123|
||Table 2-49 • Calibrated Analog Channel Accuracy 1,2,3is new.|2-124|
||Table 2-50 • Analog Channel Accuracy: Monitoring Standard Positive Voltagesis<br>new.|2-125|
||InTable 2-57 • Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and AT<br>(x = 3)*, the following I/O Bank names were changed:<br>Hot-Swap changed to Standard<br>LVDS changed to Advanced|2-131|
||InTable 2-58 • Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x = 1),<br>and AT (x = 3), the following I/O Bank names were changed:<br>Hot-Swap changed to Standard<br>LVDS changed to Advanced|2-132|
||In the title ofTable 2-64 • I/O Standards Supported by Bank Type, LVDS I/O was<br>changed to Advanced I/O.|2-134|
||The title was changed from "Fusion Standard, LVDS, and Standard plus Hot-Swap<br>I/O" toTable 2-68 • Fusion Standard and Advanced I/O Features. In addition, the<br>table headings were all updated. The heading used to be Standard and LVDS I/O<br>and was changed to Advanced I/O. Standard Hot-Swap was changed to just<br>Standard.|2-136|
||This sentence was deleted from the"Slew Rate Control and Drive Strength" section:<br>The Standard hot-swap I/Os do not support slew rate control. In addition, these<br>references were changed:<br>• From: Fusion hot-swap I/O (Table 2-69 on page 2-122) To: Fusion Standard I/O<br>• From: Fusion LVDS I/O (Table 2-70 on page 2-122) To: Fusion Advanced I/O|2-152|
||The"Cold-Sparing Support" sectionwas significantly updated.|2-143|
||In the title ofTable 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settings,<br>Hot-Swap was changed to Standard.|2-153|
||In the title ofTable 2-76 • Fusion Advanced I/O Standards—SLEW and OUT_DRIVE<br>Settings, LVDS was changed to Advanced.|2-153|
||In the title ofTable 2-81 • Fusion Standard and Advanced I/O Attributes vs. I/O<br>Standard Applications, LVDS was changed to Advanced.|2-157|
||InFigure 2-111 • Naming Conventions of Fusion Devices with Three Digital I/O<br>BanksandFigure 2-112 • Naming Conventions of Fusion Devices with Four I/O<br>Banksthe following names were changed:<br>Hot-Swap changed to Standard<br>LVDS changed to Advanced|2-160|
||TheFigure 2-113 • Timing Modelwas updated.|2-161|
||In the notes forTable 2-86 • Summary of Maximum and Minimum DC Input Levels<br>Applicable to Commercial and Industrial Conditions, TJwas changed to TA.|2-166|
**5-11**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Advance v1.0<br>(continued)|This change table states that in the"208-Pin PQFP" tablelisted under the Advance<br>v0.8 changes, the AFS090 device had a pin change. That is incorrect. Pin 102 was<br>updated for AFS250 and AFS600. The function name changed from VCC33ACAPto<br>VCC33A.|3-8|
|Advance v0.9<br>(October 2007)|In<br>the<br>"Package<br>I/Os:<br>Single-/Double-Ended<br>(Analog)"<br>table,<br>the<br>AFS1500/M7AFS1500 I/O counts were updated for the following devices:<br>FG484: 223/109<br>FG676: 252/126|II|
||In the"108-Pin QFN" table, the function changed from VCC33ACAPto VCC33Afor the<br>following pin:<br>B25|3-2|
||In the"180-Pin QFN" table, the function changed from VCC33ACAPto VCC33Afor the<br>following pins:<br>AFS090: B29<br>AFS250: B29|3-4|
||In the"208-Pin PQFP" table, the function changed from VCC33ACAPto VCC33Afor the<br>following pins:<br>AFS090: 102<br>AFS250: 102|3-8|
||In the"256-Pin FBGA" table, the function changed from VCC33ACAPto VCC33Afor the<br>following pins:<br>AFS090: T14<br>AFS250: T14<br>AFS600: T14<br>AFS1500: T14|3-12|
|Advance v0.9<br>(continued)|In the"484-Pin FBGA" table, the function changed from VCC33ACAPto VCC33Afor the<br>following pins:<br>AFS600: AB18<br>AFS1500: AB18|3-20|
||In the"676-Pin FBGA" table, the function changed from VCC33ACAPto VCC33Afor the<br>following pins:<br>AFS1500: AD20|3-28|
|Advance v0.8<br>(June 2007)|Figure 2-16 • Fusion Clocking Optionsand the"RC Oscillator" sectionwere updated<br>to change GND_OSC and VCC_OSC to GNDOSC and VCCOSC.|2-20,2-21|
||Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macrowas updated<br>to change the positions of OADIVRST and OADIVHALF, and a note was added.|2-25|
||The"Crystal Oscillator" sectionwas updated to include information about controlling<br>and enabling/disabling the crystal oscillator.|2-22|
||Table 2-11 · Electrical Characteristics of the Crystal Oscillatorwas updated to<br>change the typical value of IDYNXTALfor 0.032–0.2 MHz to 0.19.|2-24|
||The"1.5 V Voltage Regulator" sectionwas updated to add "or floating" in the<br>paragraph stating that an external pull-down is required on TRST to power down the<br>VR.|2-41|
||The"1.5 V Voltage Regulator" sectionwas updated to include information on<br>powering down with the VR.|2-41|
**Revision 8**
**5-12**
_Datasheet Information_
|**Revision**<br>~~ee~~|**Changes**<br>~~ee~~|**Table**<br>~~ee~~|
|---|---|---|
|Advance v0.8<br>(continued)<br>~~ee~~<br>~~Pe~~|This sentence was updated in the"No-Glitch MUX (NGMUX)" sectionto delete GLA:<br>The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e.,<br>internal signal or GLC).<br>~~ee~~|2-32<br>~~ee~~|
||InTable 2-13 • NGMUX Configuration and Selection Table, 10 and 11 were deleted.|2-32|
||The method to enable sleep mode was updated for bit 0 inTable 2-16 • RTC<br>Control/Status Register.|2-38|
||S2 was changed to D2 inFigure 2-39 • Read Waveform (Pipe Mode, 32-bit access)<br>for RD[31:0] was updated.|2-51|
||The definitions for bits 2 and 3 were updated inTable 2-24 • Page Status Bit<br>Definition.|2-52|
||Figure 2-46 • FlashROM Timing Diagramwas updated.<br>~~a~~|2-58<br>~~a~~|
||Table 2-26 • FlashROM Access Timeis new.|2-58|
||Figure 2-55 • Write Access After Write onto Same Address,Figure 2-56 • Read<br>Access After Write onto Same Address, andFigure 2-57 • Write Access After Read<br>onto Same Addressare new.<br>~~po~~|2-68–<br>2-70<br>~~po~~|
||Table 2-31 • RAM4K9andTable 2-32 • RAM512X18were updated.<br>~~po~~|2-71,2-72<br>~~po~~|
||The VAREF and SAMPLE functions were updated inTable 2-36 • Analog Block Pin<br>Description.|2-82|
||The title ofFigure 2-72 • Timing Diagram for Current Monitor Strobewas updated to<br>add the word "positive."|2-91|
||The"Gate Driver" sectionwas updated to give information about the switching rate<br>in High Current Drive mode.|2-94|
||The"ADC Description" sectionwas updated to include information about the<br>SAMPLE and BUSY signals and the maximum frequencies for SYSCLK and<br>ADCCLK.EQ 2was updated to add parentheses around the entire expression in the<br>denominator.|2-102|
||Table 2-46 · Analog Channel SpecificationsandTable 2-47 · ADC Characteristics in<br>Direct Input Modewere updated.|2-118,<br>2-121|
||The note was removed fromTable 2-55 • Analog Multiplexer Truth Table—AV (x = 0),<br>AC (x = 1), and AT (x = 3).|2-131|
||Table 2-63 • Internal Temperature Monitor Control Truth Tableis new.<br>~~Pe~~|2-132<br>~~ee~~|
||The"Cold-Sparing Support" sectionwas updated to add information about cases<br>where current draw can occur.<br>~~ee~~<br>~~Pe~~|2-143<br>~~ee~~<br>~~ee~~|
||Figure 2-104 • Solution 4was updated.<br>~~ee~~<br>~~Pe~~|2-147<br>~~ee~~<br>~~ee~~|
||Table 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settingswas updated.<br>~~Pe~~|2-153<br>~~ee~~|
||The"GNDA Ground (analog)" sectionand"GNDAQ Ground (analog quiet)" section<br>were updated to add information about maximum differential voltage.|2-224|
||The"VAREFAnalog Reference Voltage" sectionand"VPUMP Programming Supply<br>Voltage" sectionwere updated.|2-226|
||The"VCCPLA/BPLL Supply Voltage" sectionwas updated to include information<br>about the east and west PLLs.|2-225|
||The VCOMPLFpin description was deleted.|N/A|
||The “Axy Analog Input/Output”sectionwas updated with information about<br>grounding and floating the pin.<br>~~ee~~|2-226<br>~~ee~~|
**5-13**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**Revision**<br>~~ee~~|**Changes**<br>~~ee~~|**Table**<br>~~ee~~|
|---|---|---|
|Advance v0.8<br>(continued)<br>~~ee~~<br>~~Pe~~<br>~~Pe~~<br>~~Pe~~|The voltage range in the"VPUMP Programming Supply Voltage" sectionwas<br>updated. The parenthetical reference to "pulled up" was removed from the<br>statement, "VPUMPcan be left floating or can be tied (pulled up) to any voltage<br>between 0 V and 3.6 V."<br>~~ee~~|2-225<br>~~ee~~|
||The “ATRTNx Temperature Monitor Return”sectionwas updated with information<br>about grounding and floating the pin.|2-226|
||The following text was deleted from the"VREF I/O Voltage Reference" section: (all<br>digital I/O).|2-225|
||The"NCAP Negative Capacitor" sectionand"PCAP Positive Capacitor" section<br>were updated to include information about the type of capacitor that is required to<br>connect the two.|2-228|
||1 µF was changed to 100 pF in the"XTAL1 Crystal Oscillator Circuit Input".<br>~~Pe~~|2-228<br>|
||The"Programming" sectionwas updated to include information about VCCOSC.<br>~~Pe~~|2-229<br>|
||The VMV pins have now been tied internally with the VCCIpins.<br>~~Pea~~|N/A<br>~~a~~|
||The AFS090"108-Pin QFN" tablewas updated.<br>~~a~~<br>~~Pe~~|3-2<br>~~a~~<br>|
||The AFS090 and AFS250 devices were updated in the"108-Pin QFN" table.<br>~~Pe~~|3-2<br>|
||The AFS250 device was updated in the"208-Pin PQFP" table.<br>~~Pe~~|3-8<br>|
||The AFS600 device was updated in the"208-Pin PQFP" table.<br>|3-8<br>|
||The AFS090, AFS250, AFS600, and AFS1500 devices were updated in the"256-Pin<br>FBGA" table.<br>|3-12<br>|
||The AFS600 and AFS1500 devices were updated in the"484-Pin FBGA" table.<br>~~a~~<br>~~Pe~~|3-20<br>~~a~~<br>|
|Advance v0.7<br>(January 2007)<br>~~Pe~~|The AFS600 device was updated in the"676-Pin FBGA" table.<br>~~Pe~~|3-28<br>|
||The AFS1500 digital I/O count was updated in the"Fusion Family" table.<br>~~Pe~~|I<br><br>~~ee~~|
||The AFS1500 digital I/O count was updated in the"Package I/Os: Single-/Double-<br>Ended (Analog)" table.<br>~~ee~~|II<br>~~ee~~<br>~~ee~~|
|Advance v0.6<br>(October 2006)<br><br>~~Pe~~<br>~~Pe~~|The second paragraph of the"PLL Macro" sectionwas updated to include<br>information about POWERDOWN.<br>~~ee~~<br>~~Pe~~|2-30<br>~~ee~~<br>~~ee~~<br>|
||The description for bit 0 was updated inTable 2-17 · RTC Control/Status Register.<br>~~Pe~~|2-38<br>|
||3.9 was changed to 7.8 in the"Crystal Oscillator (Xtal Osc)" section.<br>~~Pe~~|2-40.<br>|
||All function descriptions inTable 2-18 · Signals for VRPSM Macro.<br>|2-42<br>|
||InTable 2-19 • Flash Memory Block Pin Names, the RD[31:0] description was<br>updated.<br>|2-43<br>|
||The"RESET" sectionwas updated.<br>~~a~~<br>~~Pe~~|2-61<br>~~a~~|
||The"RESET" sectionwas updated.<br>~~Pe~~|2-64|
||Table 2-35 • FIFOwas updated.<br>~~Pe~~|2-79|
||The VAREF function description was updated inTable 2-36 • Analog Block Pin<br>Description.|2-82|
||The"Voltage Monitor" sectionwas updated to include information about low power<br>mode and sleep mode.|2-86|
||The text in the"Current Monitor" sectionwas changed from 2 mV to 1 mV.|2-90<br>~~ee~~|
||The"Gate Driver" sectionwas updated to include information about forcing 1 V on<br>the drain.<br>~~ee~~|2-94<br>~~ee~~<br>~~ee~~|
**Revision 8**
**5-14**
_Datasheet Information_
|**Revision**|**Changes**|**Table**|
|---|---|---|
|Advance v0.6<br>(continued)|The"Analog-to-Digital Converter Block" sectionwas updated with the following<br>statement:<br>"All results are MSB justified in the ADC."|2-99|
||The information about the ADCSTART signal was updated in the"ADC Description"<br>section.|2-102|
||Table 2-46 · Analog Channel Specificationswas updated.|2-118|
||Table 2-47 · ADC Characteristics in Direct Input Modewas updated.|2-121|
||Table 2-51 • ACM Address Decode Table for Analog Quadwas updated.|2-127|
||InTable 2-53 • Analog Quad ACM Byte Assignment, the Function and Default<br>Setting for Bit 6 in Byte 3 was updated.|2-130|
||The"Introduction" sectionwas updated to include information about digital inputs,<br>outputs, and bibufs.|2-133|
||InTable 2-69 • Fusion Pro I/O Features, the programmable delay descriptions were<br>updated for the following features:<br>Single-ended receiver<br>Voltage-referenced differential receiver<br>LVDS/LVPECL differential receiver features|2-137|
||The"User I/O Naming Convention" sectionwas updated to include "V" and "z"<br>descriptions|2-159|
||The"VCC33PMPAnalog Power Supply (3.3 V)" sectionwas updated to include<br>information about avoiding high current draw.|2-224|
||The"VCCNVMFlash Memory Block Power Supply (1.5 V)" sectionwas updated to<br>include information about avoiding high current draw.|2-224|
||The"VMVx I/O Supply Voltage (quiet)" sectionwas updated to include this<br>statement: VMV and VCCI must be connected to the same power supply and VCCI<br>pins within a given I/O bank.|2-185|
||The"PUB Push Button" sectionwas updated to include information about leaving<br>the pin floating if it is not used.|2-228|
||The"PTBASE Pass Transistor Base" sectionwas updated to include information<br>about leaving the pin floating if it is not used.|2-228|
||The"PTEM Pass Transistor Emitter" sectionwas updated to include information<br>about leaving the pin floating if it is not used.|2-228|
||The heading was incorrect in the"208-Pin PQFP" table. It should be AFS250 and not<br>AFS090.|3-8|
**5-15**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
|**Revision**<br>~~a~~|**Changes**|**Table**|
|---|---|---|
|Advance v0.5<br>(June 2006)<br>~~a~~<br>~~Ce~~|The low power modes of operation were updated and clarified.<br>~~Ce~~|N/A<br>~~||~~<br>|
||The AFS1500 digital I/O count was updated inTable 1 • Fusion Family.<br>~~Ce~~|i<br>~~||~~<br>|
||The AFS1500 digital I/O count was updated in the"Package I/Os: Single-/Double-<br>Ended (Analog)" table.<br>~~Ce~~|ii<br>~~||~~<br>|
||The"Voltage Regulator Power Supply Monitor (VRPSM)"was updated.<br>~~pO~~|2-36<br>~~pO~~|
||Figure 2-45 • FlashROM Timing Diagramwas updated.<br>~~pO~~|2-53<br>~~pO~~|
||The"256-Pin FBGA" tablefor the AFS1500 is new.<br>~~pO~~|3-12<br>~~pO~~|
|Advance v0.4<br>(April 2006)<br>~~a a~~|The G was moved in the"Product Ordering Codes" section.<br>~~a~~|III<br>~~a~~|
|Advance v0.3<br>(April 2006)<br>~~a~~|The"Features and Benefits" sectionwas updated.<br>~~a~~|I<br>~~a~~|
||The"Fusion Family" tablewas updated.<br>~~pO~~|I<br>~~pO~~|
||The"Package I/Os: Single-/Double-Ended (Analog)" tablewas updated.<br>~~pO~~|II<br>~~pO~~|
||The"Product Ordering Codes" tablewas updated.<br>~~pO~~<br>~~a~~|III<br>~~pO~~<br>~~a~~|
||The"Temperature Grade Offerings" tablewas updated.<br>~~a~~<br>~~a~~|IV<br>~~a~~<br>~~a~~|
||The"General Description" sectionwas updated to include ARM information.|1-1|
||Figure 2-46 • FlashROM Timing Diagramwas updated.<br>~~a~~|2-58<br>~~a~~|
||The"FlashROM" sectionwas updated.<br>~~a~~|2-57<br>~~a~~|
||The"RESET" sectionwas updated.<br>~~pO~~|2-61<br>~~pO~~|
||The"RESET" sectionwas updated.<br>~~pO~~<br>~~a~~|2-64<br>~~pO~~<br>~~a~~|
||Figure 2-27 · Real-Time Counter Systemwas updated.<br>~~a~~<br>~~a~~|2-35<br>~~a~~<br>~~a~~|
||Table 2-19 • Flash Memory Block Pin Nameswas updated.|2-43<br>~~ee~~|
||Figure 2-33 • Flash Memory Block Diagramwas updated to include AUX block<br>information.<br>~~ee~~|2-45<br>~~ee~~<br>~~ee~~|
||Figure 2-34 • Flash Memory Block Organizationwas updated to include AUX block<br>information.|2-46<br>~~ee~~|
||The note in the"Program Operation" sectionwas updated.<br>~~a~~|2-48<br>~~a~~|
||Figure 2-76 • Gate Driver Examplewas updated.|2-95|
||The"Analog Quad ACM Description" sectionwas updated.|2-130<br>~~ee~~|
||Information about the maximum pad input frequency was added to the"Gate Driver"<br>section.<br>~~ee~~|2-94<br>~~ee~~<br>~~ee~~|
||Figure 2-65 • Analog Block Macrowas updated.<br>~~ee~~<br>~~a~~|2-81<br>~~ee~~<br>~~ee~~<br>~~a~~|
||Figure 2-65 • Analog Block Macrowas updated.<br>~~a~~<br>~~a~~|2-81<br>~~a~~<br>~~a~~|
||The"Analog Quad" sectionwas updated.|2-84|
||The"Voltage Monitor" sectionwas updated.<br>~~a~~|2-86<br>~~a~~|
||The"Direct Digital Input" sectionwas updated.<br>~~a~~|2-89<br>~~a~~|
||The"Current Monitor" sectionwas updated.<br>~~a~~|2-90<br>~~a~~|
||Information about the maximum pad input frequency was added to the"Gate Driver"<br>section.|2-94|
**Revision 8**
**5-16**
_Datasheet Information_
|**Revision**<br>~~Ce~~|**Changes**<br>~~Ce~~|**Table**|
|---|---|---|
|Advance v0.3<br>(continued)<br>~~Ce~~<br>~~Ce~~|The"Temperature Monitor" sectionwas updated.<br>~~Ce~~<br>~~Ce~~|2-96|
||EQ 2is new.<br>~~Ce~~<br>~~Ce~~|2-103|
||The"ADC Description" sectionwas updated.<br>~~Ce~~|2-102|
||Figure 2-16 • Fusion Clocking Optionswas updated.|2-20|
||Table 2-46 · Analog Channel Specificationswas updated.|2-118|
||The notes inTable 2-72 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V<br>Input Tolerance Capabilitieswere updated.|2-144|
||The"Simultaneously Switching Outputs and PCB Layout" sectionis new.|2-149|
||LVPECL and LVDS were updated inTable 2-81 • Fusion Standard and Advanced I/O<br>Attributes vs. I/O Standard Applications.<br>~~ee~~|2-157<br>~~ee~~|
||LVPECL and LVDS were updated inTable 2-82 • Fusion Pro I/O Attributes vs. I/O<br>Standard Applications.|2-158|
||The"Timing Model"was updated.|2-161|
||All voltage-referenced Minimum and Maximum DC Input and Output Level tables<br>were updated.<br>~~ee~~|N/A<br>~~ee~~|
||All Timing Characteristic tables were updated|N/A|
||Table 2-83 • Summary of Maximum and Minimum DC Input and Output Levels<br>Applicable to Commercial and Industrial Conditionswas updated.|2-165|
||Table 2-79 • Summary of I/O Timing Characteristics – Software Default Settings<br>was updated.|2-134|
||Table 2-93 • I/O Output Buffer Maximum Resistances 1was updated.|2-171|
||The"BLVDS/M-LVDS" sectionis new. BLVDS and M-LVDS are two new I/O<br>standards included in the datasheet.<br>~~ee~~|2-211<br>~~ee~~|
||The"CoreMP7 and Cortex-M1 Software Tools" sectionis new.|2-257|
||Table 2-83 • Summary of Maximum and Minimum DC Input and Output Levels<br>Applicable to Commercial and Industrial Conditionswas updated.|2-165|
||Table 2-79 • Summary of I/O Timing Characteristics – Software Default Settings<br>was updated.|2-134|
||Table 2-93 • I/O Output Buffer Maximum Resistances 1was updated.|2-171|
||The"BLVDS/M-LVDS" sectionis new. BLVDS and M-LVDS are two new I/O<br>standards included in the datasheet.<br>~~ee~~|2-211<br>~~ee~~|
||The"108-Pin QFN" tablefor the AFS090 device is new.<br>~~ee~~|3-2<br>~~ee~~|
||The"180-Pin QFN" tablefor the AFS090 device is new.|3-4|
||The"208-Pin PQFP" tablefor the AFS090 device is new.|3-8|
||The"256-Pin FBGA" tablefor the AFS090 device is new.|3-12|
||The"256-Pin FBGA" tablefor the AFS250 device is new.|3-12|
**5-17**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
## **Datasheet Categories**
## _**Categories**_
In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "Fusion Device Status" table, is designated as either “Product Brief,” “Advance,” “Preliminary,” or “Production.” The definitions of these categories are as follows:
## _**Product Brief**_
The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information.
## _**Advance**_
This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.
## _**Preliminary**_
The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
## _**Production**_
This version contains information that is considered to be final.
## **Export Administration Regulations (EAR)**
The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
## **Safety Critical, Life Support, and High-Reliability Applications Policy**
The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information.
**Revision 8**
**5-18**
_Datasheet Information_
**5-19**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
**Revision 8**
**5-20**
_Datasheet Information_
**5-21**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
**Revision 8**
**5-22**
_Datasheet Information_
**5-23**
**Revision 8**
_Fusion Family of Mixed Signal FPGAs_
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Microsemi Corporation (MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet Solutions; Power-overEthernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 4,800 employees globally. Learn more at **www.microsemi.com** .
## **Microsemi Corporate Headquarters**
One Enterprise, Aliso Viejo, CA 92656 USA
**Within the USA** : +1 (800) 713-4113 **Outside the USA** : +1 (949) 380-6100 **Sales** : +1 (949) 380-6136 **Fax** : +1 (949) 215-4996
**E-mail: sales.support@microsemi.com**
© 2018 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.
51700092-8/05.18
Updated at June 9, 2026
Microchip Technology Inc. is a leading global provider of smart, connected, and secure embedded control solutions. Known for enabling engineers to design with confidence, the company delivers a comprehensive product portfolio that reduces total system costs and accelerates time to market across the industrial, automotive, communications, and computing sectors. Our extensive selection of Microchip components highlights the manufacturer's strength in both discrete semiconductors and advanced wireless connectivity. We carry a robust lineup of highly efficient single MOSFETs and Schottky diodes tailored for demanding power management and switching applications. Alongside these essential discretes, engineers can source a wide array of ready-to-use networking modules, prominently featuring Bluetooth and WLAN adapters that streamline the development of modern IoT and connected devices. Rounding out the offering is a diverse range of Microchip integrated circuits and specialized components. This includes versatile I/O expanders for simplified system integration, precision timing solutions such as MEMS oscillators and pulse generators, as well as AC/DC LED driver ICs and sub-2.4GHz RF transceivers. Backed by Microchip's renowned commitment to exceptional quality and reliable performance, these components provide scalable, dependable building blocks for complex electronic designs.
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