A3P250-VQG100
FPGA, PLL, ProASIC3, 68 I/O's, 350 MHz, 2048 Cells, 1.425 V to 1.575 V, VQFP-100
- Manufacturer: MICROCHIP
- Product type: FPGAs
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (04-Feb-2026)
- FPGA Type: Flash based FPGA
- FPGA Family: ProASIC3
- IC Mounting: Surface Mount
- No. of Pins: 100Pins
- Speed Grade: -
- No. of I/O's: 68I/O's
- Product Range: ProASIC3 A3P250
- Qualification: -
- Total RAM Bits: 36Kbit
- No.of User I/Os: 68I/O's
- Clock Management: PLL
- Logic Case Style: VQFP
- IC Case / Package: VQFP
- No. of Macrocells: 2048Macrocells
- I/O Supply Voltage: 3.3V
- No. of Logic Cells: 2048Logic Cells
- Process Technology: 130nm (CMOS)
- No. of Logic Blocks: 2048
- Core Supply Voltage Max: 1.575V
- Core Supply Voltage Min: 1.425V
- Operating Frequency Max: 350MHz
- Operating Temperature Max: 85°C
- Operating Temperature Min: 0°C
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 12.71 € |
| Current stock | 100+ |
| Lead time | 30 days |
**Revision 18 DS0097**
## **ProASIC3 Flash Family FPGAs with Optional Soft ARM Support**
## **Features and Benefits**
## **Advanced I/O**
- 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
## **High Capacity**
- 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
- 15 K to 1 M System Gates
- Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
- Up to 144 Kbits of True Dual-Port SRAM
- Up to 300 User I/Os
- Bank-Selectable I/O Voltages—up to 4 Banks per Chip
- Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X[†] and LVCMOS 2.5 V / 5.0 V Input
## **Reprogrammable Flash Technology**
- 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
- Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
- Instant On Level 0 Support
- Single-Chip Solution
- I/O Registers on Input, Output, and Enable Paths
- • Hot-Swappable and Cold Sparing I/Os[‡]
- Retains Programmed Design when Powered Off
## **High Performance**
- Programmable Output Slew Rate[†] and Drive Strength
- 350 MHz System Performance
- Weak Pull-Up/-Down
- 3.3 V, 66 MHz 64-Bit PCI[†]
- IEEE 1149.1 (JTAG) Boundary Scan Test
- • Pin-Compatible Packages across the ProASIC3 Family
## **In-System Programming (ISP) and Security**
## **Clock Conditioning Circuit (CCC) and PLL[†]**
- ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM[®] -enabled ProASIC[®] 3 devices) via JTAG (IEEE 1532–compliant)[†]
- Six CCC Blocks, One with an Integrated PLL
- Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
- FlashLock[®] to Secure FPGA Contents
## **Low Power**
- Wide Input Frequency Range (1.5 MHz to 350 MHz)
## **Embedded Memory**[†]
- Core Voltage for Low Power
- Support for 1.5 V-Only Systems
- 1 Kbit of FlashROM User Nonvolatile Memory
- Low-Impedance Flash Switches
- SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)[†]
## **High-Performance Routing Hierarchy**
- Segmented, Hierarchical Routing and Clock Structure
- True Dual-Port SRAM (except ×18)
## **ARM Processor Support in ProASIC3 FPGAs**
|**ProASIC3 Devices**<br>~~**2**~~<br>~~GN~~<br>~~a~~|**A3P015**~~**1**~~<br>~~GN~~<br>~~ny~~|**A3P030**<br>~~GN~~<br>~~ny~~|**A3P060**<br>~~GN~~<br>~~UNO~~|**A3P125**<br>~~GN~~<br>~~GO~~<br>~~(N(R~~|**A3P250**<br>~~GN~~<br>~~GO~~<br>~~(N(R~~|**A3P400**<br>~~GN~~<br>~~GO~~<br>~~a~~|**A3P600**<br>~~GN~~<br>~~GO~~|**A3P1000**<br>~~GN~~|
|---|---|---|---|---|---|---|---|---|
|**Cortex-M1 Devices **~~**2**~~<br>~~a~~|~~ny~~|~~ny~~|~~UNO~~|~~GO~~<br>~~(N(R~~<br>~~GO~~|**M1A3P250**<br>~~GO~~<br>~~(N(R~~<br>~~GO~~|**M1A3P400**<br>~~GO~~<br>~~a~~<br>~~GO~~|**M1A3P600**<br>~~GO~~<br>~~GO~~|**M1A3P1000**|
|**System Gates**<br>~~GN~~|15,000<br>~~ny~~<br>~~GN~~|30,000<br>~~ny ~~<br>~~GN~~|60,000<br> ~~UNO ~~<br>~~GN~~<br>~~I~~|125,000<br> ~~(N(R~~<br>~~GN~~<br>~~GO~~|250,000<br>~~(N(R ~~<br>~~GN~~<br>~~GO~~<br>~~OO~~|400,000<br> ~~a~~<br>~~GN~~<br>~~GO~~<br>~~OO~~|600,000<br>~~GN~~<br>~~GO~~<br>~~OO~~|1,000,000<br>~~GN~~|
|Typical Equivalent Macrocells<br>~~GO~~|128<br>~~GO~~|256<br>~~GO~~|512<br>~~GO~~<br>~~I~~<br>~~I~~|1,024<br>~~GO~~<br>~~GO~~|2,048<br>~~GO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|–<br>~~GO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|–<br>~~GO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|–<br>~~GO~~|
|**VersaTiles (D-flip-flops)**<br>~~GO~~|384<br>~~GO~~|768<br>~~GO~~|1,536<br>~~I~~<br>~~GO~~<br>~~I~~<br>~~I~~|3,072<br>~~GO~~|6,144<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|9,216<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|13,824<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|24,576<br>~~GO~~|
|**RAM Kbits (1,024 bits)**<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|18<br>~~I~~<br>~~GO~~<br>~~I~~|36<br>~~GO~~<br>~~OO~~|36<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|54<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|108<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|144<br>~~GO~~|
|**4,608-Bit Blocks**<br>~~sO~~|–<br>~~sO~~|–<br>~~sO~~|4<br>~~I~~<br>~~sO~~|8<br>~~sO~~<br>~~OO~~|8<br>~~OO~~<br>~~sO~~<br>~~OO~~<br>~~CO~~|12<br>~~OO~~<br>~~sO~~<br>~~OO~~<br>~~CO~~|24<br>~~OO~~<br>~~sO~~<br>~~OO~~<br>~~CO~~|32<br>~~sO~~|
|**FlashROM Kbits**<br>~~**3**~~<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|1<br>~~OO~~<br>~~eG~~|1<br>~~OO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|1<br>~~OO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|1<br>~~OO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|1<br>~~eG~~|
|**Secure (AES) ISP **~~**3**~~<br>~~eG~~|–<br>~~eG~~|–<br>~~eG~~|Yes<br>~~eG~~|Yes<br>~~eG~~<br>~~GO~~|Yes<br>~~CO~~<br>~~eG~~<br>~~CO~~<br>~~GO~~|Yes<br>~~CO~~<br>~~eG~~<br>~~CO~~<br>~~GO~~|Yes<br>~~CO~~<br>~~eG~~<br>~~CO~~<br>~~GO~~|Yes<br>~~eG~~|
|**Integrated PLL in CCCs**<br>~~**4**~~<br>~~OG~~|–<br>~~OG~~|–<br>~~OG~~|1<br>~~OG~~|1<br>~~OG~~<br>~~GO~~|1<br>~~CO~~<br>~~OG~~<br>~~GO~~<br>~~OO~~|1<br>~~CO~~<br>~~OG~~<br>~~GO~~<br>~~OO~~|1<br>~~CO~~<br>~~OG~~<br>~~GO~~<br>~~OO~~|1<br>~~OG~~|
|**VersaNet Globals **~~**4**~~<br>~~eG~~|6<br>~~eG~~|6<br>~~eG~~|18<br>~~eG~~|18<br>~~GO~~<br>~~eG~~|18<br>~~GO~~<br>~~eG~~<br>~~OO~~<br>~~CO~~|18<br>~~GO~~<br>~~eG~~<br>~~OO~~<br>~~CO~~|18<br>~~GO~~<br>~~eG~~<br>~~OO~~<br>~~CO~~|18<br>~~eG~~|
|**I/O Banks**<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|4<br>~~OO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|4<br>~~OO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|4<br>~~OO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|4<br>~~eG~~|
|**Maximum User I/Os**<br>~~eG~~|49<br>~~eG~~|81<br>~~eG~~|96<br>~~eG~~|133<br>~~eG~~|157<br>~~CO~~<br>~~eG~~<br>~~CO~~|194<br>~~CO~~<br>~~eG~~<br>~~CO~~|235<br>~~CO~~<br>~~eG~~<br>~~CO~~|300<br>~~eG~~|
_Notes:_
_1. A3P015 is not recommended for new designs._
_2. Refer to the Cortex-M1 product brief for more information._
_3. AES is not available for Cortex-M1 ProASIC3 devices._
_4. Six chip (main) and three quadrant global networks are available for A3P060 and above._
_5. The M1A3P250 device does not support this package._
_6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet._
_7. Package not available._
_† A3P015 and A3P030 devices do not support this feature._
_‡ Supported only by A3P015 and A3P030 devices._
**March 2016** © 2016 Microsemi Corporation
**I**
_ProASIC3 Flash Family FPGAs_
||~~**1**~~||||||||
|---|---|---|---|---|---|---|---|---|
|**ProASIC3 Devices**<br>~~**2**~~|**A3P015**~~**1**~~|**A3P030**|**A3P060**|**A3P125**|**A3P250**|**A3P400**|**A3P600**|**A3P1000**|
|**Cortex-M1 Devices **~~**2**~~|||||**M1A3P250**|**M1A3P400**|**M1A3P600**|**M1A3P1000**|
|**Package Pins**<br>QFN<br>CS<br>VQFP<br>TQFP<br>PQFP<br>FBGA|QN68|QN48, QN68,<br>QN1327<br>VQ100|QN1327<br>CS121<br>VQ100<br>TQ144<br>FG144|QN1327<br>VQ100<br>TQ144<br>PQ208<br>FG144|QN1327<br>VQ100<br>PQ208<br>FG144/256 5|PQ208<br>FG144/256/<br>484|PQ208<br>FG144/256/<br>484|PQ208<br>FG144/256/<br>484|
_Notes:_
_1. A3P015 is not recommended for new designs._
_2. Refer to the Cortex-M1 product brief for more information._
_3. AES is not available for Cortex-M1 ProASIC3 devices._
_4. Six chip (main) and three quadrant global networks are available for A3P060 and above._
_5. The M1A3P250 device does not support this package._
_6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet._
_7. Package not available._
**Revision 18**
**II**
_ProASIC3 Flash Family FPGAs_
## **[1] I/Os Per Package**
|**ProASIC3**<br>**Devices**|**A3P0152**|**A3P030**|**A3P060**|**A3P125**|**A3P250 3**|**A3P250 3**|**A3P400 3**|**A3P400 3**|**A3P600**|**A3P600**|**A3P1000**|**A3P1000**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Cortex-M1**<br>**Devices**|||||**M1A3P250 3,5**||**M1A3P400 3**||**M1A3P600**||**M1A3P1000**||
|**Package**<br>~~es~~|**I/O Type**||||||||||||
||**Single-Ended I/O**<br>~~rs~~|**Single-Ended I/O**<br>~~rs~~|**Single-Ended I/O**<br>~~res~~|**Single-Ended I/O**<br>~~rs~~|**Single-Ended I/O4**<br>~~rd~~|**Differential I/O Pairs**<br>~~ne~~|**Single-Ended I/O4**<br>~~rs~~|**Differential I/O Pairs**<br>~~(Os~~|**Single-Ended I/O4**<br>~~Gs~~|**Differential I/O Pairs**|**Single-Ended I/O4**|**Differential I/O Pairs**|
|QN48<br>~~es~~<br>~~ee~~|–<br>~~rs~~<br>~~ee~~|34<br>~~rs~~<br>~~rs~~|–<br>~~res~~<br>~~rs~~|–<br>~~rs~~<br>~~(rs~~|–<br>~~rd~~<br>~~(Os~~|–<br>~~ne~~<br>~~(Os~~|~~rs~~<br>~~(Os~~|–<br>~~(Os~~<br>~~(Os~~|–<br>~~Gs~~|–|–|–|
|QN68<br>~~es ~~<br>~~ee~~<br>~~PT~~|49<br> ~~rs ~~<br>~~ee~~<br>~~PT~~|49<br> ~~rs~~<br>~~rs~~|–<br>~~res ~~<br>~~rs~~<br>~~ee~~|–<br> ~~rs ~~<br>~~(rs~~<br>~~(re~~|–<br> ~~rd ~~<br>~~(Os~~<br>~~ree~~|–<br> ~~ne~~<br>~~(Os~~<br>~~ree~~|–<br>~~rs ~~<br>~~(Os~~<br>~~rs~~|–<br> ~~(Os~~<br>~~(Os~~<br>~~Qs~~|~~Gs~~<br>~~Qs~~|–|–|–|
|QN1327<br>~~ee~~<br>~~es~~<br>~~PT~~|–<br>~~ee~~<br>~~es~~<br>~~PT~~|81<br>~~rs~~<br>~~es~~|80<br>~~rs~~<br>~~es~~<br>~~ee~~|84<br>~~(rs ~~<br>~~es~~<br>~~(re~~|87<br> ~~(Os~~<br>~~es~~<br>~~ree~~|19<br>~~(Os~~<br>~~es~~<br>~~ree~~|–<br>~~(Os~~<br>~~es~~<br>~~rs~~|–<br>~~(Os~~<br>~~es~~<br>~~Qs~~|~~es~~<br>~~Qs~~|–<br>~~es~~|–<br>~~es~~|–<br>~~es~~|
|CS121<br>~~PT~~<br>~~PT~~|–<br>~~PT~~<br>~~PT~~|–<br>~~ee~~|96<br>~~ee~~<br>~~ee~~|–<br>~~(re~~|–<br>~~ree~~|–<br>~~ree~~|–<br>~~rs~~|–<br>~~Qs~~|–<br>~~Qs~~|–|–|–|
|VQ100<br>~~PT~~|–<br>~~PT~~|77<br>~~ee~~|71<br>~~ee~~|71|68|13|–|–||–|–|–|
|TQ144<br>~~PT~~<br>~~PT~~<br>~~es~~|–<br>~~PT~~<br>~~PT~~<br>~~rs~~|–<br>~~ee~~<br>~~rs~~|91<br>~~ee~~<br>~~res~~|100<br>~~rs~~|–<br>~~rd~~|–<br>~~ne~~|–<br>~~rs~~|–<br>~~(Os~~|–<br>~~Gs~~|–|–|–|
|PQ208<br>~~PT~~<br>~~es~~<br>~~ee~~|–<br>~~PT~~<br>~~rs~~<br>~~ee~~|–<br>~~rs~~<br>~~rs~~|–<br>~~res~~<br>~~rs~~|133<br>~~rs~~<br>~~(rs~~|151<br>~~rd~~<br>~~(Os~~|34<br>~~ne~~<br>~~(Os~~|151<br>~~rs~~<br>~~(Os~~|34<br>~~(Os~~<br>~~(Os~~|154<br>~~Gs~~|35|154|35|
|FG144<br>~~es ~~<br>~~ee~~<br>~~PTE~~|–<br> ~~rs ~~<br>~~ee~~<br>~~PTE~~|–<br> ~~rs~~<br>~~rs~~<br>~~PTE~~|96<br>~~res ~~<br>~~rs~~<br>~~ee~~|97<br> ~~rs ~~<br>~~(rs~~<br>~~(re~~|97<br> ~~rd ~~<br>~~(Os~~<br>~~ree~~|24<br> ~~ne~~<br>~~(Os~~<br>~~ree~~|97<br>~~rs ~~<br>~~(Os~~<br>~~rs~~|25<br> ~~(Os~~<br>~~(Os~~<br>~~Qs~~|97<br>~~Gs~~<br>~~Qs~~|25|97|25|
|FG2565,6<br>~~ee~~<br>~~es~~<br>~~PTE~~|–<br>~~ee~~<br>~~es~~<br>~~PTE~~|–<br>~~rs~~<br>~~es~~<br>~~PTE~~|–<br>~~rs~~<br>~~es~~<br>~~ee~~|–<br>~~(rs ~~<br>~~es~~<br>~~(re~~|157<br> ~~(Os~~<br>~~es~~<br>~~ree~~|38<br>~~(Os~~<br>~~es~~<br>~~ree~~|178<br>~~(Os~~<br>~~es~~<br>~~rs~~|38<br>~~(Os~~<br>~~es~~<br>~~Qs~~|177<br>~~es~~<br>~~Qs~~|43<br>~~es~~|177<br>~~es~~|44<br>~~es~~|
|FG4846<br>~~PTE~~|–<br>~~PTE~~|–<br>~~PTE~~|–<br>~~ee~~|–<br>~~(re~~|–<br>~~ree~~|–<br>~~ree~~|194<br>~~rs~~|38<br>~~Qs~~|235<br>~~Qs~~|60|300|74|
|_Notes:_<br>_1. When considering migrating your design to a lower- or higher-density device, refer to theProASIC3 FPGA Fabric User Guide_ _to_<br>_ensure complying with design and board migration requirements._<br>_2. A3P015 is not recommended for new designs._<br>_3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to_<br>_theProASIC3 FPGA Fabric Users Guide_ _for position assignments of the 15 LVPECL pairs._<br>_4. Each used differential I/O pair reduces the number of single-ended I/Os available by two._<br>_5. The M1A3P250 device does not support FG256 package._<br>_6. FG256 and FG484 are footprint-compatible packages._<br>_7. Package not available._<br>~~ee(re ree~~<br>~~rsQs~~<br>~~PTE~~|||||||||||||
_Notes:_
_1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User Guide to ensure complying with design and board migration requirements._
_2. A3P015 is not recommended for new designs._
_3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to the ProASIC3 FPGA Fabric Users Guide for position assignments of the 15 LVPECL pairs._
_4. Each used differential I/O pair reduces the number of single-ended I/Os available by two._
_5. The M1A3P250 device does not support FG256 package._
_6. FG256 and FG484 are footprint-compatible packages._
_7. Package not available._
**Table 1 • ProASIC3 FPGAs Package Sizes Dimensions**
|**Package**<br>~~fT~~|**CS121**<br>~~fT~~<br>~~|~~|**QN48**|**QN68**|**QN132** *****|**VQ100**|**TQ144**|**PQ208**|**FG144**|**FG256**|**FG484**|
|---|---|---|---|---|---|---|---|---|---|---|
|Length × Width<br>(mm × mm)<br>~~fT~~|6 × 6<br>~~fT~~<br>~~|~~|6 × 6|8 × 8|8 × 8|14 × 14|20 × 20|28 × 28|13 × 13|17 × 17|23 × 23|
|Nominal Area<br>(mm2)<br>~~fT~~<br>~~ee~~|36<br>~~fT~~<br>~~|~~<br>~~ee~~|36<br>~~rs~~|64<br>~~res~~|64<br>~~es~~|196<br>~~Gees~~|400<br>~~Gees~~|784<br>~~Gees~~|169|289|529|
|Pitch (mm)<br>~~ee~~<br>~~ee~~|0.5<br>~~ee~~<br>~~ee~~|0.4<br>~~rs~~<br>~~es~~|0.4<br>~~res~~<br>~~rs~~|0.5<br>~~es~~<br>~~rs~~|0.5<br>~~Gees~~<br>~~rs es~~|0.5<br>~~Gees~~<br>~~es~~|0.5<br>~~Gees~~<br>~~Oe~~|1.0|1.0|1.0|
|Height (mm)<br>~~ee~~<br>~~ee~~|0.99<br>~~ee~~<br>~~ee~~|0.90<br>~~rs ~~<br>~~es~~|0.90<br> ~~res ~~<br>~~rs~~|0.75<br> ~~es~~<br>~~rs~~|1.00<br>~~Gees~~<br>~~rs es~~|1.40<br>~~Gees~~<br>~~es~~|3.40<br>~~Gees~~<br>~~Oe~~|1.45|1.60|2.23|
_Note: * Package not available_
**Revision 18**
**III**
_ProASIC3 Flash Family FPGAs_
## **ProASIC3 Ordering Information**
**==> picture [473 x 316] intentionally omitted <==**
**----- Start of picture text -----**<br>
A3P1000 _ 1 FG G 144 I Y<br>Security Feature<br>Y = Device Includes License to Implement IP Based on the<br>Cryptography Research, Inc. (CRI) Patent Portfolio<br>Blank = Device Does Not Include License to Implement IP Based<br>on the Cryptography Research, Inc. (CRI) Patent Portfolio<br>Note: Only devices with packages greater than or equal to 5x5 are supported<br>Application (Temperature Range)<br>Blank = Commercial (0°C to +85°C Junction Temperature)<br>I = Industrial (–40°C to +100°C Junction Temperature)<br>PP= Pre-Production<br>ES= Engineering Sample (Room Temperature Only)<br>Package Lead Count<br>Lead-Free Packaging<br>Blank = Standard Packaging<br>G= RoHS-Compliant (Green) Packaging (some packages also halogen-free)<br>Package Type<br>QN [=] Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)<br>VQ [=] Very Thin Quad Flat Pack (0.5 mm pitch)<br>TQ [=] Thin Quad Flat Pack (0.5 mm pitch)<br>PQ [=] Plastic Quad Flat Pack (0.5 mm pitch)<br>FG [=] Fine Pitch Ball Grid Array (1.0 mm pitch)<br>Speed Grade CS [=] Chip Scale Package (0.5 mm pitch)<br>Blank = Standard<br>1 = 15% Faster than Standard<br>Part Number 2 = 25% Faster than Standard<br>ProASIC3 Devices<br>A3P015 = 15,000 System Gates (A3P015 is not recommended for new designs.)<br>A3P030 = 30,000 System Gates<br>A3P060 = 60,000 System Gates<br>A3P125 = 125,000 System Gates<br>A3P250 = 250,000 System Gates<br>A3P400 = 400,000 System Gates<br>A3P600 = 600,000 System Gates<br>A3P1000 = 1,000,000 System Gates<br>**----- End of picture text -----**<br>
## **ProASIC3 Devices with Cortex-M1**
M1A3P250 = 250,000 System Gates M1A3P400 = 400,000 System Gates M1A3P600 = 600,000 System Gates M1A3P1000 = 1,000,000 System Gates
## **ProASIC3 Device Status**
|**ProASIC3 Devices**|**Status**|**Cortex-M1 Devices**|**Status**|
|---|---|---|---|
|A3P015|Not recommended for new designs.|||
|A3P030|Production|||
|A3P060|Production|||
|A3P125|Production|||
|A3P250|Production|M1A3P250|Production|
|A3P400|Production|M1A3P400|Production|
|A3P600|Production|M1A3P600|Production|
|A3P1000|Production|M1A3P1000|Production|
**Revision 18**
**IV**
_ProASIC3 Flash Family FPGAs_
## ProASIC3 Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ProASIC3 DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108
Pin Descriptions Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Package Pin Assignments QN48 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 QN68 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 QN132 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CS121 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 VQ100 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 TQ144 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 PQ208 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 FG144 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 FG256 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 FG484 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
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## **1 – ProASIC3 Device Family Overview**
## **General Description**
ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those of the ProASI ~~C~~[PLUS] ® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption.
## **Flash Advantages**
## _**Reduced Cost of Ownership**_
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based ProASIC3 devices allow all functionality to be Instant On; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/ communications, computing, and avionics markets.
## _**Security**_
The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves.
ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams are always encrypted. There is no user access to encryption for the FlashROM programming data.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks.
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Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3 device provides the best available security for programmable logic designs.
## _**Single Chip**_
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system powerup (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability.
## _**Instant On**_
Flash-based ProASIC3 devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The Instant On feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time.
## _**Firm Errors**_
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
## _**Low Power**_
Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3 devices also have low dynamic power consumption to further maximize power savings.
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_ProASIC3 Device Family Overview_
## **Advanced Flash Technology**
The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced flashbased, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy.
## **Advanced Architecture**
The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and Figure 1-2 on page 1-4):
- FPGA VersaTiles
- Dedicated FlashROM
- Dedicated SRAM/FIFO memory[†]
- Extensive CCCs and PLLs[†]
- Advanced I/O structure
**==> picture [435 x 232] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bank 0<br>“Ty CECE CECECEC E CE CE CELEL EL EL E LE L E L ELLEELIE CCC<br>— | | [| || a<br>RAM Block<br>4,608-Bit Dual-Port<br>SRAM or FIFO Block*<br>SEEeEeESEe<br>I/Os<br>VersaTile<br>ISP AES User Nonvolatile<br>Charge Pumps<br>Decryption* FlashROM<br>Bank 1<br>Bank 1 Bank 0<br>Bank 1 Bank 0<br>**----- End of picture text -----**<br>
_Note: *Not supported by A3P015 and A3P030 devices_
_**Figure 1-1 •**_ **ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and A3P125)**
> _† The A3P015 and A3P030 do not support PLL or SRAM._
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**==> picture [446 x 259] intentionally omitted <==**
**----- Start of picture text -----**<br>
“poo o o o ooo o o Bank 0 o oo ooo o o oo o o o o oooool CCC<br>— | | || | | a RAM Block<br>4,608-Bit Dual-Port<br>SRAM or FIFO Block<br>spate eneatn el<br>I/Os<br>VersaTile<br>| | | | | | A | | | RAM Block<br>4,608-Bit Dual-Port<br>ISP AES User Nonvolatile<br>Charge Pumps SRAM or FIFO Block<br>Decryption FlashROM<br>(A3P600 and A3P1000)<br>[s saaosasncncncsusasasncncsuscsusacncncacaaaa[y Bank 2 ]<br>Bank 3 Bank 1<br>Bank 3 Bank 1<br>**----- End of picture text -----**<br>
_**Figure 1-2 •**_ **ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)**
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D- flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Microsemi ProASIC family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design.
## _**VersaTiles**_
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC[PLUS] ® core tiles. The ProASIC3 VersaTile supports the following:
- All 3-input logic functions—LUT-3 equivalent
- Latch with clear or set
- D-flip-flop with clear or set
- Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
**==> picture [464 x 87] intentionally omitted <==**
**----- Start of picture text -----**<br>
LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set<br>Data Y<br>X1 Data Y<br>X2 LUT-3 Y CLK D-FF CLK D-FF<br>X3 CLR<br>Enable<br>CLR<br>**----- End of picture text -----**<br>
_**Figure 1-3 •**_ **VersaTile Configurations**
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_ProASIC3 Device Family Overview_
## _**User Nonvolatile FlashROM**_
ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications:
- Internet protocol addressing (wireless or fixed)
- System calibration settings
- Device serialization and/or inventory control
- Subscription-based business models (for example, set-top boxes)
- Secure key storage for secure communications algorithms
- Asset management/tracking
- Date stamping
- Version management
The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in security keys stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte.
The ProASIC3 development software solutions, Libero[®] System-on-Chip (SoC) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
## _**SRAM and FIFO**_
ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015 and A3P030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
## _**PLL and CCC**_
ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not have a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block.
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The CCC block has these key features:
- Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
- Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
- Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
- 2 programmable delay types for clock skew minimization
- Clock frequency synthesis (for PLL only)
Additional CCC specifications:
- Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only).
- Output duty cycle = 50% ± 1.5% or better (for PLL only)
- Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only)
- Maximum acquisition time = 300 µs (for PLL only)
- Low power consumption of 5 mW
- Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)
- Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz / fOUT_CCC) (for PLL only)
## _**Global Clocking**_
ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets.
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_ProASIC3 Device Family Overview_
## _**I/Os with Advanced I/O Standards**_
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1).
_**Table 1-1 •**_ **I/O Standards Supported**
|**I/O Bank Type**|**Device and Bank Location**|**I/O Standards Supported**|**I/O Standards Supported**|**I/O Standards Supported**|
|---|---|---|---|---|
|||**LVTTL/**<br>**LVCMOS**|**PCI/PCI-X**|**LVPECL, LVDS,**<br>**B-LVDS, M-LVDS**|
|Advanced|East and west Banks of A3P250 and<br>larger devices||||
|Standard Plus|North and south banks of A3P250 and<br>larger devices<br>All banks of A3P060 and A3P125|||Not supported|
|Standard|All banks of A3P015 and A3P030||Not<br>supported|Not supported|
Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following:
- Single-Data-Rate applications
- Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS. B-LVDS and M- LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a poweredup system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating.
## _**Wide Range I/O Support**_
ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications.
## **Specifying I/O States During Programming**
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the _FlashPro User’s Guide_ for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-4 on page 1-8).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High
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- 0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming
Z -Tristate: I/O is tristated
_**Figure 1-4 •**_ **I/O States During Programming Window**
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation.
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## **2 – ProASIC3 DC and Switching Characteristics**
## **General Specifications**
## **Operating Conditions**
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied.
_**Table 2-1 •**_ **Absolute Maximum Ratings**
|**Symbol**|**Parameter**|**Limits**|**Units**|
|---|---|---|---|
|VCC|DC core supply voltage|–0.3 to 1.65|V|
|VJTAG|JTAG DC voltage|–0.3 to 3.75|V|
|VPUMP|Programming voltage|–0.3 to 3.75|V|
|VCCPLL|Analog power supply (PLL)|–0.3 to 1.65|V|
|VCCI|DC I/O output buffer supply voltage|–0.3 to 3.75|V|
|VMV|DC I/O input buffer supply voltage|–0.3 to 3.75|V|
|VI|I/O input voltage|–0.3 V to 3.6 V<br>(when I/O hot insertion mode is enabled)<br>–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower<br>(when I/O hot-insertion mode is disabled)|V|
|TSTG<br>2|Storage temperature|–65 to +150|°C|
|TJ<br>2|Junction temperature|+125|°C|
_Notes:_
_1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3._
_2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information._
_3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating limits, refer to Table 2-2 on page 2-2._
**Revision 18**
**2-1**
_ProASIC3 Flash Family FPGAs_
_**Table 2-2 •**_ **Recommended Operating Conditions[1]**
|**Symbol**<br>~~es~~|**Parameters** 1<br>~~es~~|**Parameters** 1<br>~~es~~|**Commercial**<br>~~es~~|**Industrial**<br>~~es~~|**Units**<br>~~es~~|
|---|---|---|---|---|---|
|TJ<br>~~es~~<br>~~a ~~<br>~~es~~|Junction temperature<br>~~es~~<br> ~~es~~||0 to 852<br>~~es~~<br>~~es~~|-40 to 1002<br>~~es~~<br>~~es~~|°C<br>~~es~~<br>~~es~~|
|VCC3<br>~~es~~|1.5 V DC core supply voltage||1.425 to 1.575|1.425 to 1.575|V|
|VJTAG<br>~~es~~<br>~~a ~~<br>~~EEE~~|JTAG DC voltage<br> ~~es~~<br>~~EEE~~||1.4 to 3.6<br>~~es~~<br>~~EEE~~|1.4 to 3.6<br>~~es~~<br>~~EEE~~|V<br>~~es~~<br>~~EEE~~|
|VPUMP<br>~~EEE~~<br>~~es~~|Programming voltage<br>~~EEE~~<br>|Programming Mode<br>~~EEE~~<br>|3.15 to 3.45<br>~~EEE~~<br>~~es~~<br>|3.15 to 3.45<br>~~EEE~~<br>|V<br>~~EEE~~<br>|
|||Operation 4<br>~~EEE~~<br>~~es~~<br>|0 to 3.6<br>~~EEE~~<br>~~es~~<br>~~es~~<br>|0 to 3.6<br>~~EEE~~<br>~~es~~<br>|V<br>~~EEE~~<br>~~es~~<br>|
|VCCPLL<br>~~EEE~~<br>~~es~~|Analog power supply (PLL)<br>~~EEE~~<br>~~es~~||1.425 to 1.575<br>~~EEE~~<br>~~es~~<br>~~es~~<br>~~es~~|1.425 to 1.575<br>~~EEE~~<br>~~es~~|V<br>~~EEE~~<br>~~es~~|
|VCCI and VMV 5 <br>~~es~~|1.5 V DC supply voltage<br><br>~~es~~||1.425 to 1.575<br>~~es~~<br><br>~~es~~<br>~~es~~<br>~~es~~|1.425 to 1.575<br><br>~~es~~|V<br><br>~~es~~|
||1.8 V DC supply voltage<br>~~es~~||1.7 to 1.9<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|1.7 to 1.9<br>~~es~~|V<br>~~es~~|
||2.5 V DC supply voltage<br>~~es~~||2.3 to 2.7<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|2.3 to 2.7<br>~~es~~|V<br>~~es~~|
||3.3 V DC supply voltage<br>~~es~~||3.0 to 3.6<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|3.0 to 3.6<br>~~es~~|V<br>~~es~~|
||3.3 V wide range DC supply voltage 6<br>~~es~~||2.7 to 3.6<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|2.7 to 3.6<br>~~es~~|V<br>~~es~~|
||LVDS/B-LVDS/M-LVDS differential I/O<br>~~es~~||2.375 to 2.625<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|2.375 to 2.625<br>~~es~~|V<br>~~es~~|
||LVPECL differential I/O<br>~~es~~||3.0 to 3.6<br>~~es~~<br>~~es~~<br>~~es~~|3.0 to 3.6<br>~~es~~|V<br>~~es~~|
_Notes:_
_1. All parameters representing voltages are measured with respect to GND unless otherwise specified._
_2. Software Default Junction Temperature Range in the Libero[®] System-on-Chip (SoC) software is set to 0°C to +70°C for commercial, and -40°C to +85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures, Microsemi recommends using custom settings for temperature range before running timing and power analysis tools. For more information regarding custom settings, refer to the New Project Dialog Box in the Libero SoC Online Help._
_3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-18 on page 2-19._
_4. VPUMP can be left floating during operation (not programming mode)._
_5. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information._
_6. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation._
**Revision 18**
**2-2**
_ProASIC3 DC and Switching Characteristics_
**==> picture [442 x 217] intentionally omitted <==**
**----- Start of picture text -----**<br>
110<br>HTR<br>Lifetime 100<br>Tj (°C) (yrs)<br>90<br>70 102.7<br>85 43.8 80<br>100 20.0 70<br>105 15.6 60<br>110 12.3<br>50<br>115 9.7<br>120 7.7 40<br>125 6.2 30<br>130 5.0 20<br>135 4.0<br>10<br>140 3.3<br>145 2.7 0<br>150 2.2 70 85 100 105 110 115 120 125 130 135 140 145 150<br>Temperature (ºC)<br>Years<br>**----- End of picture text -----**<br>
_Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage._
_**Figure 2-1 •**_ **High-Temperature Data Retention (HTR)**
_**Table 2-3 •**_ **Flash Programming Limits – Retention, Storage and Operating Temperature[1]**
|**Product**<br>**Grade**|**Programming**<br>**Cycles**|**Program Retention**<br>**(biased/unbiased)**|**Maximum Storage**<br>**Temperature TSTG (°C)**|**Maximum Operating**<br>**Junction Temperature TJ (°C)2**|
|---|---|---|---|---|
|Commercial|500|20 years|110|100|
|Industrial|500|20 years|110|100|
_1. This is a stress rating only; functional operation at any condition other than those indicated is not implied._
_2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits._
_**Table 2-4 •**_ **Overshoot and Undershoot Limits[1]**
|**VCCI and VMV**|**Average VCCI–GND Overshoot or Undershoot**<br>**Duration as a Percentage of Clock Cycle2**|**Maximum Overshoot/**<br>**Undershoot2**|
|---|---|---|
|2.7 V or less|10%|1.4 V|
||5%|1.49 V|
|3 V|10%|1.1 V|
||5%|1.19 V|
|3.3 V|10%|0.79 V|
||5%|0.88 V|
|3.6 V|10%|0.45 V|
||5%|0.54 V|
_Notes:_
_1. Based on reliability requirements at 85°C._
_2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V._
_3. This table does not provide PCI overshoot/undershoot limits._
**2-3**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)**
Sophisticated power-up management circuitry is designed into every ProASIC[®] 3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges.
In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-5.
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
## **VCCI Trip Point:**
Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V
**VCC** T **rip Point:**
Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
- During programming, I/Os become tristated and weakly pulled up to VCCI.
- JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
## _**PLL Behavior at Brownout Condition**_
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/Down Behavior of Low Power Flash Devices" chapter of the _ProASIC3 FPGA Fabric User’s Guide_ for information on clock and lock recovery.
## _**Internal Power-Up Activation Sequence**_
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation.
## **Thermal Characteristics**
## _**Introduction**_
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature.
EQ can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
where:
TA = Ambient Temperature
- T = Temperature gradient between junction (silicon) and ambient T = ja * P
- ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5 on page 2-6.
P = Power dissipation
**Revision 18**
**2-4**
_ProASIC3 DC and Switching Characteristics_
**==> picture [442 x 310] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCC = VCCI + VT<br>where VT can be from 0.58 V to 0.9 V (typically 0.75 V)<br>VCC<br>VCC = 1.575 V<br>Region 4: I/O Region 5: I/O buffers are ON<br>Region 1: I/O Buffers are OFF buffers are ON. and power supplies are within<br>I/Os are functional specification.<br>(except differential I/Os meet the entire datasheet<br> but slower because VCCI and timer specifications for<br>is below specification. For the speed, VIH / VIL, VOH / VOL,<br>etc.<br>same reason, input buffers do not<br>meet VIH / VIL levels, and output<br>buffers do not meet VOH / VOL levels.<br>VCC = 1.425 V<br>Region 2: I/O buffers are ON.<br>Region 3: I/O buffers are ON.<br>I/Os are functional (except differential inputs) I/Os are functional; I/O DC<br>but slower because VCCI / VCC are below specifications are met,<br>specification. For the same reason, input but I/Os are slower because<br>buffers do not meet VIH / VIL levels, and the VCC is below specification.<br>output buffers do not meet VOH / VOL levels.<br>Activation trip point:<br>Va = 0.85 V ± 0.25 V<br>Deactivation trip point:<br>Region 1: I/O buffers are OFF<br>Vd = 0.75 V ± 0.25 V<br>t t<br>Activation trip point: Min VCCI datasheet specification VCCI<br>Va = 0.9 V ± 0.3 V voltage at a selected I/O<br>Deactivation trip point: standard; i.e., 1.425 V or 1.7 V<br>Vd = 0.8 V ± 0.3 V or 2.3 V or 3.0 V<br>**----- End of picture text -----**<br>
_**Figure 2-2 •**_ **I/O State as a Function of VCCI and VCC Voltage Levels**
## _**Package Thermal Characteristics**_
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for are shown for two air flow rates. ja
**2-5**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
The absolute maximum junction temperature is 100°C. EQ 1 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air.
Maximum Power Allowed = Max. junction temp. ( ----------------------------------------------------------------------------------------------------------------------------------------- _ja_ C)( – C/W)Max. ambient temp. (C) = 100 ----------------------------------20.5C – C/W70C **-** = 1.463 W[·]
_EQ 1_
_**Table 2-5 •**_ **Package Thermal Resistivities**
||~~ee~~|||~~EQ~~<br>|~~EQ~~<br>|~~EQ~~<br>||
|---|---|---|---|---|---|---|---|
|**Package Type**<br>~~|~~|**Device**<br>~~|~~<br>~~ee~~<br>~~a~~|**Pin Count**<br>~~|~~<br>~~ee~~|**jc**<br>~~|~~<br>~~ee~~|**ja**<br>~~a~~<br>~~|~~<br>~~EQ~~<br>|||**Units**<br>~~a~~<br>~~ee~~|
|||||**Still Air**<br>~~a~~<br>~~|~~<br>~~EQ~~<br>~~ee~~|**200 ft/min**<br>~~a~~<br>~~|~~<br>~~EQ~~<br>~~ee~~|**500 ft/min**<br>~~a~~<br>~~|~~<br>~~ee~~||
|Quad Flat No Lead|A3P030<br>~~ee~~<br>~~a~~<br>~~ee~~|132<br>~~ee~~<br>~~ee~~<br>|0.4<br>~~ee~~<br>~~ee~~<br>|21.4<br>~~EQ~~<br>~~ee~~<br>~~ee~~<br>|16.8<br>~~EQ~~<br>~~ee~~<br>~~ee~~<br>|15.3<br>~~ee~~<br>~~ee~~<br>|**°**C/W<br>~~ee~~<br>~~ee~~<br>|
||A3P060<br>~~ee ~~<br>~~a~~<br>~~ee~~<br>~~ee~~|132<br> ~~ee ~~<br>~~ee~~<br>~~**ee**~~|0.3<br> ~~ee ~~<br>~~ee~~<br>~~**ee**~~|21.2<br>~~EQ~~<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|16.6<br>~~EQ~~<br> ~~ee ~~<br>~~ee~~<br>~~**ee**~~|15.0<br> ~~ee ~~<br>~~ee~~<br>~~**e**e~~|**°**C/W<br> ~~ee~~<br>~~ee~~<br>~~**e**e~~|
||A3P125<br>~~ee~~<br>~~ee~~|132<br>~~ee~~<br>~~**ee**~~|0.2<br>~~ee~~<br>~~**ee**~~|21.1<br>~~ee~~<br>~~ee~~<br>~~ee~~|16.5<br>~~ee~~<br>~~**ee**~~|14.9<br>~~ee~~<br>~~**e**e~~<br>~~e~~|**°**C/W<br>~~ee~~<br>~~**e**e~~<br>~~e~~|
||A3P250<br>~~ee ~~<br>~~ee~~<br>~~ee~~|132<br>~~ee ~~<br> ~~**ee**~~<br>~~es~~|0.1<br> ~~ee ~~<br>~~**ee**~~<br>~~es~~|21.0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~es~~|16.4<br> ~~ee ~~<br>~~**ee**~~<br>~~es~~|14.8<br> ~~ee ~~<br>~~**e**e~~<br>~~e~~<br>~~ee~~|**°**C/W<br> ~~ee~~<br>~~**e**e~~<br>~~e~~|
|Very Thin Quad Flat Pack (VQFP)<br>~~es~~|All devices<br> <br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee Gs~~|100<br> ~~**ee** ~~<br>~~es~~<br>~~es~~<br>~~Gs~~|10.0<br> ~~**ee** ~~<br>~~es~~<br>~~es~~<br>~~es~~|35.3<br> ~~ee ~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~es~~|29.4<br> ~~**ee** ~~<br>~~es~~<br>~~es~~<br>~~es~~|27.1<br> ~~**e**e ~~<br>~~e~~<br>~~es~~<br>~~ee~~|**°**C/W<br> ~~**e**e~~<br>~~e~~<br>~~es~~|
|Thin Quad Flat Pack (TQFP)<br>~~es~~|All devices<br>~~ee~~<br>~~es~~<br>~~ee Gs~~<br>~~es~~|144<br>~~es ~~<br>~~es~~<br>~~Gs~~<br>~~es~~|11.0<br> ~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|33.5<br> ~~es ~~<br>~~es~~<br>~~es~~<br>~~rs~~|28.0<br> ~~es ~~<br>~~es~~<br>~~es~~|25.7<br> ~~ee~~<br>~~es~~|**°**C/W<br>~~es~~|
|Plastic Quad Flat Pack (PQFP)<br>~~es~~|All devices<br>~~ee Gs~~<br>~~es~~<br>~~es~~<br>~~a~~|208<br>~~Gs ~~<br>~~es~~<br>~~es~~<br>~~ee~~|8.0<br> ~~es ~~<br>~~es~~<br>~~es~~<br>~~ee~~|26.1<br> ~~es ~~<br>~~es~~<br>~~rs~~<br>~~ee~~|22.5<br> ~~es~~<br>~~es~~<br>~~ee~~|20.8<br>~~es~~<br>~~ee~~|**°**C/W<br>~~es~~<br>~~ee~~|
|Fine Pitch Ball Grid Array (FBGA)|See note*<br>~~es ~~<br>~~a~~<br>~~ee~~|144<br> ~~es ~~<br>~~ee~~<br>~~ee~~|3.8<br> ~~es ~~<br>~~ee~~<br>~~ee~~|26.9<br> ~~rs~~<br>~~ee~~<br>~~ee~~|22.9<br>~~ee~~<br>~~ee~~|21.5<br>~~ee~~<br>~~ee~~|**°**C/W<br>~~ee~~<br>~~ee~~|
||See note*<br>~~a~~<br>~~ee~~<br>~~ee~~|256<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.8<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|26.6<br> ~~ee~~<br>~~ee~~<br>~~ee~~|22.8<br>~~ee~~<br>~~ee~~<br>~~ee~~|21.5<br>~~ee ~~<br>~~ee~~<br>~~ee~~|**°**C/W<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
||See note*<br>~~ee~~<br>~~ee~~<br>~~ee~~|484<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|20.5<br> ~~ee~~<br>~~ee~~<br>~~ee~~|17.0<br>~~ee~~<br>~~ee~~<br>~~ee~~|15.9<br>~~ee ~~<br>~~ee~~<br>~~eee~~|**°**C/W<br> ~~ee~~<br>~~ee~~<br>~~eee~~|
||A3P1000<br>~~ee ~~<br>~~ee~~<br>~~a~~|144<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.3<br> ~~ee~~<br>~~ee~~<br>~~ee~~|31.6<br>~~ee~~<br>~~ee~~<br>~~ee~~|26.2<br>~~ee~~<br>~~ee~~<br>~~ee~~|24.2<br>~~ee~~<br>~~eee~~<br>~~eee~~|**°**C/W<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||A3P1000<br>~~ee~~<br>~~a~~<br>~~a~~|256<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.6<br>~~ee~~<br>~~ee~~<br>~~ee~~|28.1<br>~~ee ~~<br>~~ee~~<br>~~ee~~|24.4<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|22.7<br> ~~eee~~<br>~~eee~~<br>~~ee~~|**°**C/W<br>~~eee~~<br>~~eee~~<br>~~ee~~|
||A3P1000<br>~~a~~<br>~~a~~|484<br>~~ee~~<br>~~ee~~|8.0<br>~~ee~~<br>~~ee~~|23.3<br>~~ee ~~<br>~~ee~~|19.0<br> ~~ee ~~<br>~~ee~~|16.7<br> ~~eee~~<br>~~ee~~|**°**C/W<br>~~eee~~<br>~~ee~~|
_Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be available in future revisions of the datasheet._
## _**Temperature and Voltage Derating Factors**_
_**Table 2-6 •**_ **Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V)**
|**Array Voltage VCC**<br>**(V)**|**Junction Temperature (°C)**|**Junction Temperature (°C)**|**Junction Temperature (°C)**|**Junction Temperature (°C)**|**Junction Temperature (°C)**|**Junction Temperature (°C)**|
|---|---|---|---|---|---|---|
||**–40°C**|**0°C**|**25°C**|**70°C**|**85°C**|**100°C**|
|1.425|0.88|0.93|0.95|1.00|1.02|1.04|
|1.500|0.83|0.88|0.90|0.95|0.96|0.98|
|1.575|0.80|0.84|0.87|0.91|0.93|0.94|
**Revision 18**
**2-6**
_ProASIC3 DC and Switching Characteristics_
## **Calculating Power Dissipation**
## **Quiescent Supply Current**
_**Table 2-7 •**_ **Quiescent Supply Current Characteristics**
||**A3P015 **|**A3P030 **|**A3P060 **|**A3P125 **|**A3P250**|**A3P400**|**A3P600**|**A3P1000**|
|---|---|---|---|---|---|---|---|---|
|Typical (25°C)|2 mA|2 mA|2 mA|2 mA|3 mA|3 mA|5 mA|8 mA|
|Max. (Commercial)|10 mA|10 mA|10 mA|10 mA|20 mA|20 mA|30 mA|50 mA|
|Max. (Industrial)|15 mA|15 mA|15 mA|15 mA|30 mA|30 mA|45 mA|75 mA|
_Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-11 and Table 2-12 on page 2-9._
## **Power per I/O Pin**
## _**Table 2-8 •**_ **Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Advanced I/O Banks**
||**VMV (V)**|**Static Power**<br>**PDC2 (mW) 1**|**Dynamic Power**<br>**PAC9 (µW/MHz) 2**|
|---|---|---|---|
|**Single-Ended**||||
|3.3 V LVTTL / 3.3 V LVCMOS|3.3|–|16.22|
|3.3 V LVCMOS Wide Range3|3.3|–|16.22|
|2.5 V LVCMOS|2.5|–|5.12|
|1.8 V LVCMOS|1.8|–|2.13|
|1.5 V LVCMOS (JESD8-11)|1.5|–|1.45|
|3.3 V PCI|3.3|–|18.11|
|3.3 V PCI-X|3.3|–|18.11|
|**Differential**||||
|LVDS|2.5|2.26|1.20|
|LVPECL|3.3|5.72|1.87|
_Notes:_
_1. PDC2 is the static power (where applicable) measured on VMV._
_2. PAC9 is the total dynamic power measured on VCC and VMV._
_3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
_**Table 2-9 •**_ **Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks**
||**VMV (V)**|**Static Power**<br>**PDC2 (mW) 1**|**Dynamic Power**<br>**PAC9 (µW/MHz) 2**|
|---|---|---|---|
|**Single-Ended**||||
|3.3 V LVTTL / 3.3 V LVCMOS|3.3|–|16.23|
|3.3 V LVCMOS Wide Range3|3.3|–|16.23|
_Notes:_
_1. PDC2 is the static power (where applicable) measured on VMV._
_2. PAC9 is the total dynamic power measured on VCC and VMV._
_3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
**2-7**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-9 •**_ **Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks**
||**VMV (V)**|**Static Power**<br>**PDC2 (mW) 1**|**Dynamic Power**<br>**PAC9 (µW/MHz) 2**|
|---|---|---|---|
|2.5 V LVCMOS|2.5|–|5.14|
|1.8 V LVCMOS|1.8|–|2.13|
|1.5 V LVCMOS (JESD8-11)|1.5|–|1.48|
|3.3 V PCI|3.3|–|18.13|
|3.3 V PCI-X|3.3|–|18.13|
## _Notes:_
_1. PDC2 is the static power (where applicable) measured on VMV._
_2. PAC9 is the total dynamic power measured on VCC and VMV._
_3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
_**Table 2-10 •**_ **Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard I/O Banks**
||**VMV (V)**|**Static Power**<br>**PDC2 (mW) 1**|**Dynamic Power**<br>**PAC9 (µW/MHz) 2**|
|---|---|---|---|
|**Single-Ended**||||
|3.3 V LVTTL / 3.3 V LVCMOS|3.3|–|17.24|
|3.3 V LVCMOS Wide Range3|3.3|–|17.24|
|2.5 V LVCMOS|2.5|–|5.19|
|1.8 V LVCMOS|1.8|–|2.18|
|1.5 V LVCMOS (JESD8-11)|1.5|–|1.52|
## _Notes:_
_1. PDC2 is the static power (where applicable) measured on VMV._
_2. PAC9 is the total dynamic power measured on VCC and VMV._
_3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
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_**Table 2-11 •**_ **Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings[1] Applicable to Advanced I/O Banks**
||**CLOAD (pF)**|**VCCI (V)**|**Static Power**<br>**PDC3 (mW)2**|**Dynamic Power**<br>**PAC10 (µW/MHz)3**|
|---|---|---|---|---|
|**Single-Ended**<br>~~|~~|||||
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~ss~~|35<br>~~ss~~<br>~~es~~|3.3<br>~~ss~~|–<br>~~ss~~|468.67<br>~~ss~~|
|3.3 V LVCMOS Wide Range4<br>~~es~~|35<br>~~es~~<br>~~es~~<br>~~ns~~|3.3<br>~~es~~|–<br>~~es~~|468.67<br>~~es~~|
|2.5 V LVCMOS<br>~~es~~|35<br>~~es~~<br>~~es~~<br>~~ns~~|2.5<br>~~es~~|–<br>~~es~~|267.48<br>~~es~~|
|1.8 V LVCMOS|35<br>~~ns~~|1.8<br>~~ee~~|–<br>~~ee~~|149.46|
|1.5 V LVCMOS<br>(JESD8-11)<br>~~ee~~|35<br>~~ee~~|1.5<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|103.12<br>~~ee~~|
|3.3 V PCI<br>~~es~~<br>~~Cn~~|10<br>~~es~~<br>~~ns~~<br>|3.3<br>~~ee~~<br>~~es~~<br>|–<br>~~ee~~<br>~~es~~<br>|201.02<br>~~es~~<br>|
|3.3 V PCI-X<br>~~es~~<br>~~Cn~~|10<br>~~es~~<br>~~ns~~<br>|3.3<br>~~es~~<br>|–<br>~~es~~<br>|201.02<br>~~es~~<br>|
|**Differential**<br>~~ns~~<br>~~Cn~~|||||
|LVDS<br>~~Cnes~~|–<br>~~ns~~<br>~~es~~<br>~~es~~|2.5<br>~~es~~|7.74<br>~~es~~|88.92<br>~~es~~|
|LVPECL<br>~~ee~~|–<br>~~ee~~<br>~~es~~|3.3<br>~~ee~~|19.54<br>~~ee~~|166.52<br>~~ee~~|
_Notes:_
_1. Dynamic power consumption is given for standard load and software default drive strength and output slew._
_2. PDC3 is the static power (where applicable) measured on VCCI._
_3. PAC10 is the total dynamic power measured on VCC and VCCI._
_4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
_**Table 2-12 •**_ **Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings[1] Applicable to Standard Plus I/O Banks**
||**CLOAD (pF)**|**VCCI (V)**|**Static Power**<br>**PDC3 (mW)2**|**Dynamic Power**<br>**PAC10 (µW/MHz)3**|
|---|---|---|---|---|
|**Single-Ended**|||||
|3.3 V LVTTL / 3.3 V LVCMOS|35|3.3|–|452.67|
|3.3 V LVCMOS Wide Range4|35|3.3|–|452.67|
|2.5 V LVCMOS|35|2.5|–|258.32|
|1.8 V LVCMOS|35|1.8|–|133.59|
|1.5 V LVCMOS (JESD8-11)|35|1.5|–|92.84|
|3.3 V PCI|10|3.3|–|184.92|
|3.3 V PCI-X|10|3.3|–|184.92|
## _Notes:_
_1. Dynamic power consumption is given for standard load and software default drive strength and output slew._
_2. PDC3 is the static power (where applicable) measured on VMV._
_3. PAC10 is the total dynamic power measured on VCC and VMV._
_4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
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_**Table 2-13 •**_ **Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings[1] Applicable to Standard I/O Banks**
||**CLOAD (pF)**|**VCCI (V)**|**Static Power**<br>**PDC3 (mW) 2**|**Dynamic Power**<br>**PAC10 (µW/MHz) 3**|
|---|---|---|---|---|
|**Single-Ended**|||||
|3.3 V LVTTL / 3.3 V LVCMOS|35|3.3|–|431.08|
|3.3 V LVCMOS Wide Range4|35|3.3|–|431.08|
|2.5 V LVCMOS|35|2.5|–|247.36|
|1.8 V LVCMOS|35|1.8|–|128.46|
|1.5 V LVCMOS (JESD8-11)|35|1.5|–|89.46|
## _Notes:_
_1. Dynamic power consumption is given for standard load and software default drive strength and output slew._
_2. PDC3 is the static power (where applicable) measured on VCCI._
_3. PAC10 is the total dynamic power measured on VCC and VCCI._
_4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
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## **Power Consumption of Various Internal Resources**
_**Table 2-14 •**_ **Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices**
|**Parameter**<br>~~a~~|**Definition**<br>~~ee~~|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|**Device Specific Dynamic Contributions**<br>**(µW/MHz)**|
|---|---|---|---|---|---|---|---|---|---|
|||**A3P1000**<br>~~eee~~|**A3P600**<br>~~es~~|**A3P400**<br>~~es~~|**A3P250**<br>~~es~~|**A3P125**<br>~~es~~|**A3P060**<br>~~ee~~|**A3P030**<br>~~ee~~|**A3P015**|
|PAC1<br>~~a~~|Clock contribution of a Global Rib<br>~~ee~~|14.50 <br>~~eee~~<br>~~rs~~|12.80 <br>~~es~~<br>~~re~~|12.80<br>~~es~~|11.00 <br>~~es~~|11.00<br>~~es~~|9.30<br>~~ee~~|9.30<br>~~ee~~|9.30|
|PAC2<br>~~a~~<br>~~a es~~|Clock contribution of a Global Spine<br>~~ee ~~<br>~~es~~|2.48<br> ~~eee~~<br>~~es~~<br>~~rs~~|1.85<br>~~es ~~<br>~~es~~<br>~~re~~|1.35<br> ~~es ~~<br>~~es~~|1.58<br> ~~es ~~<br>~~es~~|0.81<br> ~~es ~~<br>~~es~~|0.81<br> ~~ee ~~<br>~~es~~|0.41<br> ~~ee~~<br>~~es~~|0.41<br>~~es~~|
|PAC3|Clock contribution of a VersaTile row|0.81<br>~~rs re~~||||||||
|PAC4<br>~~a~~|Clock contribution of a VersaTile used as a<br>sequential module<br>~~ee~~|0.12<br>~~ee~~||||||||
|PAC5|First contribution of a VersaTile used as a<br>sequential module|0.07||||||||
|PAC6|Second contribution of a VersaTile used as a<br>sequential module|0.29||||||||
|PAC7|Contribution of a VersaTile used as a<br>combinatorial Module|0.29||||||||
|PAC8|Average contribution of a routing net|0.70||||||||
|PAC9<br>~~a~~|Contribution of an I/O input pin (standard<br>dependent)<br>~~ee~~|SeeTable 2-8 on page 2-7through<br>Table 2-10 on page 2-8.<br>~~ee~~||||||||
|PAC10|Contribution of an I/O output pin (standard<br>dependent)|SeeTable 2-11 on page 2-9through<br>Table 2-13 on page 2-10.||||||||
|PAC11|Average contribution of a RAM block during a<br>read operation|25.00||||||||
|PAC12<br>~~a~~|Average contribution of a RAM block during a<br>write operation<br>~~es~~|30.00||||||||
|PAC13<br>~~a~~|Dynamic contribution for PLL<br>~~es~~|2.60||||||||
_Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC software._
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_**Table 2-15 •**_ **Different Components Contributing to the Static Power Consumption in ProASIC3 Devices**
|**Parameter**|**Definition**|**Device Specific Static Power (mW)**|**Device Specific Static Power (mW)**|**Device Specific Static Power (mW)**|**Device Specific Static Power (mW)**|**Device Specific Static Power (mW)**|**Device Specific Static Power (mW)**|**Device Specific Static Power (mW)**|**Device Specific Static Power (mW)**|
|---|---|---|---|---|---|---|---|---|---|
|||**A3P1000**|**A3P600**|**A3P400**|**A3P250**|**A3P125**|**A3P060**|**A3P030**|**A3P015**|
|PDC1|Array static power in Active mode|SeeTable 2-7 on page 2-7.||||||||
|PDC2|I/O input pin static power (standard-dependent)|SeeTable 2-8 on page 2-7through<br>Table 2-10 on page 2-8.||||||||
|PDC3|I/O output pin static power (standard-dependent)|SeeTable 2-11 on page 2-9through<br>Table 2-13 on page 2-10.||||||||
|PDC4|Static PLL contribution|2.55 mW||||||||
|PDC5|Bank quiescent power (VCCI-dependent)|SeeTable 2-7 on page 2-7.||||||||
_Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC software._
## **Power Calculation Methodology**
This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
- The number of PLLs as well as the number and the frequency of each output clock generated
- The number of combinatorial and sequential cells used in the design
- The internal clock frequencies
- The number and the standard of I/O pins used in the design
- The number of RAM blocks used in the design
- Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on page 2-14.
- Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on page 2-14.
- Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-17 on page 2-14. The calculation should be repeated for each clock domain defined in the design.
## _**Methodology**_
## _**Total Power Consumption—PTOTAL**_
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
## _**Total Static Power Consumption—PSTAT**_
PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
## _**Total Dynamic Power Consumption—PDYN**_
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
## _**Global Clock Contribution—PCLOCK**_
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the _ProASIC3 FPGA Fabric User's Guide_ .
NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the _ProASIC3 FPGA Fabric User's Guide_ .
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FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
## _**Sequential Cells Contribution—PS-CELL**_
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.
FCLK is the global clock signal frequency.
## _**Combinatorial Cells Contribution—PC-CELL**_
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.
FCLK is the global clock signal frequency.
## _**Routing Net Contribution—PNET**_
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.
FCLK is the global clock signal frequency.
## _**I/O Input Buffer Contribution—PINPUTS**_
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14.
FCLK is the global clock signal frequency.
## _**I/O Output Buffer Contribution—POUTPUTS**_
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-14.
FCLK is the global clock signal frequency.
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_ProASIC3 Flash Family FPGAs_
## **RAM Contribution—PMEMORY**
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
- FREAD-CLOCK is the memory read clock frequency.
- 2 is the RAM enable rate for read operations.
- FWRITE-CLOCK is the memory write clock frequency.
- 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-14.
## _**PLL Contribution—PPLL**_
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.[1]
## _**Guidelines**_
## _**Toggle Rate Definition**_
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples:
- The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency.
- The average toggle rate of an 8-bit counter is 25%:
- Bit 0 (LSB) = 100%
- Bit 1 = 50%
- Bit 2 = 25%
- …
- Bit 7 (MSB) = 0.78125%
- Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
## _**Enable Rate Definition**_
Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%.
_**Table 2-16 •**_ **Toggle Rate Guidelines Recommended for Power Calculation**
|**Component**|**Definition**|**Guideline**|
|---|---|---|
|1|Toggle rate of VersaTile outputs|10%|
|2|I/O buffer toggle rate|10%|
_**Table 2-17 •**_ **Enable Rate Guidelines Recommended for Power Calculation**
|**Component**|**Definition**|**Guideline**|
|---|---|---|
|1|I/O output buffer enable rate|100%|
|2|RAM enable rate for read operations|12.5%|
|3|RAM enable rate for write operations|12.5%|
> _1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution._
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## **User I/O Characteristics**
## **Timing Model**
**==> picture [462 x 338] intentionally omitted <==**
**----- Start of picture text -----**<br>
I/O Module<br>(Non-Registered)<br>Combinational Cell Combinational Cell<br>LVPECL (Applicable to<br>Y Y Advanced I/O Banks Only)L<br>tPD = 0.56 ns tPD = 0.49 ns<br>tDP = 1.34 ns<br>I/O Module<br>(Non-Registered)<br>Combinational Cell<br>Y<br>LVTTL [Output drive strength = 12 mA]<br>High slew rate<br>tPD = 0.87 ns tDP = 2.64 ns (Advanced I/O Banks)<br>I/O Module<br>Combinational Cell<br>(Non-Registered)<br>I/O Module Y<br>(Registered)<br>LVTTL [Output drive strength = 8 mA]<br>tPY = 1.05 ns High slew rate<br>tDP = 3.66 ns (Advanced I/O Banks)<br>(ApplicableLVPECL D Q tPD = 0.47 ns I/O Module<br>to Advanced Combinational Cell (Non-Registered)<br>I/O Banks only) Y<br>LVCMOS 1.5 VOutput drive strength = 4 mA<br>ttISUDICLKQ = 0.26 ns = 0.24 ns tPD = 0.47 ns tDP = 3.97 ns (Advanced I/O Banks)High slew rate<br>Input LVTTL<br>Clock I/O Module<br>Register Cell Combinational Cell Register Cell (Registered)<br>tPY = 0.76 ns (Advanced I/O Banks) D Q Y D Q D Q LVTTL 3.3 V Output drive<br>(Non-Registered)I/O Module tPD = 0.47 ns tDP = 2.64 ns strength = 12 mA High slew rate<br>(Advanced I/O Banks)<br>Gia<br>BLVDS,LVDS, ttCLKQSUD = 0.43 ns = 0.55 ns ttCLKQSUD = 0.43 ns = 0.55 ns ttOSUDOCLKQ = 0.31 ns = 0.59 ns<br>M-LVDS Input LVTTL Input LVTTL<br>(Applicable for tPY = 1.20 ns Clock Clock<br>Advanced I/O<br>Banks only) tPY = 0.76 ns tPY = 0.76 ns<br>(Advanced I/O Banks) (Advanced I/O Banks)<br>**----- End of picture text -----**<br>
_**Figure 2-3 •**_ **Timing Model**
**Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case VCC = 1.425 V**
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**==> picture [395 x 412] intentionally omitted <==**
**----- Start of picture text -----**<br>
tPY tDIN<br>D Q<br>PAD DIN<br>Y<br>CLK To Array<br>tPY = MAX(tPY(R), tPY(F)) I/O Interface<br>tDIN = MAX(tDIN(R), tDIN(F))<br>VIH<br>V V<br>PAD trip trip VIL<br>VCC<br>50% 50%<br>Y<br>GND tPY tPY<br>(R) (F)<br>VCC<br>50% 50%<br>DIN<br>GND tDIN tDIN<br>(R) (F)<br>**----- End of picture text -----**<br>
_**Figure 2-4 •**_ **Input Buffer Timing Model and Delays (Example)**
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_ProASIC3 DC and Switching Characteristics_
**==> picture [406 x 331] intentionally omitted <==**
**----- Start of picture text -----**<br>
tDOUT tDP<br>D Q PAD<br>DOUT<br>D CLK Std<br>Load<br>From Array<br>tDP = MAX(tDP(R), tDP(F))<br>I/O Interface<br>tDOUT = MAX(tDOUT(R), tDOUT(F))<br>t t<br>DOUT DOUT<br>(R) VCC<br>(F)<br>50% 50%<br>D 0 V<br>VCC<br>50% 50%<br>DOUT 0 V<br>VOH<br>Vtrip Vtrip<br>V<br>PAD OL<br>tDP tDP<br>(R) (F)<br>**----- End of picture text -----**<br>
_**Figure 2-5 •**_ **Output Buffer Model and Delays (Example)**
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**==> picture [435 x 585] intentionally omitted <==**
**----- Start of picture text -----**<br>
tEOUT<br>D Q<br>$$ ——————“— —) |<br>E CLK tZL, tZH, tHZ, tLZ, tZLS, tZHS<br>EOUT<br>D Q PAD<br>DOUT<br>D CLK<br>I/O Interface tEOUT = MAX(tEOUT(r), tEOUT(f))<br>VCC<br>D<br>VCC<br>50% 50%<br>E<br>t<br>t EOUT (F)<br>EOUT (R)<br>VCC<br>50%<br>EOUT 50% 50% tZH50% tLZ<br>tZL tHZ VCCI<br>PAD 90% VCCI<br>Vtrip Vtrip<br>VOL 10% VCCI<br>VCC<br>D<br>VCC<br>E 50% t 50% t<br>EOUT (R) EOUT (F)<br>VCC<br>50% 50%<br>EOUT 5 0%<br>tZLS VOH tZHS<br>PAD<br>Vtrip Vtrip<br>VOL<br>**----- End of picture text -----**<br>
_**Figure 2-6 •**_ **Tristate Output Buffer Timing Model and Delays (Example)**
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_ProASIC3 DC and Switching Characteristics_
## **Overview of I/O Performance**
## _**Summary of I/O DC Input and Output Levels – Default I/O Software Settings**_
_**Table 2-18 •**_ **Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Advanced I/O Banks**
|**I/O Standard**<br>~~LLL~~|**Drive**<br>**Strength**<br>~~LLL~~|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option2**<br>~~LLL~~|**Software**<br>**Strength**<br>**Slew**<br>**Rate**<br>~~LLL~~|**VIL**<br>~~LLL~~|**VIL**<br>~~LLL~~|**VIH**<br>~~LLL~~|**VIH**<br>~~LLL~~|**VOL**<br>~~LLL~~|**VOH**<br>~~LLL~~|**IOL1**<br>**mA**<br>~~LLL~~|**IOH1**<br>**mA**<br>~~LLL~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||||**Slew**<br>**Min**<br>**V**<br>~~LLL~~|**Max**<br>**V**<br>~~LLL~~|**Min**<br>**V**<br>~~LLL~~|**Max**<br>**V**<br>~~LLL~~|**Max**<br>**V**<br>~~LLL~~|**Min**<br>**V**<br>~~LLL~~|||
|3.3 V LVTTL /<br>3.3 V<br>LVCMOS|12 mA|12 mA High –0.3|12 mA High –0.3|12 mA High –0.3|12 mA High –0.3<br>0.8|2|3.6|0.4|2.4|12|12|
|3.3 V<br>LVCMOS<br>Wide Range3<br>~~ef~~|100 µA<br>~~efEE~~|12 mA High –0.3<br>~~EE~~|12 mA High –0.3<br>~~EE~~|12 mA High –0.3<br>~~EE~~|12 mA High –0.3<br>0.8|2|3.6|0.2|VCCI – 0.2|0.1|0.1|
|2.5 V<br>LVCMOS<br>~~ef~~<br>~~et~~|12 mA<br>~~efEE~~<br>~~etEE~~|12 mA High –0.3<br>~~EE~~<br>~~EE~~|12 mA High –0.3<br>~~EE~~<br>~~EE~~|12 mA High –0.3<br>~~EE~~<br>~~EE~~|12 mA High –0.3<br>0.7|1.7|2.7|0.7|1.7|12|12|
|1.8 V<br>LVCMOS<br>~~ef~~<br>~~et~~<br>~~et~~|12 mA<br>~~ef EE~~<br>~~etEE~~<br>~~et~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9<br>~~EE~~<br>~~EE~~<br>|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9<br>~~EE~~<br>~~EE~~<br>|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9<br>~~EE~~<br>~~EE~~<br>|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9<br>|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9<br>|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9<br>|0.45<br>|VCCI – 0.45 12<br>|VCCI – 0.45 12<br>|12<br>|
|1.5 V<br>LVCMOS<br>~~et~~<br>~~et~~|12 mA<br>~~et EE~~<br>~~etEE~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6<br>~~EE~~<br>~~EE~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6<br>~~EE~~<br>~~EE~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6<br>~~EE~~<br>~~EE~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6<br>~~EE~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6<br>~~EE~~|12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 <br>~~EE~~|0.25 * VCCI 0.75 * VCCI 12<br>~~EE~~|0.25 * VCCI 0.75 * VCCI 12<br>~~EE~~|0.25 * VCCI 0.75 * VCCI 12<br>~~EE~~|12<br>~~EE~~|
|3.3 V PCI<br>~~et~~<br>~~a~~<br>~~Re~~|Per PCI specifications<br>~~et~~|||||||||||
|3.3 V PCI-X<br>~~Re~~|Per PCI-X specifications|||||||||||
_Notes:_
_1. Currents are measured at 85°C junction temperature._
_2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY._
_3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
**2-19**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-19 •**_ **Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings**
**Applicable to Standard Plus I/O Banks**
|**I/O Standard**<br>||**Drive**<br>**Strength**<br>~~LAT~~|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option2**<br>~~LAT~~|**Software**<br>**Strength**<br>**Slew**<br>**Rate**<br>~~LAT~~|**VIL**<br>~~LAT~~|**VIL**<br>~~LAT~~|**VIH**<br>~~LAT~~|**VIH**<br>~~LAT~~|**VOL**<br>~~LAT~~|**VOH**<br>~~LAT~~|**IOL1**<br>**mA**<br>~~LAT~~|**IOH1**<br>**mA**<br>~~LAT~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||||**Min**<br>**V**<br>~~LAT~~|**Max**<br>**V**<br>~~LAT~~|**Min**<br>**V**<br>~~LAT~~|**Max**<br>**V**<br>~~LAT~~|**Max**<br>**V**<br>~~LAT~~|**Min**<br>**V**<br>~~LAT~~|||
|3.3 V LVTTL /<br>3.3 V<br>LVCMOS|12 mA|12 mA|High –0.3|High –0.3|0.8|2|3.6|0.4|2.4|12|12|
|3.3 V<br>LVCMOS<br>Wide Range3|100 µA|12 mA|High –0.3|High –0.3|0.8|2|3.6|0.2|VCCI – 0.2|0.1|0.1|
|2.5 V<br>LVCMOS<br>~~|~~<br>~~et~~|12 mA<br>|<br>~~etEE~~|12 mA<br>~~tee~~<br>~~EE~~|High –0.3<br>~~tee~~<br>~~EE~~|High –0.3<br>~~tee~~|0.7<br>~~tee~~|1.7<br>~~tee~~|2.7<br>~~tee~~|0.7<br>~~tee~~|1.7<br>~~tee~~|12<br>~~tee~~|12<br>~~tee~~|
|1.8 V<br>LVCMOS<br>~~et~~<br>~~|~~|8 mA<br>~~etEE~~<br>~~EEE~~|8 mA<br>~~EE~~<br>~~EEE~~|High –0.3<br>~~EE~~<br>~~EEE~~|High –0.3 <br>~~EEE~~|0.35 * VCCI 0.65 * VCCI 1.9|0.35 * VCCI 0.65 * VCCI 1.9|0.35 * VCCI 0.65 * VCCI 1.9|0.45|VCCI –<br>0.45|8|8|
|1.5 V<br>LVCMOS<br>~~et~~<br>~~|~~|4 mA<br>~~et EE~~<br>~~EEE~~|4 mA<br>~~EE~~<br>~~EEE~~|High –0.3<br>~~EE~~<br>~~EEE~~|High –0.3 <br>~~EEE~~|0.35 * VCCI 0.65 * VCCI 1.6|0.35 * VCCI 0.65 * VCCI 1.6|0.35 * VCCI 0.65 * VCCI 1.6|0.25 * VCCI 0.75 * VCCI|0.25 * VCCI 0.75 * VCCI|4|4|
|3.3 V PCI<br>~~|~~<br>~~a~~|Per PCI specifications<br>~~EEE~~|||||||||||
|3.3 V PCI-X<br>~~a~~|Per PCI-X specifications|||||||||||
_Notes:_
_1. Currents are measured at 85°C junction temperature._
_2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY._
_3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
**Revision 18**
**2-20**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-20 •**_ **Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard I/O Banks**
|**I/O Standard**|**Drive**<br>**Strength**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option2**|**Software**<br>**Strength**<br>**Slew**<br>**Rate**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL1**<br>**mA**|**IOH1**<br>**mA**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||||**Min**<br>**V**|**Max**<br>**V**|**Min**<br>**V**|**Max**<br>**V**|**Max**<br>**V**|**Min**<br>**V**|||
|3.3 V LVTTL /<br>3.3 V<br>LVCMOS|8 mA|8 mA|High –0.3|High –0.3|High –0.3<br>0.8|2|3.6|0.4|2.4|8|8|
|3.3 V<br>LVCMOS<br>Wide Range3<br>~~|~~|100 µA<br>~~ft~~|8 mA<br>~~ft~~|High –0.3|High –0.3|High –0.3<br>0.8|2|3.6|0.2|VCCI – 0.2|0.1|0.1|
|2.5 V<br>LVCMOS<br>~~|~~<br>~~Pe~~<br>~~tT~~|8 mA<br>~~ft~~<br>~~tT~~<br>~~ft~~|8 mA<br>~~ft~~<br>~~ft~~|High –0.3<br>|High –0.3<br>|High –0.3<br>0.7<br>|1.7<br>|2.7<br>|0.7<br>|1.7<br>|8<br>|8<br>|
|1.8 V<br>LVCMOS<br>~~|~~<br>~~Pe~~<br>~~tT~~<br>~~Pt~~|4 mA<br>~~ft~~<br>~~tT~~<br>~~ft~~<br>~~Pt~~<br>~~|~~|4 mA<br>~~ft~~<br>~~fttT~~<br>~~tT~~|High –0.3 0.35 * VCCI<br>~~tT~~<br>~~tTtt~~|High –0.3 0.35 * VCCI<br>~~tT~~<br>~~tt~~|High –0.3 0.35 * VCCI <br>~~tT~~<br>~~tt~~<br>~~fy~~|0.65 * VCCI<br>~~tT~~<br>~~fy~~|3.6<br>~~tT~~|0.45<br>~~tT~~|VCCI – 0.45<br>~~tT~~|4<br>~~tT~~|4<br>~~tT~~|
|1.5 V<br>LVCMOS<br>~~Pe~~<br>~~tT~~<br>~~Pt~~|2 mA<br>~~tT~~<br>~~ft~~<br>~~Pt~~<br>~~|~~|2 mA<br>~~fttT~~<br>~~tT~~|High –0.3 0.35 * VCCI<br>~~tT~~<br>~~tTtt~~|High –0.3 0.35 * VCCI<br>~~tT~~<br>~~tt~~|High –0.3 0.35 * VCCI <br>~~tT~~<br>~~tt~~<br>~~fy~~|0.65 * VCCI<br>~~tT~~<br>~~fy~~|3.6 0.25 * VCCI<br>~~tT~~|3.6 0.25 * VCCI <br>~~tT~~|0.75 * VCCI<br>~~tT~~|2<br>~~tT~~|2<br>~~tT~~|
_Notes:_
_1. Currents are measured at 85°C junction temperature._
_2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY._
_3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
## _**Table 2-21 •**_ **Summary of Maximum and Minimum DC Input Levels**
**Applicable to Commercial and Industrial Conditions**
|**DC I/O Standards**<br>~~a~~|**Commercial1**<br>~~**e**e~~|**Commercial1**<br>~~**e**e~~|**Industrial2**<br>~~e~~|**Industrial2**<br>~~e~~|
|---|---|---|---|---|
||**IIL3**<br>~~**e**~~<br>~~e~~|**IIH4**<br>~~**e**e~~<br>~~——~~<br>~~ee~~|**IIL3**<br>~~e~~<br>~~——~~<br>~~ee~~|**IIH4**<br>~~e~~<br>~~——~~|
||**µA**<br>~~**e**~~<br>~~e~~<br>~~Ps~~|**µA**<br>~~**e**e~~<br>~~——~~<br>~~ee~~|**µA**<br>~~e~~<br>~~——~~<br>~~ee~~|**µA**<br>~~e~~<br>~~——~~|
|3.3 V LVTTL / 3.3 V LVCMOS<br>~~er~~|10<br>~~e~~<br>~~er~~<br>~~Ps~~|10<br>~~——~~<br>~~ee~~<br>~~er~~|15<br>~~——~~<br>~~ee~~<br>~~er~~|15<br>~~——~~<br>~~er~~|
|3.3 V LVCMOS Wide Range<br>~~rs~~|10<br>~~Ps~~<br>~~rs~~<br>~~Ps~~|10<br>~~rs~~|15<br>~~rs~~|15<br>~~rs~~|
|2.5 V LVCMOS<br>~~er~~|10<br>~~er~~<br>~~Ps~~|10<br>~~er~~|15<br>~~er~~|15<br>~~er~~|
|1.8 V LVCMOS<br>~~rs~~|10<br>~~Ps~~<br>~~rs~~<br>~~Ps~~|10<br>~~rs~~|15<br>~~rs~~|15<br>~~rs~~|
|1.5 V LVCMOS<br>~~er~~|10<br>~~er~~<br>~~Ps~~|10<br>~~er~~|15<br>~~er~~|15<br>~~er~~|
|3.3 V PCI<br>~~rs~~|10<br>~~Ps~~<br>~~rs~~<br>~~Ps~~|10<br>~~rs~~<br>~~rs~~|15<br>~~rs~~|15<br>~~rs~~|
|3.3 V PCI-X<br>~~ee~~|10<br>~~ee~~<br>~~Ps~~|10<br>~~ee~~<br>~~rs~~|15<br>~~ee~~|15<br>~~ee~~|
_Notes:_
_1. Commercial range (0°C < TA < 70°C)_
_2. Industrial range (–40°C < TA < 85°C)_
_3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN <VIL._
_4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
**2-21**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## _**Summary of I/O Timing Characteristics – Default I/O Software Settings**_
_**Table 2-22 •**_ **Summary of AC Measuring Points**
|**_Table 2-22 •_Summary of AC Measuring Points**||
|---|---|
|**Standard**|**Measuring Trip Point (Vtrip)**|
|3.3 V LVTTL / 3.3 V LVCMOS|1.4 V|
|3.3 V LVCMOS Wide Range|1.4 V|
|2.5 V LVCMOS|1.2 V|
|1.8 V LVCMOS|0.90 V|
|1.5 V LVCMOS|0.75 V|
|3.3 V PCI|0.285 * VCCI (RR)|
||0.615 * VCCI (FF)|
|3.3 V PCI-X|0.285 * VCCI (RR)|
||0.615 * VCCI (FF)|
_**Table 2-23 •**_ **I/O AC Parameter Definitions**
|**Parameter**|**Parameter Definition**|
|---|---|
|tDP|Data to Pad delay through the Output Buffer|
|tPY|Pad to Data delay through the Input Buffer|
|tDOUT|Data to Output Buffer delay through the I/O interface|
|tEOUT|Enable to Output Buffer Tristate Control delay through the I/O interface|
|tDIN|Input Buffer to Data delay through the I/O interface|
|tHZ|Enable to Pad delay through the Output Buffer—High to Z|
|tZH|Enable to Pad delay through the Output Buffer—Z to High|
|tLZ|Enable to Pad delay through the Output Buffer—Low to Z|
|tZL|Enable to Pad delay through the Output Buffer—Z to Low|
|tZHS|Enable to Pad delay through the Output Buffer with delayed enable—Z to High|
|tZLS|Enable to Pad delay through the Output Buffer with delayed enable—Z to Low|
**Revision 18**
**2-22**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-24 •**_ **Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Advanced I/O Banks**
|**I/O Standard**|**Drive Strength**|**Equiv. Software Default**<br>**Drive Strength Option1**|**Slew Rate**|**Capacitive Load (pF)**|**External Resistor (****)**|**tDOUT (ns)**|**tDP (ns)**|**tDIN (ns)**|**tPY (ns)**|**tEOUT (ns)**|**tZL (ns)**|**tZH (ns)**|**tLZ (ns)**|**tHZ (ns)**|**tZLS (ns)**|**tZHS (ns)**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|3.3 V LVTTL /<br>3.3 V LVCMOS|12 mA 12 mA|12 mA 12 mA|High 35|High 35|– 0.45|– 0.45|2.64|0.03|0.76|0.32|2.69|2.11|2.40|2.68|4.36|3.78|ns|
|3.3 V LVCMOS<br>Wide Range2<br>~~PoE~~|100 µA<br>~~PoE~~|12 mA|High 35|High 35|– 0.45|– 0.45|4.08|0.03|0.76|0.32|4.08|3.20|3.71|4.14|6.61|5.74|ns|
|2.5 V LVCMOS<br>~~PoE~~<br>~~PoE~~|12 mA 12 mA<br>~~PoE~~<br>~~PoE~~|12 mA 12 mA|High 35|High 35|– 0.45|– 0.45|2.66|0.03|0.98|0.32|2.71|2.56|2.47|2.57|4.38|4.23|ns|
|1.8 V LVCMOS<br>~~PoE~~<br>~~PoE~~|12 mA<br>~~PoE~~<br>~~PoE~~|12 mA|High 35|High 35|– 0.45|– 0.45|2.64|0.03|0.91|0.32|2.69|2.27|2.76|3.05|4.36|3.94|ns|
|1.5 V LVCMOS<br>~~PoE~~|12 mA<br>~~PoE~~|12 mA|High 35|High 35|– 0.45|– 0.45|3.05|0.03|1.07|0.32|3.10|2.67|2.95|3.14|4.77|4.34|ns|
|3.3 V PCI|Per<br>PCI<br>spec|–|High 10|High 10|254|0.45|2.00|0.03|0.65|0.32|2.04|1.46|2.40|2.68|3.71|3.13|ns|
|3.3 V PCI-X|Per<br>PCI-X<br>spec|–|High 10 25|High 10 25|High 10 254|0.45|2.00|0.03|0.62|0.32|2.04|1.46|2.40|2.68|3.71|3.13|ns|
|LVDS<br>~~PE~~<br>~~PCE~~|24 mA<br>~~PE~~<br>~~PCErE~~|–<br>~~rE~~|High –<br>~~ET~~|High –<br>~~ET~~|– 0.45<br>~~ET~~|– 0.45 <br>~~ETTt~~|1.37 <br>~~Tt~~|0.03 <br>~~TttT~~|1.20<br>~~tT~~|–<br>~~tT~~|–|–|–|–|–|–|ns|
|LVPECL<br>~~PCE~~|24 mA<br>~~PCErE~~|–<br>~~rE~~|High –<br>~~ET~~|High –<br>~~ET~~|– 0.45<br>~~ET~~|– 0.45 <br>~~ETTt~~|1.34 <br>~~Tt~~|0.03 <br>~~TttT~~|1.05<br>~~tT~~|–<br>~~tT~~|–|–|–|–|–|–|ns|
## _Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-64 for connectivity. This resistor is not required during normal operation._
**2-23**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-25 •**_ **Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Standard Plus I/O Banks**
|**I/O Standard**|**Drive Strength**|**Equiv. Software Default**<br>**Drive Strength Option1**|**Slew Rate**|**Capacitive Load (pF)**|**External Resistor**|**tDOUT (ns)**|**tDP (ns)**|**tDIN (ns)**|**tPY (ns)**|**tEOUT (ns)**|**tZL (ns)**|**tZH (ns)**|**tLZ (ns)**|**tHZ (ns)**|**tZLS (ns)**|**tZHS (ns)**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|3.3 V LVTTL /<br>3.3 V LVCMOS|12 mA 12 mA|12 mA 12 mA|High|35|–|0.45|2.36|0.03|0.75|0.32|2.40|1.93|2.08|2.41|4.07|3.60|ns|
|3.3 V LVCMOS<br>Wide Range2<br>~~PTT~~|100 µA 12 mA<br>~~PTT~~|100 µA 12 mA <br>~~PTT~~|High|35|–|0.45|3.65|0.03|1.14|0.32|3.65|2.93|3.22|3.72|6.18|5.46|ns|
|2.5 V LVCMOS <br>~~PTT~~|12 mA 12 mA<br>~~PTT~~|12 mA 12 mA <br>~~PTT~~|High|35|–|0.45|2.39|0.03|0.97|0.32|2.44|2.35|2.11 <br>~~eee~~|2.32 <br>~~eee~~|4.11 <br>~~eee~~|4.02 <br>~~eee~~|ns<br>~~eee~~|
|1.8 V LVCMOS<br>~~PTT~~<br>~~eee~~|8 mA 8 mA<br>~~PTT~~<br>~~eee~~|8 mA 8 mA <br>~~PTT~~<br>~~eee~~|High <br>~~eee~~|35<br>~~eee~~|–<br>~~eee~~|0.45 <br>~~eee~~|3.03 <br>~~eee~~|0.03 <br>~~eee~~|0.90 <br>~~eee~~|0.32 <br>~~eee~~|2.87 <br>~~eee~~|3.03 <br>~~eee~~|2.19 <br>~~eee~~<br>~~eee~~|2.32 <br>~~eee~~<br>~~eee~~|4.54 <br>~~eee~~<br>~~eee~~|4.70 <br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|1.5 V LVCMOS|4 mA 4 mA|4 mA 4 mA|High|35|–|0.45|3.61|0.03|1.06|0.32|3.35|3.61|2.26 <br>~~eee~~|2.34 <br>~~eee~~|5.02 <br>~~eee~~|5.28 <br>~~eee~~|ns<br>~~eee~~|
|3.3 V PCI|Per<br>PCI<br>spec|–|High|10|2540.45|0.45|1.72|0.03|0.64|0.32|1.76|1.27|2.08|2.41|3.42|2.94|ns|
|3.3 V PCI-X|Per<br>PCI-X<br>spec|–|High|10|2540.45|0.45|1.72|0.03|0.62|0.32|1.76|1.27|2.08|2.41|3.42|2.94|ns|
_Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-64 for connectivity. This resistor is not required during normal operation._
**Revision 18**
**2-24**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-26 •**_ **Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Standard I/O Banks**
|**I/O Standard**|**Drive Strength**|**Equiv. Software Default**<br>**Drive Strength Option1**|**Slew Rate**|**Capacitive Load (pF)**|**External Resistor**|**tDOUT (ns)**|**tDP (ns)**|**tDIN (ns)**|**tPY (ns)**|**tEOUT (ns)**|**tZL (ns)**|**tZH (ns)**|**tLZ (ns)**|**tHZ (ns)**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|3.3 V LVTTL /<br>3.3 V LVCMOS|8 mA|8 mA|High|35|–|0.45|3.29|0.03|0.75|0.32|3.36|2.80|1.79|2.01|ns|
|3.3 V LVCMOS<br>Wide Range2<br>~~ee~~<br>~~rr~~|100 µA <br>~~ee~~|8 mA<br>~~ee~~|High<br>~~ee~~|35<br>~~ee~~|–<br>~~ee~~|0.45<br>~~ee~~|5.09<br>~~ee~~|0.03<br>~~ee~~|1.13<br>~~ee~~|0.32<br>~~ee~~|5.09<br>~~ee~~<br>~~e~~|4.25<br>~~ee~~<br>~~e~~|2.77<br>~~ee~~<br>~~e~~~~**e**~~|3.11<br>~~ee~~<br>~~**e**e~~|ns<br>~~ee~~<br>~~e~~|
|2.5 V LVCMOS<br>~~ee~~<br>~~rr~~|8 mA<br>~~ee~~<br>~~ee~~|8 mA<br>~~ee~~<br>~~ee~~|High<br>~~ee~~<br>~~eee~~|35<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|0.45<br>~~ee~~<br>~~eee~~|3.56<br>~~ee~~<br>~~eee~~|0.03<br>~~ee~~<br>~~ee~~|0.96<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~e~~|3.40<br>~~ee~~<br>~~e~~<br>~~e~~|3.56<br>~~ee~~<br>~~e~~<br>~~e~~|1.78<br>~~ee~~<br>~~e~~~~**e**~~|1.91<br>~~ee~~<br>~~**e**e~~|ns<br>~~ee~~<br>~~e~~|
|1.8 V LVCMOS<br>~~ee ~~<br>~~rr~~<br>~~PE~~|4 mA<br> ~~ee ~~<br>~~ee~~<br>~~PEEE~~|4 mA<br> ~~ee ~~<br>~~ee~~<br>~~EE~~|High<br> ~~ee~~<br>~~eee~~<br>~~EE~~|35<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|0.45<br>~~ee~~<br>~~eee~~|4.74<br>~~ee~~<br>~~eee~~|0.03<br>~~ee~~<br>~~ee~~|0.90<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~e~~|4.02<br>~~ee~~<br>~~e~~<br>~~e~~|4.74<br>~~ee~~<br>~~e~~<br>~~e~~|1.80<br>~~ee~~<br>~~e~~~~**e**~~|1.85<br>~~ee~~<br>~~**e**e~~|ns<br>~~ee~~<br>~~e~~|
|1.5 V LVCMOS<br>~~rr~~<br>~~PE~~|2 mA<br>~~ee ~~<br>~~PEEE~~|2 mA<br> ~~ee ~~<br>~~EE~~|High<br> ~~eee~~<br>~~EE~~|35<br>~~eee~~|–<br>~~eee~~|0.45<br>~~eee~~|5.71<br>~~eee ~~|0.03<br> ~~ee~~|1.06<br>~~ee~~|0.32<br>~~e~~|4.71<br>~~e~~<br>~~e~~|5.71<br>~~e~~<br>~~e~~|1.83<br>~~e~~~~**e**~~|1.83<br>~~**e**e~~|ns<br>~~e~~|
## _Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-25**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **I/O DC Characteristics**
_**Table 2-27 •**_ **Input Capacitance**
|**_Table 2-27 •_**|**_Table 2-27 •_Input Capacitance**|||||
|---|---|---|---|---|---|
|**Symbol**|**Definition**|**Conditions**|**Min**|**Max**|**Units**|
|CIN|Input capacitance|VIN = 0, f = 1.0 MHz|–|8|pF|
|CINCLK|Input capacitance on the clock pin|VIN = 0, f = 1.0 MHz|–|8|pF|
_**Table 2-28 •**_ **I/O Output Buffer Maximum Resistances[1]**
**Applicable to Advanced I/O Banks**
|**Applicable to Advanced I/O Banks**|**Applicable to Advanced I/O Banks**<br>~~es~~|||
|---|---|---|---|
|**Standard**<br>~~es~~|**Drive Strength**<br>~~es~~<br>~~es~~|**RPULL-DOWN (****)2**<br>~~es~~<br>~~es~~|**RPULL-UP(****)3**<br>~~es~~|
|3.3 V LVTTL / 3.3 V LVCMOS|2 mA<br>~~es~~<br>~~ee~~|100<br>~~ee~~<br>~~es~~<br>~~es~~|300<br>~~ee~~|
||4 mA<br>~~ee~~|100<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|300<br>~~ee~~|
||6 mA<br>~~ee~~|50<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|150<br>~~ee~~|
||8 mA<br>~~ee~~<br>~~ee~~|50<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>|150<br>~~ee~~|
||12 mA<br>~~ee~~<br>~~ee~~|25<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|75<br>~~ee~~|
||16 mA<br>~~ee~~|17<br>~~es~~<br>~~ee~~<br>~~es~~|50|
||24 mA<br>~~ee ~~<br>~~ee~~|11<br>~~es~~<br> ~~ee~~<br>~~ee~~<br>~~es~~|33<br>~~ee~~|
|3.3 V LVCMOS Wide Range4|100 µA<br>~~ee~~|Same as regular 3.3 V<br>LVCMOS<br>~~es~~<br>~~ee~~|Same as regular 3.3 V<br>LVCMOS|
|2.5 V LVCMOS|2 mA<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~|200|
||4 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|100<br> ~~ee~~<br>~~ee~~<br>~~ee~~|200|
||6 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|50<br> ~~ee~~<br>~~ee~~<br>~~ee~~|100|
||8 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|50<br> ~~ee~~<br>~~ee~~<br>~~ee~~|100|
||12 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|25<br> ~~ee~~<br>~~ee~~<br>~~ee~~|50|
||16 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|20<br> ~~ee~~<br>~~ee~~<br>~~ee~~|40|
||24 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|11<br> ~~ee~~<br>~~ee~~<br>~~ee~~|22|
|1.8 V LVCMOS|2 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|200<br> ~~ee~~<br>~~ee~~<br>~~ee~~|225|
||4 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|100<br> ~~ee~~<br>~~ee~~<br>~~ee~~|112|
||6 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|50<br> ~~ee~~<br>~~ee~~<br>~~ee~~|56|
||8 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|50<br> ~~ee~~<br>~~ee~~<br>~~ee~~|56|
||12 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|20<br> ~~ee~~<br>~~ee~~<br>~~ee~~|22|
||16 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|20<br> ~~ee~~<br>~~ee~~<br>~~ee~~|22|
|1.5 V LVCMOS|2 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|200<br> ~~ee~~<br>~~ee~~<br>~~es~~<br>|224|
||4 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|100<br> ~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|112<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|67<br>~~es~~<br>~~ee~~<br>~~**ee**~~|75|
||8 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|33<br>~~es~~<br> ~~ee~~<br>~~**ee**~~|37|
||12 mA<br> <br>~~ee ~~<br>~~ee~~|33<br> ~~ee~~<br> ~~**ee**~~|37|
|3.3 V PCI/PCI-X|Per PCI/PCI-X<br>specification<br> <br>~~ee~~|25<br> ~~**ee**~~|75|
_Notes:_
_1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx._
_2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec_
_3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec_
_4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
**Revision 18**
**2-26**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-29 •**_ **I/O Output Buffer Maximum Resistances[1]**
**Applicable to Standard Plus I/O Banks**
|**Standard**<br>~~a~~|**Drive Strength**<br>~~ee~~<br>~~ee~~|**RPULL-DOWN (****)2**<br>~~ee~~<br>~~ee~~<br>|**RPULL-UP(****)3**<br>~~ee~~|
|---|---|---|---|
|3.3 V LVTTL / 3.3 V<br>LVCMOS<br>~~a~~|2 mA<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|300<br>~~ee~~<br>~~ee~~|
||4 mA<br>~~ee~~<br>~~ee~~<br>~~a~~|100<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|300<br>|
||6 mA<br>~~ee ~~<br>~~ee~~<br>~~a~~|50<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>|150<br>|
||8 mA<br> <br>~~ee ~~<br>~~a ~~|50<br> ~~ee~~<br> ~~ee~~<br> ~~es~~|150<br>~~es~~|
||12 mA<br>~~a ~~<br>~~ee~~|25<br> ~~es~~<br>~~ee~~|75<br>~~es~~|
||16 mA<br>~~ee~~|25<br>~~ee~~|75|
|3.3 V LVCMOS Wide<br>Range4|100 µA<br>~~ee ~~<br>~~ee~~|Same as regular 3.3 V LVCMOS <br> ~~ee~~<br>~~ee~~|Same as regular 3.3 V LVCMOS|
|2.5 V LVCMOS|2 mA<br>~~ee~~|100<br>~~ee~~|200|
||4 mA<br>~~ee ~~<br>~~a ~~|100<br> ~~ee~~<br> ~~es~~|200<br>~~es~~|
||6 mA<br>~~a ~~<br>~~ee ee~~|50<br> ~~es~~<br>~~ee~~|100<br>~~es~~|
||8 mA<br>~~ee ee~~<br>~~es~~|50<br>~~ee~~<br>~~ee~~<br>|100|
||12 mA<br>~~ee ee~~<br>~~ee~~<br>~~es ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|50<br>~~ee~~|
|1.8 V LVCMOS|2 mA<br>~~es ee~~<br>~~ee~~<br>~~a~~|200<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|225<br>|
||4 mA<br>~~es ee~~<br>~~ee~~<br>~~a~~|100<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|112<br>|
||6 mA<br>~~ee~~<br>~~ee ~~<br>~~a ~~<br>~~a~~|50<br>~~ee~~<br> ~~ee~~<br> ~~es~~<br>~~es~~|56<br>~~es~~|
||8 mA<br>~~a~~<br>~~ee~~|50<br>~~es~~<br>~~ee~~|56|
|1.5 V LVCMOS|2 mA<br>~~a~~<br>~~ee~~|200<br>~~es~~<br>~~ee~~<br>~~ee~~|224|
||4 mA<br>~~ee ~~<br>~~ee~~|100<br> ~~ee~~<br>~~ee~~<br>~~ee~~|112<br>~~ee~~|
|3.3 V PCI/PCI-X|Per PCI/PCI-X<br>specification|25<br>~~ee~~|75|
_Notes:_
_1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx._
_2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec_
_3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec_
_4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
**2-27**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-30 •**_ **I/O Output Buffer Maximum Resistances[1] Applicable to Standard I/O Banks**
|**Standard**|**Drive Strength**|**RPULL-DOWN**<br>**(****)2**|**RPULL-UP**<br>**(****)3**|
|---|---|---|---|
|3.3 V LVTTL / 3.3 V LVCMOS|2 mA|100|300|
||4 mA|100|300|
||6 mA|50|150|
||8 mA|50|150|
|3.3 V LVCMOS Wide Range4|100 µA|Same as regular 3.3 V<br>LVCMOS|Same as regular<br>3.3 V LVCMOS|
|2.5 V LVCMOS|2 mA|100|200|
||4 mA|100|200|
||6 mA|50|100|
||8 mA|50|100|
|1.8 V LVCMOS|2 mA|200|225|
||4 mA|100|112|
|1.5 V LVCMOS|2 mA|200|224|
## _Notes:_
_1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx._
_2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec_
_3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec_
_4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
_**Table 2-31 •**_ **I/O Weak Pull-Up/Pull-Down Resistances**
**Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values**
|**VCCI**|**R(WEAK PULL-UP)**<br>**1**<br>**(****)**|**R(WEAK PULL-UP)**<br>**1**<br>**(****)**|**R(WEAK PULL-DOWN)**<br>**2**<br>**(****)**|**R(WEAK PULL-DOWN)**<br>**2**<br>**(****)**|
|---|---|---|---|---|
||**Min**|**Max**|**Min**|**Max**|
|3.3 V|10 k|45 k|10 k|45 k|
|3.3 V (wide range I/Os)|10 k|45 k|10 k|45 k|
|2.5 V|11 k|55 k|12 k|74 k|
|1.8 V|18 k|70 k|17 k|110 k|
|1.5 V|19 k|90 k|19 k|140 k|
_Notes:_
_1. R(WEAK PULL-UP-MAX) = (VCCIMAX – VOHspec) / I(WEAK PULL-UP-MIN)_
_2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)_
**Revision 18**
**2-28**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-32 •**_ **I/O Short Currents IOSH/IOSL**
**Applicable to Advanced I/O Banks**
||~~es~~|~~es~~||
|---|---|---|---|
|~~ee~~|**Drive Strength**<br>~~ee~~<br>~~es~~|**IOSL (mA)1**<br>~~ee~~<br>~~es~~<br>~~ee~~|**IOSH (mA)1**<br>~~ee~~<br>~~ee~~|
|3.3 V LVTTL / 3.3 V LVCMOS|2 mA<br>~~es~~<br>~~ee~~|27<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~s~~|25<br>~~ee~~<br>~~ee~~|
||4 mA<br>~~e~~|27<br>~~ee~~<br>~~e~~~~**e**~~<br>~~s~~<br>~~ee~~|25<br>~~ee~~<br>~~**e**~~|
||6 mA<br>~~ee~~<br>~~ee~~|54<br>~~s~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|51<br>~~ee~~|
||8 mA<br>~~ee~~<br>~~ee~~|54<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|51<br>~~ee~~|
||12 mA<br>~~ee~~<br>~~ee~~|109<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|103<br>~~ee~~|
||16 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|127<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~**e**e~~<br>~~e~~|132<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||24 mA<br>~~ee~~|181<br>~~**e**e~~<br>~~e~~|268<br>~~ee~~<br>~~ee~~|
|3.3 V LVCMOS Wide Range2|100 µA<br>~~ee~~<br>~~ee~~|Same as regular 3.3 V<br>LVCMOS<br>~~**e**e~~<br>~~e ~~<br>~~ee~~<br>|Same as regular 3.3 V<br>LVCMOS<br>~~ee~~<br> ~~ee~~|
|2.5 V LVCMOS|2 mA<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~<br>~~ee~~|16<br>~~ee~~|
||4 mA<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|16<br>~~ee~~<br>|
||6 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|32<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||8 mA<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|32<br>~~ee~~<br>~~eee~~|
||12 mA<br>~~ee ~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|74<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|65<br>~~ee~~<br>~~eee~~|
||16 mA<br> <br>~~ee ee~~<br>~~ee~~<br>~~ee~~|87<br> ~~ee ~~<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|83<br> ~~eee~~<br>~~ee~~|
||24 mA<br>~~ee~~<br>~~ee ~~<br>~~ee~~|124<br>~~ee~~<br> ~~e~~~~**e**~~<br>~~e~~<br>~~e~~|169<br>~~ee~~|
|1.8 V LVCMOS|2 mA<br> <br>~~ee ~~<br>~~e~~<br>~~ee~~|11<br> ~~e~~~~**e**~~<br> ~~e~~<br>~~e~~~~**e**~~<br>~~e~~<br>~~**e**e~~|9<br>~~ee~~<br>~~**e**~~<br>~~ee~~|
||4 mA<br>~~ee~~<br>~~ee~~|22<br>~~e~~<br>~~ee~~<br>~~**e**e~~<br>~~e~~|17<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~ee~~|44<br>~~**e**e~~<br>~~e~~<br>~~ee~~<br>|35<br>~~ee~~<br>~~ee~~|
||8 mA<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|51<br>~~**e**e~~<br>~~e ~~<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|45<br>~~ee~~<br> ~~ee~~<br>~~ee~~|
||12 mA<br>~~ee~~<br>~~ee~~|74<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|91<br>~~ee~~|
||16 mA<br>~~ee ~~<br>~~ee~~|74<br>~~ee~~<br> ~~e~~~~**e**~~<br>~~e~~<br>~~e~~|91<br>~~ee~~|
|1.5 V LVCMOS|2 mA<br> <br>~~ee ~~<br>~~e~~<br>~~ee~~|16<br> ~~e~~~~**e**~~<br> ~~e~~<br>~~e~~~~**e**~~<br>~~e~~<br>~~**e**e~~|13<br>~~ee~~<br>~~**e**~~<br>~~ee~~|
||4 mA<br>~~ee~~<br>~~ee~~|33<br>~~e~~<br>~~ee~~<br>~~**e**e~~<br>~~e~~|25<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||6 mA<br>~~ee~~|39<br>~~**e**e~~<br>~~e~~<br>~~ee~~|32<br>~~ee~~<br>~~ee~~|
||8 mA<br>~~ee~~<br>~~ee~~|55<br>~~**e**e~~<br>~~e ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|66<br>~~ee~~<br> ~~ee~~<br>~~ee~~|
||12 mA<br>~~ee~~|55<br>~~ee~~<br>~~ee~~<br>~~ee~~|66<br>~~ee~~|
|3.3 V PCI/PCI-X|Per PCI/PCI-X<br>specification|109<br>~~ee~~|103|
_Notes:_
_1. TJ = 100°C_
_2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
**2-29**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-33 •**_ **I/O Short Currents IOSH/IOSL**
||~~ee~~|~~ee~~||
|---|---|---|---|
|~~ae~~|**Drive Strength**<br>~~ae~~<br>~~ee~~<br>~~ee~~|**IOSL (mA)1**<br>~~ae~~<br>~~ee~~<br>~~ee~~<br>|**IOSH (mA)1**<br>~~ae~~|
|3.3 V LVTTL / 3.3 V LVCMOS|2 mA<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|27<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|25<br>~~ee~~|
||4 mA<br>~~ee ee~~<br>~~ee~~|27<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|25|
||6 mA<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|54<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|51<br>~~ee~~|
||8 mA<br>~~ee~~<br>~~ee~~|54<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|51|
||12 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|109<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~**e**e~~<br>~~e~~|103<br>~~ee~~<br>~~ee~~|
||16 mA<br>~~ee~~|109<br>~~**e**e~~<br>~~e~~|103<br>~~ee~~|
|3.3 V LVCMOS Wide Range2|100 µA<br>~~ee~~<br>~~ee~~|Same as regular<br>3.3 V LVCMOS<br>~~**e**e~~<br>~~e ~~<br>~~ee~~|Same as regular 3.3 V<br>LVCMOS<br> ~~ee~~|
|2.5 V LVCMOS|2 mA<br>~~ee~~<br>~~ee ee~~|18<br>~~ee~~<br>~~ee~~|16|
||4 mA<br>~~ee ~~<br>~~ee ee~~<br>~~ee~~|18<br> ~~ee~~<br>~~ee~~<br>~~**e**e~~|16|
||6 mA<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~<br>~~**e**e~~<br>~~e~~|32<br>~~ee~~<br>~~ee~~|
||8 mA<br>~~ee~~|37<br>~~**e**e~~<br>~~e~~<br>~~ee~~|32<br>~~ee~~<br>~~ee~~|
||12 mA<br>~~ee~~<br>~~ee~~|74<br>~~**e**e~~<br>~~e ~~<br>~~ee~~<br>~~ee~~<br>~~e~~|65<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|1.8 V LVCMOS|2 mA<br>~~e~~<br>~~ee~~|11<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~<br>~~ee~~<br>|9<br>~~ee~~<br>~~**e**~~|
||4 mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|22<br>~~e~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|17<br>~~ee~~|
||6 mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|44<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|35<br>|
||8 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|44<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~**ee**~~|35<br>~~**ee**~~|
|1.5 V LVCMOS|2 mA<br> <br>~~ee ~~<br>~~ee~~<br>~~ee~~|16<br> ~~ee~~<br> ~~ee~~<br>~~**ee**~~|13<br>~~**ee**~~|
||4 mA<br> <br>~~ee ~~<br>~~ee~~|33<br> ~~ee~~<br> ~~**ee**~~|25<br>~~**ee**~~|
|3.3 V PCI/PCI-X|Per PCI/PCI-X<br>specification<br> <br>~~ee~~|109<br> ~~**ee** ~~|103<br> ~~**ee**~~|
_Notes:_
_1. TJ = 100°C_
_2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8B specification._
**Revision 18**
**2-30**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-34 •**_ **I/O Short Currents IOSH/IOSL**
**Applicable to Standard I/O Banks**
||**Drive Strength**|**IOSL (mA)1**|**IOSH (mA)1**|
|---|---|---|---|
|3.3 V LVTTL / 3.3 V LVCMOS|2 mA|27|25|
||4 mA|27|25|
||6 mA|54|51|
||8 mA|54|51|
|3.3 V LVCMOS Wide Range2|100 µA|Same as regular 3.3 V<br>LVCMOS|Same as regular 3.3 V<br>LVCMOS|
|2.5 V LVCMOS|2 mA|18|16|
||4 mA|18|16|
||6 mA|37|32|
||8 mA|37|32|
|1.8 V LVCMOS|2 mA|11|9|
||4 mA|22|17|
|1.5 V LVCMOS|2 mA|16|13|
_Notes:_
_1. TJ = 100°C_
_2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification._
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions.
_**Table 2-35 •**_ **Duration of Short Circuit Event Before Failure**
|**Temperature**|**Time before Failure**|
|---|---|
|–40°C|> 20 years|
|0°C|> 20 years|
|25°C|> 20 years|
|70°C|5 years|
|85°C|2 years|
|100°C|0.5 years|
_**Table 2-36 •**_ **I/O Input Rise Time, Fall Time, and Related I/O Reliability**
|**Input Buffer**|**Input Rise/Fall Time (min)**|**Input Rise/Fall Time (max)**|**Reliability**|
|---|---|---|---|
|LVTTL/LVCMOS|No requirement|10 ns *|20 years (110°C)|
|LVDS/B-LVDS/<br>M-LVDS/LVPECL|No requirement|10 ns *|10 years (100°C)|
_Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals._
**2-31**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **Single-Ended I/O Characteristics**
## _**3.3 V LVTTL / 3.3 V LVCMOS**_
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer.
## _**Table 2-37 •**_ **Minimum and Maximum DC Input and Output Levels**
## **Applicable to Advanced I/O Banks**
|**3.3 V LVTTL /**<br>**3.3 V LVCMOS**<br>~~ee~~<br>~~ft~~<br>~~Re~~|**VIL**<br>~~ee~~<br>~~ftrtEt~~<br>|**VIL**<br>~~ee~~<br>~~ftrtEt~~<br>|**VIH**<br>~~ee~~<br>~~ee~~<br>~~Et~~|**VIH**<br>~~ee~~<br>~~ee~~<br>~~Et~~|**VOL**<br>~~ee~~<br>~~ee~~|**VOH**<br>~~ee~~<br>|**IOL **<br>~~ee~~<br>|**IOH**<br>~~ee~~<br>~~eee~~|**IOSL**<br>~~ee~~<br>~~eee~~|**IOSH**<br>~~ee~~<br>~~eee~~|**IIL1 **<br>~~ee~~<br>~~eee~~|**IIH2**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**<br>~~ft~~<br>~~Re~~<br>~~a~~|**Min**<br>**V**<br>~~ftrt~~<br>~~i~~|**Max**<br>**V**<br>~~rtEt~~<br>~~ed ee~~|**Min**<br>**V**<br>~~ee~~<br>~~Et~~<br>~~ee rs~~|**Max**<br>**V**<br>~~ee~~<br>~~Et~~<br>~~rs~~|**Max**<br>**V**<br>~~ee~~<br>~~eG~~|**Min**<br>**V**<br><br>~~eG~~|**mA **<br><br>~~eG Gr~~|**mA**<br>~~eee~~<br>~~Gr~~|**Max**<br>**mA3**<br>~~eee~~<br>~~Gr~~|**Max**<br>**mA3**<br>~~eee~~|**µA4 **<br>~~eee~~|**µA4**<br>~~eee~~|
|2 mA<br>~~ft~~<br>~~Re~~<br>~~a~~<br>~~Re~~|–0.3<br>~~ft rt~~<br>~~i~~<br>~~ee~~<br>|0.8<br>~~rtEt~~<br>~~ed ee~~<br>~~es~~|2<br>~~ee~~<br>~~Et~~<br>~~ee rs~~<br>~~ee~~|3.6<br>~~ee~~<br>~~Et~~<br>~~rs~~<br>~~es~~|0.4<br>~~ee ~~<br>~~eG~~<br>~~ee~~|2.4<br> <br>~~eG~~<br>~~ee~~|2<br> <br>~~eG Gr~~<br>~~Gs~~|2<br> ~~eee~~<br>~~Gr~~<br>~~Ge~~|27<br>~~eee~~<br>~~Gr~~|25<br>~~eee~~|10 10<br>~~eee~~|10 10<br>~~eee~~|
|4 mA<br><br>~~Re~~<br>~~a~~<br>~~Re~~<br>~~ee~~|–0.3<br> ~~rt~~<br>~~i~~<br>~~ee~~<br>~~i~~<br>|0.8<br>~~rt Et~~<br>~~ed ee~~<br>~~es~~<br>~~ed~~<br>|2<br>~~Et~~<br>~~ee rs~~<br>~~ee~~<br>~~ee~~<br>|3.6<br>~~Et~~<br>~~rs ~~<br>~~es~~<br>~~rs~~<br>|0.4<br> ~~eG~~<br>~~ee~~<br>~~eG~~<br>|2.4<br>~~eG~~<br>~~ee~~<br>~~eG~~<br>|4<br>~~eG Gr~~<br>~~Gs~~<br>~~eG Gr~~|4<br>~~Gr~~<br>~~Ge~~<br>~~Gr~~|27<br>~~Gr~~<br>~~Gr~~|25|10 10|10 10|
|6 mA<br>~~Re~~<br>~~ee~~<br>~~ee~~|–0.3<br>~~ee~~<br>~~i~~<br>~~ee~~<br>|0.8<br>~~es~~<br>~~ed~~<br>~~ee~~<br>|2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.6<br>~~es~~<br>~~rs~~<br>~~ee~~<br>|0.4<br>~~ee~~<br>~~eG~~<br>~~ee~~<br>|2.4<br>~~ee~~<br>~~eG~~<br>~~ee~~<br>|6<br>~~Gs~~<br>~~eG Gr~~<br>|6<br>~~Ge~~<br>~~Gr~~<br>~~eee~~<br>|54<br>~~Gr~~<br>~~eee~~|51<br>~~eee~~|10 10<br>~~eee~~|10 10<br>~~eee~~|
|8 mA<br>~~Re~~<br>~~ee~~<br>~~ee~~<br>~~a~~|–0.3<br>~~ee ~~<br>~~i~~<br>~~ee~~<br>~~ee i~~|0.8<br> ~~es~~<br>~~ed~~<br>~~ee~~<br>~~i~~|2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.6<br>~~es ~~<br>~~rs~~<br>~~ee~~<br>~~ee~~|0.4<br> ~~ee~~<br>~~eG~~<br>~~ee~~<br>~~ee Ge~~|2.4<br>~~ee~~<br>~~eG~~<br>~~ee~~<br>~~Ge Gs~~|8<br>~~Gs ~~<br>~~eG Gr~~<br>~~Gs~~|8<br> ~~Ge~~<br>~~Gr~~<br>~~eee~~<br>~~ee~~|54<br>~~Gr~~<br>~~eee~~|51<br>~~eee~~|10 10<br>~~eee~~|10 10<br>~~eee~~|
|12 mA<br><br>~~ee ~~<br>~~ee~~<br>~~a~~<br>~~Re~~|–0.3<br>~~i~~<br> ~~ee~~<br>~~ee i~~<br>~~ee~~|0.8<br>~~ed ~~<br>~~ee~~<br>~~i~~<br>~~**e**s~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~|3.6<br> ~~rs ~~<br>~~ee~~<br>~~ee~~<br>~~es~~|0.4<br> ~~eG~~<br>~~ee~~<br>~~ee Ge~~<br>~~ee~~|2.4<br>~~eG~~<br>~~ee~~<br>~~Ge Gs~~<br>~~Ge~~|12<br>~~eG Gr~~<br>~~Gs~~<br>~~Ge~~|12<br>~~Gr~~<br>~~eee~~<br>~~ee~~<br>~~**G**e~~|109<br>~~Gr~~<br>~~eee~~|103<br>~~eee~~|10<br>~~eee~~|10<br>~~eee~~|
|16 mA<br> <br>~~ee ~~<br>~~a~~<br>~~Re~~|–0.3<br> ~~ee ~~<br> ~~ee i~~<br>~~ee~~<br>~~e~~|0.8<br> ~~ee ~~<br>~~i ~~<br>~~**e**s~~<br>~~e~~|2<br> ~~ee~~<br> ~~ee ~~<br>~~e~~~~**e**~~<br>~~r~~|3.6<br>~~ee ~~<br> ~~ee ~~<br>~~es~~<br>~~rs~~|0.4<br> ~~ee ~~<br> ~~ee Ge~~<br>~~ee~~<br>~~es~~|2.4<br> ~~ee~~<br>~~Ge Gs~~<br>~~Ge~~<br>~~es~~|16 16<br>~~Gs~~ <br>~~Ge~~<br>~~Ge~~|16 16<br>~~eee~~<br> ~~ee~~<br>~~**G**e~~|127<br>~~eee ~~<br>~~e~~|132<br> ~~eee~~<br>~~e~~|10 10<br>~~eee~~|10 10<br>~~eee~~|
|24 mA<br>~~Re~~|–0.3<br>~~ee~~<br>~~e~~|0.8<br>~~**e**s~~<br>~~e~~|2<br>~~e~~~~**e**~~<br>~~r~~|3.6<br>~~es~~<br>~~rs~~|0.4<br>~~ee~~<br>~~es~~|2.4<br>~~Ge~~<br>~~es~~|24<br>~~Ge~~<br>~~Ge~~|24<br>~~**G**e~~|181<br>~~e~~|268<br>~~e~~|10 10|10 10|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at 100°C junction temperature and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
_**Table 2-38 •**_ **Minimum and Maximum DC Input and Output Levels**
**Applicable to Standard Plus I/O Banks**
|**3.3 V LVTTL /**<br>**3.3 V LVCMOS**<br>~~eee~~<br>~~Pt~~|VIL<br>~~eee~~<br>~~PtFE~~|VIL<br>~~eee~~<br>~~PtFE~~|VIH<br>~~eee~~<br>~~FETE~~|VIH<br>~~eee~~<br>~~FETE~~|VOL<br>~~eee~~<br>~~TE~~|VOH<br>~~eee~~|**IOL**<br>~~eee~~|**IOH**<br>~~eee~~|**IOSL**<br>~~eee~~|**IOSH**<br>~~eee~~|**IIL1**<br>~~eee~~|**IIH2**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**<br>~~Pt~~<br>~~Re a~~|**Min**<br>**V**<br>~~PtFE~~<br>~~a~~|**Max**<br>**V**<br>~~FE~~<br>~~es~~|**Min**<br>**V**<br>~~FETE~~<br>~~ed~~|**Max**<br>**V**<br>~~TE~~<br>~~rs~~|**Max**<br>**V**<br>~~TE~~|**Min**<br>**V**<br>~~es~~|**mA**<br>~~es~~|**mA**<br>~~es~~|**Max**<br>**mA3**<br>~~Ge~~|**Max**<br>**mA3**<br>~~GO~~|**µA4 **<br>~~GO~~|**µA4**|
|2 mA<br>~~Pt~~<br>~~Re a~~<br>~~ee ie~~|–0.3<br>~~Pt FE~~<br>~~a~~<br>~~ie~~|0.8<br>~~FE~~<br>~~es~~<br>~~es~~|2<br>~~FE TE~~<br>~~ed~~<br>~~ee~~|3.6<br>~~TE~~<br>~~rs~~<br>~~ee~~|0.4<br>~~TE~~|2.4<br>~~es~~<br>~~ds~~|2<br>~~es~~<br>~~ds~~|2<br>~~es~~<br>~~ds~~|27<br>~~Ge~~<br>~~ds~~|25<br>~~GO~~<br>~~OO~~|10<br>~~GO~~<br>~~OO~~|10|
|4 mA<br>~~Re a~~<br>~~ee ie~~<br>~~Re a~~|–0.3<br>~~a~~<br>~~ie~~<br>~~a~~|0.8<br>~~es ~~<br>~~es~~<br>~~es~~|2<br> ~~ed ~~<br>~~ee~~<br>~~ed~~|3.6<br> ~~rs~~<br>~~ee~~<br>~~rs~~|0.4|2.4<br>~~es~~<br>~~ds~~<br>~~es~~|4<br>~~es~~<br>~~ds~~<br>~~es~~|4<br>~~es~~<br>~~ds~~<br>~~es~~|27<br>~~Ge~~<br>~~ds~~<br>~~Ge~~|25<br>~~GO~~<br>~~OO~~<br>~~GO~~|10<br>~~GO~~<br>~~OO~~<br>~~GO~~|10|
|6 mA<br>~~ee ie~~<br>~~Re a~~<br>~~ee~~|–0.3<br>~~ie~~<br>~~a~~<br>~~ee~~|0.8<br>~~es ~~<br>~~es~~<br>~~ee~~|2<br> ~~ee~~<br>~~ed~~<br>~~ee~~|3.6<br>~~ee~~<br>~~rs~~<br>~~ee~~|0.4<br>~~ee~~|2.4<br>~~ds~~<br>~~es~~<br>~~ee~~|6<br>~~ds~~<br>~~es~~<br>~~ee~~|6<br>~~ds~~<br>~~es~~<br>~~ee~~|54<br>~~ds~~<br>~~Ge~~<br>~~ee~~|51<br>~~OO~~<br>~~GO~~<br>~~ee~~|10<br>~~OO~~<br>~~GO~~<br>~~ee~~|10<br>~~ee~~|
|8 mA<br>~~Re a~~<br>~~ee~~<br>~~ee i~~|–0.3<br>~~a~~<br>~~ee~~<br>~~i~~|0.8<br>~~es ~~<br>~~ee~~<br>~~ee~~|2<br> ~~ed ~~<br>~~ee~~<br>~~es~~|3.6<br> ~~rs~~<br>~~ee~~<br>~~es~~|0.4<br>~~ee~~<br>~~eG~~|2.4<br>~~es~~<br>~~ee~~<br>~~eG~~|8<br>~~es~~<br>~~ee~~<br>~~eG~~|8<br>~~es~~<br>~~ee~~<br>~~ed~~|54<br>~~Ge~~<br>~~ee~~<br>~~dO~~|51<br>~~GO~~<br>~~ee~~<br>~~dO~~|10<br>~~GO~~<br>~~ee~~<br>~~dO~~|10<br>~~ee~~|
|12 mA<br>~~ee ~~<br>~~ee i~~<br>~~Re~~|–0.3<br> ~~ee ~~<br>~~i~~<br>~~ee~~|0.8<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2<br> ~~ee~~<br>~~es~~<br>~~es~~|3.6<br>~~ee ~~<br>~~es~~<br>~~es~~|0.4<br> ~~ee~~<br>~~eG~~<br>~~ee~~|2.4<br>~~ee ~~<br>~~eG~~<br>~~es~~|12<br> ~~ee ~~<br>~~eG~~<br>~~es~~|12<br> ~~ee~~<br>~~ed~~<br>~~es~~|109<br>~~ee~~<br>~~dO~~|103<br>~~ee ~~<br>~~dO~~<br>~~GO~~|10<br> ~~ee~~<br>~~dO~~<br>~~GO~~|10<br>~~ee~~|
|16 mA<br>~~ee i~~<br>~~Re~~|–0.3<br>~~i~~<br>~~ee~~|0.8<br>~~ee~~<br>~~ee~~|2<br>~~es ~~<br>~~es~~|3.6<br> ~~es ~~<br>~~es~~|0.4<br> ~~eG~~<br>~~ee~~|2.4<br>~~eG~~<br>~~es~~|16<br>~~eG~~<br>~~es~~|16<br>~~ed ~~<br>~~es~~|109<br> ~~dO~~|103<br>~~dO~~<br>~~GO~~|10<br>~~dO~~<br>~~GO~~|10|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < V_ CCI _. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at 100°C junction temperature and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**Revision 18**
**2-32**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-39 •**_ **Minimum and Maximum DC Input and Output Levels**
## **Applicable to Standard I/O Banks**
|**3.3 V LVTTL /**<br>**3.3 V LVCMOS**<br>~~ee~~<br>~~tT~~|**VIL**<br>~~ee~~<br>~~tT~~|**VIL**<br>~~ee~~<br>~~tT~~|**VIH**<br>|**VIH**<br>|**VOL**<br>|**VOH**<br>~~eee~~<br>|**IOL**<br>~~eee~~<br>|**IOH**<br>~~eee~~<br>|**IOSL**<br>~~eee~~<br>|**IOSH**<br>~~eee~~<br>|**IIL1 **<br>~~eee~~<br>|**IIH2**<br>~~eee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**<br>~~ee~~<br>~~tT~~<br>~~ee~~<br>~~ee~~|**Min**<br>**V**<br>~~ee~~<br>~~tTEe~~<br>~~es~~<br>|**Max**<br>**V**<br>~~ee~~<br>~~Ee~~<br>~~es~~<br>|**Min**<br>**V**<br>~~Ee~~<br>~~ed~~<br>|**Max**<br>**V**<br>~~Ee~~<br>~~re~~<br>|**Max**<br>**V**<br>~~Ee~~<br>|**Min**<br>**V**<br>~~eee~~<br>~~Ee~~<br>~~GO~~<br>|**mA**<br>~~eee~~<br>~~Ee~~<br>~~GO~~<br>|**mA**<br>~~eee~~<br>~~Ee~~<br>~~GO~~<br>|**Max**<br>**mA3**<br>~~eee~~<br>~~Ee~~<br>~~Gee~~<br>|**Max**<br>**mA3**<br>~~eee~~<br>~~Ee~~|**µA4 **<br>~~eee~~<br>~~Ee~~|**µA4**<br>~~eee~~<br>~~Ee~~|
|2 mA<br>~~tT~~<br>~~ee~~<br>~~ee ae~~<br>~~ee~~|–0.3<br>~~tTEe~~<br>~~es~~<br>~~ae~~<br>|0.8<br>~~Ee~~<br>~~es~~<br>~~is~~<br>|2<br>~~Ee~~<br>~~ed~~<br>~~es~~<br>|3.6<br>~~Ee~~<br>~~re~~<br>~~rs~~<br>|0.4<br>~~Ee~~<br><br>|2.4<br>~~Ee~~<br>~~GO~~<br>~~Os~~<br>|2<br>~~Ee~~<br>~~GO~~<br>~~Os~~<br>|2<br>~~Ee~~<br>~~GO~~<br>~~Os~~<br>|25<br>~~Ee~~<br>~~Gee~~<br>~~Ge~~|27<br>~~Ee~~|10<br>~~Ee~~|10<br>~~Ee~~|
|4 mA<br><br>~~ee ~~<br>~~ee ae~~<br>~~ee~~<br>~~ee~~|–0.3<br>~~Ee~~<br> ~~es~~<br>~~ae~~<br>~~e~~~~**e**~~<br>|0.8<br>~~Ee~~<br>~~es~~<br>~~is~~<br>~~**es**~~|2<br>~~Ee~~<br>~~ed~~<br>~~es~~<br>~~**es**~~|3.6<br>~~Ee~~<br>~~re~~<br>~~rs~~<br>~~es~~|0.4<br>~~Ee~~<br><br>~~**ee**~~|2.4<br>~~Ee~~<br>~~GO~~<br>~~Os~~<br>~~ee~~|4<br>~~Ee~~<br>~~GO~~<br>~~Os~~<br>~~ee~~|4<br>~~Ee~~<br>~~GO~~<br>~~Os~~<br>~~ee~~|25<br>~~Ee~~<br>~~Gee~~<br>~~Ge~~<br>~~ee~~|27<br>~~Ee~~<br>~~ee~~|10 10<br>~~Ee~~|10 10<br>~~Ee~~|
|6 mA<br> <br>~~ee ae~~<br>~~ee~~<br>~~ee~~|–0.3<br> ~~es~~<br>~~ae~~<br>~~e~~~~**e**~~<br>~~e~~|0.8<br>~~es ~~<br>~~is~~<br>~~**es**~~|2<br> ~~ed ~~<br>~~es~~<br>~~**es**~~|3.6<br> ~~re~~<br>~~rs~~<br>~~es~~<br>~~es~~|0.4<br><br>~~**ee**~~<br>|2.4<br>~~GO~~<br>~~Os~~<br>~~ee~~<br>~~GG~~|6<br>~~GO~~<br>~~Os~~<br>~~ee~~<br>~~GG~~|6<br>~~GO ~~<br>~~Os~~<br>~~ee~~<br>~~GG~~|51<br> ~~Gee~~<br>~~Ge~~<br>~~ee~~<br>~~GG~~|54<br>~~ee~~<br>~~GG~~|10<br>~~GG~~|10<br>~~GG~~|
|8 mA<br>~~ae~~<br>~~ee ~~<br>~~ee~~|–0.3<br>~~ae ~~<br> ~~e~~~~**e**~~<br>~~e~~|0.8<br> ~~is ~~<br>~~**es**~~|2<br> ~~es ~~<br>~~**es**~~|3.6<br> ~~rs ~~<br>~~es~~<br>~~es~~|0.4<br> <br>~~**ee**~~<br>|2.4<br> ~~Os~~<br>~~ee~~<br>~~GG~~|8<br>~~Os~~<br>~~ee~~<br>~~GG~~|8<br>~~Os~~<br>~~ee~~<br>~~GG~~|51<br>~~Ge~~<br>~~ee~~<br>~~GG~~|54<br>~~ee~~<br>~~GG~~|10<br>~~GG~~|10<br>~~GG~~|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at 100°C junction temperature and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
R = 1 kΩ R to VCCI for tLZ / tZL / tZLS Test Point R to GND for tHZ / tZH / tZHS Test Point ~~1 j~~ Datapath 35 pF Enable Path 35 pF for tZH / tZHS / tZL / tZLS } y 35 pF for tHZ / tLZ
_**Figure 2-7 •**_ **AC Loading**
_**Table 2-40 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**CLOAD (pF)**|
|---|---|---|---|
|0|3.3|1.4|35|
_Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points._
**2-33**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **Timing Characteristics**
_**Table 2-41 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~<br>~~ee~~|**tZHS**<br>~~ee~~<br>~~ee~~|**Units**<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|7.66<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|7.80<br>~~ee~~<br>~~ee~~|6.59<br>~~ee~~<br>~~ee~~|2.65<br>~~ee~~<br>~~ee~~|2.61<br>~~ee~~<br>~~ee~~|10.03<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.82<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.51<br> ~~ee~~<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.86<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.63<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.60<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.25<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|2.22<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.54<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.51<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~ee~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.72<br> ~~a ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.76<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.82<br>~~ee~~<br>~~ee~~<br>~~eee~~|4.92<br>~~ee~~<br>~~ee~~<br>~~eee~~|1.98<br>~~ee~~<br>~~ee ee~~<br>~~eee~~|1.95<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|7.49<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|6.59<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|4 mA|Std.<br>~~ee~~|0.66<br>~~ee~~<br>~~ee~~|7.66<br>~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee~~|1.02<br> ~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~|7.80<br> ~~ee ~~<br>~~eee~~|6.59<br> ~~ee~~<br>~~eee~~|2.65<br>~~ee ee~~<br>~~eee~~|2.61<br>~~ee ~~<br>~~ee eee~~|10.03<br> ~~ee~~<br>~~eee~~|8.82<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~Pt~~|0.56<br>~~Pt~~|6.51<br>~~ee~~<br>~~Pt~~|0.04<br>~~ee~~<br>~~Pt~~|0.86<br>~~ee ~~<br>~~Pt~~|0.36<br> ~~ee ~~<br>~~Pt~~|6.63<br> ~~eee~~<br>~~Pt~~|5.60<br>~~eee~~<br>~~Pt~~|2.25<br>~~eee ~~<br>~~Pt~~|2.22<br> ~~ee eee~~<br>~~Pt~~|8.54<br>~~eee~~<br>~~Pt~~|7.51<br>~~eee~~<br>~~Pt~~|ns<br>~~eee~~<br>~~Pt~~|
||–2<br>~~Pt~~<br>~~a~~<br>~~a~~|0.49<br>~~Pt~~<br>~~ee~~|5.72<br>~~Pt~~<br>~~ee~~|0.03<br>~~Pt~~<br>~~ee~~|0.76<br>~~Pt~~<br>~~ee~~|0.32<br>~~Pt~~<br>~~ee~~|5.82<br>~~Pt~~<br>~~ee~~|4.92<br>~~Pt~~<br>~~ee~~|1.98<br>~~Pt~~<br>~~ee~~|1.95<br>~~Pt~~<br>~~ee~~|7.49<br>~~Pt~~<br>~~ee~~<br>~~ee~~|6.59<br>~~Pt~~<br>~~ee~~<br>~~ee~~|ns<br>~~Pt~~<br>~~ee~~<br>~~ee~~|
|6 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|4.91<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|5.00<br>~~ee~~<br>~~ee~~|4.07<br>~~ee~~<br>~~ee~~|2.99<br>~~ee~~<br>~~ee~~|3.20<br>~~ee~~<br>~~ee~~|7.23<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.31<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.17<br> ~~ee~~<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.86<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.25<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.46<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.54<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|2.73<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.15<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.36<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~ee~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.66<br> ~~a ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.76<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.73<br>~~ee~~<br>~~ee~~<br>~~eee~~|3.04<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.23<br>~~ee~~<br>~~ee ee~~<br>~~eee~~|2.39<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|5.40<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|4.71<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|8 mA<br>~~a~~|Std.<br>~~ee~~|0.66<br>~~ee~~<br>~~ee~~|4.91<br>~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee~~|1.02<br> ~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~|5.00<br> ~~ee ~~<br>~~eee~~|4.07<br> ~~ee~~<br>~~eee~~|2.99<br>~~ee ee~~<br>~~eee~~|3.20<br>~~ee ~~<br>~~ee eee~~|7.23<br> ~~ee~~<br>~~eee~~|6.31<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~Pt~~|0.56<br>~~Pt~~|4.17<br>~~ee~~<br>~~Pt~~|0.04<br>~~ee~~<br>~~Pt~~|0.86<br>~~ee ~~<br>~~Pt~~|0.36<br> ~~ee ~~<br>~~Pt~~|4.25<br> ~~eee~~<br>~~Pt~~|3.46<br>~~eee~~<br>~~Pt~~|2.54<br>~~eee ~~<br>~~Pt~~|2.73<br> ~~ee eee~~<br>~~Pt~~|6.15<br>~~eee~~<br>~~Pt~~|5.36<br>~~eee~~<br>~~Pt~~|ns<br>~~eee~~<br>~~Pt~~|
||–2<br>~~a~~<br>~~ee~~|0.49<br>~~a~~<br>~~ee~~|3.66<br>~~a~~<br>~~ee~~|0.03<br>~~ee~~|0.76<br>~~ee~~|0.32<br>~~ee~~|3.73<br>~~ee~~|3.04<br>~~ee~~|2.23<br>~~eee~~<br>~~ee~~|2.39<br>~~eee~~<br>~~ee~~|5.40<br>~~eee~~<br>~~ee~~|4.71<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|12 mA<br>~~a~~<br>~~ee~~|Std.<br>~~ee~~<br>~~ee~~|0.66<br>~~ee~~<br>~~ee~~|3.53<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|3.60<br>~~ee~~<br>~~eee~~|2.82<br>~~ee~~<br>~~eee~~|3.21<br>~~ee~~<br>~~eee~~|3.58<br>~~ee~~<br>~~ee~~|5.83<br>~~ee~~<br>~~eee~~|5.06<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|~~a~~<br>~~ee~~<br>~~ee~~|–1<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.56<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.86<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.06<br> ~~ee~~<br>~~eee~~<br>~~ee~~|2.40<br>~~ee ~~<br>~~eee~~<br>~~ee~~|2.73<br> ~~ee~~<br>~~eee~~<br>~~ee~~|3.05<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.96<br> ~~ee~~<br>~~eee~~<br>~~eee~~|4.30<br>~~ee ~~<br>~~eee~~<br>~~eee~~|ns<br> ~~ee~~<br>~~eee~~<br>~~eee~~|
|~~ee ~~<br>~~ee~~|–2<br> ~~ee ~~<br>~~ee~~|0.49<br> ~~ee ~~<br>~~ee~~|2.64<br> ~~ee ~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~|0.76<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|2.69<br> ~~eee~~<br>~~ee~~|2.11<br>~~eee~~<br>~~ee~~|2.40<br>~~eee ~~<br>~~ee~~|2.68<br> ~~ee ~~<br>~~ee~~|4.36<br> ~~eee~~<br>~~eee~~|3.78<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|16 mA<br>~~ee~~|Std.<br>~~ee ~~<br>~~Pt~~|0.66<br> ~~ee ~~<br>~~Pt~~|3.33<br> ~~ee~~<br>~~Pt~~|0.04<br>~~ee~~<br>~~Pt~~|1.02<br>~~ee ~~<br>~~Pt~~|0.43<br> ~~ee ~~<br>~~Pt~~|3.39<br> ~~ee~~<br>~~Pt~~|2.56<br>~~ee~~<br>~~Pt~~|3.26<br>~~ee ~~<br>~~Pt~~|3.68<br> ~~ee ~~<br>~~Pt~~|5.63<br> ~~eee~~<br>~~Pt~~|4.80<br>~~eee~~<br>~~Pt~~|ns<br>~~eee~~<br>~~Pt~~|
||–1<br>~~Pt~~<br>~~Pt~~|0.56<br>~~Pt~~<br>~~PtET~~|2.83<br>~~Pt~~<br>~~ET~~|0.04<br>~~Pt~~<br>~~ET~~|0.86<br>~~Pt~~|0.36<br>~~Pt~~|2.89<br>~~Pt~~|2.18<br>~~Pt~~|2.77<br>~~Pt~~|3.13<br>~~Pt~~|4.79<br>~~Pt~~|4.08<br>~~Pt~~|ns<br>~~Pt~~|
||–2<br>~~Pt~~<br>~~a~~|0.49<br>~~PtET~~<br>~~ee~~|2.49<br>~~ET~~<br>~~ee~~|0.03<br>~~ET~~<br>~~ee~~|0.76|0.32<br>~~ee~~|2.53<br>~~ee~~|1.91<br>~~ee~~|2.44<br>~~ee~~|2.75<br>~~ee~~|4.20<br>~~ee~~|3.58<br>~~ee~~|ns<br>~~ee~~|
|24 mA|Std.<br>~~Pt~~<br>~~a~~<br>~~a~~|0.66<br>~~Pt ET~~<br>~~ee~~<br>~~ee~~|3.08<br>~~ET~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ET~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|3.13<br>~~ee~~<br>~~ee~~|2.12<br>~~ee~~<br>~~ee~~|3.32<br>~~ee~~<br>~~ee~~|4.06<br>~~ee~~<br>~~ee~~|5.37<br>~~ee~~|4.35<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~a~~|2.62<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.86<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.66<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.80<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.83<br> ~~ee~~<br>~~ee~~|3.45<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.57<br> ~~ee~~<br>~~ee~~|3.70<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~a~~|2.30<br> ~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.76<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|2.34<br> ~~ee~~<br>~~ee~~|1.58<br>~~ee~~<br>~~ee~~|2.48<br>~~ee~~|3.03<br>~~ee~~<br>~~ee~~|4.01<br>~~ee~~|3.25<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-34**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-42 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~ee~~|0.66<br>~~ee~~<br>~~ee~~|10.26<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|10.45<br>~~ee~~<br>~~ee~~|8.90<br>~~ee~~<br>~~ee~~|2.64<br>~~ee~~<br>~~ee~~|2.46<br>~~ee~~|12.68<br>~~eee~~<br>~~eee~~|11.13<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~<br>~~Pot~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~Pot~~|8.72<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|0.86<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|8.89<br>~~ee ~~<br>~~ee~~|7.57<br> ~~ee~~<br>~~ee~~|2.25<br>~~ee ~~<br>~~ee~~|2.09<br> ~~ee~~|10.79<br>~~eee~~<br>~~eee~~|9.47<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.49<br> ~~ee ~~<br>~~Pot~~|7.66<br> ~~ee~~|0.03<br>~~ee~~|0.76<br>~~ee ~~|0.32<br> ~~ee~~|7.80<br>~~ee ~~|6.64<br> ~~ee ~~|1.98<br> ~~ee~~|1.83|9.47<br>~~eee~~|8.31<br>~~eee~~|ns<br>~~eee~~|
|4 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.66<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|10.26<br>~~EE~~|0.04<br>~~EE~~|1.02|0.43|10.45|8.90|2.64|2.46|12.68|11.13|ns|
||–1<br>~~pt~~<br>~~a~~|0.56<br>~~ptEE~~<br>~~ee~~|8.72<br>~~EE~~<br>~~ee~~|0.04<br>~~EE~~|0.86<br>~~ee~~|0.36<br>~~ee~~|8.89<br>~~ee~~|7.57<br>~~ee~~|2.25<br>~~ee~~|2.09<br>~~eee~~|10.79<br>~~eee~~|9.47<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~pt~~<br>~~a~~<br>~~a~~|0.49<br>~~pt EE~~<br>~~ee~~<br>~~ee~~|7.66<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~EE~~<br>~~ee~~|0.76<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|7.80<br>~~ee~~<br>~~ee~~|6.64<br>~~ee~~<br>~~ee~~|1.98<br>~~ee~~<br>~~ee~~|1.83<br>~~eee~~<br>~~ee~~|9.47<br>~~eee~~<br>~~eee~~|8.31<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|6 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~a~~<br>~~ee~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.27<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.41<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.28<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.98<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.04<br> ~~eee~~<br>~~ee~~|9.65<br>~~eee ~~<br>~~eee~~<br>~~eee~~|8.52<br> ~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~<br>~~Pot~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~Pot~~|6.19<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|0.86<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|6.30<br>~~ee ~~<br>~~ee~~|5.35<br> ~~ee~~<br>~~ee~~|2.54<br>~~ee ~~<br>~~ee~~|2.59<br> ~~ee~~|8.20<br>~~eee~~<br>~~eee~~|7.25<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.49<br> ~~ee ~~<br>~~Pot~~|5.43<br> ~~ee~~|0.03<br>~~ee~~|0.76<br>~~ee ~~|0.32<br> ~~ee~~|5.53<br>~~ee ~~|4.69<br> ~~ee ~~|2.23<br> ~~ee~~|2.27|7.20<br>~~eee~~|6.36<br>~~eee~~|ns<br>~~eee~~|
|8 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.66<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|7.27<br>~~EE~~|0.04<br>~~EE~~|1.02|0.43|7.41|6.28|2.98|3.04|9.65|8.52|ns|
||–1<br>~~pt~~<br>~~a~~|0.56<br>~~ptEE~~<br>~~ee~~|6.19<br>~~EE~~<br>~~ee~~|0.04<br>~~EE~~<br>~~ee~~|0.86<br>~~ee~~|0.36<br>~~ee~~|6.30<br>~~ee~~|5.35<br>~~ee~~|2.54<br>~~ee~~|2.59<br>~~ee~~|8.20<br>~~ee~~|7.25<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~pt~~<br>~~a~~<br>~~a~~|0.49<br>~~pt EE~~<br>~~ee~~<br>~~a~~|5.43<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.76<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|5.53<br>~~ee~~<br>~~ee~~|4.69<br>~~ee~~<br>~~ee~~|2.23<br>~~ee~~<br>~~ee~~|2.27<br>~~ee~~<br>~~ee~~|7.20<br>~~ee~~<br>~~ee~~|6.36<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|12 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~a~~<br>~~ee~~|0.66<br>~~ee~~<br>~~a~~<br>~~ee~~|5.58<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee~~<br>~~ee~~|5.68<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.87<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.21<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.42<br> ~~ee ~~<br>~~ee~~|7.92<br> ~~ee~~<br>~~ee~~<br>~~eee~~|7.11<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~ee~~<br>~~Pot~~|0.56<br> ~~a~~<br>~~ee~~<br>~~Pot~~|4.75<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|0.86<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|4.84<br>~~ee ~~<br>~~ee~~|4.14<br> ~~ee~~<br>~~ee~~|2.73<br>~~ee ~~<br>~~ee~~|2.91<br> ~~ee~~|6.74<br>~~ee~~<br>~~eee~~|6.05<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.49<br> ~~ee ~~<br>~~Pot~~|4.17<br> ~~ee~~|0.03<br>~~ee~~|0.76<br>~~ee ~~|0.32<br> ~~ee~~|4.24<br>~~ee ~~|3.64<br> ~~ee ~~|2.39<br> ~~ee~~|2.55|5.91<br>~~eee~~|5.31<br>~~eee~~|ns<br>~~eee~~|
|16 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.66<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|5.21<br>~~EE~~|0.04<br>~~EE~~|1.02|0.43|5.30|4.56|3.26|3.51|7.54|6.80|ns|
||–1<br>~~pt~~<br>~~a~~|0.56<br>~~ptEE~~<br>~~ee~~|4.43<br>~~EE~~<br>~~ee~~|0.04<br>~~EE~~<br>~~ee~~|0.86<br>~~ee~~|0.36<br>~~ee~~|4.51<br>~~ee~~|3.88<br>~~ee~~|2.77<br>~~ee~~|2.99<br>~~ee~~|6.41<br>~~ee~~|5.79<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~pt~~<br>~~a~~<br>~~a~~|0.49<br>~~pt EE~~<br>~~ee~~<br>~~a~~|3.89<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.76<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|3.96<br>~~ee~~<br>~~ee~~|3.41<br>~~ee~~<br>~~ee~~|2.43<br>~~ee~~<br>~~ee~~|2.62<br>~~ee~~<br>~~ee~~|5.63<br>~~ee~~<br>~~ee~~|5.08<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|24 mA|Std.<br>~~a ~~<br>~~a~~<br>~~ee~~|0.66<br> ~~ee~~<br>~~a~~<br>~~ee~~|4.85<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.94<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.54<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.32<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.88<br>~~ee ~~<br>~~ee~~|7.18<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|6.78<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~ee~~<br>~~pt~~|0.56<br> ~~a~~<br>~~ee~~<br>~~ptEE~~|4.13<br>~~ee ~~<br>~~ee~~<br>~~EE~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~EE~~|0.86<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|4.20<br>~~ee ~~<br>~~ee~~|3.87<br> ~~ee~~<br>~~ee~~|2.82<br>~~ee ~~<br>~~ee~~|3.30<br> ~~ee~~|6.10<br>~~ee~~<br>~~eee~~|5.77<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~pt~~|0.49<br> ~~ee ~~<br>~~ptEE~~|3.62<br> ~~ee~~<br>~~EE~~|0.03<br>~~ee~~<br>~~EE~~|0.76<br>~~ee ~~|0.32<br> ~~ee~~|3.69<br>~~ee ~~|3.39<br> ~~ee ~~|2.48<br> ~~ee~~|2.90|5.36<br>~~eee~~|5.06<br>~~eee~~|ns<br>~~eee~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-35**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-43 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~a~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~Po~~|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|7.20<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|7.34<br>~~ee~~<br>~~ee~~|6.29<br>~~ee~~<br>~~ee~~|2.27<br>~~ee~~<br>~~ee~~|2.34<br>~~ee~~<br>~~ee~~|9.57<br>~~ee~~|8.52<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~|6.13<br> ~~a ~~<br>~~ee~~|0.04<br> ~~ee~~|0.85<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|6.24<br>~~ee ~~<br>~~ee~~|5.35<br> ~~ee~~<br>~~ee~~|1.93<br>~~ee~~<br>~~ee~~|1.99<br>~~ee~~<br>~~ee~~|8.14<br>~~ee~~|7.25<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a ~~<br>~~Pt~~<br>~~Po~~|0.49<br> ~~ee~~<br>~~Pt~~<br>~~Po~~|5.38<br>~~ee~~<br>~~Pt~~<br>~~Po~~|0.03<br>~~Pt~~|0.75<br>~~ee~~<br>~~Pt~~|0.32<br>~~ee ~~<br>~~Pt~~|5.48<br> ~~ee ~~<br>~~Pt~~|4.69<br> ~~ee~~<br>~~Pt~~|1.70<br>~~ee ~~<br>~~Pt~~|1.75<br> ~~ee ~~<br>~~Pt~~|7.15<br> ~~ee~~<br>~~Pt~~|6.36<br>~~Pt~~|ns<br>~~Pt~~|
|4 mA<br>~~Po~~|Std.<br>~~Po~~<br>~~Pt~~|0.66<br>~~Po~~<br>~~PtET~~|7.20<br>~~Po~~<br>~~ET~~|0.04<br>~~ET~~|1.00|0.43|7.34|6.29|2.27|2.34|9.57|8.52|ns|
||–1<br>~~Po~~<br>~~Pt~~<br>~~a~~<br>~~a~~|0.56<br>~~Po~~<br>~~PtET~~<br>~~ee~~<br>|6.13<br>~~Po~~<br>~~ET~~<br>~~a~~<br>|0.04<br>~~ET~~<br>~~ee~~<br>|0.85<br>~~ee~~<br>|0.36<br>~~ee~~<br>|6.24<br>~~ee~~<br>|5.35<br>~~ee~~<br>|1.93<br>~~ee~~<br>~~ee~~<br>|1.99<br>~~ee~~<br>~~ee~~<br>|8.14<br>~~ee~~<br>~~eee~~|7.25<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~Pt~~<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~Pt ET~~<br>~~ee~~<br>~~ee a~~<br>|5.38<br>~~ET~~<br>~~a~~<br>~~a~~<br>|0.03<br>~~ET~~<br>~~ee~~<br>~~ee~~|0.75<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|5.48<br>~~ee~~<br>~~ee ee~~|4.69<br>~~ee~~<br>~~ee~~|1.70<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.75<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.15<br>~~ee~~<br>~~eee~~|6.36<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|6 mA<br>~~Po~~|Std.<br>~~a~~<br>~~a~~ <br>~~a~~|0.66<br>~~ee ~~<br> ~~ee a~~<br>~~ee~~|4.50<br> ~~a~~<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.58<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|3.82<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.58<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.88<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.82<br>~~ee~~<br> ~~eee~~<br>~~ee~~|6.05<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
||–1<br> <br>~~a ~~|0.56<br> ~~ee a~~<br> ~~ee~~|3.83<br>~~a ~~<br>~~ee~~|0.04<br> ~~ee~~|0.85<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|3.90<br>~~ee ee~~<br>~~ee~~|3.25<br>~~ee~~<br>~~ee~~|2.19<br>~~ee~~<br>~~ee~~|2.45<br>~~ee~~<br>~~ee~~|5.80<br>~~ee~~|5.15<br>~~ee~~|ns<br>~~ee~~|
||–2<br> <br>~~Pt~~<br>~~Po~~|0.49<br> ~~ee~~<br>~~Pt~~<br>~~Po~~|3.36<br>~~ee~~<br>~~Pt~~<br>~~Po~~|0.03<br>~~Pt~~|0.75<br>~~ee~~<br>~~Pt~~|0.32<br>~~ee ~~<br>~~Pt~~|3.42<br> ~~ee ~~<br>~~Pt~~|2.85<br> ~~ee~~<br>~~Pt~~|1.92<br>~~ee ~~<br>~~Pt~~|2.15<br> ~~ee ~~<br>~~Pt~~|5.09<br> ~~ee~~<br>~~Pt~~|4.52<br>~~Pt~~|ns<br>~~Pt~~|
|8 mA<br>~~Po~~<br>~~a~~<br>~~re~~|Std.<br>~~Po~~|0.66<br>~~Po~~|4.50<br>~~Po~~|0.04|1.00|0.43|4.58|3.82|2.58|2.88|6.82|6.05|ns|
||–1<br>~~Po~~<br>~~Pt~~<br>~~PTT~~|0.56<br>~~Po~~<br>~~Pt~~<br>~~PTT~~|3.83<br>~~Po~~<br>~~Pt~~<br>~~PTTTt~~|0.04<br>~~Pt~~<br>~~Tt~~|0.85<br>~~Pt~~<br>~~Tt~~|0.36<br>~~Pt~~|3.90<br>~~Pt~~|3.25<br>~~Pt~~|2.19<br>~~Pt~~|2.45<br>~~Pt~~|5.80<br>~~Pt~~|5.15<br>~~Pt~~|ns<br>~~Pt~~|
||–2<br>~~PTT~~<br>~~**ee**~~|0.49<br>~~PTT~~<br>~~**ee**~~|3.36<br>~~PTTTt~~|0.03<br>~~Tt~~<br>~~ee~~|0.75<br>~~Tt~~<br>~~ee~~|0.32<br>~~**e**e~~|3.42<br>~~e~~~~**e**~~|2.85<br>~~eee~~|1.92<br>~~eee~~|2.15<br>~~eee~~|5.09<br>~~**eee**~~|4.52<br>~~**eee**~~|ns<br>~~**eee**~~|
|12 mA<br>~~a~~<br>~~re~~|Std.<br>~~PTT~~<br>~~**ee**~~|0.66<br>~~PTT~~<br>~~**ee**~~|3.16<br>~~PTT Tt~~<br>~~ee~~|0.04<br>~~Tt~~<br>~~ee~~<br>~~ee~~|1.00<br>~~Tt~~<br>~~ee~~<br>~~ee~~|0.43<br>~~**e**e~~<br>~~e~~|3.22<br>~~e~~~~**e**~~|2.58<br>~~eee~~<br>~~ee~~|2.79<br>~~eee~~<br>~~ee~~|3.22<br>~~eee~~<br>~~ee~~|5.45<br>~~**eee**~~|4.82<br>~~**eee**~~|ns<br>~~**eee**~~|
|~~re~~|–1<br>~~**ee**~~<br>~~a~~|0.56<br>~~**ee**~~<br>~~a~~|2.69<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~|0.85<br>~~ee~~<br>~~ee~~|0.36<br>~~**e**e~~<br>~~e~~|2.74<br>~~e~~~~**e**~~|2.20<br>~~eee~~<br>~~ee~~<br>~~eee~~|2.37<br>~~eee~~<br>~~ee~~<br>~~eee~~|2.74<br>~~eee~~<br>~~ee~~<br>~~eee~~|4.64<br>~~**eee**~~<br>~~eee~~|4.10<br>~~**eee**~~<br>~~eee~~|ns<br>~~**eee**~~<br>~~eee~~|
|~~re~~<br>~~ee~~|–2<br>~~**ee** ~~<br>~~ee~~<br>~~a~~|0.49<br> ~~**ee**~~<br>~~ee~~<br>~~a~~|2.36<br>~~ee~~<br>~~ee~~<br>~~a~~|0.03<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.75<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.32<br> ~~**e**e~~<br>~~e~~<br>~~ee~~|2.40<br>~~e~~~~**e** ~~<br>~~ee~~|1.93<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.08<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.41<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|4.07<br> ~~**eee**~~<br>~~ee~~<br>~~eee~~|3.60<br>~~**eee**~~<br>~~ee~~<br>~~eee~~|ns<br>~~**eee**~~<br>~~ee~~<br>~~eee~~|
|16 mA|Std.<br>~~a~~<br>~~Pt~~|0.66<br>~~a~~<br>~~Pt~~|3.16<br>~~a~~<br>|0.04<br>|1.00|0.43|3.22<br>~~ee~~|2.58<br>~~eee~~<br>~~ee~~|2.79<br>~~eee~~<br>~~ee~~|3.22<br>~~eee ~~<br>~~ee~~|5.45<br> ~~eee~~<br>~~eee~~|4.82<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~Pt~~<br>~~a~~|0.56<br>~~Pt ET~~<br>~~ee~~|2.69<br>~~ET~~<br>~~a~~|0.04<br>~~ET~~<br>~~ee~~|0.85<br>~~ee~~|0.36<br>~~ee~~|2.74<br>~~ee~~<br>~~ee~~|2.20<br>~~ee~~<br>~~ee~~|2.37<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.74<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.64<br>~~eee~~<br>~~ee~~|4.10<br>~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~|
||–2<br>~~Pt~~<br>~~a~~|0.49<br>~~Pt ~~<br>~~ee~~|2.36<br><br>~~a~~|0.03<br><br>~~ee~~|0.75<br>~~ee~~|0.32<br>~~ee~~|2.40<br>~~ee~~<br>~~ee~~|1.93<br>~~ee~~<br>~~ee~~|2.08<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.41<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.07<br> ~~eee~~<br>~~ee~~|3.60<br>~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-36**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-44 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~ee~~|0.66<br>~~ee~~<br>~~ee~~|9.68<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|9.86<br>~~ee~~<br>~~ee~~|8.42<br>~~ee~~<br>~~ee~~|2.28<br>~~ee~~<br>~~ee~~|2.21<br>~~ee~~|12.09<br>~~eee~~<br>~~eee~~|10.66<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~<br>~~Pot~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~Pot~~|8.23<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|0.85<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|8.39<br>~~ee ~~<br>~~ee~~|7.17<br> ~~ee~~<br>~~ee~~|1.94<br>~~ee ~~<br>~~ee~~|1.88<br> ~~ee~~|10.29<br>~~eee~~<br>~~eee~~|9.07<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.49<br> ~~ee ~~<br>~~Pot~~|7.23<br> ~~ee~~|0.03<br>~~ee~~|0.75<br>~~ee ~~|0.32<br> ~~ee~~|7.36<br>~~ee ~~|6.29<br> ~~ee ~~|1.70<br> ~~ee~~|1.65|9.03<br>~~eee~~|7.96<br>~~eee~~|ns<br>~~eee~~|
|4 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.66<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|9.68<br>~~EE~~|0.04<br>~~EE~~|1.00|0.43|9.86|8.42|2.28|2.21|12.09|10.66|ns|
||–1<br>~~pt~~<br>~~a~~|0.56<br>~~ptEE~~<br>~~ee~~|8.23<br>~~EE~~<br>~~ee~~|0.04<br>~~EE~~|0.85<br>~~ee~~|0.36<br>~~ee~~|8.39<br>~~ee~~|7.17<br>~~ee~~|1.94<br>~~ee~~|1.88<br>~~eee~~|10.29<br>~~eee~~|9.07<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~pt~~<br>~~a~~<br>~~a~~|0.49<br>~~pt EE~~<br>~~ee~~<br>~~ee~~|7.23<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~EE~~<br>~~ee~~|0.75<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|7.36<br>~~ee~~<br>~~ee~~|6.29<br>~~ee~~<br>~~ee~~|1.70<br>~~ee~~<br>~~ee~~|1.65<br>~~eee~~<br>~~ee~~|9.03<br>~~eee~~<br>~~eee~~|7.96<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|6 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~a~~<br>~~ee~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.70<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.82<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.89<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.58<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.74<br> ~~eee~~<br>~~ee~~|9.06<br>~~eee ~~<br>~~eee~~<br>~~eee~~|8.12<br> ~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~<br>~~Pot~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~Pot~~|5.70<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|0.85<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|5.80<br>~~ee ~~<br>~~ee~~|5.01<br> ~~ee~~<br>~~ee~~|2.20<br>~~ee ~~<br>~~ee~~|2.33<br> ~~ee~~|7.71<br>~~eee~~<br>~~eee~~|6.91<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.49<br> ~~ee ~~<br>~~Pot~~|5.00<br> ~~ee~~|0.03<br>~~ee~~|0.75<br>~~ee ~~|0.32<br> ~~ee~~|5.10<br>~~ee ~~|4.40<br> ~~ee ~~|1.93<br> ~~ee~~|2.05|6.76<br>~~eee~~|6.06<br>~~eee~~|ns<br>~~eee~~|
|8 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.66<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|6.70<br>~~EE~~|0.04<br>~~EE~~|1.00|0.43|6.82|5.89|2.58|2.74|9.06|8.12|ns|
||–1<br>~~pt~~<br>~~a~~|0.56<br>~~ptEE~~<br>~~ee~~|5.70<br>~~EE~~<br>~~ee~~|0.04<br>~~EE~~<br>~~ee~~|0.85<br>~~ee~~|0.36<br>~~ee~~|5.80<br>~~ee~~|5.01<br>~~ee~~|2.20<br>~~ee~~|2.33<br>~~ee~~|7.71<br>~~ee~~|6.91<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~pt~~<br>~~a~~<br>~~a~~|0.49<br>~~pt EE~~<br>~~ee~~<br>~~a~~|5.00<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.75<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|5.10<br>~~ee~~<br>~~ee~~|4.40<br>~~ee~~<br>~~ee~~|1.93<br>~~ee~~<br>~~ee~~|2.05<br>~~ee~~<br>~~ee~~|6.76<br>~~ee~~<br>~~ee~~|6.06<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|12 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~a~~<br>~~ee~~|0.66<br>~~ee~~<br>~~a~~<br>~~ee~~|5.05<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.00<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee~~<br>~~ee~~|5.14<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.51<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.79<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.08<br> ~~ee ~~<br>~~ee~~|7.38<br> ~~ee~~<br>~~ee~~<br>~~eee~~|6.75<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~ee~~<br>~~Pot~~|0.56<br> ~~a~~<br>~~ee~~<br>~~Pot~~|4.29<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|0.85<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|4.37<br>~~ee ~~<br>~~ee~~|3.84<br> ~~ee~~<br>~~ee~~|2.38<br>~~ee ~~<br>~~ee~~|2.62<br> ~~ee~~|6.28<br>~~ee~~<br>~~eee~~|5.74<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.49<br> ~~ee ~~<br>~~Pot~~|3.77<br> ~~ee~~|0.03<br>~~ee~~|0.75<br>~~ee ~~|0.32<br> ~~ee~~|3.84<br>~~ee ~~|3.37<br> ~~ee ~~|2.09<br> ~~ee~~|2.30|5.51<br>~~eee~~|5.04<br>~~eee~~|ns<br>~~eee~~|
|16 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.66<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|5.05<br>~~EE~~|0.04<br>~~EE~~|1.00|0.43|5.14|4.51|2.79|3.08|7.38|6.75|ns|
||–1<br>~~pt~~<br>~~|~~|0.56<br>~~ptEE~~<br>~~ft~~|4.29<br>~~EE~~<br>~~ft~~<br>~~ft~~|0.04<br>~~EE~~<br>~~ft~~<br>~~tT~~|0.85<br>~~tT~~~~**t**~~|0.36<br>~~**t**l~~|4.37|3.84|2.38|2.62|6.28|5.74|ns|
||–2<br>~~pt~~<br>~~|~~|0.49<br>~~pt EE~~<br>~~ft~~|3.77<br>~~EE~~<br>~~ft~~<br>~~ft~~|0.03<br>~~EE~~<br>~~ft~~<br>~~tT~~|0.75<br>~~tT~~~~**t**~~|0.32<br>~~**t**l~~|3.84|3.37|2.09<br>~~t~~|2.30<br>~~t~~|5.51<br>~~t~~|5.04<br>~~t~~|ns<br>~~t~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_**Table 2-45 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~es es~~|**tPY**<br>~~es ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~es~~|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|7.07<br>~~ee~~<br>~~ee~~|0.04<br>~~es es~~<br>~~es es~~|1.00<br>~~es ee~~<br>~~es ee~~|0.43<br>~~ee~~<br>~~ee~~|7.20<br>~~es~~<br>~~ee~~|6.23<br>~~ss~~|2.07<br>~~ss~~|2.15<br>~~ee~~|ns|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.01<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~es es~~<br>~~es es~~<br>~~es~~|0.85<br>~~es ee~~<br>~~es ee~~<br>~~se~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~se~~|6.12<br> ~~es~~<br>~~ee~~<br>~~ss~~|5.30<br>~~ss~~<br>~~ss~~|1.76<br>~~ss~~|1.83<br>~~ee~~|ns|
||–2<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.28<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.03<br>~~es es~~<br>~~es~~<br>~~es es~~|0.75<br>~~es ee~~<br>~~se~~<br>~~es ee~~|0.32<br>~~ee ~~<br>~~se~~<br>~~ee~~|5.37<br> ~~ee ~~<br>~~ss~~<br>~~es es~~|4.65<br> ~~ss~~<br>~~ss~~<br>~~es~~|1.55<br>~~ss ~~<br>~~se~~|1.60<br> ~~ee~~<br>~~se~~|ns|
|4 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.07<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~es ~~<br>~~es es~~<br>~~es es~~|1.00<br> ~~se~~<br>~~es ee~~<br>~~es ee~~|0.43<br>~~se ~~<br>~~ee~~<br>~~ee~~|7.20<br> ~~ss~~<br>~~es es~~<br>~~ss~~|6.23<br>~~ss~~<br>~~es~~<br>~~ss~~|2.07<br>~~se~~|2.15<br>~~se~~|ns|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.01<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~es es~~<br>~~es es~~<br>~~es es~~|0.85<br>~~es ee~~<br>~~es ee~~<br>~~es ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.12<br>~~es es~~<br>~~ss~~<br>~~es~~|5.30<br>~~es ~~<br>~~ss~~<br>~~es~~|1.76<br> ~~se~~<br>~~es~~|1.83<br>~~se~~|ns|
||–2<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.28<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~es es~~<br>~~es es~~<br>~~es es~~|0.75<br>~~es ee~~<br>~~es ee~~<br>~~es ee~~|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.37<br> ~~ss~~<br>~~es~~<br>~~es~~|4.65<br>~~ss~~<br>~~es~~|1.55<br>~~es~~|1.60|ns|
|6 mA<br>~~es~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.41<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~es es~~<br>~~es es~~<br>~~es es~~|1.00<br>~~es ee~~<br>~~es ee~~<br>~~es ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.49<br>~~es ~~<br>~~es~~<br>~~ee~~|3.75<br> ~~es ~~<br>~~ss~~|2.39<br> ~~es~~<br>~~ss~~|2.69<br>~~ee~~|ns|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.75<br> ~~ee ~~<br>~~ee~~<br>~~ae~~|0.04<br> ~~es es~~<br>~~es es~~<br>~~ee~~|0.85<br>~~es ee~~<br>~~es ee~~<br>~~es~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.82<br> ~~es~~<br>~~ee~~<br>~~es~~|3.19<br>~~ss~~<br>~~se~~|2.04<br>~~ss~~<br>~~se~~|2.29<br>~~ee~~<br>~~se~~|ns|
||–2<br>~~a~~<br>~~a~~<br>~~ee ee~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~|3.29<br> ~~ee~~<br>~~ae~~<br>~~Ge~~|0.03<br>~~es es~~<br>~~ee~~<br>~~es~~|0.75<br>~~es ee~~<br>~~es~~|0.32<br>~~ee ~~<br>~~ee~~|3.36<br> ~~ee ~~<br>~~es~~|2.80<br> ~~ss~~<br>~~se~~|1.79<br>~~ss ~~<br>~~se~~|2.01<br> ~~ee~~<br>~~se~~|ns|
|8 mA<br>~~es~~<br>~~a~~|Std.<br>~~a~~<br>~~ee ee~~<br>~~es~~|0.66<br>~~ee~~<br>~~ee ee~~<br>~~es~~|4.41<br>~~ae~~<br>~~Ge~~<br>~~ee~~|0.04<br>~~ee~~<br>~~es~~<br>~~Pes~~|1.00<br>~~es~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|4.49<br>~~es~~<br>~~es~~|3.75<br>~~se~~<br>~~es~~|2.39<br>~~se~~<br>~~es~~|2.69<br>~~se~~|ns|
|~~es~~<br>~~a~~|–1<br>~~a~~<br>~~ee ee~~<br>~~es~~|0.56<br>~~ee ~~<br>~~ee ee ~~<br>~~es~~|3.75<br> ~~ae ~~<br> ~~Ge~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~es~~<br>~~Pes~~|0.85<br> ~~es~~<br>~~ee~~|0.36<br>~~ee ~~<br>~~ee~~|3.82<br> ~~es ~~<br>~~es~~|3.19<br> ~~se~~<br>~~es~~|2.04<br>~~se~~<br>~~es~~|2.29<br>~~se~~|ns|
**2-37**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-45 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||–2|0.49|3.29|0.03|0.75|0.32|3.36|2.80|1.79|2.01|ns|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_**Table 2-46 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**<br>~~a~~|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~eee~~|**tLZ**<br>~~eee~~|**tHZ**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|9.46<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|9.64<br>~~ee~~<br>~~ee~~|8.54<br>~~eee~~<br>~~ee~~|2.07<br>~~eee~~<br>~~ee~~|2.04<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.05<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.85<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|8.20<br> ~~ee~~<br>~~ee~~<br>~~ee~~|7.27<br>~~eee~~<br>~~ee~~<br>~~ee~~|1.76<br>~~eee~~<br>~~ee~~<br>~~ee~~|1.73<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~a~~|7.07<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.75<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.20<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.38<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.55<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.52<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|4 mA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~a~~<br>~~ee~~|9.46<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~<br>~~ee~~|9.64<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|8.54<br> ~~ee~~<br>~~ee~~|2.07<br>~~ee~~<br>~~ee~~|2.04<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a ~~<br>~~ee~~|8.05<br> ~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|0.85<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|8.20<br>~~ee~~<br>~~ee~~|7.27<br>~~ee~~|1.76<br>~~ee~~|1.73|ns|
||–2<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.07<br> ~~ee ~~<br>~~ee ~~<br>~~ee~~|0.03<br> ~~ee~~<br> ~~ee~~<br>~~ee~~|0.75<br>~~ee ~~<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br> ~~ee~~<br>~~ee~~|7.20<br>~~ee~~<br>~~ee ~~<br>~~eeeee~~|6.38<br> ~~ee~~<br>~~eee~~|1.55<br>~~ee ~~<br>~~eee~~|1.52<br> ~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|6 mA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|6.57<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|6.69<br>~~eeeee~~<br>~~ee~~|5.98<br>~~eee~~<br>~~ee~~|2.40<br>~~eee~~<br>~~ee~~|2.57<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.59<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.85<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.69<br> ~~eeeee~~<br>~~ee~~<br>~~ee~~|5.09<br>~~eee~~<br>~~ee~~<br>~~ee~~|2.04<br>~~eee~~<br>~~ee~~<br>~~ee~~|2.19<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~a~~|4.91<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.75<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.00<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4.47<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.79<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.92<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|8 mA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~a~~<br>~~ee~~|6.57<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.69<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|5.98<br> ~~ee~~<br>~~ee~~|2.40<br>~~ee~~<br>~~ee~~|2.57<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~a~~|0.56<br> ~~a ~~<br>~~ee~~<br>~~a~~|5.59<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.85<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.69<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.09<br>~~ee~~<br>~~ee~~|2.04<br>~~ee~~<br>~~ee~~|2.19<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~a~~|4.91<br> ~~ee ~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~|0.75<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~|5.00<br>~~ee~~<br>~~ee~~|4.47<br>~~ee~~|1.79<br>~~ee~~|1.92<br>~~ee~~|ns<br>~~ee~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-38**
_ProASIC3 DC and Switching Characteristics_
## _**3.3 V LVCMOS Wide Range**_
## _**Table 2-47 •**_ **Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks**
|**3.3 V**<br>**LVCMOS**<br>**Wide Range**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**<br>~~a~~|**Software**<br>**VIL**|**Software**<br>**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL2 **|**IIH3**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~a~~||**Min**<br>**V**<br>~~ee~~|**Max**<br>**V**<br>~~es~~|**Min**<br>**V**<br>~~ee~~|**Max**<br>**V**<br>~~es~~|**Max**<br>**V**<br>~~ee~~|**Min**<br>**V**<br>~~es~~|**µA**<br>~~Oe~~|**µA**<br>~~Gd~~|**Max**<br>**mA4**<br>~~es~~|**Max**<br>**mA4**|**µA5 **|**µA5**|
|100 µA<br>~~a~~<br>~~a~~|2 mA<br>~~a~~<br>~~es~~|–0.3<br>~~ee~~<br>~~ee~~|0.8<br>~~es~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|3.6<br>~~es~~<br>~~es~~|0.2<br>~~ee~~|VDD – 0.2 <br>~~es~~<br>~~GG~~|100 <br>~~Oe~~<br>~~GG~~|100<br>~~Gd~~<br>~~GG~~|25<br>~~es~~|27<br>~~Ge~~|10 10<br>~~Ge~~|10 10|
|100 µA<br>~~a~~<br>~~a~~<br>~~a~~|4 mA<br>~~a~~<br>~~es~~<br>~~a~~|–0.3<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.8<br>~~es ~~<br>~~ee~~<br>~~es~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.6<br> ~~es~~<br>~~es~~<br>~~es~~|0.2<br>~~ee~~<br>~~ee~~|VDD – 0.2 <br>~~es ~~<br>~~GG~~<br>~~es~~|100 <br> ~~Oe ~~<br>~~GG~~<br>~~Oe~~|100<br> ~~Gd ~~<br>~~GG~~<br>~~Gd~~|25<br> ~~es~~<br>~~es~~|27<br>~~Ge~~|10 10<br>~~Ge~~|10 10|
|100 µA<br>~~a~~<br>~~a~~<br>~~a~~|6 mA<br>~~es ~~<br>~~a~~<br>~~es~~|–0.3<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.8<br> ~~ee ~~<br>~~es~~<br>~~ee~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.6<br> ~~es~~<br>~~es~~<br>~~es~~|0.2<br>~~ee~~|VDD – 0.2 <br>~~GG~~<br>~~es~~<br>~~GG~~|100 <br>~~GG~~<br>~~Oe~~<br>~~GG~~|100<br>~~GG~~<br>~~Gd~~<br>~~GG~~|51<br>~~es~~|54<br>~~Ge~~<br>~~Ge~~|10 10<br>~~Ge~~<br>~~Ge~~|10 10|
|100 µA<br>~~a~~<br>~~a~~<br>~~a~~|8 mA<br>~~a~~<br>~~es~~<br>~~ee~~|–0.3<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.8<br>~~es ~~<br>~~ee~~<br>~~ee~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.6<br> ~~es~~<br>~~es~~<br>~~es~~|0.2<br>~~ee~~<br>~~ee~~|VDD – 0.2 <br>~~es ~~<br>~~GG~~<br>~~es~~|100 <br> ~~Oe ~~<br>~~GG~~<br>~~OG~~|100<br> ~~Gd ~~<br>~~GG~~<br>~~OG~~|51<br> ~~es~~<br>~~es~~|54<br>~~Ge~~<br>~~es~~|10 10<br>~~Ge~~|10 10|
|100 µA<br>~~a~~<br>~~a~~<br>~~es~~|12 mA<br>~~es ~~<br>~~ee~~<br>~~es~~|–0.3<br> ~~ee ~~<br>~~ee~~<br>~~es~~|0.8<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.6<br> ~~es~~<br>~~es~~<br>~~es~~|0.2<br>~~ee~~|VDD – 0.2 <br>~~GG~~<br>~~es~~<br>~~QO~~|100 <br>~~GG~~<br>~~OG~~<br>~~QO GG~~|100<br>~~GG~~<br>~~OG~~<br>~~GG~~|103<br>~~es~~<br>~~GG~~|109<br>~~Ge~~<br>~~es~~<br>~~GG~~|10 10<br>~~Ge~~<br>~~GG~~|10 10|
|100 µA<br>~~a~~<br>~~es~~<br>~~a~~|16 mA<br>~~ee~~<br>~~es~~<br>~~es~~|–0.3<br>~~ee ~~<br>~~es~~<br>~~ee~~|0.8<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.6<br> ~~es~~<br>~~es~~<br>~~ee~~|0.2<br>~~ee~~<br>~~ee es~~|VDD – 0.2 <br>~~es~~<br>~~QO~~<br>~~es~~|100 <br>~~OG~~<br>~~QO GG~~<br>~~Gs~~|100<br>~~OG~~<br>~~GG~~<br>~~Ge~~|132<br>~~es~~<br>~~GG~~<br>~~es~~|127<br>~~es~~<br>~~GG~~<br>~~Gd~~|10 10<br>~~GG~~<br>~~Gd~~|10 10|
|100 µA<br>~~es~~<br>~~a~~|24 mA<br>~~es~~<br>~~es~~|–0.3<br>~~es ~~<br>~~ee~~|0.8<br> ~~ee ~~<br>~~ee~~|2<br> ~~ee ~~<br>~~ee~~|3.6<br> ~~es~~<br>~~ee~~|0.2<br>~~ee es~~|VDD – 0.2 <br>~~QO~~<br>~~es~~|100 <br>~~QO GG~~<br>~~Gs~~|100<br>~~GG~~<br>~~Ge~~|268<br>~~GG~~<br>~~es~~|181<br>~~GG~~<br>~~Gd~~|10 10<br>~~GG~~<br>~~Gd~~|10 10|
## _Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_4. Currents are measured at 85°C junction temperature._
_5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
_6. Software default selection highlighted in gray._
_**Table 2-48 •**_ **Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks**
|**3.3 V LVCMOS**<br>**Wide Range**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**<br>~~es~~|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL2 **|**IIH3**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**<br>~~Re~~||**Min**<br>**V**<br>~~es~~|**Max**<br>**V**<br>~~es~~|**Min**<br>**V**<br>~~re~~|**Max**<br>**V**<br>~~re~~|**Max**<br>**V**<br>~~es~~|**Min**<br>**V**<br>~~es~~|**µA**<br>~~Qs~~|**µA**<br>~~Qs~~|**Max**<br>**mA4**<br>~~Os~~|**Max**<br>**mA4**|**µA5 **|**µA5**|
|100 µA<br>~~Re~~<br>~~Re~~|2 mA<br>~~es~~<br>~~es~~|–0.3<br>~~es~~<br>~~es~~|0.8<br>~~es~~<br>~~ee~~|2<br>~~re~~<br>~~ee~~|3.6<br>~~re~~<br>~~ee~~|0.2<br>~~es~~<br>~~es~~|VDD – 0.2<br>~~es~~<br>~~rs~~|100 <br>~~Qs~~<br>~~Gd~~|100<br>~~Qs~~<br>~~Ge~~|25<br>~~Os~~<br>~~ns~~|27|10 10|10 10|
|100 µA<br>~~Re~~<br>~~Re~~<br>~~Re~~|4 mA<br>~~es ~~<br>~~es~~<br>~~es~~|–0.3<br> ~~es ~~<br>~~es~~<br>~~es~~|0.8<br> ~~es~~<br>~~ee~~<br>~~es~~|2<br>~~re~~<br>~~ee~~<br>~~re~~|3.6<br>~~re ~~<br>~~ee~~<br>~~re~~|0.2<br> ~~es ~~<br>~~es~~<br>~~es~~|VDD – 0.2<br> ~~es~~<br>~~rs~~<br>~~es~~|100 <br>~~Qs ~~<br>~~Gd~~<br>~~Qs~~|100<br> ~~Qs~~<br>~~Ge~~<br>~~Qs~~|25<br>~~Os~~<br>~~ns~~<br>~~Os~~|27|10 10|10 10|
|100 µA<br>~~Re~~<br>~~Re~~<br>~~Re~~|6 mA<br>~~es ~~<br>~~es~~<br>~~es~~|–0.3<br> ~~es ~~<br>~~es~~<br>~~es~~|0.8<br> ~~ee ~~<br>~~es~~<br>~~ee~~|2<br> ~~ee~~<br>~~re~~<br>~~ee~~|3.6<br>~~ee~~<br>~~re~~<br>~~ee~~|0.2<br>~~es~~<br>~~es~~<br>~~es~~|VDD – 0.2<br>~~rs~~<br>~~es~~<br>~~rs~~|100 <br>~~Gd ~~<br>~~Qs~~<br>~~Gd~~|100<br> ~~Ge ~~<br>~~Qs~~<br>~~Ge~~|51<br> ~~ns~~<br>~~Os~~<br>~~ns~~|54|10 10|10 10|
|100 µA<br>~~Re~~<br>~~Re~~<br>~~Re~~|8 mA<br>~~es ~~<br>~~es~~<br>~~es~~|–0.3<br> ~~es ~~<br>~~es~~<br>~~es~~|0.8<br> ~~es~~<br>~~ee~~<br>~~es~~|2<br>~~re~~<br>~~ee~~<br>~~re~~|3.6<br>~~re ~~<br>~~ee~~<br>~~re~~|0.2<br> ~~es ~~<br>~~es~~<br>~~es~~|VDD – 0.2<br> ~~es~~<br>~~rs~~<br>~~es~~|100 <br>~~Qs ~~<br>~~Gd~~<br>~~Qs~~|100<br> ~~Qs~~<br>~~Ge~~<br>~~Qs~~|51<br>~~Os~~<br>~~ns~~<br>~~Os~~|54|10 10|10 10|
|100 µA<br>~~Re~~<br>~~Re~~<br>~~PLE~~|12 mA<br>~~es ~~<br>~~es~~<br>~~PLE~~|–0.3<br> ~~es ~~<br>~~es~~|0.8<br> ~~ee ~~<br>~~es~~|2<br> ~~ee~~<br>~~re~~|3.6<br>~~ee~~<br>~~re~~|0.2<br>~~es~~<br>~~es~~|VDD – 0.2<br>~~rs~~<br>~~es~~|100 <br>~~Gd ~~<br>~~Qs~~|100<br> ~~Ge ~~<br>~~Qs~~|103<br> ~~ns~~<br>~~Os~~|109|10 10|10 10|
|100A<br>~~Re~~<br>~~PLE~~|16 mA<br>~~es ~~<br>~~PLE~~|–0.3<br> ~~es ~~|0.8<br> ~~es~~|2<br>~~re~~|3.6<br>~~re ~~|0.2<br> ~~es ~~|VDD – 0.2<br> ~~es~~|100 <br>~~Qs ~~|100<br> ~~Qs~~|103<br>~~Os~~|109|10 10|10 10|
## _Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_4. Currents are measured at 85°C junction temperature._
_5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
_6. Software default selection highlighted in gray._
**2-39**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-49 •**_ **Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks**
|**3.3 V**<br>**LVCMOS**<br>**Wide Range**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**<br>~~ee~~|**Software**<br>**VIL**|**Software**<br>**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL2 **|**IIH3**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~Rs~~||**Strength**<br>**Min**<br>**V**<br>~~ee~~|**Max**<br>**V**<br>~~es~~|**Min**<br>**V**<br>~~ee~~|**Max**<br>**V**<br>~~es~~|**Max**<br>**V**<br>~~es~~|**Min**<br>**V**<br>~~Gr~~|**µA**<br>~~Ge~~|**µA**<br>~~Ge~~|**Max**<br>**mA4**<br>~~OG~~|**Max**<br>**mA4**<br>~~OG~~|**µA5 **<br>~~OG~~|**µA5**|
|100 µA<br>~~Rs~~<br>~~ee~~|2 mA<br>~~ee~~<br>~~ee~~|–0.3<br>~~ee~~<br>~~ee~~|0.8<br>~~es~~<br>~~es~~|2<br>~~ee~~<br>~~ee~~|3.6<br>~~es~~<br>~~ee~~|0.2<br>~~es~~<br>~~es~~|VDD – 0.2 <br>~~Gr~~<br>~~ee~~|100 <br>~~Ge~~<br>~~ee~~|100<br>~~Ge~~<br>~~ee~~|25<br>~~OG~~|27<br>~~OG~~|10 10<br>~~OG~~|10 10|
|100 µA<br>~~Rs~~<br>~~ee~~<br>~~es~~|4 mA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–0.3<br> ~~ee ~~<br>~~ee~~<br>~~es~~|0.8<br> ~~es ~~<br>~~es~~<br>~~es~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.6<br> ~~es~~<br>~~ee~~<br>~~ee~~|0.2<br>~~es~~<br>~~es~~<br>~~Gd~~|VDD – 0.2 <br>~~Gr~~<br>~~ee~~<br>~~Gn~~|100 <br>~~Ge~~<br>~~ee~~<br>~~Gn~~|100<br>~~Ge~~<br>~~ee~~<br>~~Gn~~|25<br>~~OG~~<br>~~Gn~~|27<br>~~OG~~|10 10<br>~~OG~~<br>~~GO~~|10 10|
|100 µA<br>~~ee~~<br>~~es~~<br>~~a~~|6 mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|–0.3<br>~~ee~~<br>~~es~~<br>~~es~~|0.8<br>~~es ~~<br>~~es~~<br>~~es~~|2<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.6<br> ~~ee ~~<br>~~ee~~<br>~~eeGe~~|0.2<br> ~~es~~<br>~~Gd~~<br>~~eeGe~~|VDD – 0.2 <br>~~ee~~<br>~~Gn~~<br>~~eG~~|100 <br>~~ee~~<br>~~Gn~~<br>~~eG~~|100<br>~~ee~~<br>~~Gn~~<br>~~eG~~|51<br>~~Gn~~<br>~~eG~~|54<br>~~eG~~|10 10<br>~~GO~~<br>~~eG~~|10 10<br>~~eG~~|
|100 µA<br>~~es ~~<br>~~a~~|8 mA<br> ~~ee ~~<br>~~ee~~|–0.3<br> ~~es ~~<br>~~es~~|0.8<br> ~~es ~~<br>~~es~~|2<br> ~~ee ~~<br>~~ee~~|3.6<br> ~~ee~~<br>~~eeGe~~|0.2<br>~~Gd~~<br>~~eeGe~~|VDD – 0.2 <br>~~Gn~~<br>~~eG~~|100 <br>~~Gn~~<br>~~eG~~|100<br>~~Gn~~<br>~~eG~~|51<br>~~Gn~~<br>~~eG~~|54<br>~~eG~~|10 10<br>~~GO~~<br>~~eG~~|10 10<br>~~eG~~|
## _Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_4. Currents are measured at 85°C junction temperature._
_5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification._
_6. Software default selection highlighted in gray._
**Revision 18**
**2-40**
_ProASIC3 DC and Switching Characteristics_
## **Timing Characteristics**
## _**Table 2-50 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**|**Speed**<br>**Grade**<br>~~et~~|**tDOUT**<br>~~et~~|**tDP**<br>|**tDIN**<br>|**tPY**<br>|**tEOUT**<br>|**tZL**<br>|**tZH**<br>|**tLZ**<br>|**tHZ**<br>|**tZLS**<br>|**tZHS**<br>|**Units**<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|100 µA|4 mA|Std.<br>~~et~~<br>~~ef~~|0.60<br>~~ette~~<br>~~ef~~<br>~~|~~|11.84<br>~~te~~<br>~~rE~~|0.04 <br>~~te~~<br>~~rE~~|1.02<br>~~te~~|0.43<br>~~te~~|11.84 <br>~~te~~|10.00 <br>~~te~~|4.10 <br>~~te~~|4.04 <br>~~te~~|15.23 <br>~~te~~|13.40<br>~~te~~|ns<br>~~te~~|
|||–1<br>~~et~~<br>~~ef~~<br>~~ee~~|0.51<br>~~et~~<br>~~ef~~<br>~~|~~|10.07<br><br>~~rE~~|0.04 <br><br>~~rE~~<br>~~eee~~|0.86<br><br>~~eee~~|0.36<br><br>~~eee~~|10.07<br><br>~~eee~~|8.51<br><br>~~eee eee~~|3.48 <br><br>~~eee~~|3.44 <br><br>~~eee~~|12.96 <br><br>~~eee~~|11.40<br><br>~~eee~~|ns<br><br>~~eee~~|
|||–2<br>~~ef~~<br>~~ee~~<br>~~ee~~|0.45<br>~~ef~~<br>~~|~~<br>~~ee~~|8.84<br>~~rE~~|0.03 <br>~~rE~~<br>~~eee~~<br>~~ee~~|0.76<br>~~eee~~<br>~~ee~~|0.32<br>~~eee~~<br>~~ee~~|8.84<br>~~eee~~<br>~~eee~~|7.47<br>~~eee eee~~<br>~~eee~~|3.06 <br>~~eee~~<br>~~eee~~|3.02 <br>~~eee~~<br>~~eee~~|11.38 <br>~~eee~~<br>~~eee~~|10.00<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|100 µA|6 mA|Std.<br>~~ee~~<br>~~ee~~<br>~~a~~|0.60<br>~~ee~~<br>~~ee~~|7.59<br>~~ee~~|0.04 <br>~~eee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~eee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~eee~~<br>~~ee~~<br>~~eee~~|7.59<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.18<br>~~eee eee~~<br>~~eee~~<br>~~eee~~|4.62 <br>~~eee~~<br>~~eee~~<br>~~eee~~|4.95 <br>~~eee~~<br>~~eee~~<br>~~eee~~|10.98<br>~~eee~~<br>~~eee~~<br>~~eee~~|9.57<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|||–1<br>~~ee ~~<br>~~a~~<br>~~et~~|0.51<br> ~~ee~~<br>~~ee~~<br>~~et~~|6.45<br>~~ee~~<br>|0.04 <br>~~ee~~<br>~~ee~~<br>|0.86<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~eee~~<br>|6.45<br>~~eee~~<br>~~eee~~<br>|5.25<br>~~eee~~<br>~~eee~~<br>|3.93 <br>~~eee~~<br>~~eee~~<br>|4.21<br>~~eee~~<br>~~eee~~<br>|9.34<br>~~eee~~<br>~~eee~~<br>|8.14<br>~~eee~~<br>~~eee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>|
|||–2<br>~~a~~<br>~~et~~<br>~~et~~|0.45<br>~~ee ~~<br>~~etTE~~<br>~~et~~|5.67<br> ~~ee ~~<br>~~TE~~<br>|0.03 <br> ~~ee~~<br>~~TE~~<br>|0.76<br>~~ee~~<br>~~TE~~<br>|0.32<br>~~eee~~<br>~~TE~~<br>|5.67<br>~~eee~~<br>~~TE~~<br>|4.61<br>~~eee~~<br>~~TE~~<br>|3.45 <br>~~eee~~<br>~~TE~~<br>|3.70<br>~~eee~~<br>~~TE~~<br>|8.20<br>~~eee~~<br>~~TE~~<br>|7.15<br>~~eee~~<br>~~TE~~<br>|ns<br>~~eee~~<br>~~TE~~<br>|
|100 µA|8 mA<br>~~Po~~|Std.<br>~~et~~<br>~~et~~<br>~~ef~~|0.60<br>~~et~~<br>~~ette~~<br>~~ef~~<br>~~|~~|7.59<br><br>~~te~~<br>~~rE~~|0.04 <br><br>~~te~~<br>~~rE~~|1.02<br><br>~~te~~|0.43<br><br>~~te~~|7.59<br><br>~~te~~|6.18<br><br>~~te~~|4.62 <br><br>~~te~~|4.95 <br><br>~~te~~|10.98<br><br>~~te~~|9.57<br><br>~~te~~|ns<br><br>~~te~~|
|||–1<br>~~et~~<br>~~ef~~<br>~~PT~~|0.51<br>~~et~~<br>~~ef~~<br>~~|~~<br>~~PTTT~~|6.45<br><br>~~rE~~<br>~~TT~~|0.04 <br><br>~~rE~~<br>~~TTET~~|0.86<br><br>~~ET~~|0.36<br><br>~~ET~~|6.45<br><br>|5.25<br><br>|3.93 <br><br>|4.21<br><br>|9.34<br><br>|8.14<br><br>|ns<br><br>|
|||–2<br>~~ef~~<br>~~PT~~<br>~~Po~~|0.45<br>~~ef~~<br>~~| ~~<br>~~PTTT~~<br>|5.67<br> ~~rE~~<br>~~TT~~<br>|0.03 <br>~~rE~~<br>~~TTET~~<br>|0.76<br>~~ET~~<br>|0.32<br>~~ETTT~~<br>|5.67<br>~~TT~~<br>|4.61<br>~~TT~~<br>|3.45 <br>~~TT~~<br>|3.70<br>~~TT~~<br>|8.20<br>~~TT~~<br>|7.15<br>~~TT~~<br>|ns<br>~~TT~~<br>|
|100 µA|12 mA<br>~~Po~~<br>~~Po~~<br>~~Po~~|Std.<br>~~PT~~<br>~~Po~~<br>~~Po~~|0.60<br>~~PT TT~~<br>~~TE~~|5.46<br>~~TT~~<br>~~TE~~|0.04<br>~~TT ET~~<br>~~TE~~|1.02<br>~~ET~~<br>~~TE~~|0.43<br>~~ETTT~~<br>~~TE~~|5.46<br>~~TT~~<br>~~TE~~|4.29<br>~~TT~~<br>~~TE~~|4.97<br>~~TT~~<br>~~TE~~|5.54<br>~~TT~~<br>~~TE~~|8.86<br>~~TT~~<br>~~TE~~|7.68<br>~~TT~~<br>~~TE~~|ns<br>~~TT~~<br>~~TE~~|
|||–1<br><br>~~Po~~<br>~~Po~~<br>~~Po~~|0.51<br><br>~~TE~~<br>~~|~~<br>~~|~~|4.65<br><br>~~TE~~<br>~~EE~~|0.04<br><br>~~TE~~<br>~~EE~~|0.86<br><br>~~TE~~<br>~~EE~~|0.36<br>~~TT~~<br>~~TE~~|4.65<br>~~TT~~<br>~~TE~~|3.65<br>~~TT~~<br>~~TE~~|4.22<br>~~TT~~<br>~~TE~~|4.71<br>~~TT~~<br>~~TE~~|7.53<br>~~TT~~<br>~~TE~~|6.54<br>~~TT~~<br>~~TE~~|ns<br>~~TT~~<br>~~TE~~|
|||–2<br><br>~~Po~~<br>~~Po~~|0.45<br>~~TE~~<br>~~|~~<br>~~|~~|4.08<br>~~TE~~<br>~~EE~~|0.03<br>~~TE~~<br>~~EE~~|0.76<br>~~TE~~<br>~~EE~~|0.32<br>~~TE~~|4.08<br>~~TE~~|3.20<br>~~TE~~|3.71<br>~~TE~~|4.14<br>~~TE~~|6.61<br>~~TE~~|5.74<br>~~TE~~|ns<br>~~TE~~|
|100 µA|16 mA<br>~~Po~~|Std.<br>~~Po~~<br>~~et~~<br>~~ef~~|0.60<br>~~|~~<br>~~|~~<br>~~et~~<br>~~ef~~<br>~~|~~|5.15<br>~~EE~~<br>~~rE~~|0.04 <br>~~EE~~<br>~~rE~~|1.02<br>~~EE~~|0.43|5.15|3.89|5.04|5.69|8.55|7.29|ns|
|||–1<br>~~ef~~<br>~~ee~~|0.51<br>~~ef~~<br>~~|~~<br>~~ee~~|4.38<br>~~rE~~<br>~~ee~~|0.04 <br>~~rE~~<br>~~ee~~|0.86<br>~~ee~~|0.36<br>~~ee~~|4.38<br>~~ee~~|3.31<br>~~ee~~|4.29 <br>~~eee~~|4.84<br>~~eee~~|7.27<br>~~eee~~|6.20<br>~~eee~~|ns<br>~~eee~~|
|||–2<br>~~ef~~<br>~~ee~~|0.45<br>~~ef~~<br>~~|~~<br>~~ee~~|3.85<br>~~rE~~<br>~~ee~~|0.03 <br>~~rE~~<br>~~ee~~|0.76<br>~~ee~~|0.32<br>~~ee~~|3.85<br>~~ee~~|2.91<br>~~ee~~|3.77 <br>~~eee~~|4.25<br>~~eee~~|6.38<br>~~eee~~|5.44<br>~~eee~~|ns<br>~~eee~~|
|100 µA|24 mA|Std.<br>~~ee ~~<br>~~a~~<br>~~a~~|0.60<br> ~~ee~~<br>~~ee~~|4.75<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04 <br>~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee~~<br>~~eee~~|4.75<br>~~ee~~<br>~~eee~~<br>~~eee~~|3.22<br>~~ee~~<br>~~eee~~<br>~~eee~~|5.14 <br>~~eee~~<br>~~eee~~<br>~~eee~~|6.28<br>~~eee~~<br>~~eee~~<br>~~eee~~|8.15<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.61<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|||–1<br>~~a~~<br>~~et~~|0.51<br>~~ee~~<br>~~et~~<br>~~|~~|4.04<br>~~ee~~<br>~~r~~~~**E**~~|0.04 <br>~~ee~~<br>~~**E**~~|0.86<br>~~ee~~|0.36<br>~~eee~~|4.04<br>~~eee~~|2.74<br>~~eee~~|4.37 <br>~~eee~~|5.34<br>~~eee~~|6.93<br>~~eee~~|5.62<br>~~eee~~|ns<br>~~eee~~|
|||–2<br>~~a~~<br>~~et~~|0.45<br>~~ee ~~<br>~~et~~<br>~~|~~|3.55<br> ~~ee ~~<br>~~r~~~~**E**~~|0.03 <br> ~~ee~~<br>~~**E**~~|0.76<br>~~ee~~|0.32<br>~~eee~~|3.55<br>~~eee~~|2.40<br>~~eee~~<br>~~E~~|3.84 <br>~~eee~~<br>~~E~~|4.69<br>~~eee~~<br>~~E~~|6.09<br>~~eee~~<br>~~E~~|4.94<br>~~eee~~<br>~~E~~|ns<br>~~eee~~<br>~~E~~|
_Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. Software default selection highlighted in gray._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-41**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-51 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**|**Speed**<br>**Grade**<br>~~|~~|**tDOUT**<br>~~|~~|**tDP**<br>~~rE~~|**tDIN**<br>~~rEEE~~|**tPY**<br>~~EE~~|**tEOUT**<br>~~EE~~|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|100 µA|2 mA|Std.<br>~~|~~<br>~~ee~~<br>~~ae~~|0.60<br>~~|~~<br>~~ee~~<br>|15.86<br>~~rE~~<br>~~ee~~|0.04 <br>~~rEEE~~<br>~~ee~~|1.54<br>~~EE~~<br>~~ee~~|0.43<br>~~EE~~<br>~~ee~~|15.86 <br>~~ee~~|13.51 <br>~~ee~~|4.09 <br>~~ee~~<br>~~**e**~~|3.80 <br>~~ee~~<br>~~**e**e~~|19.25 <br>~~ee~~<br>~~eee~~|16.90<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–1<br>~~|~~<br>~~ee~~<br>~~ae~~|0.51<br>~~|~~<br>~~ee~~<br>|13.49<br>~~rE~~<br>~~ee~~|0.04 <br>~~rE EE~~<br>~~ee~~|1.31<br>~~EE~~<br>~~ee~~|0.36<br>~~EE~~<br>~~ee~~|13.49 <br>~~ee~~|11.49 <br>~~ee~~|3.48 <br>~~ee~~<br>~~**e**~~|3.23 <br>~~ee~~<br>~~**e**e~~|16.38 <br>~~ee~~<br>~~eee~~|14.38<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–2<br>~~ee~~<br>~~ae ~~|0.45<br>~~ee~~<br> ~~a~~|11.84<br>~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.15<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|11.84 <br>~~ee~~<br>~~e~~|10.09 <br>~~ee~~<br>~~e~~|3.05 <br>~~ee~~<br>~~**e**~~<br>~~e~~|2.84 <br>~~ee~~<br>~~**e**e~~|14.38 <br>~~ee~~<br>~~eee~~<br>~~e~~|12.62<br>~~ee~~<br>~~eee~~<br>~~e~~|ns<br>~~ee~~<br>~~eee~~<br>~~e~~|
|100 µA|4 mA|Std.<br>~~ae ~~<br>~~a~~<br>~~et~~|0.60<br> <br>~~ee~~<br>~~et~~<br>~~fT~~|11.25<br>~~ee ~~<br>~~fT~~|0.04 <br> ~~ee~~|1.54<br>~~ee ~~|0.43<br> ~~ee~~|11.25<br>~~ee~~|9.54<br>~~ee~~|4.61 <br>~~**e**~~<br>~~ee~~|4.70 <br>~~**e**e ~~<br>~~ee~~|14.64 <br> ~~eee~~<br>~~ee~~|12.93<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|||–1<br>~~et~~<br>~~et~~|0.51<br>~~et~~<br>~~fT~~<br>~~etTr~~|9.57<br>~~fT~~<br>~~Tr~~|0.04|1.31|0.36|9.57|8.11|3.92|4.00|12.46|11.00|ns|
|||–2<br>~~et~~<br>~~et~~|0.45<br>~~et~~<br>~~fT~~<br>~~etTr~~|8.40<br>~~fT~~<br>~~Tr~~|0.03|1.15|0.32|8.40|7.12|3.44|3.51|10.93|9.66|ns|
|100 µA|6 mA|Std.<br>~~et~~<br>~~eee~~<br>~~ee~~<br>~~a~~|0.60<br>~~et Tr~~<br>~~eee~~<br>~~ee~~|11.25<br>~~Tr~~<br>~~eee~~<br>~~ee~~|0.04 <br>~~eee~~<br>~~ee~~|1.54<br>~~eee~~<br>~~ee~~|0.43<br>~~eee~~<br>~~ee~~|11.25<br>~~eee~~<br>~~ee~~|9.54<br>~~eee~~<br>~~ee~~|4.61 <br>~~eee~~<br>~~ee~~<br>~~ee~~|4.70 <br>~~eee~~<br>~~ee~~<br>~~ee~~|14.64 <br>~~eee~~<br>~~ee~~<br>~~eee~~|12.93<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|||–1<br>~~ee~~<br>~~a~~|0.51<br>~~ee~~|9.57<br>~~ee~~|0.04 <br>~~ee~~|1.31<br>~~ee~~|0.36<br>~~ee~~|9.57<br>~~ee~~|8.11<br>~~ee~~|3.92 <br>~~ee~~<br>~~ee~~|4.00 <br>~~ee~~<br>~~ee~~|12.46 <br>~~ee~~<br>~~eee~~|11.00<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–2<br>~~ee~~<br>~~a~~|0.45<br>~~ee~~<br>~~a ~~|8.40<br>~~ee~~<br> ~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.15<br>~~ee~~<br>~~ee ~~|0.32<br>~~ee~~<br> ~~ee~~|8.40<br>~~ee~~<br>~~ee~~|7.12<br>~~ee~~<br>~~ee ~~|3.44 <br>~~ee~~<br>~~ee~~<br> ~~ee~~|3.51 <br>~~ee~~<br>~~ee ~~<br>~~ee ~~|10.93<br>~~ee~~<br> ~~eee~~<br> ~~ee~~|9.66<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|100 µA|8 mA|Std.<br>~~a~~<br>~~et~~|0.60<br>~~ee~~<br>~~et~~<br>~~fT~~|8.63<br>~~ee ~~<br>~~fT~~|0.04 <br> ~~ee~~|1.54<br>~~ee ~~|0.43<br> ~~ee~~|8.63<br>~~ee~~|7.39<br>~~ee~~|4.96 <br>~~ee~~|5.28 <br>~~ee~~|12.02 <br>~~ee~~|10.79<br>~~ee~~|ns<br>~~ee~~|
|||–1<br>~~et~~<br>~~et~~|0.51<br>~~et~~<br>~~fT~~<br>~~etTr~~|7.34<br>~~fT~~<br>~~Tr~~|0.04|1.31|0.36|7.34|6.29|4.22|4.49|10.23|9.18|ns|
|||–2<br>~~et~~<br>~~et~~<br>~~|~~|0.45<br>~~et~~<br>~~fT~~<br>~~etTr~~<br>~~|~~|6.44<br>~~fT~~<br>~~Tr~~<br>~~rE~~|0.03 <br>~~rEEE~~|1.15<br>~~EE~~|0.32<br>~~EE~~|6.44|5.52|3.70|3.94|8.98|8.06|ns|
|100 µA|16 mA|Std.<br>~~et~~<br>~~|~~<br>~~ee~~|0.60<br>~~et Tr~~<br>~~|~~<br>~~ee~~|8.05<br>~~Tr~~<br>~~rE~~<br>~~ee~~|0.04 <br>~~rEEE~~<br>~~ee~~|1.54<br>~~EE~~<br>~~ee~~|0.43<br>~~EE~~<br>~~ee~~|8.05<br>~~ee~~|6.93<br>~~ee~~|5.03 <br>~~ee~~|5.43 <br>~~ee~~|11.44 <br>~~eee~~|10.32<br>~~eee~~|ns<br>~~eee~~|
|||–1<br>~~|~~<br>~~ee~~|0.51<br>~~|~~<br>~~ee~~|6.85<br>~~rE~~<br>~~ee~~|0.04 <br>~~rE EE~~<br>~~ee~~|1.31<br>~~EE~~<br>~~ee~~|0.36<br>~~EE~~<br>~~ee~~|6.85<br>~~ee~~|5.90<br>~~ee~~|4.28 <br>~~ee~~|4.62<br>~~ee~~|9.74<br>~~eee~~|8.78<br>~~eee~~|ns<br>~~eee~~|
|||–2<br>~~ee ~~<br>~~a~~|0.45<br> ~~ee~~<br>~~a ~~|6.01<br>~~ee~~<br> ~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.15<br>~~ee~~<br>~~ee ~~|0.32<br>~~ee~~<br> ~~ee~~|6.01<br>~~ee~~<br>~~ee~~|5.18<br>~~ee ~~<br>~~ee ~~|3.76 <br> ~~ee~~<br> ~~ee~~|4.06<br>~~ee ~~<br>~~ee ~~|8.55<br> ~~eee~~<br> ~~ee~~|7.71<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|100 µA|24 mA|Std.<br>~~a~~<br>~~et~~|0.60<br>~~ee~~<br>~~et~~<br>~~fT~~|7.50<br>~~ee ~~<br>~~fT~~|0.04 <br> ~~ee~~|1.54<br>~~ee ~~|0.43<br> ~~ee~~|7.50<br>~~ee~~|6.90<br>~~ee~~|5.13 <br>~~ee~~|6.00 <br>~~ee~~|10.89 <br>~~ee~~|10.29<br>~~ee~~|ns<br>~~ee~~|
|||–1<br>~~et~~<br>~~et~~|0.51<br>~~et~~<br>~~fT~~<br>~~et~~<br>~~fT~~|6.38<br>~~fT~~<br>~~fTEE~~|0.04 <br>~~EE~~|1.31<br>~~EE~~|0.36|6.38|5.87|4.36|5.11|9.27|8.76|ns|
|||–2<br>~~et~~<br>~~et~~|0.45<br>~~et~~<br>~~fT~~<br>~~et~~<br>~~fT~~|5.60<br>~~fT~~<br>~~fTEE~~|0.03 <br>~~EE~~|1.15<br>~~EE~~|0.32|5.60|5.15|3.83|4.48|8.13|7.69|ns|
_Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-42**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-52 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**|**Speed**<br>**Grade**<br>~~Pf~~|**tDOUT**<br>~~Pf~~<br>~~|~~|**tDP**<br>~~rE~~|**tDIN**<br>~~rE~~|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|100 µA|2 mA|Std.<br>~~Pf~~<br>~~ee~~|0.60<br>~~Pf~~<br>~~|~~<br>~~ee~~|11.14<br>~~rE~~<br>~~ee~~|0.04 <br>~~rE~~<br>~~ee~~|1.52<br>~~ee~~|0.43<br>~~eee~~|11.14<br>~~eee~~|9.54<br>~~eee~~|3.51 <br>~~eee~~|3.61 <br>~~eee~~|14.53 <br>~~eee~~|12.94<br>~~eee~~|ns<br>~~eee~~|
|||–1<br>~~Pf~~<br>~~ee~~<br>~~ee~~|0.51<br>~~Pf~~<br>~~|~~<br>~~ee~~<br>~~ee~~|9.48<br>~~rE~~<br>~~ee~~<br>~~ee~~|0.04 <br>~~rE~~<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.36<br>~~eee~~<br>~~ee~~|9.48<br>~~eee~~<br>~~ee~~|8.12<br>~~eee~~<br>~~ee~~|2.99 <br>~~eee~~<br>~~eee~~|3.07 <br>~~eee~~<br>~~eee~~|12.36 <br>~~eee~~<br>~~eee~~|11.00<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|||–2<br>~~ee ~~<br>~~ee~~<br>~~a~~|0.45<br> ~~ee~~<br>~~ee~~<br>~~ee~~|8.32<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.03 <br>~~ee~~<br>~~ee~~<br>~~ee~~|1.14<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~eee~~<br>~~ee~~<br>~~ee~~|8.32<br>~~eee~~<br>~~ee~~<br>~~eee~~|7.13<br>~~eee~~<br>~~ee~~<br>~~eee~~|2.62 <br>~~eee~~<br>~~eee~~<br>~~eee~~|2.70 <br>~~eee~~<br>~~eee~~<br>~~eee~~|10.85<br>~~eee~~<br>~~eee~~<br>~~eee~~|9.66<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|100 µA|4 mA|Std.<br>~~ee ~~<br>~~a~~<br>~~Pt~~|0.60<br> ~~ee ~~<br>~~ee~~<br>~~PtTE~~|6.96<br> ~~ee~~<br>~~ee~~<br>~~TE~~|0.04 <br>~~ee~~<br>~~ee~~<br>~~TE~~|1.52<br>~~ee ~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee~~|6.96<br>~~ee~~<br>~~eee~~|5.79<br>~~ee~~<br>~~eee~~|3.99 <br>~~eee~~<br>~~eee~~|4.45 <br>~~eee~~<br>~~eee~~|10.35<br>~~eee~~<br>~~eee~~|9.19<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|||–1<br>~~a~~<br>~~Pt~~<br>~~et~~|0.51<br>~~ee ~~<br>~~PtTE~~<br>~~etTr~~|5.92<br> ~~ee~~<br>~~TE~~<br>~~Tr~~|0.04 <br>~~ee ~~<br>~~TE~~|1.29<br> ~~ee~~|0.36<br>~~ee~~|5.92<br>~~eee~~|4.93<br>~~eee~~|3.39 <br>~~eee~~|3.78<br>~~eee~~|8.81<br>~~eee~~|7.82<br>~~eee~~|ns<br>~~eee~~|
|||–2<br>~~Pt~~<br>~~et~~<br>~~ef~~|0.45<br>~~Pt TE~~<br>~~etTr~~<br>~~ef~~<br>~~|~~|5.20<br>~~TE~~<br>~~Tr~~<br>~~rE~~|0.03 <br>~~TE~~<br>~~rE~~|1.14|0.32|5.20|4.33|2.98|3.32|7.73|6.86|ns|
|100 µA|6 mA|Std.<br>~~et~~<br>~~ef~~<br>~~ee~~|0.60<br>~~et Tr~~<br>~~ef~~<br>~~|~~|6.96<br>~~Tr~~<br>~~rE~~<br>~~ee~~|0.04 <br>~~rE~~<br>~~ee~~|1.52<br>~~ee~~|0.43<br>~~eee~~|6.96<br>~~eee~~|5.79<br>~~eee~~|3.99 <br>~~eee~~|4.45 <br>~~eee~~|10.35<br>~~eee~~|9.19<br>~~eee~~|ns<br>~~eee~~|
|||–1<br>~~ef~~<br>~~ee~~<br>~~PT~~|0.51<br>~~ef~~<br>~~|~~<br>~~PTTT~~|5.92<br>~~rE~~<br>~~ee~~<br>~~TT~~|0.04 <br>~~rE~~<br>~~ee~~<br>~~TTET~~|1.29<br>~~ee~~<br>~~ET~~|0.36<br>~~eee~~<br>~~ET~~|5.92<br>~~eee~~<br>|4.93<br>~~eee~~<br>|3.39 <br>~~eee~~<br>|3.78<br>~~eee~~<br>|8.81<br>~~eee~~<br>|7.82<br>~~eee~~<br>|ns<br>~~eee~~<br>|
|||–2<br>~~ee~~<br>~~PT~~<br>~~Pt~~|0.45<br>~~PTTT~~<br>~~Pt~~|5.20<br>~~ee~~<br>~~TT~~<br>|0.03 <br>~~ee~~<br>~~TTET~~<br>|1.14<br>~~ee ~~<br>~~ET~~<br>|0.32<br> ~~eee~~<br>~~ETTT~~<br>|5.20<br>~~eee~~<br>~~TT~~<br>|4.33<br>~~eee~~<br>~~TT~~<br>|2.98 <br>~~eee ~~<br>~~TT~~<br>|3.32<br> ~~eee~~<br>~~TT~~<br>|7.73<br>~~eee~~<br>~~TT~~<br>|6.86<br>~~eee~~<br>~~TT~~<br>|ns<br>~~eee~~<br>~~TT~~<br>|
|100 µA|8 mA|Std.<br>~~PT~~<br>~~Pt~~|0.60<br>~~PT TT~~<br>~~PtTE~~|4.89<br>~~TT~~<br>~~TE~~|0.04<br>~~TT ET~~<br>~~TE~~|1.52<br>~~ET~~<br>~~TE~~|0.43<br>~~ETTT~~<br>~~TE~~|4.89<br>~~TT~~<br>~~TE~~|3.92<br>~~TT~~<br>~~TE~~|4.31<br>~~TT~~<br>~~TE~~|4.98<br>~~TT~~<br>~~TE~~|8.28<br>~~TT~~<br>~~TE~~|7.32<br>~~TT~~<br>~~TE~~|ns<br>~~TT~~<br>~~TE~~|
|||–1<br><br>~~Pt~~<br>~~PT~~<br>~~PT~~|0.51<br><br>~~Pt~~<br>~~PT~~<br>~~PTTE~~|4.16<br><br><br>~~TE~~|0.04<br><br><br>~~TE~~|1.29<br><br>|0.36<br>~~TT~~<br>|4.16<br>~~TT~~<br>|3.34<br>~~TT~~<br>|3.67<br>~~TT~~<br>|4.24<br>~~TT~~<br>|7.04<br>~~TT~~<br>|6.22<br>~~TT~~<br>|ns<br>~~TT~~<br>|
|||–2<br>~~PT~~<br>~~Pt~~|0.45<br>~~PTTE~~<br>~~Pt~~<br>~~|~~|3.65<br>~~TE~~<br>~~rE~~|0.03<br>~~TE~~<br>~~rE~~|1.14|0.32|3.65|2.93|3.22|3.72|6.18|5.46|ns|
|100 µA|16 mA|Std.<br>~~PT~~<br>~~Pt~~<br>~~ee~~|0.60<br>~~PT TE~~<br>~~Pt~~<br>~~|~~<br>~~ee~~|4.89<br>~~TE~~<br>~~rE~~<br>~~ee~~|0.04 <br>~~TE~~<br>~~rE~~<br>~~ee~~|1.52<br>~~ee~~|0.43<br>~~eee~~|4.89<br>~~eee~~|3.92<br>~~eee~~|4.31 <br>~~eee~~|4.98<br>~~eee~~|8.28<br>~~eee~~|7.32<br>~~eee~~|ns<br>~~eee~~|
|||–1<br>~~Pt~~<br>~~ee~~<br>~~a~~|0.51<br>~~Pt~~<br>~~| ~~<br>~~ee~~<br>~~a~~|4.16<br> ~~rE~~<br>~~ee~~<br>~~ee~~|0.04 <br>~~rE~~<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.36<br>~~eee~~<br>~~ee~~|4.16<br>~~eee~~<br>~~ee~~|3.34<br>~~eee~~<br>~~ee~~|3.67 <br>~~eee~~<br>~~eee~~|4.24<br>~~eee~~<br>~~eee eee~~|7.04<br>~~eee~~<br>~~eee~~|6.22<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|||–2<br>~~ee ~~<br>~~a~~|0.45<br> ~~ee~~<br>~~a~~|3.65<br>~~ee~~<br>~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.14<br>~~ee ~~<br>~~ee~~|0.32<br> ~~eee~~<br>~~ee~~|3.65<br>~~eee~~<br>~~ee~~|2.93<br>~~eee~~<br>~~ee~~|3.22 <br>~~eee~~<br>~~eee~~|3.72<br>~~eee~~<br>~~eee eee~~|6.18<br>~~eee~~<br>~~eee~~|5.46<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
_Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. Software default selection highlighted in gray._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-43**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-53 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**|**Speed**<br>**Grade**<br>~~|~~|**tDOUT**<br>~~|~~|**tDP**<br>~~rE~~|**tDIN**<br>~~rEEE~~|**tPY**<br>~~EE~~|**tEOUT**<br>~~EE~~|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|100 µA|2 mA|Std.<br>~~|~~<br>~~ee~~<br>~~ae~~|0.60<br>~~|~~<br>~~ee~~<br>|14.97<br>~~rE~~<br>~~ee~~|0.04 <br>~~rEEE~~<br>~~ee~~|1.52<br>~~EE~~<br>~~ee~~|0.43<br>~~EE~~<br>~~ee~~|14.97 <br>~~ee~~|12.79 <br>~~ee~~|3.52 <br>~~ee~~<br>~~**e**~~|3.41 <br>~~ee~~<br>~~**e**e~~|18.36 <br>~~ee~~<br>~~eee~~|16.18<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–1<br>~~|~~<br>~~ee~~<br>~~ae~~|0.51<br>~~|~~<br>~~ee~~<br>|12.73<br>~~rE~~<br>~~ee~~|0.04 <br>~~rE EE~~<br>~~ee~~|1.29<br>~~EE~~<br>~~ee~~|0.36<br>~~EE~~<br>~~ee~~|12.73 <br>~~ee~~|10.88 <br>~~ee~~|2.99 <br>~~ee~~<br>~~**e**~~|2.90 <br>~~ee~~<br>~~**e**e~~|15.62 <br>~~ee~~<br>~~eee~~|13.77<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–2<br>~~ee~~<br>~~ae ~~|0.45<br>~~ee~~<br> ~~a~~|11.18<br>~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.14<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|11.18<br>~~ee~~<br>~~e~~|9.55<br>~~ee~~<br>~~e~~|2.63 <br>~~ee~~<br>~~**e**~~<br>~~e~~|2.55 <br>~~ee~~<br>~~**e**e~~|13.71 <br>~~ee~~<br>~~eee~~<br>~~e~~|12.08<br>~~ee~~<br>~~eee~~<br>~~e~~|ns<br>~~ee~~<br>~~eee~~<br>~~e~~|
|100 µA|4 mA|Std.<br>~~ae ~~<br>~~a~~<br>~~et~~|0.60<br> <br>~~ee~~<br>~~et~~<br>~~fT~~|10.36<br>~~ee ~~<br>~~fT~~|0.04 <br> ~~ee~~|1.52<br>~~ee ~~|0.43<br> ~~ee~~|10.36<br>~~ee~~|8.93<br>~~ee~~|3.99 <br>~~**e**~~<br>~~ee~~|4.24 <br>~~**e**e ~~<br>~~ee~~|13.75 <br> ~~eee~~<br>~~ee~~|12.33<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|||–1<br>~~et~~<br>~~et~~|0.51<br>~~et~~<br>~~fT~~<br>~~etTr~~|8.81<br>~~fT~~<br>~~Tr~~|0.04|1.29|0.36|8.81|7.60|3.39|3.60|11.70|10.49|ns|
|||–2<br>~~et~~<br>~~et~~|0.45<br>~~et~~<br>~~fT~~<br>~~etTr~~|7.74<br>~~fT~~<br>~~Tr~~|0.03|1.14|0.32|7.74|6.67|2.98|3.16|10.27|9.21|ns|
|100 µA|6 mA|Std.<br>~~et~~<br>~~eee~~<br>~~ee~~<br>~~a~~|0.60<br>~~et Tr~~<br>~~eee~~<br>~~ee~~|10.36<br>~~Tr~~<br>~~eee~~<br>~~ee~~|0.04 <br>~~eee~~<br>~~ee~~|1.52<br>~~eee~~<br>~~ee~~|0.43<br>~~eee~~<br>~~ee~~|10.36<br>~~eee~~<br>~~ee~~|8.93<br>~~eee~~<br>~~ee~~|3.99 <br>~~eee~~<br>~~ee~~<br>~~ee~~|4.24 <br>~~eee~~<br>~~ee~~<br>~~ee~~|13.75 <br>~~eee~~<br>~~ee~~<br>~~eee~~|12.33<br>~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|||–1<br>~~ee~~<br>~~a~~|0.51<br>~~ee~~|8.81<br>~~ee~~|0.04 <br>~~ee~~|1.29<br>~~ee~~|0.36<br>~~ee~~|8.81<br>~~ee~~|7.60<br>~~ee~~|3.39 <br>~~ee~~<br>~~ee~~|3.60 <br>~~ee~~<br>~~ee~~|11.70 <br>~~ee~~<br>~~eee~~|10.49<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–2<br>~~ee~~<br>~~a~~|0.45<br>~~ee~~<br>~~a ~~|7.74<br>~~ee~~<br> ~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.14<br>~~ee~~<br>~~ee ~~|0.32<br>~~ee~~<br> ~~ee~~|7.74<br>~~ee~~<br>~~ee~~|6.67<br>~~ee~~<br>~~ee ~~|2.98 <br>~~ee~~<br>~~ee~~<br> ~~ee~~|3.16 <br>~~ee~~<br>~~ee ~~<br>~~ee ~~|10.27<br>~~ee~~<br> ~~eee~~<br> ~~ee~~|9.21<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|100 µA|8 mA|Std.<br>~~a~~<br>~~et~~|0.60<br>~~ee~~<br>~~et~~<br>~~fT~~|7.81<br>~~ee ~~<br>~~fT~~|0.04 <br> ~~ee~~|1.52<br>~~ee ~~|0.43<br> ~~ee~~|7.81<br>~~ee~~|6.85<br>~~ee~~|4.32 <br>~~ee~~|4.76 <br>~~ee~~|11.20 <br>~~ee~~|10.24<br>~~ee~~|ns<br>~~ee~~|
|||–1<br>~~et~~<br>~~et~~|0.51<br>~~et~~<br>~~fT~~<br>~~etTr~~|6.64<br>~~fT~~<br>~~Tr~~|0.04|1.29|0.36|6.64|5.82|3.67|4.05|9.53|8.71|ns|
|||–2<br>~~et~~<br>~~et~~<br>~~|~~|0.45<br>~~et~~<br>~~fT~~<br>~~etTr~~<br>~~|~~|5.83<br>~~fT~~<br>~~Tr~~<br>~~rE~~|0.03 <br>~~rEEE~~|1.14<br>~~EE~~|0.32<br>~~EE~~|5.83|5.11|3.22|3.56|8.36|7.65|ns|
|100 µA|16 mA|Std.<br>~~et~~<br>~~|~~<br>~~ee~~|0.60<br>~~et Tr~~<br>~~|~~<br>~~ee~~|7.81<br>~~Tr~~<br>~~rE~~<br>~~ee~~|0.04 <br>~~rEEE~~<br>~~ee~~|1.52<br>~~EE~~<br>~~ee~~|0.43<br>~~EE~~<br>~~ee~~|7.81<br>~~ee~~|6.85<br>~~ee~~|4.32 <br>~~ee~~|4.76 <br>~~ee~~|11.20 <br>~~eee~~|10.24<br>~~eee~~|ns<br>~~eee~~|
|||–1<br>~~|~~<br>~~ee~~|0.51<br>~~|~~<br>~~ee~~|6.64<br>~~rE~~<br>~~ee~~|0.04 <br>~~rE EE~~<br>~~ee~~|1.29<br>~~EE~~<br>~~ee~~|0.36<br>~~EE~~<br>~~ee~~|6.64<br>~~ee~~|5.82<br>~~ee~~|3.67 <br>~~ee~~|4.05<br>~~ee~~|9.53<br>~~eee~~|8.71<br>~~eee~~|ns<br>~~eee~~|
|||–2<br>~~ee ~~<br>~~a~~|0.45<br> ~~ee~~<br>a|5.83<br>~~ee~~<br> ~~ee~~|0.03 <br>~~ee~~<br>~~ee~~|1.14<br>~~ee~~<br>~~ee ~~|0.32<br>~~ee~~<br> ~~ee~~|5.83<br>~~ee~~<br>~~ee~~|5.11<br>~~ee ~~<br>~~ee ~~|3.22 <br> ~~ee~~<br> ~~ee~~|3.56<br>~~ee ~~<br>~~ee ee~~|8.36<br> ~~eee~~<br>~~ee~~|7.65<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
_Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-44**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-54 •**_ **3.3 V LVTTL / 3.3 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|100 µA|2 mA|Std.<br>~~PTE~~<br>~~a~~|0.60<br>~~PTE~~<br>~~ee~~|10.93<br>~~PTE~~<br>~~ee~~|0.04<br>~~PTE~~<br>~~ee~~|1.52<br>~~PTE~~<br>~~ee~~|0.43<br>~~PTE~~<br>~~ee~~|10.93<br>~~PTE~~<br>~~ee~~|9.46<br>~~PTE~~<br>~~ee~~|3.20<br>~~PTE~~<br>~~ee~~|3.32<br>~~PTE~~<br>~~eee~~|ns<br>~~PTE~~<br>~~eee~~|
|||–1<br>~~a~~<br>~~a~~|0.51<br>~~ee~~<br>~~ee~~|9.29<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|9.29<br>~~ee~~<br>~~ee~~|8.04<br>~~ee~~<br>~~ee~~|2.72<br>~~ee~~<br>~~ee~~|2.82<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|||–2<br>~~a~~<br>~~a~~<br>~~a~~|0.45<br>~~ee ~~<br>~~ee~~<br>~~ee~~|8.16<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.13<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~|8.16<br> ~~ee~~<br>~~ee~~<br>~~ee~~|7.06<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.39<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.48<br> ~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|100 µA|4 mA|Std.<br>~~a~~<br>~~a~~|0.60<br>~~ee ~~<br>~~ee~~|10.93<br> ~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee~~|1.52<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~<br>~~ee~~|10.93<br> ~~ee~~<br>~~ee~~<br>~~ee eee~~|9.46<br>~~ee~~<br>~~ee~~<br>~~eee~~|3.20<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|3.32<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|ns<br> ~~ee~~<br>~~ee~~<br>~~eee~~|
|||–1<br>~~a~~<br>~~ee~~|0.51<br>~~ee~~<br>~~ee~~|9.29<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|9.29<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|8.04<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.72<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.82<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|||–2<br>~~PT~~|0.45<br>~~PT~~|8.16<br>~~PT~~|0.03<br>~~PT~~|1.13<br>~~ee~~<br>~~PT~~|0.32<br>~~ee~~<br>~~PT~~|8.16<br>~~ee eee~~<br>~~PT~~|7.06<br>~~eee~~<br>~~PT~~|2.39<br>~~eee~~<br>~~PT~~|2.48<br>~~eee~~<br>~~PT~~|ns<br>~~eee~~<br>~~PT~~|
|100 µA|6 mA|Std.<br>~~PTE~~<br>~~a~~|0.60<br>~~PTE~~<br>~~ee~~|6.82<br>~~PTE~~<br>~~ee~~|0.04<br>~~PTE~~<br>~~ee~~|1.52<br>~~PTE~~<br>~~ee~~|0.43<br>~~PTE~~<br>~~ee~~|6.82<br>~~PTE~~<br>~~ee~~|5.70<br>~~PTE~~<br>~~ee~~|3.70<br>~~PTE~~<br>~~ee~~|4.16<br>~~PTE~~<br>~~ee~~|ns<br>~~PTE~~<br>~~ee~~|
|||–1<br>~~a~~<br>~~PF~~|0.51<br>~~ee~~<br>~~PFCTT~~|5.80<br>~~ee~~<br>~~CTT~~|0.04<br>~~ee~~<br>~~CTT~~|1.29<br>~~ee~~<br>|0.36<br>~~ee~~<br>|5.80<br>~~ee~~<br>|4.85<br>~~ee~~<br>|3.15<br>~~ee~~<br>|3.54<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||–2<br>~~a~~<br>~~PF~~|0.45<br>~~ee ~~<br>~~PFCTT~~|5.09<br> ~~ee~~<br>~~CTT~~|0.03<br>~~ee ~~<br>~~CTTETT~~|1.13<br> ~~ee~~<br>~~ETT~~|0.32<br>~~ee ~~<br>~~ETT~~|5.09<br> ~~ee~~<br>~~ETT~~|4.25<br>~~ee~~<br>~~ETT~~|2.77<br>~~ee ~~<br>~~ETT~~|3.11<br> ~~ee ~~<br>~~ETT~~|ns<br> ~~ee~~<br>~~ETT~~|
|100 µA|8 mA|Std.<br>~~PF~~<br>~~PTE~~|0.60<br>~~PF CTT~~<br>~~PTE~~|6.82<br>~~CTT~~<br>~~PTE~~|0.04<br>~~CTT~~<br>~~PTE~~|1.52<br><br>~~PTE~~|0.43<br><br>~~PTE~~|6.82<br><br>~~PTE~~|5.70<br><br>~~PTE~~|3.70<br><br>~~PTE~~|4.16<br><br>~~PTE~~|ns<br><br>~~PTE~~|
|||–1<br>~~PTE~~<br>~~PT~~|0.51<br>~~PTE~~<br>~~PTEE~~|5.80<br>~~PTE~~<br>~~EE~~|0.04<br>~~PTE~~<br>~~EE~~|1.29<br>~~PTE~~<br>~~EE~~|0.36<br>~~PTE~~|5.80<br>~~PTE~~|4.85<br>~~PTE~~|3.15<br>~~PTE~~|3.54<br>~~PTE~~|ns<br>~~PTE~~|
|||–2<br>~~PT~~|0.45<br>~~PTEE~~|5.09<br>~~EE~~|0.03<br>~~EE~~|1.13<br>~~EE~~|0.32|5.09|4.25|2.77|3.11|ns|
_Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. Software default selection highlighted in gray._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-45**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-55 •**_ **3.3 V LVTTL / 3.3 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Equiv.**<br>**Software**<br>**Default**<br>**Drive**<br>**Strength**<br>**Option1**|**Speed**<br>**Grade**<br>~~Pt~~|**tDOUT**<br>~~Pt~~|**tDP**<br>|**tDIN**<br>|**tPY**<br>|**tEOUT**<br>|**tZL**<br>|**tZH**<br>|**tLZ**<br>|**tHZ**<br>|**Units**<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|100 µA|2 mA|Std.<br>~~Pt~~<br>~~a~~<br>~~a~~|0.60<br>~~PtET~~<br>~~ee~~<br>|14.64<br>~~ET~~<br>~~ee~~<br>|0.04<br>~~ET~~<br>~~ee~~<br>|1.52<br>~~ET~~<br>~~ee~~<br>|0.43<br>~~ET~~<br>~~ee~~<br>|14.64<br>~~ET~~<br>~~ee~~<br>|12.97<br>~~ET~~<br>~~ee~~<br>~~ee~~<br>|3.21<br>~~ET~~<br>~~ee~~<br>~~ee~~<br>|3.15<br>~~ET~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ET~~<br>~~ee~~<br>~~ee~~|
|||–1<br>~~Pt~~<br>~~a~~<br>~~a~~<br>~~a~~|0.51<br>~~Pt~~<br>~~ee~~<br>~~ee~~<br>|12.45<br><br>~~ee~~<br>~~**ee**~~|0.04<br><br>~~ee~~<br>~~**ee**~~|1.29<br><br>~~ee~~<br>|0.36<br><br>~~ee~~<br>~~ee~~|12.45<br><br>~~ee~~<br>~~ee~~|11.04<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|2.73<br><br>~~ee~~<br>~~ee~~<br>~~**e**~~|2.68<br><br>~~ee~~<br>~~ee~~<br>~~**e**e~~|ns<br><br>~~ee~~<br>~~ee~~|
|||–2<br>~~a~~<br>~~a~~ <br>~~a~~|0.45<br>~~ee~~<br> ~~ee~~<br>|10.93<br>~~ee~~<br>~~**ee**~~|0.03<br>~~ee~~<br>~~**ee**~~|1.13<br>~~ee~~<br>|0.32<br>~~ee~~<br>~~ee~~|10.93<br>~~ee~~<br>~~ee~~|9.69<br>~~ee~~<br>~~ee ~~<br>~~ee~~|2.39<br>~~ee~~<br> ~~ee~~<br>~~**e**~~|2.35<br>~~ee~~<br>~~ee ~~<br>~~**e**e~~|ns<br>~~ee~~<br> ~~ee~~|
|100 µA|4 mA|Std.<br> <br>~~a ~~<br>~~Pt~~|0.60<br> ~~ee ~~<br> ~~a~~<br>~~Pt~~|14.64<br> ~~**ee**~~|0.04<br>~~**ee** ~~|1.52<br> <br>~~ee~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee ~~<br>~~ee~~|14.64<br>~~ee ~~<br> ~~ee~~<br>~~ee~~|12.97<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|3.21<br> ~~**e**~~<br>~~eee~~|3.15<br>~~**e**e~~<br>~~e~~<br>~~eee~~|ns<br>~~e~~<br>~~eee~~|
|||–1<br>~~ee~~<br>~~Pt~~|0.51<br>~~ee~~<br>~~Pt~~|12.45<br>~~ee~~|0.04<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|12.45<br>~~ee~~<br>~~ee~~|11.04<br>~~ee~~<br>~~eee~~|2.73<br>~~ee~~<br>~~eee~~|2.68<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–2<br>~~Pt~~<br>~~Pt~~|0.45<br>~~Pt~~<br>~~Pt~~|10.93<br>|0.03<br>|1.13<br>~~ee~~<br>|0.32<br>~~ee ~~<br>|10.93<br> ~~ee ~~<br>|9.69<br> ~~eee~~<br>|2.39<br>~~eee~~<br>|2.35<br>~~eee~~<br>|ns<br>~~eee~~<br>|
|100 µA|6 mA|Std.<br>~~Pt~~<br>~~a~~|0.60<br>~~PtET~~<br>~~ee~~|10.16<br>~~ET~~<br>~~ee~~|0.04<br>~~ET~~<br>~~ee~~|1.52<br>~~ET~~<br>~~ee~~|0.43<br>~~ET~~<br>~~ee~~|10.16<br>~~ET~~<br>~~ee~~|9.08<br>~~ET~~<br>~~eee~~|3.71<br>~~ET~~<br>~~eee~~|3.98<br>~~ET~~<br>~~eee~~|ns<br>~~ET~~<br>~~ee~~|
|||–1<br>~~Pt~~<br>~~a~~<br>~~a~~|0.51<br>~~Pt~~<br>~~ee~~<br>~~ee~~|8.64<br><br>~~ee~~<br>~~ee~~|0.04<br><br>~~ee~~<br>~~ee~~|1.29<br><br>~~ee~~<br>~~ee~~|0.36<br><br>~~ee~~<br>~~ee~~|8.64<br><br>~~ee~~<br>~~ee~~|7.73<br><br>~~eee~~<br>~~ee~~|3.15<br><br>~~eee~~<br>~~ee~~|3.39<br><br>~~eee~~<br>~~ee~~|ns<br><br>~~ee~~<br>~~ee~~|
|||–2<br>~~a~~<br>~~a~~|0.45<br>~~ee ~~<br>~~ee~~|7.58<br> ~~ee ~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~|1.13<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~|7.58<br>~~ee ~~<br>~~ee~~|6.78<br> ~~eee~~<br>~~ee~~|2.77<br>~~eee~~<br>~~ee~~|2.97<br>~~eee ~~<br>~~ee~~|ns<br> ~~ee~~<br>~~ee~~|
|100 µA|8 mA|Std.<br>~~a~~<br>~~a ~~|0.60<br>~~ee ~~<br> ~~a~~|10.16<br> ~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee ~~|1.52<br> ~~ee~~<br> ~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee ~~<br>~~ee~~|10.16<br> ~~ee~~<br> ~~ee~~<br>~~ee~~|9.08<br>~~ee ~~<br>~~ee ~~<br>~~eee~~|3.71<br> ~~ee~~<br> ~~ee~~<br>~~eee~~|3.98<br>~~ee ~~<br>~~ee~~<br>~~eee~~|ns<br> ~~ee~~<br>~~ee~~<br>~~eee~~|
|||–1<br>~~ee~~|0.51<br>~~ee~~|8.64<br>~~ee~~|0.04<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|8.64<br>~~ee~~<br>~~ee~~|7.73<br>~~ee~~<br>~~eee~~|3.15<br>~~ee~~<br>~~eee~~|3.39<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–2<br>~~PTE~~|0.45<br>~~PTE~~|7.58<br>~~PTE~~|0.03<br>~~PTE~~|1.13<br>~~ee~~<br>~~PTE~~|0.32<br>~~ee ~~<br>~~PTE~~|7.58<br> ~~ee ~~<br>~~PTE~~|6.78<br> ~~eee~~<br>~~PTE~~|2.77<br>~~eee~~<br>~~PTE~~|2.97<br>~~eee~~<br>~~PTE~~|ns<br>~~eee~~<br>~~PTE~~|
_Notes:_
_1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-46**
_ProASIC3 DC and Switching Characteristics_
## _**2.5 V LVCMOS**_
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5 V applications.
_**Table 2-56 •**_ **Minimum and Maximum DC Input and Output Levels**
## **Applicable to Advanced I/O Banks**
|**2.5 V LVCMOS**<br>~~a~~<br>~~ft~~|**VIL**<br>~~es~~<br>~~ft~~|**VIL**<br>~~es~~<br>~~ft~~|**VIH**<br>~~es~~<br>|**VIH**<br>~~es~~<br>|**VOL**<br>~~res~~<br>|**VOH**<br>~~Gd~~<br>|**IOL **<br>~~Gd~~<br>|**IOH**<br>~~Gn~~<br>|**IOSL**<br>|**IOSH**<br>|**IIL1 **<br>|**IIH2**<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**<br>~~a~~<br>~~ft~~<br>~~a~~|**Min.**<br>**V**<br>~~es~~<br>~~ftet~~<br>~~ee~~|**Max.**<br>**V**<br>~~es ~~<br>~~et~~<br>~~es ee~~|**Min.**<br>**V**<br> ~~es~~<br>~~et~~<br>~~ee es~~|**Max.**<br>**V**<br>~~es~~<br>~~et~~<br>~~es~~|**Max.**<br>**V**<br>~~res ~~<br>~~et~~<br>~~ee~~|**Min.**<br>**V**<br> ~~Gd~~<br>~~et~~<br>~~ee~~|**mA **<br>~~Gd ~~<br>~~et~~<br>~~Gs~~|**mA**<br> ~~Gn~~<br>~~et~~<br>~~Ge~~|**Max.**<br>**mA3**<br>~~et~~|**Max.**<br>**mA3**<br>~~et~~|**µA4 **<br>~~et~~|**µA4**<br>~~et~~|
|2 mA<br>~~ft~~<br>~~a~~<br>~~Re i~~|–0.3<br>~~ft~~<br>~~ee~~<br>~~i~~|0.7<br><br>~~es ee~~<br>~~ed~~|1.7<br><br>~~ee es~~<br>~~ee rs~~|2.7<br><br>~~es~~<br>~~rs~~|0.7<br><br>~~ee~~<br>~~eG~~|1.7<br><br>~~ee~~<br>~~eG~~|2<br><br>~~Gs~~<br>~~eG~~|2<br><br>~~Ge~~<br>~~Gr~~|18<br><br>~~Gr~~|16<br>|10 10<br>|10 10<br>|
|4 mA<br>~~a~~<br>~~Re i~~<br>~~a~~|–0.3<br>~~ee~~<br>~~i~~<br>~~ee~~|0.7<br>~~es ee~~<br>~~ed~~<br>~~es ee~~|1.7<br>~~ee es~~<br>~~ee rs~~<br>~~ee es~~|2.7<br>~~es ~~<br>~~rs~~<br>~~es~~|0.7<br> ~~ee~~<br>~~eG~~<br>~~ee~~|1.7<br>~~ee ~~<br>~~eG~~<br>~~ee~~|4<br> ~~Gs ~~<br>~~eG~~<br>~~Gs~~|4<br> ~~Ge~~<br>~~Gr~~<br>~~Ge~~|18<br>~~Gr~~|16|10 10|10 10|
|6 mA<br>~~Re i~~<br>~~a~~<br>~~ee~~|–0.3<br>~~i~~<br>~~ee~~<br>~~ee~~|0.7<br>~~ed ~~<br>~~es ee~~<br>~~es~~|1.7<br> ~~ee rs~~<br>~~ee es~~<br>~~ee~~|2.7<br>~~rs ~~<br>~~es~~<br>~~es ee~~|0.7<br> ~~eG~~<br>~~ee~~<br>~~ee~~|1.7<br>~~eG~~<br>~~ee~~<br>~~Ge~~|6<br>~~eG ~~<br>~~Gs~~<br>~~Ge~~|6<br> ~~Gr~~<br>~~Ge~~<br>~~ee~~|37<br>~~Gr~~|32|10 10|10 10|
|8 mA<br>~~a~~<br>~~ee~~<br>~~PoE~~|–0.3<br>~~ee~~<br>~~ee~~<br>~~PoE~~|0.7<br>~~es ee~~<br>~~es~~|1.7<br>~~ee es~~<br>~~ee~~<br>~~ee~~|2.7<br>~~es ~~<br>~~es ee~~<br>~~ee~~|0.7<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.7<br>~~ee ~~<br>~~Ge~~|8<br> ~~Gs ~~<br>~~Ge~~|8<br> ~~Ge~~<br>~~ee~~|37|32|10 10|10 10|
|12 mA<br>~~ee~~<br>~~PoE~~<br>~~ee~~|–0.3<br>~~ee~~<br>~~PoE~~<br>~~ee~~|0.7<br>~~es ~~<br>~~ee~~|1.7<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.7<br>~~es ee~~<br>~~ee~~<br>~~es~~|0.7<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.7<br> ~~Ge~~<br>~~Ge~~|12<br>~~Ge ~~<br>~~Ge~~|12<br> ~~ee~~<br>~~Gn~~|74<br>~~Gn~~|65|10|10|
|16 mA<br>~~PoE~~<br>~~ee~~<br>~~ee~~|–0.3<br>~~PoE~~<br>~~ee~~<br>~~ee~~|0.7<br>~~ee~~<br>~~ee~~|1.7<br>~~ee~~<br>~~ee~~<br>~~ee es~~|2.7<br>~~ee~~<br>~~es~~<br>~~es~~|0.7<br>~~ee~~<br>~~ee~~<br>~~re~~|1.7<br>~~Ge~~<br>~~Ge~~|16<br>~~Ge~~<br>~~Ge~~|16<br>~~Gn~~<br>~~Gr~~|87<br>~~Gn~~|83|10 10|10 10|
|24 mA<br>~~ee~~<br>~~ee~~|–0.3<br>~~ee ~~<br>~~ee~~|0.7<br> ~~ee ~~<br>~~ee~~|1.7<br> ~~ee~~<br>~~ee es~~|2.7<br>~~es~~<br>~~es~~|0.7<br>~~ee ~~<br>~~re~~|1.7<br> ~~Ge~~<br>~~Ge~~|24<br>~~Ge~~<br>~~Ge~~|24<br>~~Gn~~<br>~~Gr~~|124<br>~~Gn~~|169|10 10|10 10|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
_**Table 2-57 •**_ **Minimum and Maximum DC Input and Output Levels**
## **Applicable to Standard Plus I/O Banks**
|**2.5 V LVCMOS**<br>~~es~~|**VIL**<br>~~es~~|**VIL**<br>~~es~~|**VIH**<br>~~ers~~|**VIH**<br>~~ers~~|**VOL**<br>~~rr~~|**VOH**<br>~~Gs~~|**IOL **<br>~~Gs~~|**IOH**<br>~~Gs~~|**IOSL**<br>~~Gs~~|**IOSH**<br>~~GO~~|**IIL1 **<br>~~GO~~|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**<br>~~es ~~<br>~~eee~~<br>~~es~~|**Min.**<br>**V**<br> ~~es~~<br>~~eee~~<br>~~ee~~|**Max.**<br>**V**<br>~~es~~<br>~~eee~~<br>~~es~~|**Min.**<br>**V**<br>~~ers~~<br>~~eee~~<br>~~es~~|**Max.**<br>**V**<br>~~ers ~~<br>~~eee~~<br>~~es~~|**Max.**<br>**V**<br> ~~rr ~~<br>~~eee~~<br>~~re~~|**Min.**<br>**V**<br> ~~Gs~~<br>~~eee~~<br>~~Gs~~|**mA**<br>~~Gs~~<br>~~eee~~<br>~~Gs~~|**mA**<br>~~Gs~~<br>~~eee~~<br>~~Gs~~|**Max.**<br>**mA3**<br>~~Gs~~<br>~~eee~~<br>~~Gs~~|**Max.**<br>**mA3**<br>~~GO~~<br>~~eee~~<br>~~OO~~|**µA4 **<br>~~GO~~<br>~~eee~~<br>~~OO~~|**µA4**<br>~~eee~~|
|2 mA<br>~~es~~<br>~~es~~|–0.3<br>~~ee~~<br>~~es~~|0.7<br>~~es~~<br>~~es~~|1.7<br>~~es~~<br>~~ee~~|2.7<br>~~es~~<br>~~rs~~|0.7<br>~~re~~|1.7<br>~~Gs~~<br>~~Gs~~|2<br>~~Gs~~<br>~~Gs~~|2<br>~~Gs~~<br>~~Gs~~|18<br>~~Gs~~<br>~~Gs~~|16<br>~~OO~~<br>~~OO~~|10<br>~~OO~~<br>~~OO~~|10|
|4 mA<br>~~es ~~<br>~~es~~<br>~~es~~|–0.3<br> ~~ee~~<br>~~es~~<br>~~ee~~|0.7<br>~~es ~~<br>~~es~~<br>~~es~~|1.7<br> ~~es~~<br>~~ee~~<br>~~es~~|2.7<br>~~es ~~<br>~~rs~~<br>~~es~~|0.7<br> ~~re ~~<br>~~re~~|1.7<br> ~~Gs~~<br>~~Gs~~<br>~~Gs~~|4<br>~~Gs~~<br>~~Gs~~<br>~~Gs~~|4<br>~~Gs~~<br>~~Gs~~<br>~~Gs~~|18<br>~~Gs~~<br>~~Gs~~<br>~~Gs~~|16<br>~~OO~~<br>~~OO~~<br>~~OO~~|10 10<br>~~OO~~<br>~~OO~~<br>~~OO~~|10 10|
|6 mA<br>~~es~~<br>~~es~~<br>~~re~~|–0.3<br>~~es~~<br>~~ee~~<br>~~ee~~|0.7<br>~~es ~~<br>~~es~~<br>~~ee~~|1.7<br> ~~ee ~~<br>~~es~~<br>~~ee~~|2.7<br> ~~rs~~<br>~~es~~<br>~~ee~~|0.7<br>~~re~~<br>~~ee~~|1.7<br>~~Gs~~<br>~~Gs~~<br>~~ee~~|6<br>~~Gs~~<br>~~Gs~~<br>~~ee~~|6<br>~~Gs~~<br>~~Gs~~<br>~~eee~~|37<br>~~Gs~~<br>~~Gs~~<br>~~eee~~|32<br>~~OO~~<br>~~OO~~<br>~~eee~~|10<br>~~OO~~<br>~~OO~~<br>~~eee~~|10<br>~~eee~~|
|8 mA<br>~~es ~~<br>~~re~~<br>~~es~~|–0.3<br> ~~ee~~<br>~~ee~~<br>~~es~~|0.7<br>~~es ~~<br>~~ee~~<br>~~es~~|1.7<br> ~~es~~<br>~~ee~~<br>~~es~~|2.7<br>~~es ~~<br>~~ee~~<br>~~es~~|0.7<br> ~~re ~~<br>~~ee~~|1.7<br> ~~Gs~~<br>~~ee~~<br>~~Gs~~|8<br>~~Gs~~<br>~~ee~~<br>~~Gs~~|8<br>~~Gs~~<br>~~eee~~<br>~~Gs~~|37<br>~~Gs~~<br>~~eee~~<br>~~Gs~~|32<br>~~OO~~<br>~~eee~~<br>~~OO~~|10 10<br>~~OO~~<br>~~eee~~<br>~~OO~~|10 10<br>~~eee~~|
|12 mA<br>~~re~~<br>~~es~~|–0.3<br>~~ee ~~<br>~~es~~|0.7<br> ~~ee ~~<br>~~es~~|1.7<br> ~~ee ~~<br>~~es~~|2.7<br> ~~ee ~~<br>~~es~~|0.7<br> ~~ee~~|1.7<br>~~ee ~~<br>~~Gs~~|12<br> ~~ee~~<br>~~Gs~~|12<br>~~eee~~<br>~~Gs~~|74<br>~~eee ~~<br>~~Gs~~|65<br> ~~eee~~<br>~~OO~~|10<br>~~eee~~<br>~~OO~~|10<br>~~eee~~|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**2-47**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-58 •**_ **Minimum and Maximum DC Input and Output Levels**
**Applicable to Standard I/O Banks**
|**2.5 V LVCMOS**<br>~~i~~|**VIL**<br>~~es ees~~|**VIL**<br>~~es ees~~|**VIH**<br>~~ees~~|**VIH**<br>~~ees~~|**VOL**<br>~~rs~~|**VOH**<br>~~rsGd~~|**IOL **<br>~~Gd~~|**IOH**<br>~~Gn~~|**IOSL**|**IOSH**|**IIL1 **|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**<br>~~i ~~<br>~~eee~~<br>~~es ee~~|**Min.**<br>**V**<br> ~~es~~<br>~~eee~~<br>~~ee~~|**Max.,**<br>**V**<br>~~es ees~~<br>~~eee~~<br>~~ee~~|**Min.**<br>**V**<br>~~ees~~<br>~~eee~~<br>~~es~~|**Max.**<br>**V**<br>~~ees ~~<br>~~eee~~<br>~~dd~~|**Max.**<br>**V**<br> ~~rs~~<br>~~eee~~<br>~~dd~~|**Min.**<br>**V**<br>~~rs Gd~~<br>~~eee~~<br>~~dd~~<br>~~eG~~|**mA **<br>~~Gd ~~<br>~~eee~~<br>~~eG~~|**mA**<br> ~~Gn~~<br>~~eee~~<br>~~Ge~~|**Max.**<br>**mA3**<br>~~eee~~<br>~~es~~|**Max.**<br>**mA3**<br>~~eee~~|**µA4 **<br>~~eee~~|**µA4**<br>~~eee~~|
|2 mA<br>~~es ee~~<br>~~a~~|–0.3<br>~~ee~~<br>~~ee~~|0.7<br>~~ee~~<br>~~ee~~|1.7<br>~~es~~<br>~~ee es~~|3.6<br>~~dd~~<br>~~es~~|0.7<br>~~dd~~<br>~~re~~|1.7<br>~~dd~~<br>~~eG~~<br>~~reGe~~|2<br>~~eG~~<br>~~Ge~~|2<br>~~Ge~~<br>~~Od~~|16<br>~~es~~|18|10|10|
|4 mA<br>~~es ee~~<br>~~a~~<br>~~rr~~|–0.3<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.7<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.7<br>~~es ~~<br>~~ee es~~<br>~~eee~~|3.6<br> ~~dd~~<br>~~es~~<br>~~eee~~|0.7<br>~~dd~~<br>~~re~~<br>~~eee~~|1.7<br>~~dd~~<br>~~eG~~<br>~~reGe~~<br>~~ee~~|4<br>~~eG ~~<br>~~Ge~~|4<br> ~~Ge ~~<br>~~Od~~<br>~~eee~~|16<br> ~~es~~<br>~~eee~~|18<br>~~eee~~|10 10<br>~~eee~~|10 10<br>~~eee~~|
|6 mA<br>~~a~~<br>~~rr~~<br>~~ee ae~~|–0.3<br>~~ee~~<br>~~ee~~<br>~~ae~~|0.7<br>~~ee ~~<br>~~ee~~<br>~~es~~|1.7<br> ~~ee es~~<br>~~eee~~<br>~~re~~|3.6<br>~~es ~~<br>~~eee~~<br>~~es ee~~|0.7<br> ~~re~~<br>~~eee~~<br>~~ee~~|1.7<br>~~re Ge~~<br>~~ee~~<br>~~Oe~~|6<br>~~Ge ~~<br>~~Oe~~|6<br> ~~Od~~<br>~~eee~~<br>~~ee~~|32<br>~~eee~~|37<br>~~eee~~|10<br>~~eee~~|10<br>~~eee~~|
|8 mA<br>~~rr~~<br>~~ee ae~~|–0.3<br>~~ee ~~<br>~~ae~~|0.7<br> ~~ee ~~<br>~~es~~|1.7<br> ~~eee~~<br>~~re~~|3.6<br>~~eee ~~<br>~~es ee~~|0.7<br> ~~eee ~~<br>~~ee~~|1.7<br> ~~ee~~<br>~~Oe~~|8<br>~~Oe~~|8<br>~~eee~~<br>~~ee~~|32<br>~~eee ~~|37<br> ~~eee~~|10<br>~~eee~~|10<br>~~eee~~|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
R = 1 kΩ R to VCCI for tLZ / tZL / tZLS Test Point R to GND for tHZ / tZH / tZHS Test Point ~~1 j~~ Datapath 35 pF Enable Path 35 pF for tZH / tZHS / tZL / tZLS } } 35 pF for tHZ / tLZ
_**Figure 2-8 •**_ **AC Loading**
_**Table 2-59 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**CLOAD (pF)**|
|---|---|---|---|
|0|2.5|1.2|35|
_Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points._
**Revision 18**
**2-48**
_ProASIC3 DC and Switching Characteristics_
## **Timing Characteristics**
_**Table 2-60 •**_ **2.5 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a ~~<br>~~a~~|0.60<br> ~~ee~~<br>~~ee~~|8.66<br>~~ee~~ <br>~~ee~~|0.04<br> a<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~|7.83<br>~~ee~~<br>~~ee~~|8.66<br>~~ee ~~<br>~~ee~~|2.68<br> ~~ee~~<br>~~ee~~|2.30<br>~~ee~~<br>~~ee~~|10.07<br>~~eee~~<br>~~eee~~|10.90<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~|0.51<br>~~ee~~<br>~~ee~~|7.37<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.11<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~|6.66<br>~~ee~~<br>~~ee~~|7.37<br>~~ee~~<br>~~ee~~|2.28<br>~~ee~~<br>~~ee~~|1.96<br>~~ee~~<br>~~ee~~|8.56<br>~~eee~~<br>~~ee~~|9.27<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~ee~~<br>~~Pt~~|0.45<br>~~ee ~~<br>~~ee~~<br>~~PtEE~~|6.47<br> ~~ee ~~<br>~~ee~~<br>~~EE~~|0.03<br> ~~ee~~<br>~~ee~~<br>~~EE~~|0.98<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~|5.85<br>~~ee~~<br>~~ee~~|6.47<br>~~ee~~<br>~~ee~~|2.00<br>~~ee~~<br>~~ee~~|1.72<br>~~ee~~<br>~~ee~~|7.52<br>~~eee~~<br>~~ee~~|8.14<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|6 mA|Std.<br>~~ee~~<br>~~Pt~~<br>~~Pt~~|0.60<br>~~ee ~~<br>~~PtEE~~<br>~~PtEE~~|5.17<br> ~~ee ~~<br>~~EE~~<br>~~EE~~|0.04<br> ~~ee~~<br>~~EE~~<br>~~EE~~|1.31<br>~~ee ~~|0.43<br> ~~ee~~|5.04<br>~~ee ~~|5.17<br> ~~ee~~|3.05<br>~~ee ~~|3.00<br> ~~ee~~|7.27<br>~~ee~~|7.40<br>~~ee ~~|ns<br> ~~ee~~|
||–1<br>~~Pt~~<br>~~Pt~~<br>~~Pt~~|0.51<br>~~Pt EE~~<br>~~PtEE~~<br>~~PtET~~|4.39<br>~~EE~~<br>~~EE~~<br>~~ET~~|0.04<br>~~EE~~<br>~~EE~~<br>~~ET~~|1.11|0.36|4.28|4.39|2.59|2.55|6.19|6.30|ns|
||–2<br>~~Pt~~<br>~~Pt~~|0.45<br>~~Pt EE~~<br>~~PtET~~|3.86<br>~~EE~~<br>~~ET~~|0.03<br>~~EE~~<br>~~ET~~|0.98|0.32|3.76|3.86|2.28|2.24|5.43|5.53|ns|
|8 mA|Std.<br>~~Pt~~<br>~~a ~~<br>~~a~~|0.60<br>~~Pt ET~~<br> ~~ee~~<br>~~ee~~|5.17<br>~~ET~~<br>~~ee~~ <br>~~ee~~|0.04<br>~~ET~~<br> a<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~|5.04<br>~~ee~~<br>~~ee~~|5.17<br>~~ee ~~<br>~~ee~~|3.05<br> ~~ee~~<br>~~ee~~|3.00<br>~~ee~~<br>~~ee~~|7.27<br>~~eee~~<br>~~eee~~|7.40<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~Pt~~|0.51<br>~~ee~~<br>~~PtTt~~|4.39<br>~~ee~~<br>~~Tt~~|0.04<br>~~ee~~<br>~~Tt~~|1.11<br>~~ee~~|0.36|4.28<br>~~ee~~|4.39<br>~~ee~~|2.59<br>~~ee~~|2.55<br>~~ee~~|6.19<br>~~eee~~|6.30<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~a~~<br>~~Pt~~<br>~~Pt~~|0.45<br>~~ee ~~<br>~~PtTt~~<br>~~PtEt~~|3.86<br> ~~ee ~~<br>~~Tt~~<br>~~Et~~|0.03<br> ~~ee~~<br>~~Tt~~<br>~~Et~~|0.98<br>~~ee~~|0.32|3.76<br>~~ee~~|3.86<br>~~ee~~|2.28<br>~~ee~~|2.24<br>~~ee~~|5.43<br>~~eee~~|5.53<br>~~eee~~|ns<br>~~eee~~|
|12 mA<br>~~Pp~~|Std.<br>~~Pt~~<br>~~Pt~~<br>~~Pt~~|0.60<br>~~Pt Tt~~<br>~~PtEt~~<br>~~PtEE~~|3.56<br>~~Tt~~<br>~~Et~~<br>~~EE~~|0.04<br>~~Tt~~<br>~~Et~~<br>~~EE~~|1.31|0.43|3.63|3.43|3.30|3.44|5.86|5.67|ns|
||–1<br>~~Pt~~<br>~~Pt~~<br>~~Pp~~<br>~~|~~|0.51<br>~~Pt Et~~<br>~~PtEE~~<br>~~hE~~|3.03<br>~~Et~~<br>~~EE~~<br>~~hE~~<br>~~|~~|0.04<br>~~Et~~<br>~~EE~~|1.11|0.36|3.08|2.92|2.81|2.92|4.99|4.82|ns|
||–2<br>~~Pt~~<br>~~Pp~~<br>~~|~~|0.45<br>~~Pt EE~~<br>~~hE~~|2.66<br>~~EE~~<br>~~hE~~<br>~~|~~|0.03<br>~~EE~~|0.98|0.32|2.71|2.56|2.47|2.57|4.38|4.23|ns|
|16 mA<br>~~Pp~~|Std.<br>~~Pp~~<br>~~|~~<br>~~ee~~<br>~~ee~~|0.60<br>~~hE~~<br>~~ee ~~<br>~~ee~~|3.35<br>~~hE~~<br>~~|~~<br> ~~a~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|3.41<br>~~ee~~<br>~~ee~~|3.06<br>~~ee ~~<br>~~ee~~|3.36<br> ~~ee~~<br>~~ee~~|3.55<br>~~ee ~~<br>~~ee~~|5.65<br> ~~eee~~<br>~~eee~~|5.30<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~ee~~|0.51<br>~~ee~~<br>~~ee~~|2.85<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.11<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|2.90<br>~~ee~~<br>~~ee~~|2.60<br>~~ee~~<br>~~ee~~|2.86<br>~~ee~~<br>~~ee~~|3.02<br>~~ee~~<br>~~ee~~|4.81<br>~~eee~~<br>~~ee~~|4.51<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–2<br>~~ee~~<br>~~ee~~<br>~~Pt~~|0.45<br>~~ee ~~<br>~~ee~~<br>~~PtEE~~|2.50<br> ~~a~~<br>~~ee~~<br>~~EE~~|0.03<br>~~ee~~<br>~~ee~~<br>~~EE~~|0.98<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~|2.55<br>~~ee~~<br>~~ee~~|2.29<br>~~ee ~~<br>~~ee~~|2.51<br> ~~ee~~<br>~~ee~~|2.65<br>~~ee~~<br>~~ee~~|4.22<br>~~eee~~<br>~~ee~~|3.96<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|24 mA|Std.<br>~~ee~~<br>~~Pt~~<br>~~Pt~~|0.60<br>~~ee ~~<br>~~PtEE~~<br>~~PtEE~~|3.09<br> ~~ee ~~<br>~~EE~~<br>~~EE~~|0.04<br> ~~ee~~<br>~~EE~~<br>~~EE~~|1.31<br>~~ee ~~|0.43<br> ~~ee~~|3.15<br>~~ee ~~|2.44<br> ~~ee~~|3.44<br>~~ee ~~|4.00<br> ~~ee~~|5.38<br>~~ee~~|4.68<br>~~ee ~~|ns<br> ~~ee~~|
||–1<br>~~Pt~~<br>~~Pt~~<br>~~Pt~~|0.51<br>~~Pt EE~~<br>~~PtEE~~<br>~~PtET~~|2.63<br>~~EE~~<br>~~EE~~<br>~~ET~~|0.04<br>~~EE~~<br>~~EE~~<br>~~ET~~|1.11|0.36|2.68|2.08|2.92|3.40|4.58|3.98|ns|
||–2<br>~~Pt~~<br>~~Pt~~|0.45<br>~~Pt EE~~<br>~~PtET~~|2.31<br>~~EE~~<br>~~ET~~|0.03<br>~~EE~~<br>~~ET~~|0.98|0.32|2.35|1.82|2.57|2.98|4.02|3.49|ns|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-49**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-61 •**_ **2.5 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~ee~~|0.60<br>~~ee~~<br>~~ee~~|11.40<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|11.22<br>~~ee~~<br>~~ee~~|11.40<br>~~ee~~<br>~~ee~~|2.68<br>~~ee~~<br>~~ee~~|2.20<br>~~ee~~|13.45<br>~~eee~~<br>~~eee~~|13.63<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~<br>~~Pot~~|0.51<br>~~ee ~~<br>~~ee~~<br>~~Pot~~|9.69<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|1.11<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|9.54<br>~~ee ~~<br>~~ee~~|9.69<br> ~~ee~~<br>~~ee~~|2.28<br>~~ee ~~<br>~~ee~~|1.88<br> ~~ee~~|11.44<br>~~eee~~<br>~~eee~~|11.60<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.45<br> ~~ee ~~<br>~~Pot~~|8.51<br> ~~ee~~|0.03<br>~~ee~~|0.98<br>~~ee ~~|0.32<br> ~~ee~~|8.38<br>~~ee ~~|8.51<br> ~~ee ~~|2.00<br> ~~ee~~|1.65|10.05<br>~~eee~~|10.18<br>~~eee~~|ns<br>~~eee~~|
|6 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.60<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|7.96<br>~~EE~~|0.04<br>~~EE~~|1.31|0.43|8.11|7.81|3.05|2.89|10.34|10.05|ns|
||–1<br>~~pt~~<br>~~a~~|0.51<br>~~ptEE~~<br>~~ee~~|6.77<br>~~EE~~<br>~~ee~~|0.04<br>~~EE~~|1.11<br>~~ee~~|0.36<br>~~ee~~|6.90<br>~~ee~~|6.65<br>~~ee~~|2.59<br>~~ee~~|2.46<br>~~eee~~|8.80<br>~~eee~~|8.55<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~pt~~<br>~~a~~<br>~~a~~|0.45<br>~~pt EE~~<br>~~ee~~<br>~~ee~~|5.94<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~EE~~<br>~~ee~~|0.98<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|6.05<br>~~ee~~<br>~~ee~~|5.84<br>~~ee~~<br>~~ee~~|2.28<br>~~ee~~<br>~~ee~~|2.16<br>~~eee~~<br>~~ee~~|7.72<br>~~eee~~<br>~~eee~~|7.50<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|8 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~a~~<br>~~ee~~|0.60<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.96<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.31<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.11<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.81<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.05<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.89<br> ~~eee~~<br>~~ee~~|10.34<br>~~eee ~~<br>~~eee~~<br>~~eee~~|10.05<br> ~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~<br>~~Pot~~|0.51<br>~~ee ~~<br>~~ee~~<br>~~Pot~~|6.77<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|1.11<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|6.90<br>~~ee ~~<br>~~ee~~|6.65<br> ~~ee~~<br>~~ee~~|2.59<br>~~ee ~~<br>~~ee~~|2.46<br> ~~ee~~|8.80<br>~~eee~~<br>~~eee~~|8.55<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.45<br> ~~ee ~~<br>~~Pot~~|5.94<br> ~~ee~~|0.03<br>~~ee~~|0.98<br>~~ee ~~|0.32<br> ~~ee~~|6.05<br>~~ee ~~|5.84<br> ~~ee ~~|2.28<br> ~~ee~~|2.16|7.72<br>~~eee~~|7.50<br>~~eee~~|ns<br>~~eee~~|
|12 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.60<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|6.18<br>~~EE~~|0.04<br>~~EE~~|1.31|0.43|6.29|5.92|3.30|3.32|8.53|8.15|ns|
||–1<br>~~pt~~<br>~~a~~|0.51<br>~~ptEE~~<br>~~ee~~|5.26<br>~~EE~~<br>~~ee~~|0.04<br>~~EE~~<br>~~ee~~|1.11<br>~~ee~~|0.36<br>~~ee~~|5.35<br>~~ee~~|5.03<br>~~ee~~|2.81<br>~~ee~~|2.83<br>~~ee~~|7.26<br>~~ee~~|6.94<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~pt~~<br>~~a~~<br>~~a~~|0.45<br>~~pt EE~~<br>~~ee~~<br>~~a~~|4.61<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.98<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|4.70<br>~~ee~~<br>~~ee~~|4.42<br>~~ee~~<br>~~ee~~|2.47<br>~~ee~~<br>~~ee~~|2.48<br>~~ee~~<br>~~ee~~|6.37<br>~~ee~~<br>~~ee~~|6.09<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|16 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~a~~<br>~~ee~~|0.60<br>~~ee~~<br>~~a~~<br>~~ee~~|5.76<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.31<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee~~<br>~~ee~~|5.87<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.53<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.44<br> ~~ee ~~<br>~~ee~~|8.11<br> ~~ee~~<br>~~ee~~<br>~~eee~~|7.76<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~ee~~<br>~~Pot~~|0.51<br> ~~a~~<br>~~ee~~<br>~~Pot~~|4.90<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|1.11<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|4.99<br>~~ee ~~<br>~~ee~~|4.70<br> ~~ee~~<br>~~ee~~|2.86<br>~~ee ~~<br>~~ee~~|2.92<br> ~~ee~~|6.90<br>~~ee~~<br>~~eee~~|6.60<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~ee ~~<br>~~Pot~~|0.45<br> ~~ee ~~<br>~~Pot~~|4.30<br> ~~ee~~|0.03<br>~~ee~~|0.98<br>~~ee ~~|0.32<br> ~~ee~~|4.38<br>~~ee ~~|4.13<br> ~~ee ~~|2.51<br> ~~ee~~|2.57|6.05<br>~~eee~~|5.80<br>~~eee~~|ns<br>~~eee~~|
|24 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~<br>~~pt~~|0.60<br>~~Pot~~<br>~~Pt~~<br>~~ptEE~~|5.51<br>~~EE~~|0.04<br>~~EE~~|1.31|0.43|5.50|5.51|3.43|3.87|7.74|7.74|ns|
||–1<br>~~pt~~<br>~~|~~|0.51<br>~~ptEE~~<br>~~ft~~|4.68<br>~~EE~~<br>~~ft~~<br>~~ft~~|0.04<br>~~EE~~<br>~~ft~~<br>~~tT~~|1.11<br>~~tT~~~~**t**~~|0.36<br>~~**t**l~~|4.68|4.68|2.92|3.29|6.58|6.59|ns|
||–2<br>~~pt~~<br>~~|~~|0.45<br>~~pt EE~~<br>~~ft~~|4.11<br>~~EE~~<br>~~ft~~<br>~~ft~~|0.03<br>~~EE~~<br>~~ft~~<br>~~tT~~|0.98<br>~~tT~~~~**t**~~|0.32<br>~~**t**l~~|4.11|4.11|2.56<br>~~t~~|2.89<br>~~t~~|5.78<br>~~t~~|5.78<br>~~t~~|ns<br>~~t~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-50**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-62 •**_ **2.5 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~a~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|8.28<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~|1.30<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|7.41<br>~~ee~~<br>~~ee~~|8.28<br>~~ee~~<br>~~ee~~|2.25<br>~~ee~~<br>~~ee~~|2.07<br>~~ee~~<br>~~ee~~|9.64<br>~~ee~~|10.51<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~|7.04<br> ~~a ~~<br>~~ee~~|0.04<br> ~~ee~~|1.10<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|6.30<br>~~ee ~~<br>~~ee~~|7.04<br> ~~ee~~<br>~~ee~~|1.92<br>~~ee~~<br>~~ee~~|1.76<br>~~ee~~<br>~~ee~~|8.20<br>~~ee~~|8.94<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a ~~<br>~~Pt~~<br>~~Po~~|0.49<br> ~~ee~~<br>~~Pt~~<br>~~Po~~|6.18<br>~~ee~~<br>~~Pt~~<br>~~Po~~|0.03<br>~~Pt~~|0.97<br>~~ee~~<br>~~Pt~~|0.32<br>~~ee ~~<br>~~Pt~~|5.53<br> ~~ee ~~<br>~~Pt~~|6.18<br> ~~ee~~<br>~~Pt~~|1.68<br>~~ee ~~<br>~~Pt~~|1.55<br> ~~ee ~~<br>~~Pt~~|7.20<br> ~~ee~~<br>~~Pt~~|7.85<br>~~Pt~~|ns<br>~~Pt~~|
|6 mA|Std.<br>~~Po~~<br>~~Pt~~|0.66<br>~~Po~~<br>~~PtET~~|4.85<br>~~Po~~<br>~~ET~~|0.04<br>~~ET~~|1.30|0.43|4.65|4.85|2.59|2.71|6.88|7.09|ns|
||–1<br>~~Po~~<br>~~Pt~~<br>~~a~~<br>~~a~~|0.56<br>~~Po~~<br>~~PtET~~<br>~~ee~~<br>|4.13<br>~~Po~~<br>~~ET~~<br>~~a~~<br>|0.04<br>~~ET~~<br>~~ee~~<br>|1.10<br>~~ee~~<br>|0.36<br>~~ee~~<br>|3.95<br>~~ee~~<br>|4.13<br>~~ee~~<br>|2.20<br>~~ee~~<br>~~ee~~<br>|2.31<br>~~ee~~<br>~~ee~~<br>|5.85<br>~~ee~~<br>~~eee~~|6.03<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~Pt~~<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~Pt ET~~<br>~~ee~~<br>~~ee a~~<br>|3.62<br>~~ET~~<br>~~a~~<br>~~a~~<br>|0.03<br>~~ET~~<br>~~ee~~<br>~~ee~~|0.97<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|3.47<br>~~ee~~<br>~~ee ee~~|3.62<br>~~ee~~<br>~~ee~~|1.93<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.02<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.14<br>~~ee~~<br>~~eee~~|5.29<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|8 mA|Std.<br>~~a~~<br>~~a~~ <br>~~a~~|0.66<br>~~ee ~~<br> ~~ee a~~<br>~~ee~~|4.85<br> ~~a~~<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.30<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.65<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|4.85<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.59<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.71<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.88<br>~~ee~~<br> ~~eee~~<br>~~ee~~|7.09<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
||–1<br> <br>~~a ~~|0.56<br> ~~ee a~~<br> ~~ee~~|4.13<br>~~a ~~<br>~~ee~~|0.04<br> ~~ee~~|1.10<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|3.95<br>~~ee ee~~<br>~~ee~~|4.13<br>~~ee~~<br>~~ee~~|2.20<br>~~ee~~<br>~~ee~~|2.31<br>~~ee~~<br>~~ee~~|5.85<br>~~ee~~|6.03<br>~~ee~~|ns<br>~~ee~~|
||–2<br> <br>~~a~~|0.49<br> ~~ee~~<br>~~a~~|3.62<br>~~ee~~<br>~~a~~|0.03<br>~~eee~~|0.97<br>~~ee~~<br>~~eee~~|0.32<br>~~ee ~~<br>~~eee~~|3.47<br> ~~ee ~~<br>~~eee~~|3.62<br> ~~ee~~<br>~~eee~~|1.93<br>~~ee ~~<br>~~eee~~|2.02<br> ~~ee ~~<br>~~eee~~|5.14<br> ~~ee~~<br>~~eee~~|5.29<br>~~eee~~|ns<br>~~eee~~|
|12 mA|Std.<br>~~Pot~~|0.66<br>~~Pot~~|3.21<br>~~Pot~~|0.04<br>~~Pot~~|1.30<br>~~Pot~~|0.43<br>~~Pot~~|3.27<br>~~Pot~~|3.14<br>~~Pot~~|2.82<br>~~Pot~~|3.11<br>~~Pot~~|5.50<br>~~Pot~~|5.38<br>~~Pot~~|ns<br>~~Pot~~|
||–1<br>~~Pt~~|0.56<br>~~Pt~~|2.73<br>~~TE~~|0.04<br>~~TE~~|1.10|0.36|2.78|2.67|2.40|2.65|4.68|4.57|ns|
||–2<br>~~re~~|0.49<br>~~re~~|2.39<br>~~eee~~|0.03<br>~~eee~~|0.97<br>~~eee~~|0.32<br>~~eee~~|2.44<br>~~eee~~|2.35<br>~~eee~~|2.11<br>~~eee~~|2.32<br>~~eee~~|4.11<br>~~eee~~|4.02<br>~~eee~~|ns<br>~~eee~~|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_**Table 2-63 •**_ **2.5 V LVCMOS Low Slew**
## **Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**<br>~~Pot~~|**Speed**<br>**Grade**<br>~~Pot~~|**tDOUT**<br>~~Pot~~|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**tZLS**|**tZHS**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|4 mA<br>~~Pot~~<br>~~pot~~<br>~~pt~~<br>~~a~~|Std.<br>~~Pot~~|0.66<br>~~Pot~~|10.84|0.04|1.30|0.43|10.64|10.84|2.26|1.99|12.87|13.08|ns|
||–1<br>~~Pot~~<br>~~pot~~<br>~~pt~~|0.56<br>~~Pot~~<br>~~pot~~<br>~~ptEE~~|9.22<br>~~pot~~<br>~~EE~~|0.04<br>~~pot~~<br>~~EE~~|1.10<br>~~pot~~|0.36<br>~~pot~~|9.05<br>~~pot~~|9.22<br>~~pot~~|1.92<br>~~pot~~|1.69<br>~~pot~~|10.95<br>~~pot~~|11.12<br>~~pot~~|ns<br>~~pot~~|
||–2<br>~~pt~~<br>~~a~~|0.49<br>~~ptEE~~<br>~~ee~~|8.10<br>~~EE~~|0.03<br>~~EE~~<br>~~ee~~|0.97<br>~~ee~~|0.32<br>~~ee~~|7.94<br>~~ee~~|8.10<br>~~ee~~|1.68<br>~~ee~~|1.49<br>~~eee~~|9.61<br>~~eee~~|9.77<br>~~eee~~|ns<br>~~eee~~|
|6 mA<br>~~pt~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~Pot~~|Std.<br>~~pt~~<br>~~a~~<br>~~a~~|0.66<br>~~pt EE~~<br>~~ee~~<br>|7.37<br>~~EE~~<br>|0.04<br>~~EE~~<br>~~ee~~|1.30<br>~~ee~~|0.43<br>~~ee~~|7.50<br>~~ee~~|7.36<br>~~ee~~<br>~~ee~~|2.59<br>~~ee~~<br>~~ee~~|2.61<br>~~eee~~<br>~~eee~~|9.74<br>~~eee~~<br>~~eee~~|9.60<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~ee~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.27<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.10<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.38<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.26<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.20<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.22<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|8.29<br>~~eee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|8.16<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~Pot~~|0.49<br> ~~ee~~<br>~~Pot~~|5.50<br>~~ee~~|0.03<br>~~ee~~|0.97<br>~~ee~~|0.32<br>~~ee~~|5.60<br>~~ee~~|5.50<br>~~ee~~<br>~~eee~~|1.93<br>~~ee ~~<br>~~eee~~|1.95<br> ~~eee~~<br>~~eee~~|7.27<br>~~eee ~~<br>~~eee~~|7.17<br> ~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|8 mA<br><br>~~Pot~~<br>~~pot~~<br>~~pt~~<br>~~a~~|Std.<br> <br>~~Pot~~|0.66<br> ~~ee~~<br>~~Pot~~|7.37<br>~~ee~~|0.04<br>~~ee~~|1.30<br>~~ee~~|0.43<br>~~ee ~~|7.50<br> ~~ee ~~|7.36<br> ~~eee~~|2.59<br>~~eee~~|2.61<br>~~eee ~~|9.74<br> ~~eee~~|9.60<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~Pot~~<br>~~pot~~<br>~~pt~~|0.56<br>~~Pot~~<br>~~pot~~<br>~~ptEE~~|6.27<br>~~pot~~<br>~~EE~~|0.04<br>~~pot~~<br>~~EE~~|1.10<br>~~pot~~|0.36<br>~~pot~~|6.38<br>~~pot~~|6.26<br>~~pot~~|2.20<br>~~pot~~|2.22<br>~~pot~~|8.29<br>~~pot~~|8.16<br>~~pot~~|ns<br>~~pot~~|
||–2<br>~~pt~~<br>~~a~~|0.49<br>~~ptEE~~<br>~~ee~~|5.50<br>~~EE~~|0.03<br>~~EE~~<br>~~ee~~|0.97<br>~~ee~~|0.32<br>~~ee~~|5.60<br>~~ee~~|5.50<br>~~ee~~|1.93<br>~~ee~~|1.95<br>~~eee~~|7.27<br>~~eee~~|7.17<br>~~eee~~|ns<br>~~eee~~|
|12 mA<br>~~pt~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~pt~~<br>~~a~~<br>~~a~~|0.66<br>~~pt EE~~<br>~~ee~~<br>~~ee~~|5.63<br>~~EE~~<br>~~a~~|0.04<br>~~EE~~<br>~~ee~~<br>~~ee~~|1.30<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|5.73<br>~~ee~~<br>~~ee~~|5.51<br>~~ee~~<br>~~ee~~|2.83<br>~~ee~~<br>~~ee~~|3.01<br>~~eee~~<br>~~ee~~|7.97<br>~~eee~~<br>~~ee~~|7.74<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~<br>~~a~~|4.79<br>~~a~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.10<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.88<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.68<br> ~~ee~~<br>~~ee~~|2.41<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.56<br> ~~eee~~<br>~~ee~~<br>~~ee~~|6.78<br>~~eee ~~<br>~~ee~~<br>~~ee~~|6.59<br> ~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~a~~|4.20<br> ~~a ~~<br>~~a~~|0.03<br> ~~ee~~<br>~~ee~~|0.97<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|4.28<br> ~~ee ~~<br>~~ee~~|4.11<br> ~~ee~~|2.11<br>~~ee ~~<br>~~ee~~|2.25<br> ~~ee ~~<br>~~ee~~|5.95<br> ~~ee ~~<br>~~ee~~|5.78<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
**2-51**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-64 •**_ **2.5 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~a~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|8.20<br>~~a~~<br>~~ie~~|0.04<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|7.24<br>~~ee~~<br>~~ee~~|8.20<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.03<br>~~ee~~<br>~~ee~~|1.91<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.98<br> ~~a~~<br>~~ie~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.10<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.16<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.98<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.73<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.62<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~<br>~~ee~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.13<br> ~~ie~~<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.96<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.41<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.13<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.52<br>~~ee~~<br>~~ee~~<br>~~eee~~|1.43<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|4 mA|Std.<br>~~ee~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~|8.20<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.29<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~ee~~<br>~~ee~~|7.24<br>~~ee ~~<br>~~ee~~<br>~~ee~~|8.20<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2.03<br> ~~ee~~<br>~~eee~~<br>~~eee~~|1.91<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.98<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.10<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.16<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.98<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.73<br> ~~eee~~<br>~~eee~~<br>~~ee~~|1.62<br>~~eee ~~<br>~~eee~~<br>~~ee~~|ns<br> ~~eee~~<br>~~eee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.13<br> ~~ee~~<br>~~ee~~<br>~~a~~|0.03<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.96<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.32<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|5.41<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.13<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.52<br> ~~eee~~<br>~~ee~~<br>~~ee~~|1.43<br>~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|6 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.77<br> ~~ee ~~<br>~~a~~<br>~~ie~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.29<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.43<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4.55<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4.77<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.38<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.55<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|ns<br> ~~ee~~<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~|4.05<br> ~~a~~<br>~~ie~~|0.04<br>~~ee~~<br>~~ee~~|1.10<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee ~~<br>~~ee~~|3.87<br> ~~ee ~~<br>~~ee~~|4.05<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.03<br>~~ee~~<br>~~ee~~|2.17<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~a~~<br>~~PTT~~<br>~~ee~~|0.49<br>~~ee ~~<br>~~PTT~~|3.56<br> ~~ie~~<br>~~PTT~~|0.03<br>~~ee~~<br>~~PTT~~|0.96<br>~~ee~~<br>~~PTT~~|0.32<br>~~ee~~<br>~~PTT~~<br>~~ee~~|3.40<br>~~ee~~<br>~~PTT~~<br>~~ee~~|3.56<br>~~ee~~<br>~~ee~~<br>~~PTT~~<br>~~eee~~|1.78<br>~~ee~~<br>~~PTT~~<br>~~eee~~|1.91<br>~~ee~~<br>~~PTT~~<br>~~eee~~|ns<br>~~ee~~<br>~~PTT~~<br>~~ee~~|
|8 mA|Std.<br>~~ee~~<br>~~ee~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|4.77<br>~~ee~~<br>~~ee ee~~|0.04<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.55<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.77<br>~~ee~~<br>~~eee~~<br>~~ee~~|2.38<br>~~ee~~<br>~~eee~~<br>~~eee~~|2.55<br>~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~|4.05<br>~~ee ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.10<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.87<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.05<br>~~eee~~<br>~~ee~~<br>~~ee~~|2.03<br>~~eee~~<br>~~eee~~<br>~~ee~~|2.17<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
||–2<br>~~ee~~<br>~~a~~|0.49<br>~~ee~~<br>~~ee~~|3.56<br>~~ee ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.96<br>~~ee ~~<br>~~ee~~|0.32<br>~~ee ~~<br> ~~ee ~~<br>~~ee~~|3.40<br> ~~ee ~~<br> ~~ee ~~<br>~~ee~~|3.56<br> ~~eee~~<br> ~~ee ~~<br>~~ee~~|1.78<br>~~eee~~<br> ~~eee~~<br>~~ee~~|1.91<br>~~eee ~~<br>~~eee ~~<br>~~ee~~|ns<br> ~~ee~~<br> ~~eee~~<br>~~ee~~|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_**Table 2-65 •**_ **2.5 V LVCMOS Low Slew**
## **Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**<br>~~a~~|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|11.00<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|10.37<br>~~ee~~<br>~~ee~~|11.00<br>~~ee~~|2.03<br>~~ee~~<br>~~eee~~|1.83<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~|9.35<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.10<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.83<br>~~ee ~~<br>~~ee~~<br>~~ee~~|9.35<br> ~~ee~~<br>~~ee~~|1.73<br>~~ee ~~<br>~~eee~~<br>~~ee~~|1.56<br> ~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|8.21<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|0.03<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|0.96<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.75<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.21<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.52<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.37<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|4 mA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~<br>~~a~~|11.00<br>~~ee ~~<br>~~ee~~<br>~~a~~|0.04<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.29<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~<br>~~ee~~|10.37<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|11.00<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.03<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.83<br> ~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~|
||–1<br>~~a~~<br>~~a ~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br> ~~a~~<br>~~ee~~|9.35<br>~~ee~~<br>~~a~~<br>~~i~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.10<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|8.83<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|9.35<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.73<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.56<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–2<br> <br>~~a~~<br>~~a~~<br>~~a~~|0.49<br> ~~a ~~<br>~~ee~~<br>~~ee~~<br>|8.21<br> ~~a ~~<br>~~i~~<br>~~ee~~<br>|0.03<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.96<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>|7.75<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|8.21<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.52<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.37<br>~~ee~~|ns<br>~~ee~~|
|6 mA<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.50<br> ~~i ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.29<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.43<br> ~~ee ee~~<br>~~ee~~<br>~~ee~~|7.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.50<br> ~~ee~~<br>~~ee~~|2.39<br>~~ee~~<br>~~ee~~<br>~~eee~~|2.46<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–1<br>~~a~~ <br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br> ~~ee~~<br>~~ee~~|6.38<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.10<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.26<br> ~~ee ~~<br>~~ee~~<br>~~**e**e~~|6.38<br> ~~ee~~<br>~~ee~~|2.03<br>~~ee ~~<br>~~eee~~<br>~~ee~~|2.10<br> ~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~|
||–2<br> <br>~~a~~<br>~~a~~<br>~~a~~|0.49<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|5.60<br> ~~ee ~~<br>~~ee~~<br>~~e~~<br>|0.03<br> ~~ee ~~<br>~~ee~~<br>~~e~~<br>|0.96<br> ~~ee~~<br>~~ee~~<br>~~e~~<br>|0.32<br>~~ee ~~<br>~~ee~~<br>~~e~~<br>|5.49<br> ~~ee~~<br>~~**e**e~~<br>~~eee~~<br>|5.60<br>~~ee~~<br>~~ee~~<br>|1.78<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|1.84<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|8 mA<br>~~a~~<br>~~a~~<br>~~a~~|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|7.50<br> ~~ee ~~<br>~~e~~<br>~~ee~~<br>|0.04<br> ~~ee ~~<br>~~e~~<br>~~ee~~<br>|1.29<br> ~~ee ~~<br>~~e~~<br>~~ee~~<br>|0.43<br> ~~ee ~~<br>~~e~~<br>~~ee~~<br>|7.36<br> ~~**e**e ~~<br>~~eee~~<br>~~**e**e~~<br>|7.50<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.39<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.46<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–1<br>~~a~~ <br>~~a~~|0.56<br>~~ee~~<br> ~~ee~~<br>|6.38<br>~~e~~<br>~~ee~~<br>|0.04<br>~~e~~<br>~~ee~~<br>|1.10<br>~~e~~<br>~~ee~~<br>|0.36<br>~~e~~<br>~~ee~~<br>|6.26<br>~~eee ~~<br>~~**e**e~~<br>~~es~~|6.38<br> ~~ee~~<br>~~ee~~|2.03<br>~~ee~~<br>~~ee~~|2.10<br>~~ee~~|ns<br>~~ee~~|
||–2<br> <br>~~a ~~|0.49<br> ~~ee ~~<br> ~~a~~|5.60<br> ~~ee~~<br>~~e~~|0.03<br>~~ee ~~<br>~~e~~|0.96<br> ~~ee ~~<br>~~e~~|0.32<br> ~~ee ~~<br>~~e~~|5.49<br> ~~**e**e~~<br>~~ees~~|5.60<br>~~ee~~|1.78<br>~~ee~~|1.84|ns|
**Revision 18**
**2-52**
_ProASIC3 DC and Switching Characteristics_
## _**1.8 V LVCMOS**_
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
_**Table 2-66 •**_ **Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks**
|**1.8 V**<br>**LVCMOS**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL1 **|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~a~~|**Min**<br>**V**<br>~~a~~|**Max**<br>**V**<br>~~ee~~|**Min**<br>**V**<br>~~ee es~~|**Max**<br>**V**<br>~~es~~|**Max**<br>**V**<br>~~es es~~|**Min**<br>**V**<br>~~es~~|**mA **<br>~~fe~~|**mA**<br>~~ee~~|**Max**<br>**mA3**<br>~~ee~~|**Max**<br>**mA3**|**µA4 **|**µA4**|
|2 mA<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|0.35 * VCCI<br>~~ee~~<br>~~ee ee~~|0.65 * VCCI<br>~~ee es~~<br>~~ee~~|1.9<br>~~es~~<br>~~es~~|0.45<br>~~es es~~<br>~~es~~|VCCI – 0.45 2<br>~~es~~<br>~~es~~|VCCI – 0.45 2<br>~~fe~~<br>~~Oe~~|2<br>~~ee~~<br>~~Oe~~|11<br>~~ee~~<br>~~ee~~|9|10 10|10 10|
|4 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a ~~<br>~~a~~<br>~~a~~|0.35 * VCCI<br> ~~ee~~<br>~~ee ee~~<br>~~ee ee~~|0.65 * VCCI<br>~~ee es~~<br>~~ee~~<br>~~ee~~|1.9<br>~~es ~~<br>~~es~~<br>~~ee~~|0.45<br> ~~es es~~<br>~~es~~<br>~~ee~~|VCCI – 0.45 4<br>~~es ~~<br>~~es~~<br>~~ee~~|VCCI – 0.45 4<br> ~~fe ~~<br>~~Oe~~<br>~~ee~~|4<br> ~~ee ~~<br>~~Oe~~<br>~~ee~~|22<br> ~~ee~~<br>~~ee~~|17|10 10|10 10|
|6 mA<br>~~a ~~<br>~~a~~<br>~~a~~|–0.3<br> ~~a~~<br>~~a~~<br>~~ae~~|0.35 * VCCI<br>~~ee ee~~<br>~~ee ee~~<br>~~ee~~|0.65 * VCCI<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.9<br> ~~es ~~<br>~~ee~~<br>~~ee~~|0.45<br> ~~es ~~<br>~~ee~~<br>~~ee ee~~|VCCI – 0.45<br> ~~es~~<br>~~ee~~<br>~~ee~~|6<br>~~Oe~~<br>~~ee~~<br>~~ee ee~~|6<br>~~Oe ~~<br>~~ee~~<br>~~ee~~|44<br> ~~ee~~<br>~~ee~~|35|10 10|10 10|
|8 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~ae~~<br>~~ee a~~|0.35 * VCCI<br>~~ee ee~~<br>~~ee~~<br>~~a~~|0.65 * VCCI<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.9<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.45<br> ~~ee ~~<br>~~ee ee~~<br>~~ee es~~|VCCI – 0.45 8<br> ~~ee~~<br>~~ee~~<br>~~es~~|VCCI – 0.45 8<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~|8<br>~~ee~~<br>~~ee~~<br>~~ee~~|51<br>~~ee~~<br>~~ee~~|45|10 10|10 10|
|12 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~ae~~<br>~~ee a~~<br>~~a~~|0.35 * VCCI<br>~~ee~~<br>~~a~~<br>~~a~~|0.65 * VCCI<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.9<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.45<br> ~~ee ee~~<br>~~ee es~~<br>~~ee es~~|VCCI – 0.45<br>~~ee ~~<br>~~es~~<br>~~es~~|12<br> ~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|12<br>~~ee~~<br>~~ee~~<br>~~ee~~|74<br>~~ee~~<br>~~ee~~<br>~~ee~~|91|10|10<br>10|
|16 mA<br>~~a~~<br>~~a~~|–0.3<br>~~ee a~~<br>~~a~~|0.35 * VCCI<br>~~a~~<br>~~a~~|0.65 * VCCI<br>~~ee~~<br>~~ee~~|1.9<br>~~ee ~~<br>~~ee~~|0.45<br> ~~ee es~~<br>~~ee es~~|VCCI – 0.45 16<br>~~es ~~<br>~~es~~|VCCI – 0.45 16<br> ~~ee ee~~<br>~~ee ee~~|16<br>~~ee~~<br>~~ee~~|74<br>~~ee~~<br>~~ee~~|91|10 10|10 10|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
_**Table 2-67 •**_ **Minimum and Maximum DC Input and Output Levels**
## **Applicable to Standard Plus I/O I/O Banks**
|**1.8 V**<br>**LVCMOS**<br>~~ee~~|**VIL**<br>~~ee~~|**VIL**<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VOL**<br>~~ee~~|**VOH**<br>~~ee~~<br>~~ee~~|**IOL **<br>~~ee~~|**IOH**<br>~~ee~~<br>~~eee~~|**IOSL**<br>~~ee~~<br>~~eee~~|**IOSH**<br>~~ee~~<br>~~eee~~|**IIL1**<br>~~ee~~<br>~~eee~~|**IIH2**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~eee~~<br>~~a~~|**Min**<br>**V**<br>~~eee~~<br>~~a~~|**Max**<br>**V**<br>~~eee~~<br>~~es~~|**Min**<br>**V**<br>~~ee~~<br>~~eee~~<br>~~es~~|**Max**<br>**V**<br>~~ee~~<br>~~eee~~<br>~~es~~|**Max**<br>**V**<br>~~eee~~<br>~~es es~~|**Min**<br>**V**<br>~~ee~~<br>~~eee~~<br>~~es~~|**mA**<br>~~eee~~<br>~~Ge~~|**mA**<br>~~eee~~<br>~~eee~~<br>~~Ge~~|**Max**<br>**mA3**<br>~~eee~~<br>~~eee~~<br>~~Ge~~|**Max**<br>**mA3**<br>~~eee~~<br>~~eee~~|**µA4 **<br>~~eee~~<br>~~eee~~|**µA4**<br>~~eee~~<br>~~eee~~|
|2 mA<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|0.35 * VCCI<br>~~es~~<br>~~ee~~|0.65 * VCCI<br>~~es~~<br>~~es~~|3.6<br>~~es~~<br>~~es~~|0.45<br>~~es es~~<br>~~ss~~|VCCI – 0.45<br>~~es~~<br>~~ss~~|2<br>~~Ge~~<br>~~Ge~~|2<br>~~Ge~~<br>~~Ge~~|11<br>~~Ge~~|9|10|10|
|4 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~<br>~~a~~|0.35 * VCCI<br>~~es~~<br>~~ee~~<br>~~ee~~|0.65 * VCCI<br>~~es~~<br>~~es~~<br>~~es~~|3.6<br>~~es~~<br>~~es~~<br>~~ee~~|0.45<br>~~es es~~<br>~~ss~~<br>~~es~~|VCCI – 0.45<br>~~es ~~<br>~~ss~~<br>~~es~~|4<br> ~~Ge~~<br>~~Ge~~<br>~~Ge~~|4<br>~~Ge~~<br>~~Ge~~<br>~~Ge~~|22<br>~~Ge~~<br>~~ee~~|17|10|10|
|6 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~<br>~~a~~|0.35 * VCCI<br>~~ee ~~<br>~~ee~~<br>~~es~~|0.65 * VCCI<br> ~~es~~<br>~~es~~<br>~~ss~~|3.6<br>~~es ~~<br>~~ee~~<br>~~ss~~|0.45<br> ~~ss~~<br>~~es~~<br>~~dG~~|VCCI – 0.45<br>~~ss ~~<br>~~es~~<br>~~dG~~|6<br> ~~Ge ~~<br>~~Ge~~<br>~~dG~~|6<br> ~~Ge~~<br>~~Ge~~<br>~~GG~~|44<br>~~ee~~<br>~~GG~~|35<br>~~GG~~|10<br>~~GO~~|10|
|8 mA<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|0.35 * VCCI<br>~~ee~~<br>~~es~~|0.65 * VCCI<br>~~es ~~<br>~~ss~~|3.6<br> ~~ee~~<br>~~ss~~|0.45<br>~~es~~<br>~~dG~~|VCCI – 0.45<br>~~es ~~<br>~~dG~~|8<br> ~~Ge ~~<br>~~dG~~|8<br> ~~Ge ~~<br>~~GG~~|44<br> ~~ee~~<br>~~GG~~|35<br>~~GG~~|10<br>~~GO~~|10|
## _Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**2-53**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-68 •**_ **Minimum and Maximum DC Input and Output Levels**
## **Applicable to Standard I/O Banks**
|**1.8 V**<br>**LVCMOS**<br>~~ee~~<br>~~pot~~|**VIL**<br>~~ee~~<br>~~pot tt~~|**VIL**<br>~~ee~~<br>~~pot tt~~|**VIH**<br>~~ee~~<br>~~tt~~|**VIH**<br>~~ee~~<br>~~tt~~|**VOL**<br>~~ee~~|**VOH**<br>~~eee~~|**IOL**<br>~~eee~~|**IOH**<br>~~eee~~|**IOSL**<br>~~eee~~|**IOSH**<br>~~eee~~|**IIL1**<br>~~eee~~|**IIH2**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~ee~~<br>~~pot~~<br>~~a~~|**Min.**<br>**V**<br>~~ee~~<br>~~pot tt~~<br>~~ee~~|**Max.**<br>**V**<br>~~ee~~<br>~~tt~~<br>~~ee~~|**Min.**<br>**V**<br>~~ee~~<br>~~tt~~<br>~~ee~~|**Max.**<br>**V**<br>~~ee~~<br>~~ee~~|**Max.**<br>**V**<br>~~ee ~~|**Min.**<br>**V**<br> ~~eee~~<br>~~ee~~|**mA**<br>~~eee~~<br>~~ee~~|**mA**<br>~~eee~~<br>~~ee~~|**Max.**<br>**mA3**<br>~~eee~~<br>~~ee~~|**Max.**<br>**mA3**<br>~~eee~~<br>~~ee~~|**µA4 **<br>~~eee~~<br>~~ee~~|**µA4**<br>~~eee~~<br>~~ee~~|
|2 mA<br>~~pot~~<br>~~a~~<br>~~a~~|–0.3<br>~~pot tt~~<br>~~ee~~<br>~~ee~~|0.35 * VCCI<br>~~tt~~<br>~~ee~~<br>~~ee~~|0.65 * VCCI<br>~~tt~~<br>~~ee~~<br>~~ee~~|3.6<br>~~ee~~<br>~~ee~~|0.45 VCCI – 0.45<br>~~ee~~|0.45 VCCI – 0.45<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|9<br>~~ee~~<br>~~ee~~|11<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|
|4 mA<br>~~a ~~<br>~~a~~|–0.3<br> ~~ee~~<br>~~ee~~|0.35 * VCCI<br>~~ee~~<br>~~ee~~|0.65 * VCCI<br>~~ee~~<br>~~ee~~|3.6<br>~~ee~~<br>~~ee~~|0.45<br>~~ee~~|VCCI – 0.45<br>~~ee ~~<br>~~ee~~|4<br> ~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|17<br>~~ee ~~<br>~~ee~~|22<br> ~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**==> picture [323 x 68] intentionally omitted <==**
**----- Start of picture text -----**<br>
R = 1 kΩ R to VCCI for tLZ / tZL / tZLS<br>Test Point R to GND for tHZ / tZH / tZHS<br>Test Point<br>1 4<br>Datapath 35 pF Enable Path<br>35 pF for tZH / tZHS / tZL / tZLS<br>1 1 35 pF for tHZ / tLZ<br>**----- End of picture text -----**<br>
_**Figure 2-9 •**_ **AC Loading**
_**Table 2-69 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**CLOAD (pF)**|
|---|---|---|---|
|0|1.8|0.9|35|
_Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points._
**Revision 18**
**2-54**
_ProASIC3 DC and Switching Characteristics_
## **Timing Characteristics**
_**Table 2-70 •**_ **1.8 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>|**tDP**<br>|**tDIN**|**tPY**|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~**e**e~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a ee~~<br>~~a~~|0.66<br>~~ee~~<br>~~a~~|11.86<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|9.14<br>~~ee~~<br>~~ee~~<br>~~ee~~|11.86<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.77<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.66<br>~~ee~~<br>~~ee~~<br>~~ee~~|11.37<br>~~ee~~<br>~~**e**e~~|14.10<br>~~ee~~<br>~~eee~~<br>~~e~~|ns<br>~~ee~~<br>~~eee~~<br>~~e~~|
||–1<br>~~a ~~<br>~~ee~~|0.56<br> ~~a~~<br>~~ee~~|10.09<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.04<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.77<br>~~ee ~~<br>~~ee~~<br>~~ee~~|10.09<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.41<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|9.67<br> ~~**e**e ~~<br>~~ee~~|11.99<br> ~~eee~~<br>~~e~~<br>~~ee~~|ns<br>~~eee~~<br>~~e~~<br>~~ee~~|
||–2<br> <br>~~ee~~|0.49<br> ~~a ~~<br>~~ee~~|8.86<br> ~~a~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.91<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~|6.82<br>~~ee~~<br>~~ee~~|8.86<br>~~ee~~<br>~~ee~~|2.07<br>~~ee ~~<br>~~ee~~|1.24<br> ~~ee~~<br>~~ee~~|8.49<br>~~ee~~|10.53<br>~~e~~<br>~~ee~~|ns<br>~~e~~<br>~~ee~~|
|4 mA|Std.<br>~~ee~~<br>~~Pt~~|0.66<br>~~ee ~~<br>~~Pt~~|6.91<br> ~~ee ~~<br>~~Pt~~|0.04<br> ~~ee~~<br>~~Pt~~|1.22<br>~~ee ~~<br>~~Pt~~|0.43<br> ~~ee~~<br>~~Pt~~|5.86<br>~~ee~~<br>~~Pt~~|6.91<br>~~ee ~~<br>~~Pt~~|3.22<br> ~~ee~~<br>~~Pt~~|2.84<br>~~ee~~<br>~~Pt~~|8.10<br>~~ee~~<br>~~Pt~~|9.15<br>~~ee~~<br>~~Pt~~|ns<br>~~ee~~<br>~~Pt~~|
||–1<br>~~Pot~~<br>~~pt~~|0.56<br>~~Pot~~<br>~~pt~~|5.88<br>~~Pot~~<br>|0.04<br>~~Pot~~<br>|1.04<br>~~Pot~~<br>|0.36<br>~~Pot~~<br>|4.99<br>~~Pot~~<br>|5.88<br>~~Pot~~<br>|2.74<br>~~Pot~~<br>|2.41<br>~~Pot~~<br>|6.89<br>~~Pot~~<br>|7.78<br>~~Pot~~<br>|ns<br>~~Pot~~<br>|
||–2<br>~~pt~~<br>~~a~~|0.49<br>~~ptEE~~<br>|5.16<br>~~EE~~<br>|0.03<br>~~EE~~|0.91<br>~~EE~~|0.32<br>~~EE~~<br>~~ee~~|4.38<br>~~EE~~<br>~~ee~~|5.16<br>~~EE~~<br>~~ee~~|2.41<br>~~EE~~<br>~~ee~~|2.12<br>~~EE~~<br>~~ee~~|6.05<br>~~EE~~<br>~~**e**e~~|6.83<br>~~EE~~<br>~~eee~~|ns<br>~~EE~~<br>~~eee~~|
|6 mA|Std.<br>~~pt~~<br>~~a ee~~<br>~~a~~|0.66<br>~~pt~~<br>~~ee~~<br>~~a~~|4.45<br><br>~~ee~~<br>~~a~~|0.04<br><br>~~ee~~<br>~~ee~~|1.22<br><br>~~ee~~<br>~~ee~~|0.43<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|4.18<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|4.45<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|3.53<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|3.38<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|6.42<br><br>~~ee~~<br>~~**e**e~~|6.68<br><br>~~ee~~<br>~~eee~~<br>~~e~~|ns<br><br>~~ee~~<br>~~eee~~<br>~~e~~|
||–1<br>~~a ~~<br>~~ee~~|0.56<br> ~~a~~<br>~~ee~~|3.78<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.04<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.56<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.78<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.00<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.88<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|5.46<br> ~~**e**e ~~<br>~~ee~~|5.69<br> ~~eee~~<br>~~e~~<br>~~ee~~|ns<br>~~eee~~<br>~~e~~<br>~~ee~~|
||–2<br> <br>~~ee~~|0.49<br> ~~a ~~<br>~~ee~~|3.32<br> ~~a~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.91<br>~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~|3.12<br>~~ee~~<br>~~ee~~|3.32<br>~~ee~~<br>~~ee~~|2.64<br>~~ee ~~<br>~~ee~~|2.53<br> ~~ee~~<br>~~ee~~|4.79<br>~~ee~~|4.99<br>~~e~~<br>~~ee~~|ns<br>~~e~~<br>~~ee~~|
|8 mA|Std.<br>~~ee~~<br>~~Pt~~|0.66<br>~~ee ~~<br>~~Pt~~|3.92<br> ~~ee ~~<br>~~Pt~~|0.04<br> ~~ee~~<br>~~Pt~~|1.22<br>~~ee ~~<br>~~Pt~~|0.43<br> ~~ee~~<br>~~Pt~~|3.93<br>~~ee~~<br>~~Pt~~|3.92<br>~~ee ~~<br>~~Pt~~|3.60<br> ~~ee~~<br>~~Pt~~|3.52<br>~~ee~~<br>~~Pt~~|6.16<br>~~ee~~<br>~~Pt~~|6.16<br>~~ee~~<br>~~Pt~~|ns<br>~~ee~~<br>~~Pt~~|
||–1<br>~~Pot~~|0.56<br>~~Pot~~|3.34<br>~~Pot~~|0.04<br>~~Pot~~|1.04<br>~~Pot~~|0.36<br>~~Pot~~|3.34<br>~~Pot~~|3.34<br>~~Pot~~|3.06<br>~~Pot~~|3.00<br>~~Pot~~|5.24<br>~~Pot~~|5.24<br>~~Pot~~|ns<br>~~Pot~~|
||–2<br>~~Pt~~<br>~~Pt~~|0.49<br>~~Pt~~<br>~~Pt~~|2.93<br>~~Pt~~<br>|0.03<br>~~Pt~~<br>|0.91<br>~~Pt~~<br>|0.32<br>~~Pt~~<br>|2.93<br>~~Pt~~<br>|2.93<br>~~Pt~~<br>|2.69<br>~~Pt~~<br>|2.63<br>~~Pt~~<br>|4.60<br>~~Pt~~<br>|4.60<br>~~Pt~~<br>|ns<br>~~Pt~~<br>|
|12 mA<br>~~Pot~~|Std.<br>~~Pt~~<br>~~Pot~~|0.66<br>~~PtEE~~<br>~~PotEE~~|3.53<br>~~EE~~<br>~~EE~~|0.04<br>~~EE~~<br>~~EE~~|1.22<br>~~EE~~|0.43<br>~~EE~~|3.60<br>~~EE~~|3.04<br>~~EE~~|3.70<br>~~EE~~|4.08<br>~~EE~~|5.84<br>~~EE~~|5.28<br>~~EE~~|ns<br>~~EE~~|
||–1<br>~~Pt~~<br>~~Pot~~<br>~~Pt~~|0.56<br>~~Pt~~<br>~~PotEE~~<br>~~PtEE~~|3.01<br><br>~~EE~~<br>~~EE~~|0.04<br><br>~~EE~~<br>~~EE~~|1.04<br>|0.36<br>|3.06<br>|2.59<br>|3.15<br>|3.47<br>|4.96<br>|4.49<br>|ns<br>|
||–2<br>~~Pot~~<br>~~Pt~~|0.49<br>~~Pot EE~~<br>~~PtEE~~|2.64<br>~~EE~~<br>~~EE~~|0.03<br>~~EE~~<br>~~EE~~|0.91|0.32|2.69|2.27|2.76|3.05|4.36|3.94|ns|
|16 mA<br>~~pF~~|Std.<br>~~Pt~~<br>~~Pt~~|0.66<br>~~Pt EE~~<br>~~Pt~~|3.53<br>~~EE~~<br>~~Pt~~|0.04<br>~~EE~~<br>~~Pt~~|1.22<br>~~Pt~~|0.43<br>~~Pt~~|3.60<br>~~Pt~~|3.04<br>~~Pt~~|3.70<br>~~Pt~~|4.08<br>~~Pt~~|5.84<br>~~Pt~~|5.28<br>~~Pt~~|ns<br>~~Pt~~|
||–1<br>~~Pot~~<br>~~pF~~<br>~~|~~|0.56<br>~~Pot~~<br>~~|~~|3.01<br>~~Pot~~<br>~~UE~~|0.04<br>~~Pot~~<br>~~UEcE~~|1.04<br>~~Pot~~<br>~~cE~~|0.36<br>~~Pot~~|3.06<br>~~Pot~~|2.59<br>~~Pot~~|3.15<br>~~Pot~~|3.47<br>~~Pot~~|4.96<br>~~Pot~~|4.49<br>~~Pot~~|ns<br>~~Pot~~|
||–2<br>~~pF~~<br>~~|~~|0.49<br>~~|~~|2.64<br>~~UE~~|0.03<br>~~UEcE~~|0.91<br>~~cE~~|0.32|2.69|2.27|2.76|3.05|4.36|3.94|ns|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-55**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-71 •**_ **1.8 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~a~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~|15.53<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|14.11<br>~~ee~~<br>~~ee~~|15.53<br>~~ee~~<br>~~ee~~|2.78<br>~~ee~~<br>~~ee~~|1.60<br>~~ee~~<br>~~ee~~|16.35<br>~~ee~~<br>~~ee~~|17.77<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~ee~~|0.56<br> ~~a~~<br>~~a~~<br>~~ee~~|13.21<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.04<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~<br>~~ee~~|12.01<br>~~ee ~~<br>~~ee~~<br>~~ee~~|13.21<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2.36<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.36<br>~~ee~~<br>~~ee~~<br>~~eee~~|13.91<br>~~ee ~~<br>~~ee~~<br>~~eee~~|15.11<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~ee~~|0.49<br> ~~a~~<br>~~ee~~|11.60<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.91<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|10.54<br> ~~ee ~~<br>~~ee~~|11.60<br> ~~ee ~~<br>~~ee~~|2.07<br> ~~ee~~<br>~~ee~~|1.19<br>~~ee~~<br>~~eee~~|12.21<br>~~ee ~~<br>~~eee~~|13.27<br> ~~ee~~<br>~~eee~~|ns<br>~~eee~~|
|4 mA|Std.<br>~~ee~~<br>~~PF~~|0.66<br>~~ee~~<br>~~PF~~|10.48<br>~~PF~~|0.04<br>~~ee~~<br>~~PF~~|1.22<br>~~ee~~<br>~~PF~~|0.43<br>~~ee ~~<br>~~PF~~|10.41<br> ~~ee ~~<br>~~PF~~|10.48<br> ~~ee~~<br>~~PF~~|3.23<br>~~ee ~~<br>~~PF~~|2.73<br> ~~eee~~<br>~~PF~~|12.65<br>~~eee ~~<br>~~PF~~|12.71<br> ~~eee~~<br>~~PF~~|ns<br>~~eee~~<br>~~PF~~|
||–1<br>~~PFE~~<br>~~a~~|0.56<br>~~PFE~~<br>~~ee~~|8.91<br>~~PFE~~<br>~~ee~~|0.04<br>~~PFE~~<br>~~ee~~|1.04<br>~~PFE~~<br>~~ee~~|0.36<br>~~PFE~~<br>~~ee~~|8.86<br>~~PFE~~<br>~~ee~~|8.91<br>~~PFE~~<br>~~ee~~|2.75<br>~~PFE~~<br>~~ee~~|2.33<br>~~PFE~~<br>~~ee~~|10.76<br>~~PFE~~<br>~~eee~~|10.81<br>~~PFE~~<br>~~eee~~|ns<br>~~PFE~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~a~~|7.82<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.91<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|7.77<br>~~ee~~<br>~~ee~~|7.82<br>~~ee~~<br>~~ee~~|2.41<br>~~ee~~<br>~~ee~~|2.04<br>~~ee~~<br>~~ee~~|9.44<br>~~eee~~<br>~~ee~~|9.49<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|6 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~a~~<br>~~a~~|8.05<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~<br>~~ee~~|8.20<br> ~~ee~~<br>~~ee~~<br>~~ee~~|7.84<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.54<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.27<br>~~ee ~~<br>~~ee~~<br>~~ee~~|10.43<br> ~~eee~~<br>~~ee~~<br>~~ee~~|10.08<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~ee~~|0.56<br> ~~a~~<br>~~a~~<br>~~ee~~|6.85<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.04<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~<br>~~ee~~|6.97<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.67<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.01<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.78<br>~~ee~~<br>~~ee~~<br>~~eee~~|8.88<br>~~ee ~~<br>~~ee~~<br>~~eee~~|8.57<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~ee~~|0.49<br> ~~a~~<br>~~ee~~|6.01<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.91<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|6.12<br> ~~ee ~~<br>~~ee~~|5.86<br> ~~ee ~~<br>~~ee~~|2.64<br> ~~ee~~<br>~~ee~~|2.44<br>~~ee~~<br>~~eee~~|7.79<br>~~ee ~~<br>~~eee~~|7.53<br> ~~ee~~<br>~~eee~~|ns<br>~~eee~~|
|8 mA|Std.<br>~~ee~~<br>~~PF~~<br>~~PFE~~|0.66<br>~~ee~~<br>~~PF~~<br>~~PFE~~|7.50<br>~~PF~~<br>~~PFE~~|0.04<br>~~ee~~<br>~~PF~~|1.22<br>~~ee~~<br>~~PF~~|0.43<br>~~ee ~~<br>~~PF~~|7.64<br> ~~ee ~~<br>~~PF~~|7.30<br> ~~ee~~<br>~~PF~~|3.61<br>~~ee ~~<br>~~PF~~|3.41<br> ~~eee~~<br>~~PF~~|9.88<br>~~eee ~~<br>~~PF~~|9.53<br> ~~eee~~<br>~~PF~~|ns<br>~~eee~~<br>~~PF~~|
||–1<br>~~PFE~~<br>~~a~~|0.56<br>~~PFE~~<br>~~ee~~|6.38<br>~~PFE~~<br>~~ee~~|0.04|1.04<br>~~ee~~|0.36<br>~~ee~~|6.50<br>~~ee~~|6.21<br>~~ee~~|3.07<br>~~ee~~|2.90<br>~~ee~~|8.40<br>~~ee~~|8.11<br>~~ee~~|ns<br>~~ee~~|
||–2<br>~~PFE~~<br>~~a~~<br>~~a~~|0.49<br>~~PFE~~<br>~~ee~~<br>~~ae~~|5.60<br>~~PFE~~<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~|0.91<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|5.71<br>~~ee~~<br>~~ee~~|5.45<br>~~ee~~<br>~~ee~~|2.69<br>~~ee~~<br>~~ee~~|2.55<br>~~ee~~<br>~~ee~~|7.38<br>~~ee~~<br>~~ee~~|7.12<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|12 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ae~~<br>~~a~~|7.29<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.23<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.29<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.71<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.95<br>~~ee ~~<br>~~ee~~<br>~~ee~~|9.47<br> ~~ee~~<br>~~ee~~<br>~~ee~~|9.53<br>~~ee ~~<br>~~ee~~<br>~~ee~~|ns<br> ~~ee~~<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~ee~~|0.56<br> ~~ae ~~<br>~~a~~<br>~~ee~~|6.20<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.04<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~<br>~~ee~~|6.15<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.20<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.15<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.36<br>~~ee ~~<br>~~ee~~<br>~~eee~~|8.06<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|8.11<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|ns<br> ~~ee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~ee~~|0.49<br> ~~a~~<br>~~ee~~|5.45<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.91<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|5.40<br> ~~ee ~~<br>~~ee~~|5.45<br> ~~ee ~~<br>~~ee~~|2.77<br> ~~ee~~<br>~~ee~~|2.95<br>~~ee~~<br>~~eee~~|7.07<br>~~ee ~~<br>~~eee~~|7.12<br> ~~ee~~<br>~~eee~~|ns<br>~~eee~~|
|16 mA|Std.<br>~~ee~~<br>~~PF~~|0.66<br>~~ee~~<br>~~PF~~|7.29<br>~~PF~~|0.04<br>~~ee~~<br>~~PF~~|1.22<br>~~ee~~<br>~~PF~~|0.43<br>~~ee ~~<br>~~PF~~|7.23<br> ~~ee ~~<br>~~PF~~|7.29<br> ~~ee~~<br>~~PF~~|3.71<br>~~ee ~~<br>~~PF~~|3.95<br> ~~eee~~<br>~~PF~~|9.47<br>~~eee ~~<br>~~PF~~|9.53<br> ~~eee~~<br>~~PF~~|ns<br>~~eee~~<br>~~PF~~|
||–1<br>~~PFE~~<br>~~a~~|0.56<br>~~PFE~~<br>~~ee~~|6.20<br>~~PFE~~<br>~~ee~~|0.04<br>~~PFE~~<br>~~ee~~|1.04<br>~~PFE~~<br>~~ee~~|0.36<br>~~PFE~~<br>~~ee~~|6.15<br>~~PFE~~<br>~~ee~~|6.20<br>~~PFE~~<br>~~ee~~|3.15<br>~~PFE~~<br>~~ee~~|3.36<br>~~PFE~~<br>~~ee~~|8.06<br>~~PFE~~<br>~~ee~~|8.11<br>~~PFE~~<br>~~ee~~|ns<br>~~PFE~~<br>~~ee~~|
||–2<br>~~a~~|0.49<br>~~ee~~|5.45<br>~~ee~~|0.03<br>~~ee~~|0.91<br>~~ee~~|0.32<br>~~ee~~|5.40<br>~~ee~~|5.45<br>~~ee~~|2.77<br>~~ee~~|2.95<br>~~ee~~|7.07<br>~~ee~~|7.12<br>~~ee~~|ns<br>~~ee~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-56**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-72 •**_ **1.8 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~a~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~|11.33<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.20<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|8.72<br>~~ee~~<br>~~ee~~|11.33<br>~~ee~~<br>~~ee~~|2.24<br>~~ee~~<br>~~ee~~|1.52<br>~~ee~~<br>~~ee~~|10.96<br>~~ee~~<br>~~ee~~|13.57<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~ee~~|0.56<br> ~~a~~<br>~~a~~<br>~~ee~~|9.64<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~<br>~~ee~~|7.42<br>~~ee ~~<br>~~ee~~<br>~~ee~~|9.64<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.91<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.29<br>~~ee~~<br>~~ee~~<br>~~eee~~|9.32<br>~~ee ~~<br>~~ee~~<br>~~eee~~|11.54<br> ~~eee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–2<br>~~a ~~<br>~~ee~~|0.49<br> ~~a~~<br>~~ee~~|8.46<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.90<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~|6.51<br> ~~ee ~~<br>~~ee~~|8.46<br> ~~ee ~~<br>~~ee~~|1.68<br> ~~ee~~<br>~~ee~~|1.14<br>~~ee~~<br>~~eee~~|8.18<br>~~ee ~~<br>~~eee~~|10.13<br> ~~ee~~<br>~~eee~~|ns<br>~~eee~~|
|4 mA|Std.<br>~~ee~~<br>~~PF~~|0.66<br>~~ee~~<br>~~PF~~|6.48<br>~~PF~~|0.04<br>~~ee~~<br>~~PF~~|1.20<br>~~ee~~<br>~~PF~~|0.43<br>~~ee ~~<br>~~PF~~|5.48<br> ~~ee ~~<br>~~PF~~|6.48<br> ~~ee~~<br>~~PF~~|2.65<br>~~ee ~~<br>~~PF~~|2.60<br> ~~eee~~<br>~~PF~~|7.72<br>~~eee ~~<br>~~PF~~|8.72<br> ~~eee~~<br>~~PF~~|ns<br>~~eee~~<br>~~PF~~|
||–1<br>~~PFE~~<br>~~a~~|0.56<br>~~PFE~~<br>~~ee~~|5.51<br>~~PFE~~<br>~~ee~~|0.04<br>~~PFE~~<br>~~ee~~|1.02<br>~~PFE~~<br>~~ee~~|0.36<br>~~PFE~~<br>~~ee~~|4.66<br>~~PFE~~<br>~~ee~~|5.51<br>~~PFE~~<br>~~ee~~|2.25<br>~~PFE~~<br>~~ee~~|2.21<br>~~PFE~~<br>~~ee~~|6.56<br>~~PFE~~<br>~~eee~~|7.42<br>~~PFE~~<br>~~eee~~|ns<br>~~PFE~~<br>~~eee~~|
||–2<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br>~~a~~|4.84<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|0.90<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|4.09<br>~~ee~~<br>~~ee~~|4.84<br>~~ee~~<br>~~ee~~|1.98<br>~~ee~~<br>~~ee~~|1.94<br>~~ee~~<br>~~ee~~|5.76<br>~~eee~~<br>~~ee~~|6.51<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|6 mA<br>~~Pot~~|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee ~~<br>~~a~~<br>~~a~~|4.06<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.20<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.84<br> ~~ee~~<br>~~ee~~<br>~~ee~~|4.06<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.93<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.10<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6.07<br> ~~eee~~<br>~~ee~~<br>~~ee~~|6.30<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br> ~~a~~<br>~~a~~|3.45<br>~~ee ~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~|1.02<br>~~ee ~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~|3.27<br>~~ee ~~<br>~~ee~~|3.45<br> ~~ee ~~<br>~~ee~~|2.49<br> ~~ee~~<br>~~ee~~|2.64<br>~~ee~~<br>~~ee~~|5.17<br>~~ee ~~<br>~~ee~~|5.36<br> ~~eee~~<br>~~ee~~|ns<br>~~eee~~|
||–2<br>~~a ~~<br>~~PEE~~<br>~~Pot~~|0.49<br> ~~a~~<br>~~PEE~~<br>~~PotEE~~|3.03<br>~~ee~~<br>~~PEE~~<br>~~EE~~|0.03<br>~~ee ~~<br>~~PEE~~<br>~~EEEE~~|0.90<br> ~~ee~~<br>~~PEE~~<br>~~EE~~|0.32<br>~~ee ~~<br>~~PEE~~<br>~~EE~~|2.87<br> ~~ee ~~<br>~~PEE~~|3.03<br> ~~ee ~~<br>~~PEE~~|2.19<br> ~~ee~~<br>~~PEE~~|2.32<br>~~ee~~<br>~~PEE~~|4.54<br>~~ee ~~<br>~~PEE~~|4.70<br> ~~ee~~<br>~~PEE~~|ns<br>~~PEE~~|
|8 mA<br>~~Pot~~|Std.<br>~~Pot~~<br>~~Pt~~|0.66<br>~~PotEE~~<br>~~PtTE~~|4.06<br>~~EE~~<br>~~TE~~|0.04<br>~~EEEE~~<br>~~TEEt~~|1.20<br>~~EE~~<br>~~Et~~|0.43<br>~~EE~~<br>~~Et~~|3.84|4.06|2.93|3.10|6.07|6.30|ns|
||–1<br>~~Pot~~<br>~~Pt~~<br>~~Pt~~|0.56<br>~~Pot EE~~<br>~~PtTE~~<br>~~PtTE~~|3.45<br>~~EE~~<br>~~TE~~<br>~~TE~~|0.04<br>~~EE EE~~<br>~~TEEt~~<br>~~TErE~~|1.02<br>~~EE~~<br>~~Et~~<br>~~rE~~<br>~~TE~~|0.36<br>~~EE~~<br>~~Et~~<br>~~TErE~~|3.27<br>~~rE~~|3.45|2.49|2.64|5.17|5.36|ns|
||–2<br>~~Pt~~<br>~~Pt~~|0.49<br>~~Pt TE~~<br>~~PtTE~~|3.03<br>~~TE~~<br>~~TE~~|0.03<br>~~TE Et~~<br>~~TErE~~|0.90<br>~~Et~~<br>~~rE~~<br>~~TE~~|0.32<br>~~Et~~<br>~~TErE~~|2.87<br>~~rE~~|3.03|2.19|2.32|4.54|4.70|ns|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-57**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-73 •**_ **1.8 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~ee~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~eee~~|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~ee~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|14.80<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.20<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee ee~~|13.49<br>~~ee~~<br>~~ee~~|14.80<br>~~ee~~<br>~~ee~~|2.25<br>~~ee~~<br>~~ee~~|1.46<br>~~eee~~<br>~~ee~~|15.73<br>~~eee~~<br>~~ee~~|17.04<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–1<br>~~ee ~~<br>~~a~~<br>~~ee~~|0.56<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|12.59<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee ~~<br>~~ee ee~~<br>~~ee~~|11.48<br> ~~ee~~<br>~~ee~~<br>~~ee~~|12.59<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.91<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.25<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|13.38<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|14.49<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~ee~~|0.49<br>~~ee ~~<br>~~ee~~|11.05<br> ~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.90<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee ee~~<br>~~ee~~|10.08<br>~~ee~~<br>~~ee~~|11.05<br>~~ee~~<br>~~ee~~|1.68<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.09<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|11.75<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|12.72<br> ~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|4 mA|Std.<br>~~ee ~~<br>~~PTT~~<br>~~PT~~|0.66<br> ~~ee ~~<br>~~PTT~~<br>~~PTTT~~|9.90<br> ~~ee~~<br>~~PTT~~<br>~~TT~~|0.04<br>~~ee~~<br>~~PTT~~<br>~~TT~~|1.20<br>~~ee~~<br>~~PTT~~|0.43<br>~~ee~~<br>~~PTT~~|9.73<br>~~ee~~<br>~~PTT~~|9.90<br>~~ee~~<br>~~PTT~~|2.65<br>~~ee~~<br>~~ee ~~<br>~~PTT~~|2.50<br>~~ee~~<br> ~~ee ~~<br>~~PTT~~|11.97<br>~~ee~~<br> ~~eee~~<br>~~PTT~~|12.13<br>~~ee~~<br>~~eee~~<br>~~PTT~~|ns<br>~~ee~~<br>~~eee~~<br>~~PTT~~|
||–1<br>~~PT~~<br>~~P|~~|0.56<br>~~PTTT~~<br>~~P|EET~~|8.42<br>~~TT~~<br>~~EET~~|0.04<br>~~TT~~<br>~~EET~~|1.02<br>~~EET~~|0.36|8.28|8.42|2.26|2.12|10.18|10.32|ns|
||–2<br>~~PT~~<br>~~P|~~<br>~~ee~~|0.49<br>~~PT TT~~<br>~~P|EET~~<br>~~ee~~|7.39<br>~~TT~~<br>~~EET~~<br>~~ee~~|0.03<br>~~TT~~<br>~~EET~~<br>~~ee~~|0.90<br>~~EET~~<br>~~ee~~|0.32<br>~~ee~~|7.27<br>~~ee~~|7.39<br>~~ee~~|1.98<br>~~ee~~|1.86<br>~~eee~~|8.94<br>~~eee~~|9.06<br>~~eee~~|ns<br>~~eee~~|
|6 mA|Std.<br>~~P|~~<br>~~ee~~<br>~~a~~|0.66<br>~~P| EET~~<br>~~ee~~<br>~~ee~~|7.44<br>~~EET~~<br>~~ee~~<br>~~ee~~|0.04<br>~~EET~~<br>~~ee~~<br>~~ee~~|1.20<br>~~EET~~<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee ee~~|7.58<br>~~ee~~<br>~~ee~~|7.32<br>~~ee~~<br>~~ee~~|2.94<br>~~ee~~<br>~~ee~~|2.99<br>~~eee~~<br>~~ee~~|9.81<br>~~eee~~<br>~~ee~~|9.56<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–1<br>~~ee ~~<br>~~a~~<br>~~ee~~|0.56<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|6.33<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee ~~<br>~~ee ee~~<br>~~ee~~|6.44<br> ~~ee~~<br>~~ee~~<br>~~ee~~|6.23<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.50<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.54<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.35<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|8.13<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~ee~~|0.49<br>~~ee ~~<br>~~ee~~|5.55<br> ~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.90<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee ee~~<br>~~ee~~|5.66<br>~~ee~~<br>~~ee~~|5.47<br>~~ee~~<br>~~ee~~|2.19<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.23<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|7.33<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|7.14<br> ~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|8 mA|Std.<br>~~ee ~~<br>~~PTT~~|0.66<br> ~~ee ~~<br>~~PTT~~|7.44<br> ~~ee~~<br>~~PTT~~|0.04<br>~~ee~~<br>~~PTT~~|1.20<br>~~ee~~<br>~~PTT~~|0.43<br>~~ee~~<br>~~PTT~~|7.58<br>~~ee~~<br>~~PTT~~|7.32<br>~~ee~~<br>~~PTT~~|2.94<br>~~ee~~<br>~~ee ~~<br>~~PTT~~|2.99<br>~~ee~~<br> ~~ee ~~<br>~~PTT~~|9.81<br>~~ee~~<br> ~~eee~~<br>~~PTT~~|9.56<br>~~ee~~<br>~~eee~~<br>~~PTT~~|ns<br>~~ee~~<br>~~eee~~<br>~~PTT~~|
||–1<br>~~PTT~~<br>~~ee~~|0.56<br>~~PTT~~<br>~~ee~~|6.33<br>~~PTT~~<br>~~ee~~|0.04<br>~~PTT~~<br>~~ee~~|1.02<br>~~PTT~~<br>~~ee~~|0.36<br>~~PTT~~<br>~~ee~~|6.44<br>~~PTT~~<br>~~ee~~|6.23<br>~~PTT~~<br>~~ee~~|2.50<br>~~PTT~~|2.54<br>~~PTT~~<br>~~ee~~|8.35<br>~~PTT~~<br>~~eee~~|8.13<br>~~PTT~~<br>~~eee~~|ns<br>~~PTT~~<br>~~eee~~|
||–2<br>~~ee~~|0.49<br>~~ee~~|5.55<br>~~ee~~|0.03<br>~~ee~~|0.90<br>~~ee~~|0.32<br>~~ee~~|5.66<br>~~ee~~|5.47<br>~~ee~~|2.19|2.23<br>~~ee~~|7.33<br>~~eee~~|7.14<br>~~eee~~|ns<br>~~eee~~|
## _**Table 2-74 •**_ **1.8 V LVCMOS High Slew**
## **Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~ee~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~ee~~|0.66<br>~~ee~~|11.21<br>~~ee~~|0.04<br>~~ee~~|1.20<br>~~ee~~|0.43<br>~~ee~~<br>~~eee~~|8.53<br>~~ee~~<br>~~eee~~|11.21<br>~~ee~~<br>~~ee~~|1.99<br>~~ee~~<br>~~eee~~|1.21<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee ~~<br>~~ee~~<br>~~a~~|0.56<br> ~~ee ~~<br>~~ee~~<br>|9.54<br> ~~ee ~~<br>~~ee~~<br>|0.04<br> ~~ee~~<br>~~ee~~<br>|1.02<br>~~ee~~<br>~~ee~~<br>|0.36<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|7.26<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|9.54<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.69<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|1.03<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
||–2<br>~~ee~~<br>~~a~~<br>~~es~~|0.49<br>~~ee~~<br>~~ee~~<br>|8.37<br>~~ee~~<br>~~ee~~<br>|0.03<br>~~ee~~<br>~~ee~~<br>|0.90<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|6.37<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|8.37<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.49<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|0.90<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|
|4 mA|Std.<br>~~a~~ <br>~~es~~<br>~~ae~~|0.66<br> ~~ee~~<br>~~**ee**~~|6.34<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.20<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|5.38<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.34<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.41<br> ~~eee~~<br>~~ee~~<br>~~**e**e~~|2.48<br>~~eee ~~<br>~~ee~~<br>~~ee~~|ns<br> ~~eee~~<br>~~ee~~<br>~~e~~~~**e**e~~|
||–1<br> <br>~~es~~<br>~~ae~~|0.56<br> ~~ee~~<br>~~**ee**~~|5.40<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.58<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.40<br>~~ee~~<br>~~ee~~<br>~~e~~|2.05<br>~~ee~~<br>~~**e**e~~<br>~~e~~|2.11<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~e~~~~**e**e~~<br>~~e~~|
||–2<br> <br>~~es ~~<br>~~ae~~|0.49<br> ~~ee ~~<br> ~~**ee**~~|4.74<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.90<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.32<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.02<br> ~~ee~~<br>~~ee~~<br>~~ee~~|4.74<br>~~ee ~~<br>~~ee~~<br>~~e~~|1.80<br> ~~ee ~~<br>~~**e**e~~<br>~~e~~|1.85<br> ~~ee ~~<br>~~ee~~|ns<br> ~~ee~~<br>~~e~~~~**e**e~~<br>~~e~~|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-58**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-75 •**_ **1.8 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~eo~~|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~es~~|15.01<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.20<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|13.15<br>~~ee~~<br>~~es~~|15.01<br>~~es~~|1.99<br>~~ee~~<br>~~ee~~|1.99<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~ee ~~<br>~~es~~<br>~~ee~~|12.77<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.02<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~ee~~<br>~~ee~~|11.19<br>~~ee~~<br>~~es~~<br>~~ee~~|12.77<br>~~es~~<br>~~ee~~|1.70<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.70<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|ns<br> ~~ee~~<br>~~ee~~|
||–2<br>~~a~~<br>~~a~~<br>~~eo~~|0.49<br>~~es ~~<br>~~ee~~|11.21<br> ~~ee~~<br>~~ee~~|0.03<br>~~ee ~~<br>~~ee~~|0.90<br> ~~ee ~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~|9.82<br>~~es~~<br>~~ee~~|11.21<br>~~es ~~<br>~~ee~~|1.49<br> ~~ee ~~<br>~~ee~~|1.49<br> ~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|4 mA<br>~~eo~~|Std.<br>~~a~~<br>~~eo~~<br>~~a~~|0.66<br>~~ee ~~<br>~~a~~|10.10<br> ~~ee ~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~ee~~|1.20<br> ~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|9.55<br>~~ee ~~<br>~~ee~~|10.10<br> ~~ee ~~<br>~~ee~~|2.41<br> ~~ee~~<br>~~ee~~|2.37<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~eo~~<br>~~a~~<br>~~a~~|0.56<br>~~a~~<br>~~ee~~|8.59<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~|8.13<br>~~ee~~<br>~~ee~~|8.59<br>~~ee~~<br>~~ee~~|2.05<br>~~ee~~<br>~~ee~~|2.02<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a~~<br>~~ee~~|7.54<br>~~ee ~~<br>~~ee~~|0.03<br> ~~ee ~~<br>~~ee~~|0.90<br> ~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|7.13<br>~~ee ~~<br>~~ee~~|7.54<br> ~~ee ~~<br>~~ee~~|1.80<br> ~~ee~~<br>~~ee~~|1.77<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
## _**1.5 V LVCMOS (JESD8-11)**_
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
_**Table 2-76 •**_ **Minimum and Maximum DC Input and Output Levels**
## **Applicable to Advanced I/O Banks**
|**1.5 V**<br>**LVCMOS**<br>~~re~~<br>~~|~~|**VIL**<br>~~re~~<br>|**VIL**<br>~~re~~<br>|**VIH**<br>~~re~~<br>~~ee~~|**VIH**<br>~~re~~<br>~~ee~~|**VOL**<br>~~re~~<br>~~ee~~|**VOH**<br>~~re~~<br>~~eee~~|**IOL **<br>~~re~~<br>~~eee~~|**IOH **<br>~~re~~<br>~~eee~~|**IOSL**<br>~~re~~<br>~~eee~~|**IOSH **<br>~~re~~<br>~~eee~~|**IIL1 **<br>~~re~~<br>~~eee~~|**IIH2**<br>~~re~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~| ~~<br>~~a~~|**Min.**<br>**V**<br> ~~ft~~<br>~~ae~~|**Max.**<br>**V**<br>~~ft~~<br>~~es~~|**Min.**<br>**V**<br>~~ee~~<br>~~ee~~|**Max.,**<br>**V**<br>~~ee ~~<br>~~ed~~|**Max.**<br>**V**<br> ~~ee ~~<br>~~ss~~|**Min.**<br>**V**<br> ~~eee~~<br>~~ss~~|**mA **<br>~~eee~~<br>~~Os~~|**mA**<br>~~eee~~<br>~~Oe~~|**Max.**<br>**mA3**<br>~~eee~~<br>~~es~~|**Max.**<br>**mA3**<br>~~eee~~|**µA4 **<br>~~eee~~|**µA4**<br>~~eee~~|
|2 mA<br>~~a~~<br>~~a~~|–0.3<br>~~ae~~<br>~~ee~~|0.35 * VCCI 0.65 * VCCI 1.575<br>~~es~~<br>~~es~~|0.35 * VCCI 0.65 * VCCI 1.575<br>~~ee~~<br>~~es~~|0.35 * VCCI 0.65 * VCCI 1.575<br>~~ed~~<br>~~es~~|0.25 * VCCI 0.75 * VCCI 2<br>~~ss~~<br>~~Gs~~|0.25 * VCCI 0.75 * VCCI 2<br>~~ss~~<br>~~Gs~~|0.25 * VCCI 0.75 * VCCI 2<br>~~Os~~<br>~~Gs~~|2<br>~~Oe~~<br>~~Ge~~|16<br>~~es~~<br>~~Gs~~|13|10 10|10 10|
|4 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ae~~<br>~~ee~~<br>~~ae~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~es~~<br>~~es~~<br>~~es~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ee~~<br>~~es~~<br>~~ee~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ed ~~<br>~~es~~<br>~~ed~~|0.25 * VCCI 0.75 * VCCI 4<br> ~~ss~~<br>~~Gs~~<br>~~ss~~|0.25 * VCCI 0.75 * VCCI 4<br>~~ss ~~<br>~~Gs~~<br>~~ss~~|0.25 * VCCI 0.75 * VCCI 4<br> ~~Os ~~<br>~~Gs~~<br>~~Os~~|4<br> ~~Oe ~~<br>~~Ge~~<br>~~Oe~~|33<br> ~~es~~<br>~~Gs~~<br>~~es~~|25|10 10|10 10|
|6 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ee~~<br>~~ae~~<br>~~ae~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~es ~~<br>~~es~~<br>~~es~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br> ~~es~~<br>~~ee~~<br>~~es~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~es~~<br>~~ed~~<br>~~es er~~|0.25 * VCCI 0.75 * VCCI<br>~~Gs~~<br>~~ss~~<br>~~er~~|0.25 * VCCI 0.75 * VCCI<br>~~Gs~~<br>~~ss~~<br>~~ee~~|6<br>~~Gs ~~<br>~~Os~~<br>~~Qs~~|6<br> ~~Ge~~<br>~~Oe~~<br>~~Qe~~|39<br>~~Gs~~<br>~~es~~|32|10 10|10 10|
|8 mA<br>~~a~~<br>~~a~~<br>~~a~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ae~~<br>~~ae~~<br>~~a~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~es~~<br>~~es~~<br>~~es~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ee~~<br>~~es~~<br>~~es~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ed ~~<br>~~es er~~<br>~~es~~|0.25 * VCCI 0.75 * VCCI<br> ~~ss~~<br>~~er~~<br>~~fs~~|0.25 * VCCI 0.75 * VCCI<br>~~ss ~~<br>~~ee~~<br>~~fs~~|8<br> ~~Os ~~<br>~~Qs~~<br>~~fs~~|8<br> ~~Oe ~~<br>~~Qe~~<br>~~Gs~~|55<br> ~~es~~<br>~~es~~|66<br>~~Ge~~|10 10<br>~~Ge~~|10 10|
|12 mA<br>~~a ~~<br>~~a~~|–0.3<br> ~~ae~~<br>~~a~~|0.35 * VCCI<br>~~es ~~<br>~~es~~|0.65 * VCCI<br> ~~es ~~<br>~~es~~|1.575<br> ~~es er~~<br>~~es~~|0.25 * VCCI<br>~~er~~<br>~~fs~~|0.75 * VCCI<br>~~ee~~<br>~~fs~~|12<br>~~Qs ~~<br>~~fs~~|12<br> ~~Qe~~<br>~~Gs~~|55<br>~~es~~|66<br>~~Ge~~|10<br>~~Ge~~|10|
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**2-59**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-77 •**_ **Minimum and Maximum DC Input and Output Levels**
**Applicable to Standard Plus I/O Banks**
|**1.5 V**<br>**LVCMOS**<br>~~eee~~|**VIL**<br>~~eee~~|**VIL**<br>~~eee~~|**VIH**<br>~~eee~~|**VIH**<br>~~eee~~|**VOL**<br>~~eee~~|**VOH**<br>~~eee~~|**IOL **<br>~~eee~~|**IOH**<br>~~eee~~|**IOSL**<br>~~eee~~|**IOSH**<br>~~eee~~|**IIL1 **<br>~~eee~~|**IIH2**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**<br>~~eee~~<br>~~a~~|**Min.**<br>**V**<br>~~eee~~<br>~~ae a~~|**Max.**<br>**V**<br>~~eee~~<br>~~a~~|**Min.**<br>**V**<br>~~eee~~<br>~~ee~~|**Max.**<br>**V**<br>~~eee~~<br>~~es~~|**Max.**<br>**V**<br>~~eee~~<br>~~ee~~|**Min.**<br>**V**<br>~~eee~~<br>~~es~~|**mA **<br>~~eee~~<br>~~Oe~~|**mA**<br>~~eee~~<br>~~re~~|**Max.**<br>**mA3**<br>~~eee~~<br>~~ee~~|**Max.**<br>**mA3**<br>~~eee~~|**µA4 **<br>~~eee~~|**µA4**<br>~~eee~~|
|2 mA<br>~~a~~<br>~~a~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ae a~~<br>~~a~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~a~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575<br>~~ee~~<br>~~es~~|–0.3 0.35 * VCCI 0.65 * VCCI 1.575 <br>~~es~~<br>~~es~~|0.25 * VCCI 0.75 * VCCI 2<br>~~ee~~<br>~~ee~~|0.25 * VCCI 0.75 * VCCI 2<br>~~es~~<br>~~rs~~|0.25 * VCCI 0.75 * VCCI 2<br>~~Oe~~<br>~~Gd dG~~|2<br>~~re~~<br>~~dG~~|16<br>~~ee~~<br>~~dG~~|13<br>~~dG~~|10 10<br>~~dG~~|10 10|
|4 mA<br>~~a~~<br>~~a~~|–0.3<br>~~ae a~~<br>~~a~~|0.35 * VCCI<br>~~a~~|0.35 * VCCI<br>0.65 * VCCI<br>~~ee~~<br>~~es~~|1.575<br>~~es~~<br>~~es~~|0.25 * VCCI<br>~~ee ~~<br>~~ee~~|0.75 * VCCI<br> ~~es ~~<br>~~rs~~|4<br> ~~Oe ~~<br>~~Gd dG~~|4<br> ~~re~~<br>~~dG~~|33<br>~~ee~~<br>~~dG~~|25<br>~~dG~~|10<br>~~dG~~|10|
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges_
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
_**Table 2-78 •**_ **Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks**
|**1.5 V**<br>**LVCMOS**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH **|**IOSL **|**IOSH **|**IIL1 **|**IIH2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive**<br>**Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**mA **|**mA**|**Max.**<br>**mA3**|**Max.**<br>**mA3**|**µA4 **|**µA4**|
|2 mA|–0.3|0.35 * VCCI|0.35 * VCCI<br>0.65 * VCCI|3.6|0.25 * VCCI|0.75 * VCCI|2|2|13|16|10|10|
_Notes:_
_1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL._
_2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges._
_3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_4. Currents are measured at 85°C junction temperature._
_5. Software default selection highlighted in gray._
**==> picture [323 x 68] intentionally omitted <==**
**----- Start of picture text -----**<br>
R = 1 kΩ R to VCCI for tLZ / tZL / tZLS<br>Test Point R to GND for tHZ / tZH / tZHS<br>Test Point<br>1 j<br>Datapath 35 pF Enable Path<br>35 pF for tZH / tZHS / tZL / tZLS<br>} y 35 pF for tHZ / tLZ<br>**----- End of picture text -----**<br>
_**Figure 2-10 •**_ **AC Loading**
_**Table 2-79 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**CLOAD (pF)**|
|---|---|---|---|
|0|1.5|0.75|35|
_Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points._
**Revision 18**
**2-60**
_ProASIC3 DC and Switching Characteristics_
## **Timing Characteristics**
_**Table 2-80 •**_ **1.5 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~ae~~|**tDOUT**<br>~~a~~|**tDP**<br>~~a~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~ae~~<br>~~ae~~|0.66<br>~~a~~<br>~~a~~|8.36<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.44<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|6.82<br>~~ee~~|8.36<br>~~ee~~<br>~~ee~~|3.39<br>~~ee~~<br>~~ee~~|2.77<br>~~ee~~<br>~~ee~~|9.06<br>~~ee~~<br>~~ee~~|10.60<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~ae ~~<br>~~ae~~<br>~~a~~|0.56<br> ~~a ~~<br>~~a~~<br>~~ee~~|7.11<br> ~~a ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|5.80<br>~~ee~~<br>~~ee~~|7.11<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.88<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.35<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7.71<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|9.02<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|ns<br> ~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~ae ~~<br>~~a~~<br>~~ee~~|0.49<br> ~~a~~<br>~~ee~~<br>~~ee~~|6.24<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.07<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~<br>~~ee~~|5.10<br>~~ee~~<br>~~ee~~<br>~~eee~~|6.24<br>~~ee ~~<br>~~ee~~<br>~~eee~~|2.53<br> ~~ee~~<br>~~ee~~<br>~~eee~~|2.06<br>~~ee ~~<br>~~ee~~<br>~~eee~~|6.76<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|7.91<br> ~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|4 mA|Std.<br>~~a~~<br>~~ee~~|0.66<br>~~ee ~~<br>~~ee~~|5.31<br> ~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee~~|1.44<br> ~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~|4.85<br> ~~ee~~<br>~~eee~~|5.31<br>~~ee ~~<br>~~eee~~|3.74<br> ~~ee~~<br>~~eee~~|3.40<br>~~ee ~~<br>~~eee~~|7.09<br> ~~ee ~~<br>~~eee~~|7.55<br> ~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~Pott~~<br>~~Pt~~|0.56<br>~~ee~~<br>~~Pott~~<br>~~PtTT~~|4.52<br>~~ee~~<br>~~Pott~~<br>~~TT~~|0.04<br>~~ee~~<br>~~Pott~~<br>~~TT~~|1.22<br>~~ee~~<br>~~Pott~~|0.36<br>~~ee ~~<br>~~Pott~~|4.13<br> ~~eee~~<br>~~Pott~~|4.52<br>~~eee ~~<br>~~Pott~~|3.18<br> ~~eee~~<br>~~Pott~~|2.89<br>~~eee ~~<br>~~Pott~~|6.03<br> ~~eee~~<br>~~Pott~~|6.42<br>~~eee~~<br>~~Pott~~|ns<br>~~eee~~<br>~~Pott~~|
||–2<br>~~Pt~~<br>~~ae~~|0.49<br>~~PtTT~~<br>~~a~~|3.97<br>~~TT~~<br>~~a~~|0.03<br>~~TT~~<br>~~ee~~|1.07<br>~~ee~~|0.32<br>~~ee~~|3.62|3.97<br>~~ee~~|2.79<br>~~ee~~|2.54<br>~~ee~~|5.29<br>~~ee~~|5.64<br>~~ee~~|ns<br>~~ee~~|
|6 mA|Std.<br>~~Pt~~<br>~~ae~~<br>~~ae~~|0.66<br>~~Pt TT~~<br>~~a~~<br>~~a~~|4.67<br>~~TT~~<br>~~a~~<br>~~ee~~|0.04<br>~~TT~~<br>~~ee~~<br>~~ee~~|1.44<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|4.55<br>~~ee~~|4.67<br>~~ee~~<br>~~ee~~|3.82<br>~~ee~~<br>~~ee~~|3.56<br>~~ee~~<br>~~ee~~|6.78<br>~~ee~~<br>~~ee~~|6.90<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~ae ~~<br>~~ae~~<br>~~a~~|0.56<br> ~~a ~~<br>~~a~~<br>~~ee~~|3.97<br> ~~a ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.87<br>~~ee~~<br>~~ee~~|3.97<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.25<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.03<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5.77<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|5.87<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|ns<br> ~~ee~~<br>~~ee~~<br>~~eee~~|
||–2<br>~~ae ~~<br>~~a~~<br>~~ee~~|0.49<br> ~~a~~<br>~~ee~~<br>~~ee~~|3.49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.07<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.32<br> ~~ee~~<br>~~ee~~<br>~~ee~~|3.40<br>~~ee~~<br>~~ee~~<br>~~eee~~|3.49<br>~~ee ~~<br>~~ee~~<br>~~eee~~|2.85<br> ~~ee~~<br>~~ee~~<br>~~eee~~|2.66<br>~~ee ~~<br>~~ee~~<br>~~eee~~|5.07<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|5.16<br> ~~ee~~<br>~~eee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|8 mA|Std.<br>~~a~~<br>~~ee~~|0.66<br>~~ee ~~<br>~~ee~~|4.08<br> ~~ee~~<br>~~ee~~|0.04<br>~~ee ~~<br>~~ee~~|1.44<br> ~~ee~~<br>~~ee~~|0.43<br>~~ee ~~<br>~~ee~~|4.15<br> ~~ee~~<br>~~eee~~|3.58<br>~~ee ~~<br>~~eee~~|3.94<br> ~~ee~~<br>~~eee~~|4.20<br>~~ee ~~<br>~~eee~~|6.39<br> ~~ee ~~<br>~~eee~~|5.81<br> ~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
||–1<br>~~ee~~<br>~~Pott~~|0.56<br>~~ee~~<br>~~Pott~~|3.47<br>~~ee~~<br>~~Pott~~|0.04<br>~~ee~~<br>~~Pott~~|1.22<br>~~ee~~<br>~~Pott~~|0.36<br>~~ee ~~<br>~~Pott~~|3.53<br> ~~eee~~<br>~~Pott~~|3.04<br>~~eee ~~<br>~~Pott~~|3.36<br> ~~eee~~<br>~~Pott~~|3.58<br>~~eee ~~<br>~~Pott~~|5.44<br> ~~eee~~<br>~~Pott~~|4.95<br>~~eee~~<br>~~Pott~~|ns<br>~~eee~~<br>~~Pott~~|
||–2<br>~~ee~~<br>~~ee~~|0.49<br>~~ee~~<br>~~ee~~|3.05<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~|1.07<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|3.10<br>~~ee~~|2.67<br>~~ee~~|2.95<br>~~eee~~<br>~~ee~~|3.14<br>~~eee~~<br>~~ee~~|4.77<br>~~eee~~<br>~~eee~~|4.34<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|12 mA<br>~~Pot~~|Std.<br>~~ee~~<br>~~Pot~~|0.66<br>~~ee~~<br>~~PotTE~~|4.08<br>~~ee~~<br>~~TE~~|0.04<br>~~ee~~<br>~~TE~~|1.44<br>~~ee~~<br>~~TE~~|0.43<br>~~ee~~|4.15<br>~~ee~~|3.58<br>~~ee~~|3.94<br>~~ee~~|4.20<br>~~ee~~|6.39<br>~~eee~~|5.81<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~ee ~~<br>~~Pot~~<br>~~Pt~~|0.56<br> ~~ee ~~<br>~~PotTE~~<br>~~Pt~~<br>~~|~~|3.47<br> ~~ee~~<br>~~TE~~<br>~~EE~~|0.04<br>~~ee ~~<br>~~TE~~<br>~~EE~~|1.22<br> ~~ee~~<br>~~TE~~<br>~~EE~~|0.36<br>~~ee ~~|3.53<br> ~~ee ~~|3.04<br> ~~ee ~~|3.36<br> ~~ee~~|3.58<br>~~ee ~~|5.44<br> ~~eee~~|4.95<br>~~eee~~|ns<br>~~eee~~|
||–2<br>~~Pot~~<br>~~Pt~~|0.49<br>~~Pot TE~~<br>~~Pt~~<br>~~|~~|3.05<br>~~TE~~<br>~~EE~~|0.03<br>~~TE~~<br>~~EE~~|1.07<br>~~TE~~<br>~~EE~~|0.32|3.10|2.67|2.95|3.14|4.77|4.34|ns|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-61**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-81 •**_ **1.5 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~<br>~~a~~|**tDOUT**<br>~~ee~~<br>|**tDP**<br>~~ee~~<br>|**tDIN**<br>~~ee~~<br>|**tPY**<br>~~ee~~<br>|**tEOUT**<br>~~ee~~<br>|**tZL**<br>~~ee~~<br>|**tZH**<br>~~ee~~<br>~~ee~~<br>|**tLZ**<br>~~ee~~<br>~~ee~~<br>|**tHZ**<br>~~ee~~<br>~~ee~~<br>|**tZLS**<br>~~ee~~<br>~~ee~~<br>|**tZHS**<br>~~ee~~<br>~~ee~~<br>|**Units**<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~a~~|12.78<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.44<br>~~ee~~<br>~~ee ee~~|0.43<br>~~ee~~<br>~~ee ee~~|12.81<br>~~ee~~<br>~~ee~~|12.78<br>~~ee~~<br>~~ee~~<br>~~es~~|3.40<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.64<br>~~ee~~<br>~~ee~~<br>~~es~~|15.05<br>~~ee~~<br>~~ee~~<br>~~ee~~|15.02<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br>~~a~~<br>~~a ~~<br>~~a~~|0.56<br>~~ee ~~<br> ~~a~~<br>~~ee~~|10.87<br> ~~ee~~<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|10.90<br>~~ee~~<br>~~ee~~<br>~~ee~~|10.87<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~|2.89<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.25<br>~~ee~~<br> ~~ee ~~<br>~~es~~<br>~~ee~~|12.80<br>~~ee~~<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|12.78<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br> <br>~~a~~<br>~~ee~~|0.49<br> ~~a ~~<br>~~ee~~<br>~~ee~~|9.55<br> ~~ee~~<br>~~a~~<br>|0.03<br>~~ee~~<br>~~ee~~<br>|1.07<br>~~ee ee~~<br>~~ee~~<br>|0.32<br>~~ee ee~~<br>~~ee~~<br>|9.57<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>|9.55<br> ~~es ~~<br>~~ee~~<br>~~eee eee~~<br>|2.54<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br>|1.97<br> ~~es ~~<br>~~ee~~<br>~~eee~~<br>|11.24<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>|11.22<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>|
|4 mA|Std.<br>~~ee~~<br>~~ee~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|10.01<br> ~~a~~<br>~~ee~~<br><br>|0.04<br>~~ee~~<br>~~ee~~<br><br>|1.44<br>~~ee~~<br>~~ee~~<br><br>|0.43<br>~~ee ~~<br>~~ee~~<br><br>|10.19<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~ee~~<br>|9.55<br>~~ee ~~<br>~~ee~~<br>~~eee eee~~<br><br>~~ee~~<br>|3.75<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|3.27<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|12.43<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|11.78<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~|8.51<br>~~eee~~<br>~~ee~~|0.04<br>~~eee~~<br>~~ee~~|1.22<br>~~eee~~<br>~~ee~~|0.36<br>~~eee~~<br>~~ee~~|8.67<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|8.12<br>~~eee eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|3.19<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~ee~~|2.78<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~ee~~|10.57<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~ee~~|10.02<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~<br>~~ee~~|
||–2<br>~~ee~~<br>~~a ~~<br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>|7.47<br><br>~~ee~~<br>~~ee~~<br>|0.03<br><br>~~ee~~<br>~~ee~~<br>|1.07<br><br>~~ee~~<br>~~ee~~<br>|0.32<br><br>~~ee~~<br>~~ee~~<br>|7.61<br>~~eee~~<br><br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|7.13<br>~~eee eee~~<br><br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.80<br>~~eee~~<br><br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.44<br>~~eee~~<br><br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|9.28<br>~~eee~~<br><br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|8.80<br>~~eee~~<br><br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~eee~~<br><br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|6 mA|Std.<br> <br>~~a~~<br>~~a~~<br>~~a~~|0.66<br> ~~ee~~<br>~~ee~~<br>~~a~~|9.33<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.44<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~|0.43<br> ~~ee~~<br>~~ee~~<br>~~ee ee~~|9.51<br>~~ee~~<br>~~ee~~<br>~~ee~~|8.89<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|3.83<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.43<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~es~~|11.74<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|11.13<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~|0.56<br>~~ee ~~<br> ~~a~~<br>~~ee~~|7.94<br> ~~ee~~<br>~~ee~~<br>~~a~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.22<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|0.36<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|8.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.56<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~|3.26<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.92<br>~~ee~~<br> ~~ee ~~<br>~~es~~<br>~~ee~~|9.99<br>~~ee~~<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|9.47<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||–2<br> <br>~~a~~<br>~~ee~~|0.49<br> ~~a ~~<br>~~ee~~<br>~~ee~~|6.97<br> ~~ee~~<br>~~a~~|0.03<br>~~ee~~<br>~~ee~~|1.07<br>~~ee ee~~<br>~~ee~~|0.32<br>~~ee ee~~<br>~~ee~~|7.10<br>~~ee ~~<br>~~ee~~<br>~~eee~~|6.64<br> ~~es ~~<br>~~ee~~<br>~~eee eee~~|2.86<br> ~~ee ~~<br>~~ee~~<br>~~eee~~|2.56<br> ~~es ~~<br>~~ee~~<br>~~eee~~|8.77<br> ~~ee~~<br>~~ee~~<br>~~eee~~|8.31<br>~~ee~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|8 mA|Std.<br>~~ee~~<br>~~ee~~<br>~~a~~|0.66<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|8.91<br> ~~a~~<br>~~ee~~<br>|0.04<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|1.44<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|0.43<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>|9.07<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|8.89<br>~~ee ~~<br>~~ee~~<br>~~eee eee~~<br>~~ee~~<br>|3.95<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|4.05<br> ~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|11.31<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|11.13<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>|
||–1<br>~~ee~~<br>~~a~~<br>~~a~~|0.56<br>~~ee~~<br>~~ee~~<br>|7.58<br>~~ee~~<br>|0.04<br>~~eee~~<br>~~ee~~<br>|1.22<br>~~eee~~<br>~~ee~~<br>|0.36<br>~~eee~~<br>~~ee~~<br>|7.72<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|7.57<br>~~eee eee~~<br>~~ee~~<br>~~ee~~<br>|3.36<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|3.44<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|9.62<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|9.47<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>|
||–2<br>~~ee~~<br>~~a~~ <br>~~a~~<br>~~a~~|0.49<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>|6.65<br>~~ee~~<br>~~ee~~<br>|0.03<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|1.07<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|0.32<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>|6.78<br>~~eee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|6.64<br>~~eee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.95<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|3.02<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|8.45<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|8.31<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|12 mA|Std.<br> <br>~~a~~ <br>~~a~~<br>~~a~~|0.66<br> ~~ee ~~<br> ~~ee~~<br>~~**a**~~|8.91<br> ~~ee ~~<br>~~ee~~<br>~~e~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~|1.44<br>~~ee ~~<br>~~ee~~<br>~~**e** ee~~|0.43<br> ~~ee~~<br>~~ee~~<br>~~ee ee~~|9.07<br>~~ee ~~<br>~~ee~~<br>~~ee~~|8.89<br> ~~ee~~<br>~~ee~~<br>~~es~~|3.95<br>~~ee ~~<br>~~ee~~<br>~~ee~~|4.05<br> ~~ee ~~<br>~~ee~~<br>~~es~~|11.31<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|11.13<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–1<br> <br>~~a ~~<br>~~a~~|0.56<br> ~~ee ~~<br> ~~**a**~~|7.58<br> ~~ee ~~<br>~~e~~|0.04<br> ~~ee~~<br>~~e~~~~**e**~~|1.22<br>~~ee ~~<br>~~**e** ee~~|0.36<br> ~~ee~~<br>~~ee ee~~|7.72<br>~~ee ~~<br>~~ee~~|7.57<br> ~~ee~~<br>~~es~~|3.36<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3.44<br> ~~ee ~~<br>~~es~~<br>~~ee~~|9.62<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|9.47<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–2<br> <br>~~a~~|0.49<br> ~~**a** ~~|6.65<br> ~~e~~<br>~~a~~|0.03<br>~~e~~~~**e**~~|1.07<br>~~**e** ee~~|0.32<br>~~ee ee~~|6.78<br>~~ee ~~|6.64<br> ~~es ~~|2.95<br> ~~ee ~~<br>~~e~~<br>~~ee~~|3.02<br> ~~es ~~<br>~~e~~<br>~~ee~~|8.45<br> ~~ee~~<br>~~e~~<br>~~ee~~|8.31<br>~~ee~~<br>~~e~~<br>~~ee~~|ns<br>~~e~~<br>~~ee~~|
_**Table 2-82 •**_ **1.5 V LVCMOS High Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**<br>~~ae~~|**Speed**<br>**Grade**<br>~~ae~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**|**tZLS**<br>~~eee~~|**tZHS**<br>~~eee~~|**Units**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~ae~~<br>~~a~~<br>~~Pt~~<br>~~PT~~|Std.<br>~~ae~~<br>~~a~~|0.66<br>~~ee~~<br>~~ee~~|7.83<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.42<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|6.42<br>~~ee~~<br>~~ee~~|7.83<br>~~ee~~<br>~~ee~~|2.71<br>~~ee~~<br>~~ee~~|2.55|8.65<br>~~eee~~<br>~~ee~~|10.07<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||–1<br>~~ae ~~<br>~~a~~<br>~~Pt~~|0.56<br> ~~ee ~~<br>~~ee~~<br>~~Pt~~|6.66<br> ~~ee ~~<br>~~ee~~<br>|0.04<br> ~~ee~~<br>~~ee~~<br>|1.21<br>~~ee ~~<br>~~ee~~<br>|0.36<br> ~~ee~~<br>~~ee~~<br>|5.46<br>~~ee~~<br>~~ee~~<br>|6.66<br>~~ee~~<br>~~ee~~<br>|2.31<br>~~ee~~<br>~~ee~~<br>|2.17<br>|7.36<br>~~eee~~<br>~~ee~~<br>|8.56<br>~~eee~~<br>~~ee~~<br>|ns<br>~~eee~~<br>~~ee~~<br>|
||–2<br>~~a~~<br>~~Pt~~<br>~~PT~~|0.49<br>~~ee ~~<br>~~PtTT~~<br>~~PTUE~~|5.85<br> ~~ee~~<br>~~TT~~<br>~~UE~~|0.03<br>~~ee ~~<br>~~TT~~|1.06<br> ~~ee~~<br>~~TT~~|0.32<br>~~ee ~~<br>~~TT~~|4.79<br> ~~ee~~<br>~~TT~~|5.85<br>~~ee~~<br>~~TT~~|2.02<br>~~ee~~<br>~~TT~~|1.90<br>~~TT~~|6.46<br>~~ee~~<br>~~TT~~|7.52<br>~~ee ~~<br>~~TT~~|ns<br> ~~ee~~<br>~~TT~~|
|4 mA<br>~~Pt~~<br>~~PT~~<br>~~eee~~<br>~~eee~~|Std.<br>~~Pt~~<br>~~PT~~|0.66<br>~~Pt~~<br>~~PTUE~~|4.84<br><br>~~UE~~|0.04<br>|1.42<br>|0.43<br>|4.49<br>|4.84<br>|3.03<br>|3.13<br>|6.72<br>|7.08<br><br>~~eee~~|ns<br><br>~~eee~~|
||–1<br>~~PT~~<br>~~eee~~|0.56<br>~~PT UE~~<br>~~eee~~|4.12<br>~~UE~~<br>~~eee~~|0.04<br>~~eee~~|1.21<br>~~eee~~|0.36<br>~~eee~~|3.82<br>~~eee~~|4.12<br>~~eee~~|2.58<br>~~eee~~|2.66<br>~~eee~~|5.72<br>~~eee~~|6.02<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
||–2<br>~~eee~~|0.49<br>~~eee~~|3.61<br>~~eee~~|0.03<br>~~eee~~|1.06<br>~~eee~~|0.32<br>~~eee~~|3.35<br>~~eee~~|3.61<br>~~eee~~|2.26<br>~~eee~~|2.34<br>~~eee~~|5.02<br>~~eee~~|5.28<br>~~eee~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~<br>~~eee~~|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-62**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-83 •**_ **1.5 V LVCMOS Low Slew**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks**
|**Drive**<br>**Strength**<br>~~a~~|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~ee~~|**tDP**<br>~~ee~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~ee~~|**tZH**<br>~~ee~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**tZLS**|**tZHS**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~Po~~|Std.<br>~~a~~<br>~~a~~|0.66<br>~~ee~~<br>~~ie~~|12.08<br>~~ee~~<br>~~ie~~|0.04<br>~~ee~~<br>~~ee~~|1.42<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~es~~|12.01<br>~~ee~~<br>~~ee~~|12.08<br>~~ee~~<br>~~se~~|2.72<br>~~ee~~<br>~~se~~|2.43<br>~~ee~~<br>~~se~~|14.24 <br>~~ee~~|14.31<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a~~<br>~~a~~<br>~~ee~~|0.56<br>~~ee ~~<br>~~ie~~<br>~~ee~~|10.27<br> ~~ee ~~<br>~~ie~~<br>~~ee~~|0.04<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.21<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee~~<br>~~es~~<br>~~ee~~|10.21<br>~~ee ~~<br>~~ee~~<br>~~ee~~|10.27<br> ~~ee~~<br>~~se~~<br>~~ee~~|2.31<br>~~ee ~~<br>~~se~~<br>~~ee~~|2.06<br> ~~ee~~<br>~~se~~<br>~~ee~~|12.12 <br>~~ee~~<br>~~eee~~|12.18<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
||–2<br>~~a~~<br>~~ee~~<br>~~Po~~|0.49<br>~~ie~~<br>~~ee~~<br>~~Po~~|9.02<br>~~ie ~~<br>~~ee~~<br>~~Po~~|0.03<br> ~~ee ~~<br>~~ee~~|1.06<br> ~~ee ~~<br>~~ee~~|0.32<br> ~~es ~~<br>~~ee~~|8.97<br> ~~ee~~<br>~~ee~~|9.02<br>~~se~~<br>~~ee~~|2.03<br>~~se~~<br>~~ee~~|1.81<br>~~se ~~<br>~~ee~~|10.64 <br> ~~ee~~<br>~~eee~~|10.69<br>~~eee~~|ns<br>~~eee~~|
|4 mA<br>~~ee~~<br>~~Po~~<br>~~PTET~~<br>~~a~~|Std.<br>~~ee ~~<br>~~Po~~|0.66<br> ~~ee~~<br>~~Po~~|9.28<br>~~ee ~~<br>~~Po~~|0.04<br> ~~ee~~|1.42<br>~~ee~~|0.43<br>~~ee ~~|9.45<br> ~~ee~~|8.91<br>~~ee~~|3.04<br>~~ee ~~|3.00<br> ~~ee ~~|11.69<br> ~~eee~~|11.15<br>~~eee~~|ns<br>~~eee~~|
||–1<br>~~Po~~<br>~~PTET~~<br>~~a~~|0.56<br>~~Po~~<br>~~PTET~~<br>~~ee~~|7.89<br>~~Po~~<br>~~PTET~~<br>~~ee~~|0.04<br>~~PTET~~<br>~~ee~~|1.21<br>~~PTET~~<br>~~ee~~|0.36<br>~~PTET~~<br>~~ee~~|8.04<br>~~PTET~~<br>~~ee~~|7.58<br>~~PTET~~<br>~~ee~~|2.58<br>~~PTET~~<br>~~ee~~|2.55<br>~~PTET~~<br>~~ee~~|9.94<br>~~PTET~~<br>~~eee~~|9.49<br>~~PTET~~<br>~~eee~~|ns<br>~~PTET~~<br>~~eee~~|
||–2<br>~~a~~|0.49<br>~~ee~~|6.93<br>~~ee~~|0.03<br>~~ee~~|1.06<br>~~ee~~|0.32<br>~~ee~~|7.06<br>~~ee~~|6.66<br>~~ee~~|2.27<br>~~ee~~|2.24<br>~~ee~~|8.73<br>~~eee~~|8.33<br>~~eee~~|ns<br>~~eee~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_**Table 2-84 •**_ **1.5 V LVCMOS High Slew**
## **Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**tEOUT**|**tZL**|**tZH**|**tLZ**|**tHZ**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~PT~~|0.66<br>~~PT~~|7.65<br>~~PT~~|0.04<br>~~PT~~|1.42<br>~~PT~~|0.43<br>~~PT~~|6.31<br>~~PT~~|7.65<br>~~PT~~|2.45<br>~~PT~~|2.45<br>~~PT~~|ns<br>~~PT~~|
||–1<br>~~PT~~|0.56<br>~~PT~~|6.50<br>~~PT~~|0.04<br>~~PT~~|1.21<br>~~PT~~<br>~~ee~~|0.36<br>~~PT~~<br>~~ee~~|5.37<br>~~PT~~<br>~~eee~~|6.50<br>~~PT~~<br>~~eee~~|2.08<br>~~PT~~<br>~~eee~~|2.08<br>~~PT~~<br>~~eee~~|ns<br>~~PT~~<br>~~eee~~|
||–2<br>~~ee~~|0.49<br>~~ee~~|5.71<br>~~ee~~|0.03<br>~~ee~~|1.06<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|4.71<br>~~ee~~<br>~~eee~~|5.71<br>~~ee~~<br>~~eee~~|1.83<br>~~ee~~<br>~~eee~~|1.83<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
_Notes:_
_1. Software default selection highlighted in gray._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
## _**Table 2-85 •**_ **1.5 V LVCMOS Low Slew**
## **Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks**
|**Drive**<br>**Strength**|**Speed**<br>**Grade**<br>~~a~~|**tDOUT**<br>~~a~~|**tDP**<br>~~a~~|**tDIN**<br>~~ee~~|**tPY**<br>~~ee~~|**tEOUT**<br>~~ee~~|**tZL**<br>~~es~~|**tZH**<br>~~es~~|**tLZ**<br>~~ee~~|**tHZ**<br>~~ee~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2 mA|Std.<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~|12.33<br>~~a~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~|1.42<br>~~ee~~<br>~~ee~~|0.43<br>~~ee~~<br>~~ee~~|11.79<br>~~es~~<br>~~ee~~|12.33<br>~~es~~<br>~~ee~~|2.45<br>~~ee~~<br>~~ee~~|2.32<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
||–1<br>~~a ~~<br>~~a~~<br>~~a~~|0.56<br> ~~a ~~<br>~~a~~<br>~~ee~~|10.49<br> ~~a~~<br>~~ee~~<br>~~ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.21<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.36<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|10.03<br> ~~es ~~<br>~~ee~~<br>~~ee~~|10.49<br> ~~es ~~<br>~~ee~~<br>~~ee~~|2.08<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.98<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
||–2<br>~~a ~~<br>~~a~~|0.49<br> ~~a~~<br>~~ee~~|9.21<br>~~ee ~~<br>~~ee~~|0.03<br> ~~ee~~<br>~~ee~~|1.06<br>~~ee~~<br>~~ee~~|0.32<br>~~ee~~<br>~~ee~~|8.81<br>~~ee~~<br>~~ee~~|9.21<br>~~ee~~<br>~~ee~~|1.83<br>~~ee~~<br>~~ee~~|1.73<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**2-63**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## _**3.3 V PCI, 3.3 V PCI-X**_
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.
_**Table 2-86 •**_ **Minimum and Maximum DC Input and Output Levels**
|**3.3 V PCI/PCI-X**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL **|**IOH**|**IOSL**|**IOSH**|**IIL**|**IIH**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Drive Strength**|**Min.**<br>**V**|**Max.**<br>**V**|**Min.**<br>**V**|**Max.**<br>**V**|**Max,.**<br>**V**|**Min.**<br>**V**|**mA **|**mA**|**Max.**<br>**mA1**|**Max.**<br>**mA1**|**µA2 **|**µA2**|
|Per PCI specification|Per PCI curves||||||||||10|10|
_Notes:_
_1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage._
_2. Currents are measured at 85°C junction temperature._
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable path characterization are described in Figure 2-11.
**==> picture [400 x 61] intentionally omitted <==**
**----- Start of picture text -----**<br>
R = 25Ω R to VCCI for tDP (F) R = 1 kΩ R to VCCI for tLZ / tZL / tZLS<br>Test Point R to GND for tDP (R) Test Point R to GND for tHZ / tZH / tZHS<br>Datapath Enable Path 10 pF for tZH / tZHS / tZL / tZLS<br>7 1 5 pF for tHZ / tLZ<br>**----- End of picture text -----**<br>
_**Figure 2-11 •**_ **AC Loading**
AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is described in Table 2-87.
_**Table 2-87 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|**CLOAD (pF)**|
|---|---|---|---|
|0|3.3|0.285 * VCCI for tDP(R)<br>0.615 * VCCI for tDP(F)|10|
_Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points._
**Revision 18**
**2-64**
_ProASIC3 DC and Switching Characteristics_
## **Timing Characteristics**
_**Table 2-88 •**_ **3.3 V PCI/PCI-X**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks**
|~~a~~|~~a~~|~~ae~~|~~ee~~|~~ee~~|~~ee~~|~~es~~|~~ee~~|~~es~~|~~es~~|~~ee~~|~~es~~||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Speed Grade**<br>~~a~~<br>~~a~~|**tDOUT**<br>~~a~~<br>~~es~~|**tDP**<br>~~ae~~<br>~~es ee~~|**tDIN**<br>~~ee~~<br>~~ee~~|**tPY**<br>~~ee~~<br>~~es es~~|**tEOUT**<br>~~ee~~<br>~~es~~|**tZL**<br>~~es~~<br>~~ed~~|**tZH**<br>~~ee~~<br>~~rs~~|**tLZ**<br>~~es~~|**tHZ**<br>~~es~~|**tZLS**<br>~~ee~~|**tZHS**<br>~~es~~|**Units**|
|Std.<br>~~a~~<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~es~~<br>~~a~~|2.68<br>~~ae ~~<br>~~es ee~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.86<br> ~~ee ~~<br>~~es es~~<br>~~ee~~|0.43<br> ~~ee~~<br>~~es~~<br>~~ee~~|2.73<br>~~es ~~<br>~~ed~~<br>~~es~~|1.95<br> ~~ee~~<br>~~rs~~<br>~~ee~~|3.21<br>~~es ~~<br>~~es~~|3.58<br> ~~es ~~<br>~~es~~|4.97<br> ~~ee ~~<br>~~ee~~|4.19<br> ~~es~~<br>~~es~~|ns|
|–1<br>~~a~~<br>~~a~~<br>~~a~~|0.56<br>~~es~~<br>~~a~~<br>~~ee~~|2.28<br>~~es ee~~<br>~~ee~~<br>~~es ee~~|0.04<br>~~ee~~<br>~~ee~~<br>~~ee Gs~~|0.73<br>~~es es~~<br>~~ee~~<br>~~Gs~~|0.36<br>~~es~~<br>~~ee~~<br>~~es~~|2.32<br>~~ed~~<br>~~es~~<br>~~ss~~|1.66<br>~~rs~~<br>~~ee~~<br>~~ss~~|2.73<br>~~es~~<br>~~rs~~|3.05<br>~~es~~<br>~~rs~~|4.22<br>~~ee~~|3.56<br>~~es~~|ns|
|–2<br>~~a~~<br>~~a~~|0.49<br>~~a~~<br>~~ee~~|2.00<br>~~ee~~<br>~~es ee~~|0.03<br>~~ee ~~<br>~~ee Gs~~|0.65<br> ~~ee ~~<br>~~Gs~~|0.32<br> ~~ee~~<br>~~es~~|2.04<br>~~es ~~<br>~~ss~~|1.46<br> ~~ee~~<br>~~ss~~|2.40<br>~~es ~~<br>~~rs~~|2.68<br> ~~es ~~<br>~~rs~~|3.71<br> ~~ee ~~|3.13<br> ~~es~~|ns|
## _**Table 2-89 •**_ **3.3 V PCI/PCI-X**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks**
|**Speed Grade**<br>~~es~~<br>~~ae~~|**tDOUT**<br>~~ee~~<br>~~a~~|**tDP**<br>~~es~~<br>~~ee~~|**tDIN**<br>~~Gs~~<br>~~ee~~|**tPY**<br>~~Gs~~<br>~~es ee~~|**tEOUT**<br>~~ns~~<br>~~ee~~|**tZL**<br>~~(nD~~<br>~~es~~|**tZH**<br>~~(nD I~~<br>~~es~~|**tLZ**<br>~~I~~<br>~~ee~~|**tHZ**<br>~~S(O~~<br>~~es~~|**tZLS**<br>~~S(O~~<br>~~es~~|**tZHS**<br>~~es~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Std.<br>~~es ~~<br>~~ae~~<br>~~es~~|0.66<br> ~~ee~~<br>~~a~~<br>~~es~~|2.31<br>~~es ~~<br>~~ee~~<br>~~es~~|0.04<br> ~~Gs~~<br>~~ee~~<br>~~ns~~|0.85<br>~~Gs ~~<br>~~es ee~~<br>~~ns~~|0.43<br> ~~ns~~<br>~~ee~~<br>~~ns~~|2.35<br>~~(nD~~<br>~~es~~<br>~~(nD~~|1.70<br>~~(nD I~~<br>~~es~~<br>~~(nD I~~|2.79<br>~~I~~<br>~~ee~~<br>~~I~~|3.22<br>~~S(O~~<br>~~es~~<br>~~(O~~|4.59<br>~~S(O~~<br>~~es~~<br>~~(O~~|3.94<br>~~es~~|ns|
|–1<br>~~ae ~~<br>~~es~~<br>~~a~~|0.56<br> ~~a~~<br>~~es~~<br>~~a~~|1.96<br>~~ee ~~<br>~~es~~<br>~~ee~~|0.04<br> ~~ee ~~<br>~~ns~~<br>~~ee~~|0.72<br> ~~es ee~~<br>~~ns~~<br>~~es ee~~|0.36<br>~~ee ~~<br>~~ns~~<br>~~ee~~|2.00<br> ~~es ~~<br>~~(nD~~<br>~~es~~|1.45<br> ~~es~~<br>~~(nD I~~<br>~~ee~~|2.37<br>~~ee ~~<br>~~I~~<br>~~ed~~|2.74<br> ~~es~~<br>~~(O~~<br>~~es~~|3.90<br>~~es~~<br>~~(O~~<br>~~es~~|3.35<br>~~es~~<br>~~es~~|ns|
|–2<br>~~es~~<br>~~a~~|0.49<br>~~es~~<br>~~a~~|1.72<br>~~es~~<br>~~ee~~|0.03<br>~~ns~~<br>~~ee~~|0.64<br>~~ns ~~<br>~~es ee~~|0.32<br> ~~ns~~<br>~~ee~~|1.76<br>~~(nD~~<br>~~es~~|1.27<br>~~(nD I~~<br>~~ee~~|2.08<br>~~I~~<br>~~ed~~|2.41<br>~~(O~~<br>~~es~~|3.42<br>~~(O~~<br>~~es~~|2.94<br>~~es~~|ns|
## **Differential I/O Characteristics**
## _**Physical Implementation**_
Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards.
## _**LVDS**_
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-12. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes).
**==> picture [455 x 90] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bourns Part Number: CAT16-LV4F12<br>FPGA FPGA<br>OUTBUF_LVDS P P<br>165 Z0 = 50 <br>+ INBUF_LVDS<br>140 100 <br>–<br>165 Z0 = 50 <br>N N<br>**----- End of picture text -----**<br>
_**Figure 2-12 •**_ **LVDS Circuit Diagram and Board-Level Implementation**
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_ProASIC3 Flash Family FPGAs_
_**Table 2-90 •**_ **LVDS Minimum and Maximum DC Input and Output Levels**
|~~ee~~|~~es es~~|~~es~~|~~es~~|~~ee~~||
|---|---|---|---|---|---|
|**DC Parameter**<br>~~ee~~<br>~~ae~~|**Description**<br>~~es es~~<br>~~es~~|**Min.**<br>~~es~~<br>~~es~~|**Typ.**<br>~~es~~<br>~~es~~<br>~~ee Ge~~|**Max.**<br>~~ee~~<br>~~Ge~~|**Units**|
|VCCI<br>~~ee~~<br>~~ae~~<br>~~es~~|Supply Voltage<br>~~es es~~<br>~~es~~<br>~~ee~~|2.375<br>~~es~~<br>~~es~~<br>~~ee~~|2.5<br>~~es~~<br>~~es~~<br>~~ee Ge~~<br>~~ee~~|2.625<br>~~ee~~<br>~~Ge~~<br>~~ee~~|V<br>~~ee~~|
|VOL<br>~~ae~~<br>~~es~~<br>~~es ee~~|Output Low Voltage<br>~~es ~~<br>~~ee~~<br>~~ee~~|0.9<br> ~~es~~<br>~~ee~~|1.075<br>~~es~~<br>~~ee Ge~~<br>~~ee~~|1.25<br>~~Ge~~<br>~~ee~~|V<br>~~ee~~|
|VOH<br>~~es~~<br>~~es ee~~<br>~~es~~|Output High Voltage<br>~~ee~~<br>~~ee~~|1.25<br>~~ee~~|1.425<br>~~ee~~|1.6<br>~~ee~~|V<br>~~ee~~|
|IOL 1<br>~~es ee~~<br>~~es~~<br>~~re~~|Output Lower Current<br>~~ee~~<br>~~es~~|0.65<br>~~es~~|0.91<br>~~es~~|1.16<br>~~es~~|mA<br>~~es~~|
|IOH 1<br>~~es~~<br>~~re~~<br>~~ee~~<br>~~ee~~|Output High Current<br>~~es~~<br>~~es~~|0.65<br>~~es~~<br>~~es~~<br>~~ee~~|0.91<br>~~es~~<br>~~es~~<br>~~es~~|1.16<br>~~es~~<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~es~~|
|VI<br>~~re~~<br>~~ee~~<br>~~ee~~<br>~~ae~~|Input Voltage<br>~~es~~<br>~~es~~<br>~~es~~|0<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~es~~|~~es~~<br>~~es~~<br>~~es~~<br>~~ee~~|2.925<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~Ge~~|V<br>~~es~~<br>~~es~~|
|IIH 2,3<br>~~ee~~<br>~~ee~~<br>~~ae~~<br>~~es~~|Input High Leakage Current<br>~~es~~<br>~~es~~<br>~~es~~<br>|~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~<br>~~ee~~<br>~~ee~~|10<br>~~es~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|µA<br>~~es~~|
|IIL 2,4<br>~~ee~~<br>~~ae~~<br>~~es ee~~<br>~~es~~|Input Low Leakage Current<br>~~es~~<br>~~es~~<br>~~ee~~|~~ee~~<br>~~es~~<br>~~es~~|~~es ~~<br>~~ee~~<br>~~ee~~|10<br> ~~ee~~<br>~~Ge~~<br>~~Ge~~|µA|
|VODIFF<br>~~ae~~<br>~~es ee~~<br>~~es~~|Differential Output Voltage<br>~~es ~~<br>~~es~~<br>~~ee~~|250<br> ~~es ~~<br>~~es~~|350<br> ~~ee ~~<br>~~ee~~|450<br> ~~Ge~~<br>~~Ge~~|mV|
|VOCM<br>~~es ee~~<br>~~es~~<br>~~re~~|Output Common Mode Voltage<br>~~es ~~<br>~~ee~~<br>~~es~~|1.125<br> ~~es ~~<br>~~es~~|1.25<br> ~~ee ~~<br>~~es~~|1.375<br> ~~Ge~~<br>~~es~~|V<br>~~es~~|
|VICM<br>~~ee~~<br>~~es~~<br>~~re~~<br>~~a~~|Input Common Mode Voltage<br>~~ee~~<br>~~es~~<br>~~es es~~|0.05<br>~~es~~<br>~~es~~|1.25<br>~~es~~|2.35<br>~~es~~|V<br>~~es~~|
|VIDIFF<br>~~re~~<br>~~a~~|Input Differential Voltage<br>~~es~~<br>~~es es~~|100<br>~~es~~<br>~~es~~|350<br>~~es~~|~~es~~|mV<br>~~es~~|
## _Notes:_
_1. IOL/ IOH defined by VODIFF/(Resistor Network)_
_2. Currents are measured at 85°C junction temperature._
_3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <VCCI. Input current is larger when operating outside recommended ranges._
_4. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN <VIL._
_**Table 2-91 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
|**Input Low (V)**|**Input High (V)**|**Measuring Point* (V)**|
|---|---|---|
|1.075|1.325|Cross point|
_Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-92 •**_ **LVDS**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V**
|**Speed Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**Units**|
|---|---|---|---|---|---|
|Std.|0.66|1.83|0.04|1.60|ns|
|–1|0.56|1.56|0.04|1.36|ns|
|–2|0.49|1.37|0.03|1.20|ns|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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_ProASIC3 DC and Switching Characteristics_
## _**B-LVDS/M-LVDS**_
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to highperformance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-13. The input and output buffer delays are available in the LVDS section in Table 2-92.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5").
**==> picture [458 x 110] intentionally omitted <==**
**----- Start of picture text -----**<br>
Receiver Transceiver Driver Receiver Transceiver<br>EN EN D EN EN EN BIBUF_LVDS<br>R T R T<br>+ - + - + - + - + -<br>RS RS RS RS RS RS RS RS RS RS<br>Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub ...<br>Z0 Z0 Z0 Z0 Z0 Z0<br>RT Z0 Z0 Z0 Z0 Z0 Z0 RT<br>**----- End of picture text -----**<br>
_**Figure 2-13 •**_ **B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers**
## _**LVPECL**_
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-14. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different.
**==> picture [466 x 89] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bourns Part Number: CAT16-PC4F12<br>FPGA FPGA<br>OUTBUF_LVPECL P 100 Z0 = 50 P<br>+ INBUF_LVPECL<br>187 W 100 <br>–<br>100 Z0 = 50 <br>N N<br>**----- End of picture text -----**<br>
_**Figure 2-14 •**_ **LVPECL Circuit Diagram and Board-Level Implementation**
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_ProASIC3 Flash Family FPGAs_
_**Table 2-93 •**_ **Minimum and Maximum DC Input and Output Levels**
|~~a~~|~~es~~|~~rs~~|~~ee~~|~~es~~|~~es~~||||
|---|---|---|---|---|---|---|---|---|
|**DC Parameter**<br>~~a~~|**Description**<br>~~es~~|**Min.**<br>~~rs~~|**Max.**<br>~~ee~~|**Min.**<br>~~es~~|**Max.**<br>~~es~~|**Min.**|**Max.**|**Units**|
|VCCI<br>~~a~~<br>~~a~~<br>~~Re~~|Supply Voltage<br>~~es ~~<br>~~rs~~|3.0<br> ~~rs ee ~~<br>~~rsQQ~~||3.3<br> ~~es es~~<br>~~QQ~~||3.6||V|
|VOL<br>~~Re~~<br>~~ee~~<br>~~a~~|Output Low Voltage<br>~~rs~~<br>~~es~~<br>|0.96<br>~~rs~~<br>~~es~~<br>~~es~~<br>|1.27<br>~~QQ~~<br>~~es~~<br>~~**e**e~~<br>|1.06<br>~~QQ~~<br>~~es~~<br>~~se~~|1.43<br>~~QQ~~<br>~~es~~<br>~~se~~|1.30<br>~~es~~|1.57<br>~~es~~|V<br>~~es~~|
|VOH<br>~~Re~~<br>~~ee~~<br>~~a~~<br>~~Re~~|Output High Voltage<br>~~rs ~~<br>~~es~~<br>|1.8<br> ~~rs~~<br>~~es~~<br>~~es~~<br><br>~~es~~|2.11<br>~~QQ~~<br>~~es~~<br>~~**e**e~~<br><br>~~es~~|1.92<br>~~QQ~~<br>~~es~~<br>~~se~~<br>~~ee~~|2.28<br>~~QQ~~<br>~~es~~<br>~~se~~<br>~~ee~~|2.13<br>~~es~~<br>~~es~~|2.41<br>~~es~~|V<br>~~es~~|
|VIL, VIH<br>~~ee~~<br>~~a ~~<br>~~Re~~<br>~~ee~~|Input Low, Input High Voltages<br>~~es~~<br> ~~e~~<br>~~rs~~|0<br>~~es~~<br>~~es ~~<br>~~e~~<br>~~es~~<br>~~rs~~|3.6<br>~~es~~<br> ~~**e**e ~~<br>~~e~~<br>~~es~~<br>~~Gn~~|0<br>~~es~~<br> ~~se~~<br>~~ee~~<br>~~QO~~|3.6<br>~~es~~<br>~~se~~<br>~~ee~~<br>~~QO~~|0<br>~~es~~<br>~~es~~|3.6<br>~~es~~|V<br>~~es~~|
|VODIFF<br>~~Re~~<br>~~ee~~<br>~~a~~|Differential Output Voltage<br>~~rs~~<br>~~rs~~|0.625<br>~~es~~<br>~~rs~~<br>~~rs~~|0.97<br>~~es~~<br>~~Gn~~<br>~~Qe~~|0.625<br>~~ee~~<br>~~QO~~<br>~~Qe~~|0.97<br>~~ee~~<br>~~QO~~<br>~~Gs~~|0.625<br>~~es~~<br>~~Gs~~|0.97|V|
|VOCM<br>~~Re~~<br>~~ee~~<br>~~a~~<br>~~ae~~|Output Common-Mode Voltage<br>~~rs~~<br>~~rs~~<br>~~es~~|1.762<br>~~es ~~<br>~~rs~~<br>~~rs~~<br>~~ee~~|1.98<br> ~~es ~~<br>~~Gn~~<br>~~Qe~~<br>~~ee~~|1.762<br> ~~ee~~<br>~~QO~~<br>~~Qe~~<br>~~es~~|1.98<br>~~ee ~~<br>~~QO~~<br>~~Gs~~<br>~~es~~|1.762<br> ~~es~~<br>~~Gs~~<br>~~es~~|1.98|V|
|VICM<br>~~ee~~<br>~~a~~<br>~~ae~~|Input Common-Mode Voltage<br>~~rs ~~<br>~~rs ~~<br>~~es~~<br>~~rs~~|1.01<br> ~~rs~~<br> ~~rs~~<br>~~ee~~<br>~~rs~~|2.57<br>~~Gn ~~<br>~~Qe~~<br>~~ee~~<br>~~es~~|1.01<br> ~~QO~~<br>~~Qe~~<br>~~es~~<br>~~es~~|2.57<br>~~QO~~<br>~~Gs~~<br>~~es~~|1.01<br>~~Gs~~<br>~~es~~|2.57|V|
|VIDIFF<br>~~ae~~|Input Differential Voltage<br>~~es~~<br>~~rs~~|300<br>~~ee~~<br>~~rs~~|~~ee~~<br>~~es~~|300<br>~~es~~<br>~~es~~|~~es~~|300<br>~~es~~||mV|
_**Table 2-94 •**_ **AC Waveforms, Measuring Points, and Capacitive Loads**
_Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points._
## _**Timing Characteristics**_
_**Table 2-95 •**_ **LVPECL**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V**
|**Speed Grade**|**tDOUT**|**tDP**|**tDIN**|**tPY**|**Units**|
|---|---|---|---|---|---|
|Std.|0.66|1.80|0.04|1.40|ns|
|–1|0.56|1.53|0.04|1.19|ns|
|–2|0.49|1.34|0.03|1.05|ns|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-68**
_ProASIC3 DC and Switching Characteristics_
## **I/O Register Specifications**
## _**Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset**_
**==> picture [459 x 332] intentionally omitted <==**
**----- Start of picture text -----**<br>
Preset L<br>D<br>DOUT<br>Data_out<br>PRE Y F PRE<br>E<br>Data D Q Core D Q<br>C DFN1E1P1 Array G DFN1E1P1<br>E E<br>Enable<br>B EOUT<br>H<br>CLK I<br>A<br>J PRE<br>D Q<br>K DFN1E1P1<br>Data Input I/O Register with: E<br>Active High Enable<br>Active High Preset<br>Positive-Edge Triggered<br>Data Output Register and<br>Enable Output Register with:<br>Active High Enable<br>Active High Preset<br>Postive-Edge Triggered<br>CLKBUF INBUF INBUF<br>CLK Enable D_Enable<br>Pad Out<br>INBUF<br>INBUF TRIBUF<br>INBUF<br>CLKBUF<br>**----- End of picture text -----**<br>
_**Figure 2-15 •**_ **Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset**
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_ProASIC3 Flash Family FPGAs_
_**Table 2-96 •**_ **Parameter Definition and Measuring Nodes**
|**Parameter Name**<br>~~a ee~~|**Parameter Definition**<br>~~ee~~|**Measuring Nodes**<br>**(from, to)***<br>~~—~~<br>|
|---|---|---|
|tOCLKQ<br><br>~~**es**~~|Clock-to-Q of the Output Data Register<br>|H, DOUT<br><br>~~S|~~|
|tOSUD<br><br>~~**es**~~|Data Setup Time for the Output Data Register<br>|F, H<br>~~|~~<br>~~S|~~|
|tOHD<br>~~**es**~~|Data Hold Time for the Output Data Register|F, H<br>~~S|~~|
|tOSUE<br>~~**ee**~~|Enable Setup Time for the Output Data Register|G, H<br>~~PT~~|
|tOHE<br>~~**ee**~~|Enable Hold Time for the Output Data Register|G, H<br>~~PT~~|
|tOPRE2Q<br>~~**ee**~~|Asynchronous Preset-to-Q of the Output Data Register|L, DOUT<br>~~PT~~|
|tOREMPRE<br>~~**es**~~|Asynchronous Preset Removal Time for the Output Data Register|L, H<br>~~S|~~|
|tORECPRE<br>~~**es**~~|Asynchronous Preset Recovery Time for the Output Data Register|L, H<br>~~S|~~|
|tOECLKQ<br>~~**es**~~|Clock-to-Q of the Output Enable Register|H, EOUT<br>~~S|~~|
|tOESUD<br>~~**ee**~~|Data Setup Time for the Output Enable Register|J, H<br>~~PT~~|
|tOEHD<br>~~**ee**~~|Data Hold Time for the Output Enable Register|J, H<br>~~PT~~|
|tOESUE<br>~~**ee**~~<br>~~ee~~|Enable Setup Time for the Output Enable Register<br>~~ee~~|K, H<br>~~PT~~<br>~~ee~~|
|tOEHE<br>~~ee~~|Enable Hold Time for the Output Enable Register<br>~~ee~~|K, H<br>~~ee~~|
|tOEPRE2Q<br>~~ee~~|Asynchronous Preset-to-Q of the Output Enable Register<br>~~ee~~|I, EOUT<br>~~ee~~|
|tOEREMPRE<br>|Asynchronous Preset Removal Time for the Output Enable Register<br>~~a~~|I, H<br>~~a~~|
|tOERECPRE<br>~~**ee**~~|Asynchronous Preset Recovery Time for the Output Enable Register<br>~~a~~|I, H<br>~~PS~~<br>~~a~~|
|tICLKQ<br>~~**ee**~~|Clock-to-Q of the Input Data Register<br>~~a~~|A, E<br>~~PS~~<br>~~a~~|
|tISUD<br>~~**ee**~~|Data Setup Time for the Input Data Register<br>|C, A<br>~~PS~~<br>|
|tIHD<br>~~es~~<br>~~a~~|Data Hold Time for the Input Data Register|C, A<br>~~PT~~|
|tISUE<br>~~es~~|Enable Setup Time for the Input Data Register|B, A<br>~~PT~~|
|tIHE<br>~~es~~<br>~~**ee**~~|Enable Hold Time for the Input Data Register|B, A<br>~~PT~~<br>~~PT~~|
|tIPRE2Q<br>~~**ee**~~|Asynchronous Preset-to-Q of the Input Data Register|D, E<br>~~PS~~<br>~~PT~~|
|tIREMPRE<br>~~**ee**~~<br>~~ee~~|Asynchronous Preset Removal Time for the Input Data Register<br>~~ee~~|D, A<br>~~PT~~<br>~~ee~~|
|tIRECPRE<br>~~ee~~|Asynchronous Preset Recovery Time for the Input Data Register<br>~~ee~~|D, A<br>~~ee~~|
**Revision 18**
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_ProASIC3 DC and Switching Characteristics_
## _**Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear**_
**==> picture [463 x 350] intentionally omitted <==**
**----- Start of picture text -----**<br>
DOUT<br>Y Core Data_out FF<br>Data D Q D Q<br>CC DFN1E1C1 EE Array DFN1E1C1<br>GG<br>E E EOUT<br>Enable<br>BB CLR CLR<br>LL<br>HH<br>CLK i nn<br>AA<br>JJ<br>CLR D Q<br>DD<br>DFN1E1C1<br>KK<br>E<br>> Data Input I/O Register with o er CLR F<br>Active High Enable<br>Active High Clear<br>Positive-Edge Triggered Data Output Register and<br>Enable Output Register with<br>Active High Enable<br>Active High Clear<br>INBUF INBUF CLKBUF Positive-Edge Triggered<br>I kw kX<br>Enable D_Enable CLK<br>Pad Out<br>INBUF TRIBUF<br>INBUF<br>CLKBUF<br>INBUF<br>**----- End of picture text -----**<br>
_**Figure 2-16 •**_ **Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear**
**2-71**
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_ProASIC3 Flash Family FPGAs_
_**Table 2-97 •**_ **Parameter Definition and Measuring Nodes**
|**Parameter Name**<br>~~ee~~|**Parameter Definition**<br>|**Measuring Nodes**<br>**(from, to)***<br>~~—~~<br>|
|---|---|---|
|tOCLKQ<br>~~ee~~<br>~~**ee**~~|Clock-to-Q of the Output Data Register<br>~~ee~~<br>~~||~~|HH, DOUT<br>~~—~~<br>~~ee~~<br>~~||~~|
|tOSUD<br>~~ee~~<br>~~**ee**~~|Data Setup Time for the Output Data Register<br><br>~~||~~|FF, HH<br>~~—~~<br><br>~~||~~|
|tOHD<br>~~**ee**~~|Data Hold Time for the Output Data Register<br>~~||~~|FF, HH<br>~~||~~|
|tOSUE<br>~~**ee**~~|Enable Setup Time for the Output Data Register<br>~~|~~|GG, HH<br>~~|~~|
|tOHE<br>~~a~~|Enable Hold Time for the Output Data Register|GG, HH|
|tOCLR2Q<br>~~a~~|Asynchronous Clear-to-Q of the Output Data Register|LL, DOUT<br>~~Pe~~|
|tOREMCLR<br>~~**ee**~~|Asynchronous Clear Removal Time for the Output Data Register<br>~~|~~|LL, HH<br>~~|~~|
|tORECCLR<br>~~**ee**~~|Asynchronous Clear Recovery Time for the Output Data Register<br>~~|~~|LL, HH<br>~~|~~|
|tOECLKQ<br>~~**ee**~~|Clock-to-Q of the Output Enable Register<br>~~|~~|HH, EOUT<br>~~|~~|
|tOESUD<br>~~**ee**~~|Data Setup Time for the Output Enable Register<br>~~|~~|JJ, HH<br>~~|~~|
|tOEHD<br>~~a~~|Data Hold Time for the Output Enable Register|JJ, HH|
|tOESUE<br>~~a~~|Enable Setup Time for the Output Enable Register|KK, HH<br>~~Pe~~|
|tOEHE<br>~~a~~|Enable Hold Time for the Output Enable Register<br>~~a~~|KK, HH<br>~~a~~|
|tOECLR2Q|Asynchronous Clear-to-Q of the Output Enable Register|II, EOUT|
|tOEREMCLR<br>~~es~~|Asynchronous Clear Removal Time for the Output Enable Register|II, HH|
|tOERECCLR<br>~~es~~<br>~~es~~|Asynchronous Clear Recovery Time for the Output Enable Register|II, HH<br>~~PC~~|
|tICLKQ<br>~~es~~<br>~~es~~|Clock-to-Q of the Input Data Register|AA, EE<br>~~PC~~|
|tISUD<br>~~es~~|Data Setup Time for the Input Data Register|CC, AA<br>~~PC~~|
|tIHD<br>~~ee~~<br>~~a~~|Data Hold Time for the Input Data Register<br>|CC, AA<br>~~Pe~~<br>|
|tISUE<br>~~ee~~|Enable Setup Time for the Input Data Register<br>~~en~~|BB, AA<br>~~Pe~~<br>~~en~~|
|tIHE<br>~~ee~~<br>~~es~~|Enable Hold Time for the Input Data Register<br>|BB, AA<br>~~Pe~~<br><br>~~Pe~~|
|tICLR2Q<br>~~es~~|Asynchronous Clear-to-Q of the Input Data Register|DD, EE<br>~~PC~~<br>~~Pe~~|
|tIREMCLR<br>~~es~~<br>~~a~~|Asynchronous Clear Removal Time for the Input Data Register|DD, AA<br>~~Pe~~|
|tIRECCLR<br>~~a es~~|Asynchronous Clear Recovery Time for the Input Data Register<br>~~es~~|DD, AA<br>~~es~~|
_Note: *See Figure 2-16 on page 2-71 for more information._
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_ProASIC3 DC and Switching Characteristics_
## _**Input Register**_
|tICKMPWH tICKMPWL|
|---|
|50%<br>Preset<br>Clear<br>Out_1<br>CLK<br>Data<br>Enable<br>tISUE<br>50%<br>50%<br>tISUD<br>tIHD<br>50%<br>50%<br>1<br>0<br>tIHE<br>tIRECPRE<br>tIREMPRE<br>tIRECCLR<br>tIREMCLR<br>tIWCLR<br>tIWPRE<br>tIPRE2Q<br>tICLR2Q<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>~~EM A~~U ~~a~~<br>ee oe<br>ee ee ee<br>iu ~~aa~~<br>~~a~~|
|tICLKQ|
|**_Figure 2-17 •_Input Register Timing Diagram**|
|**_Timing Characteristics_**|
|**_Table 2-98 •_Input Data Register Propagation Delays**|
|**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**|
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std. Units**<br>tICLKQ<br>Clock-to-Q of the Input Data Register<br>0.24 0.27 0.32<br>ns<br>tISUD<br>Data Setup Time for the Input Data Register<br>0.26 0.30 0.35<br>ns<br>tIHD<br>Data Hold Time for the Input Data Register<br>0.00 0.00 0.00<br>ns<br>tISUE<br>Enable Setup Time for the Input Data Register<br>0.37 0.42 0.50<br>ns<br>tIHE<br>Enable Hold Time for the Input Data Register<br>0.00 0.00 0.00<br>ns<br>tICLR2Q<br>Asynchronous Clear-to-Q of the Input Data Register<br>0.45 0.52 0.61<br>ns<br>tIPRE2Q<br>Asynchronous Preset-to-Q of the Input Data Register<br>0.45 0.52 0.61<br>ns<br>tIREMCLR<br>Asynchronous Clear Removal Time for the Input Data Register<br>0.00 0.00 0.00<br>ns<br>tIRECCLR<br>Asynchronous Clear Recovery Time for the Input Data Register<br>0.22 0.25 0.30<br>ns<br>tIREMPRE<br>Asynchronous Preset Removal Time for the Input Data Register<br>0.00 0.00 0.00<br>ns<br>tIRECPRE<br>Asynchronous Preset Recovery Time for the Input Data Register<br>0.22 0.25 0.30<br>ns<br>tIWCLR<br>Asynchronous Clear Minimum Pulse Width for the Input Data Register<br>0.22 0.25 0.30<br>ns<br>tIWPRE<br>Asynchronous Preset Minimum Pulse Width for the Input Data Register<br>0.22 0.25 0.30<br>ns<br>~~ee~~<br>~~oi~~<br>~~ee~~<br>~~a~~<br>~~aee~~<br>~~a~~<br>~~ee~~<br>~~oo~~<br>~~ee~~<br>~~oi~~<br>~~ee~~<br>~~a~~|
|tICKMPWH<br>Clock Minimum Pulse Width High for the Input Data Register<br>0.36 0.41 0.48<br>ns|
|tICKMPWL<br>Clock Minimum Pulse Width Low for the Input Data Register<br>0.32 0.37 0.43<br>ns|
_**Figure 2-17 •**_ **Input Register Timing Diagram**
## _**Timing Characteristics**_
_**Table 2-98 •**_ **Input Data Register Propagation Delays**
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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_ProASIC3 Flash Family FPGAs_
## _**Output Register**_
**==> picture [454 x 251] intentionally omitted <==**
**----- Start of picture text -----**<br>
tOCKMPWH tOCKMPWL<br>50% 50% 50% 50% 50% 50% 50%<br>CLK<br>tOSUD tOHD<br>Data_out 1 50% 0 50%<br>PA<br>S s<br>Enable 50% tOREMPRE<br>tOHE tOWPRE tORECPRE<br>50% 50% 50%<br>Preset tOSUE<br>tOWCLR tORECCLR tOREMCLR<br>50% 50% 50%<br>Clear<br>t<br>OPRE2Q<br>DOUT 50% 50% t 50%<br>OCLR2Q<br>1 |<br>t<br>OCLKQ<br>**----- End of picture text -----**<br>
_**Figure 2-18 •**_ **Output Register Timing Diagram**
## _**Timing Characteristics**_
_**Table 2-99 •**_ **Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|~~ee~~|**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 VJ = 70°C, Worst-Case VCC = 1.425 V = 70°C, Worst-Case VCC = 1.425 V**|||||
|---|---|---|---|---|---|
|**Parameter**<br>~~ee~~<br>~~ee~~|**Description**|**–2**|**–1**|**Std.**|**Units**|
|tOCLKQ<br>~~ee~~<br>~~ee~~<br>~~es~~|Clock-to-Q of the Output Data Register<br>~~ee~~|0.59<br>~~Gt~~|0.67<br>~~Gd~~|0.79<br>~~Gs~~|ns|
|tOSUD<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~|Data Setup Time for the Output Data Register<br>~~ee~~<br>~~nS~~|0.31<br>~~Gt~~<br>~~nS~~<br>~~I~~|0.36<br>~~Gd~~<br>~~nS~~<br>~~(I~~|0.42<br>~~Gs~~<br>~~nS~~|ns<br>~~nS~~|
|tOHD<br>~~es~~<br>~~ee~~<br>~~ee~~|Data Hold Time for the Output Data Register<br>~~ee~~<br>~~nS~~|0.00<br>~~Gt ~~<br>~~nS~~<br>~~I~~|0.00<br> ~~Gd ~~<br>~~nS~~<br>~~(I~~|0.00<br> ~~Gs~~<br>~~nS~~|ns<br>~~nS~~|
|tOSUE<br>~~ee~~<br>~~ee~~<br>~~ee~~|Enable Setup Time for the Output Data Register<br>~~nS~~<br>~~GO~~|0.44<br>~~nS~~<br>~~I~~<br>~~GO~~|0.50<br>~~nS~~<br>~~(I~~<br>~~GO~~|0.59<br>~~nS~~<br>~~GO~~|ns<br>~~nS~~<br>~~GO~~|
|tOHE<br>~~ee~~<br>~~ee~~<br>~~ee~~|Enable Hold Time for the Output Data Register<br>~~GO~~|0.00<br>~~I ~~<br>~~GO~~|0.00<br> ~~(I~~<br>~~GO~~|0.00<br>~~GO~~|ns<br>~~GO~~|
|tOCLR2Q<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Clear-to-Q of the Output Data Register<br>~~GO~~<br>~~a~~|0.80<br>~~GO~~<br>~~a~~|0.91<br>~~GO~~<br>~~a~~|1.07<br>~~GO~~<br>~~a~~|ns<br>~~GO~~<br>~~a~~|
|tOPRE2Q<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Preset-to-Q of the Output Data Register<br>~~a~~<br>~~SG~~|0.80<br>~~a~~<br>~~SG~~|0.91<br>~~a~~<br>~~SG~~|1.07<br>~~a~~<br>~~SG~~|ns<br>~~a~~<br>~~SG~~|
|tOREMCLR<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Clear Removal Time for the Output Data Register<br>~~a~~<br>~~SG~~|0.00<br>~~a~~<br>~~SG~~|0.00<br>~~a~~<br>~~SG~~|0.00<br>~~a~~<br>~~SG~~|ns<br>~~a~~<br>~~SG~~|
|tORECCLR<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Clear Recovery Time for the Output Data Register<br>~~SG~~<br>~~nS~~|0.22<br>~~SG~~<br>~~nS~~<br>~~I~~|0.25<br>~~SG~~<br>~~nS~~<br>~~(I~~|0.30<br>~~SG~~<br>~~nS~~|ns<br>~~SG~~<br>~~nS~~|
|tOREMPRE<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Preset Removal Time for the Output Data Register<br>~~nS~~|0.00<br>~~nS~~<br>~~I~~|0.00<br>~~nS~~<br>~~(I~~|0.00<br>~~nS~~|ns<br>~~nS~~|
|tORECPRE<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Preset Recovery Time for the Output Data Register<br>~~nS~~<br>~~a~~|0.22<br>~~nS~~<br>~~I~~<br>~~a~~|0.25<br>~~nS~~<br>~~(I~~<br>~~a~~|0.30<br>~~nS~~<br>~~a~~|ns<br>~~nS~~<br>~~a~~|
|tOWCLR<br>~~ee~~<br>~~ee~~<br>~~ee~~|Asynchronous Clear Minimum Pulse Width for the Output Data Register<br>~~a~~|0.22<br>~~I ~~<br>~~a~~|0.25<br> ~~(I~~<br>~~a~~|0.30<br>~~a~~|ns<br>~~a~~|
|tOWPRE<br>~~ee~~<br>~~ee~~<br>~~es~~|Asynchronous Preset Minimum Pulse Width for the Output Data Register<br>~~a~~<br>~~ee~~|0.22<br>~~a~~<br>~~Gt~~|0.25<br>~~a~~<br>~~Gd~~|0.30<br>~~a~~<br>~~Gs~~|ns<br>~~a~~|
|tOCKMPWH<br>~~ee~~<br>~~es~~<br>~~ee~~|Clock Minimum Pulse Width High for the Output Data Register<br>~~ee~~<br>~~nS~~|0.36<br>~~Gt~~<br>~~nS~~<br>~~I~~|0.41<br>~~Gd~~<br>~~nS~~|0.48<br>~~Gs~~<br>~~nS~~|ns<br>~~nS~~|
|tOCKMPWL<br>~~es~~<br>~~ee~~|Clock Minimum Pulse Width Low for the Output Data Register<br>~~ee~~<br>~~nS~~|0.32<br>~~Gt ~~<br>~~nS~~<br>~~I~~|0.37<br> ~~Gd ~~<br>~~nS~~|0.43<br> ~~Gs~~<br>~~nS~~|ns<br>~~nS~~|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-74**
_ProASIC3 DC and Switching Characteristics_
## _**Output Enable Register**_
**==> picture [462 x 262] intentionally omitted <==**
**----- Start of picture text -----**<br>
tOECKMPWH tOECKMPWL<br>50% 50% 50% 50% 50% 50% 50%<br>CLK<br>tOESUDtOEHD<br>1 50% 0 50%<br>D_Enable<br>50%<br>Enable tOEWPRE tOERECPRE tOEREMPRE<br>50% 50% 50%<br>Preset tOESUEtOEHE<br>tOEWCLR tOERECCLR tOEREMCLR<br>50% 50% 50%<br>Clear<br>q- i|‘<br>tOEPRE2Q tOECLR2Q<br>50% 50% 50%<br>EOUT<br>tOECLKQ va n ,<br>**----- End of picture text -----**<br>
_**Figure 2-19 •**_ **Output Enable Register Timing Diagram**
**2-75**
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_ProASIC3 Flash Family FPGAs_
## **Timing Characteristics**
_**Table 2-100 •**_ **Output Enable Register Propagation Delays**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
**==> picture [468 x 273] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|a es|
|tOECLKQ|Clock-to-Q of the Output Enable Register|0.59|0.67|0.79|ns|
|a este|
|tOESUD|Data Setup Time for the Output Enable Register|0.31|0.36|0.42|ns|
|a es|
|tOEHD|Data Hold Time for the Output Enable Register|0.00|0.00|0.00|ns|
|aade|
|tOESUE|Enable Setup Time for the Output Enable Register|0.44|0.50|0.58|ns|
|a ee|
|tOEHE|Enable Hold Time for the Output Enable Register|0.00|0.00|0.00|ns|
|a|
|tOECLR2Q|Asynchronous Clear-to-Q of the Output Enable Register|0.67|0.76|0.89|ns|
|a|
|tOEPRE2Q|Asynchronous Preset-to-Q of the Output Enable Register|0.67|0.76|0.89|ns|
|ee|es|
|tOEREMCLR|Asynchronous Clear Removal Time for the Output Enable Register|0.00|0.00|0.00|ns|
|a eses|ee|es|
|tOERECCLR|Asynchronous Clear Recovery Time for the Output Enable Register|0.22|0.25|0.30|ns|
|a a|
|tOEREMPRE|Asynchronous Preset Removal Time for the Output Enable Register|0.00|0.00|0.00|ns|
|a|ee|
|tOERECPRE|Asynchronous Preset Recovery Time for the Output Enable Register|0.22|0.25|0.30|ns|
|a|
|tOEWCLR|Asynchronous Clear Minimum Pulse Width for the Output Enable Register|0.22|0.25|0.30|ns|
|a|
|tOEWPRE|Asynchronous Preset Minimum Pulse Width for the Output Enable Register|0.22|0.25|0.30|ns|
|ee|es|
|tOECKMPWH|Clock Minimum Pulse Width High for the Output Enable Register|0.36|0.41|0.48|ns|
|a eses|ee|es|
|tOECKMPWL|Clock Minimum Pulse Width Low for the Output Enable Register|0.32|0.37|0.43|ns|
|a ee|
**----- End of picture text -----**<br>
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-76**
_ProASIC3 DC and Switching Characteristics_
## **DDR Module Specifications** _**Input DDR Module**_
**==> picture [406 x 301] intentionally omitted <==**
**----- Start of picture text -----**<br>
Input DDR<br>INBUF<br>A<br>Data D Out_QF<br>(to core)<br>FF1<br>B E Out_QR<br>CLK<br>(to core)<br>CLKBUF<br>FF2<br>C<br>CL R<br>INBUF<br>DDR_IN<br>**----- End of picture text -----**<br>
_**Figure 2-20 •**_ **Input DDR Timing Model**
_**Table 2-101 •**_ **Parameter Definitions**
|**Parameter Name**|**Parameter Definition**|**Measuring Nodes (from, to)**|
|---|---|---|
|tDDRICLKQ1|Clock-to-Out Out_QR|B, D|
|tDDRICLKQ2|Clock-to-Out Out_QF|B, E|
|tDDRISUD|Data Setup Time of DDR input|A, B|
|tDDRIHD|Data Hold Time of DDR input|A, B|
|tDDRICLR2Q1|Clear-to-Out Out_QR|C, D|
|tDDRICLR2Q2|Clear-to-Out Out_QF|C, E|
|tDDRIREMCLR|Clear Removal|C, B|
|tDDRIRECCLR|Clear Recovery|C, B|
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_ProASIC3 Flash Family FPGAs_
|CLK|||
|---|---|---|
|tDDRIHD<br>tDDRISUD|||
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>Data|9||
|tDDRIRECCLR|||
|tDDRIREMCLR<br>tDDRICLR2Q1<br>CLR<br>Out_QF<br>tDDRICLKQ1<br>2<br>4<br>6<br>~~p= ee~~|||
|**_Figure 2-21 •_Input DDR Timing Diagram**<br>tDDRICLR2Q2<br>Out_QR<br>3<br>5<br>7<br>tDDRICLKQ2<br>ni<br>~~nn)~~<br>~~a~~<br>~~ae~~|||
|**_Timing Characteristics_**|||
|**_Table 2-102 •_Input DDR Propagation Delays**|||
|**Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V**|||
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std.**<br>**Units**<br>tDDRICLKQ1<br>Clock-to-Out Out_QR for Input DDR<br>0.27<br>0.31<br>0.37<br>ns<br>tDDRICLKQ2<br>Clock-to-Out Out_QF for Input DDR<br>0.39<br>0.44<br>0.52<br>ns<br>tDDRISUD<br>Data Setup for Input DDR (Fall)<br>0.25<br>0.28<br>0.33<br>ns<br>Data Setup for Input DDR (Rise)<br>0.25<br>0.28<br>0.33<br>ns<br>tDDRIHD<br>Data Hold for Input DDR (Fall)<br>0.00<br>0.00<br>0.00<br>ns<br>Data Hold for Input DDR (Rise)<br>0.00<br>0.00<br>0.00<br>ns<br>tDDRICLR2Q1<br>Asynchronous Clear-to-Out Out_QR for Input DDR<br>0.46<br>0.53<br>0.62<br>ns<br>tDDRICLR2Q2<br>Asynchronous Clear-to-Out Out_QF for Input DDR<br>0.57<br>0.65<br>0.76<br>ns<br>tDDRIREMCLR<br>Asynchronous Clear Removal time for Input DDR<br>0.00<br>0.00<br>0.00<br>ns<br>tDDRIRECCLR<br>Asynchronous Clear Recovery time for Input DDR<br>0.22<br>0.25<br>0.30<br>ns<br>tDDRIWCLR<br>Asynchronous Clear Minimum Pulse Width for Input DDR<br>0.22<br>0.25<br>0.30<br>ns<br>tDDRICKMPWH<br>Clock Minimum Pulse Width High for Input DDR<br>0.36<br>0.41<br>0.48<br>ns<br>tDDRICKMPWL<br>Clock Minimum Pulse Width Low for Input DDR<br>0.32<br>0.37<br>0.43<br>ns<br>FDDRIMAX<br>Maximum Frequency for Input DDR<br>350<br>309<br>263<br>MHz<br>~~esee~~<br>~~es~~<br>~~es~~<br>~~nea~~<br>~~Be~~<br>~~a~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~a~~|||
_**Figure 2-21 •**_ **Input DDR Timing Diagram**
## _**Timing Characteristics**_
_**Table 2-102 •**_ **Input DDR Propagation Delays**
_Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
**2-78**
_ProASIC3 DC and Switching Characteristics_
## _**Output DDR Module**_
**==> picture [354 x 269] intentionally omitted <==**
**----- Start of picture text -----**<br>
Output DDR<br>A<br>Data_F X<br>(from core)<br>FF1<br>B Out<br>CL K X 0<br>E<br>CLKBUF<br>C X<br>X<br>D 1 OUTBUF<br>Data_R X<br>(from core)<br>FF2<br>B<br>CLR X<br>INBUF C<br>X<br>DDR_OUT<br>**----- End of picture text -----**<br>
_**Figure 2-22 •**_ **Output DDR Timing Model**
_**Table 2-103 •**_ **Parameter Definitions**
|**Parameter Name**|**Parameter Definition**|**Measuring Nodes (from, to)**|
|---|---|---|
|tDDROCLKQ|Clock-to-Out|B, E|
|tDDROCLR2Q|Asynchronous Clear-to-Out|C, E|
|tDDROREMCLR|Clear Removal|C, B|
|tDDRORECCLR|Clear Recovery|C, B|
|tDDROSUD1|Data Setup Data_F|A, B|
|tDDROSUD2|Data Setup Data_R|D, B|
|tDDROHD1|Data Hold Data_F|A, B|
|tDDROHD2|Data Hold Data_R|D, B|
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|1<br>2<br>3<br>4<br>5<br>tDDROHD2<br>tDDROSUD2<br>CLK<br>Data_F<br>[S~~O~~|
|---|
|tDDROHD1<br>tDDROREMCLR|
|11<br>6<br>7<br>8<br>9<br>10<br>Data_R|
|tDDRORECCLR|
|2<br>8<br>3<br>9<br>tDDROREMCLR<br>tDDROCLKQ<br>CLR<br>Out<br>tDDROCLR2Q<br>7<br>10<br>4<br>4<br>~~RS~~|
||
|**_Figure 2-23 •_Output DDR Timing Diagram**|
|**_Timing Characteristics_**|
|**_Table 2-104 •_Output DDR Propagation Delays**|
|**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**|
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std.**<br>**Units**<br>tDDROCLKQ<br>Clock-to-Out of DDR for Output DDR<br>0.70<br>0.80<br>0.94<br>ns<br>tDDROSUD1<br>Data_F Data Setup for Output DDR<br>0.38<br>0.43<br>0.51<br>ns<br>tDDROSUD2<br>Data_R Data Setup for Output DDR<br>0.38<br>0.43<br>0.51<br>ns<br>tDDROHD1<br>Data_F Data Hold for Output DDR<br>0.00<br>0.00<br>0.00<br>ns<br>tDDROHD2<br>Data_R Data Hold for Output DDR<br>0.00<br>0.00<br>0.00<br>ns<br>tDDROCLR2Q<br>Asynchronous Clear-to-Out for Output DDR<br>0.80<br>0.91<br>1.07<br>ns<br>tDDROREMCLR<br>Asynchronous Clear Removal Time for Output DDR<br>0.00<br>0.00<br>0.00<br>ns<br>tDDRORECCLR<br>Asynchronous Clear Recovery Time for Output DDR<br>0.22<br>0.25<br>0.30<br>ns<br>tDDROWCLR1<br>Asynchronous Clear Minimum Pulse Width for Output DDR<br>0.22<br>0.25<br>0.30<br>ns<br>tDDROCKMPWH<br>Clock Minimum Pulse Width High for the Output DDR<br>0.36<br>0.41<br>0.48<br>ns<br>tDDROCKMPWL<br>Clock Minimum Pulse Width Low for the Output DDR<br>0.32<br>0.37<br>0.43<br>ns<br>FDDOMAX<br>Maximum Frequency for the Output DDR<br>350<br>309<br>263<br>MHz<br>~~a en~~<br>~~ttn tt~~<br>~~eeen~~<br>~~ttn te~~<br>~~eers~~<br>~~(ttt teen Gs~~<br>~~eees~~<br>~~Ge Ge es~~<br>~~eeer~~<br>~~ttn tt Gn~~<br>~~ee~~~~**e**e~~<br>~~ttt tt Gn~~<br>~~ee~~<br>~~s~~<br>~~ttn tt ts~~<br>~~eeen~~<br>~~ttn te~~<br>~~eers~~<br>~~(ttt teen Gs~~<br>~~eeee~~<br>~~Ge es es~~<br>~~eees~~<br>~~Ge Ge es~~<br>~~ee~~~~**e**e~~<br>~~**ttt**t~~~~**tGn**~~<br>~~ee~~<br>~~n~~<br>~~t~~|
_**Figure 2-23 •**_ **Output DDR Timing Diagram**
## _**Timing Characteristics**_
_**Table 2-104 •**_ **Output DDR Propagation Delays**
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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## **VersaTile Characteristics**
## **VersaTile Specifications as a Combinatorial Module**
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the _Fusion, IGLOO[®] /e, and ProASIC3/E Macro Library Guide_ .
**==> picture [411 x 345] intentionally omitted <==**
**----- Start of picture text -----**<br>
A Y<br>INV<br>><br>A A<br>OR2 Y NOR2 Y<br>B B<br>> ><br>A<br>A<br>AND2 Y<br>Y<br>NAND2<br>B<br>B<br>1) {><br>A<br>A<br>XOR2 Y B XOR 3 Y<br>B C<br>> =<br>A A<br>MAJ3 0<br>A MUX2 Y<br>B Y<br>B NAN D3 B<br>1<br>C<br>C<br>S<br>**----- End of picture text -----**<br>
_**Figure 2-24 •**_ **Sample of Combinatorial Cells**
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**==> picture [335 x 459] intentionally omitted <==**
**----- Start of picture text -----**<br>
t PD<br>A<br>NAND2 or<br>Y<br>Any Combinatorial<br>B Logic<br>tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR))<br>where edges are applicable for the particular<br>combinatorial cell<br>VCC<br>50% 50%<br>A, B, C GND<br>VCC<br>50%<br>50%<br>OUT<br>GND<br>tPD tPD<br>(FF)<br>VCC (RR)<br>OUT tPD<br>50% (FR) 50%<br>tPD GND<br>(RF)<br>**----- End of picture text -----**<br>
_**Figure 2-25 •**_ **Timing Model and Waveforms**
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## _**Timing Characteristics**_
_**Table 2-105 •**_ **Combinatorial Cell Propagation Delays**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
|**Combinatorial Cell**<br>~~es~~<br>~~es~~|**Equation**<br>~~es rs~~<br>~~rs es~~|**Parameter**<br>~~rs~~<br>~~es~~|**–2**<br>~~rs~~<br>~~es~~<br>~~es~~|**–1**|**Std.**|**Units**|
|---|---|---|---|---|---|---|
|INV<br>~~es~~<br>~~es~~<br>~~ee~~|Y = !A<br>~~es rs~~<br>~~rs es~~<br>~~es~~|tPD<br>~~rs~~<br>~~es~~<br>~~Gs~~|0.40<br>~~rs~~<br>~~es~~<br>~~es~~<br>~~Gs ee~~|0.46|0.54|ns|
|AND2<br>~~es~~<br>~~ee~~<br>~~es~~|Y = A · B<br>~~rs es~~<br>~~es~~<br>~~ed~~|tPD<br>~~es~~<br>~~Gs~~<br>~~rs~~|0.47<br>~~es~~<br>~~es~~<br>~~Gs ee~~<br>~~rsQs~~|0.54|0.63|ns|
|NAND2<br>~~ee~~<br>~~es~~<br>~~es es~~|Y = !(A · B)<br>~~es~~<br>~~ed~~<br>~~es~~|tPD<br>~~Gs~~<br>~~rs~~<br>~~rs~~|0.47<br>~~Gs ee~~<br>~~rsQs~~<br>~~rs~~<br>~~rs~~|0.54|0.63|ns|
|OR2<br>~~es~~<br>~~es es~~<br>~~es~~|Y = A + B<br>~~ed~~<br>~~es~~<br>~~Rs~~|tPD<br>~~rs~~<br>~~rs~~<br>~~es~~|0.49<br>~~rsQs~~<br>~~rs~~<br>~~rs~~<br>~~es~~<br>~~rs~~|0.55|0.65|ns|
|NOR2<br>~~es es~~<br>~~es~~<br>~~es~~|Y = !(A + B)<br>~~es ~~<br>~~Rs~~<br>~~ed~~|tPD<br> ~~rs~~<br>~~es~~<br>~~rs~~|0.49<br>~~rs~~<br>~~rs~~<br>~~es~~<br>~~rs~~<br>~~rsQs~~|0.55|0.65|ns|
|XOR2<br>~~es~~<br>~~es~~<br>~~es es~~|Y = AB<br>~~Rs~~<br>~~ed~~<br>~~es~~|tPD<br>~~es~~<br>~~rs~~<br>~~rs~~|0.74<br>~~es~~<br>~~rs~~<br>~~rsQs~~<br>~~rs~~<br>~~rs~~|0.84|0.99|ns|
|MAJ3<br>~~es~~<br>~~es es~~<br>~~es~~|Y = MAJ(A, B, C)<br>~~ed~~<br>~~es~~<br>~~Rs~~|tPD<br>~~rs~~<br>~~rs~~<br>~~es~~|0.70<br>~~rsQs~~<br>~~rs~~<br>~~rs~~<br>~~es~~<br>~~rs~~|0.79|0.93|ns|
|XOR3<br>~~es es~~<br>~~es~~<br>~~es~~|Y = ABC<br>~~es ~~<br>~~Rs~~<br>~~ed~~|tPD<br> ~~rs~~<br>~~es~~<br>~~rs~~|0.87<br>~~rs~~<br>~~rs~~<br>~~es~~<br>~~rs~~<br>~~rsQs~~|1.00|1.17|ns|
|MUX2<br>~~es~~<br>~~es~~<br>~~es es~~|Y = A !S + B S<br>~~Rs~~<br>~~ed~~<br>~~es rs~~|tPD<br>~~es~~<br>~~rs~~<br>~~rs~~|0.51<br>~~es~~<br>~~rs~~<br>~~rsQs~~<br>~~rs~~<br>~~rs~~|0.58|0.68|ns|
|AND3<br>~~es~~<br>~~es es~~|Y = A · B · C<br>~~ed~~<br>~~es rs~~|tPD<br>~~rs~~<br>~~rs~~|0.56<br>~~rsQs~~<br>~~rs~~<br>~~rs~~|0.64|0.75|ns|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
## **VersaTile Specifications as a Sequential Module**
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the _Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide_ .
**==> picture [258 x 242] intentionally omitted <==**
**----- Start of picture text -----**<br>
Data Out Data Out<br>D Q D Q<br>En<br>DFN1 DFN1E1<br>CLK CLK<br>PRE<br>Data Out Data Out<br>D Q D Q<br>En<br>DFN1C1 DFI1E1P1<br>CLK CLK<br>CLR<br>**----- End of picture text -----**<br>
_**Figure 2-26 •**_ **Sample of Sequential Cells**
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|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_<br>PRE<br>CLK<br>Data<br>EN<br>tSUE<br>50%<br>50%<br>tSUD<br>tHD<br>50%<br>50%<br>0<br>tHE<br>tRECPRE<br>tREMPRE<br>tRECCLR<br>tREMCLR<br>tWCLR<br>tWPRE<br>tCKMPWHtCKMPWL<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br>50%<br><>} Microsemi~~a~~<br>~~eee~~<br>~~e~~e|_ProASIC3 Flash Family FPGAs_|
|---|---|---|---|---|---|---|---|---|---|
|CLR||50%<br>50%|||||50%|||
|||tPRE2Q<br>tCLR2Q||||||||
|||50%<br>50%<br>50%||||||||
|Out||||||||||
|||tCLKQ||||||||
|||||||||||
|**_Figure 2-27 •_Timing Model and Waveforms**||||||||||
|**_Timing Characteristics_**||||||||||
|**_Table 2-106 •_**|**_Table 2-106 •_Register Delays**|||||||||
|**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**||||||||||
|**Parameter**<br>tCLKQ<br>tSUD<br>tHD<br>tSUE<br>tHE<br>tCLR2Q<br>tPRE2Q<br>tREMCLR<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~|**Description**<br>Clock-to-Q of the Core Register<br>Data Setup Time for the Core Register<br>Data Hold Time for the Core Register<br>Enable Setup Time for the Core Register<br>Enable Hold Time for the Core Register<br>Asynchronous Clear-to-Q of the Core Register<br>Asynchronous Preset-to-Q of the Core Register<br>Asynchronous Clear Removal Time for the Core Register||||**–2**<br>0.55<br>0.43<br>0.00<br>0.45<br>0.00<br>0.40<br>0.40<br>0.00||**–1**<br>0.63<br>0.49<br>0.00<br>0.52<br>0.00<br>0.45<br>0.45<br>0.00|**Std.**<br>0.74<br>0.57<br>0.00<br>0.61<br>0.00<br>0.53<br>0.53<br>0.00|**Units**<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|tRECCLR<br>tREMPRE<br>tRECPRE<br>~~a~~<br>~~ee~~<br>~~a~~|Asynchronous Clear Recovery Time for the Core Register<br>Asynchronous Preset Removal Time for the Core Register<br>Asynchronous Preset Recovery Time for the Core Register||||0.22<br>0.00<br>0.22||0.25<br>0.00<br>0.25|0.30<br>0.00<br>0.30|ns<br>ns<br>ns|
|tWCLR<br>tWPRE<br>tCKMPWH<br>~~a~~<br>~~ee~~<br>~~a~~|Asynchronous Clear Minimum Pulse Width for the Core Register<br>Asynchronous Preset Minimum Pulse Width for the Core Register<br>Clock Minimum Pulse Width High for the Core Register||||0.22<br>0.22<br>0.32||0.25<br>0.25<br>0.37|0.30<br>0.30<br>0.43|ns<br>ns<br>ns|
|tCKMPWL<br>~~a~~|Clock Minimum Pulse Width Low for the Core Register||||0.36||0.41|0.48|ns|
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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## **Global Resource Characteristics**
## **A3P250 Clock Tree Topology**
Clock delays are device-specific. Figure 2-28 is an example of a global tree used for clock routing. The global tree presented in Figure 2-28 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flipflops in the device.
**==> picture [454 x 108] intentionally omitted <==**
**----- Start of picture text -----**<br>
Central<br>Global Rib<br>CCC VersaTile<br>Rows<br>JOC<br>Global Spine<br>**----- End of picture text -----**<br>
_**Figure 2-28 •**_ **Example of Global Tree Use in an A3P250 Device for Clock Routing**
## **Global Tree Timing Characteristics**
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-90. Table 2-108 to Table 2-114 on page 2-89 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading.
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## **Timing Characteristics**
_**Table 2-107 •**_ **A3P015 Global Resource**
**Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [467 x 154] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|–2|–1|Std.|
|Parameter|Description|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Units|
|a eee|
|tRCKL|Input Low Delay for Global Clock|0.66|0.81|0.75|0.92|0.88|1.08|ns|
|a|P||||||
|tRCKH|Input High Delay for Global Clock|0.67|0.84|0.76|0.96|0.89|1.13|ns|
|aesee|es|es|
|tRCKMPWH|Minimum Pulse Width High for Global Clock|0.75|0.85|1.00|ns|
|a esGs|ee|
|tRCKMPWL|Minimum Pulse Width Low for Global Clock|0.85|0.96|1.13|ns|
|a rsGs|
|tRCKSW|Maximum Skew for Global Clock|0.18|0.21|0.25|ns|
|a eseees|Gses|ee|sees|ee|
|Notes:|
|1.|Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,|
|located in a lightly loaded row (single element is connected to the global net).|
**----- End of picture text -----**<br>
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values._
## _**Table 2-108 •**_ **A3P030 Global Resource**
**Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [467 x 155] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|–2|–1|Std.|
|Parameter|Description|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Units|
|eeee|ee|
|tRCKL|Input Low Delay for Global Clock|0.67|0.81|0.76|0.92|0.89|1.09|ns|
|a|Pot|ft|tT|
|tRCKH|Input High Delay for Global Clock|0.68|0.85|0.77|0.97|0.91|1.14|ns|
|a|eeee|ee|es|ee|
|tRCKMPWH|Minimum Pulse Width High for Global Clock|0.75|0.85|1.00|ns|
|a eeee|es es ee|ee|
|tRCKMPWL|Minimum Pulse Width Low for Global Clock|0.85|0.96|1.13|ns|
|a esee|es|es|es|
|tRCKSW|Maximum Skew for Global Clock|0.18|0.21|0.24|ns|
|a eseses|eses|eees|eses|
|Notes:|
|1.|Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,|
|located in a lightly loaded row (single element is connected to the global net).|
**----- End of picture text -----**<br>
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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_**Table 2-109 •**_ **A3P060 Global Resource**
|**Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**|
|---|
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std.**<br>**Units**<br>**Min.1 Max.2 Min.1 Max.2 Min.1 Max.2**<br>tRCKL<br>Input Low Delay for Global Clock<br>0.71<br>0.93<br>0.81<br>1.05<br>0.95<br>1.24<br>ns<br>tRCKH<br>Input High Delay for Global Clock<br>0.70<br>0.96<br>0.80<br>1.09<br>0.94<br>1.28<br>ns<br>tRCKMPWH<br>Minimum Pulse Width High for Global Clock<br>0.75<br>0.85<br>1.00<br>ns<br>tRCKMPWL<br>Minimum Pulse Width Low for Global Clock<br>0.85<br>0.96<br>1.13<br>ns<br>tRCKSW<br>Maximum Skew for Global Clock<br>0.26<br>0.29<br>0.34<br>ns<br>~~2~~<br>~~Pot~~ ~~fT~~<br>~~a es~~<br>~~es es ee~~<br>~~a es~~<br>~~es es es~~<br>~~a es~~<br>~~Gs~~<br>~~a~~<br>~~**e**s~~ eee ~~ee ee~~<br>~~a~~<br>~~e eee eee ee es es ee~~|
|_Notes:_|
|_1._<br>_Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,_|
|_located in a lightly loaded row (single element is connected to the global net)._|
|_2._<br>_Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully_|
|_loaded row (all available flip-flops are connected to the global net in the row)._|
|_3._<br>_For specific junction temperature and voltage supply levels, refer toTable 2-6 on page 2-6 for derating values._|
|**_Table 2-110 •_A3P125 Global Resource**|
|**Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**|
|**Parameter**<br>**Description**<br>**–2**<br>**–1**<br>**Std.**<br>**Units**<br>**Min.1 Max.2 Min.1 Max.2 Min.1 Max.2**<br>tRCKL<br>Input Low Delay for Global Clock<br>0.77<br>0.99<br>0.87<br>1.12<br>1.03<br>1.32<br>ns<br>tRCKH<br>Input High Delay for Global Clock<br>0.76<br>1.02<br>0.87<br>1.16<br>1.02<br>1.37<br>ns<br>tRCKMPWH<br>Minimum Pulse Width High for Global Clock<br>0.75<br>0.85<br>1.00<br>ns<br>tRCKMPWL<br>Minimum Pulse Width Low for Global Clock<br>0.85<br>0.96<br>1.13<br>ns<br>tRCKSW<br>Maximum Skew for Global Clock<br>0.26<br>0.29<br>0.34<br>ns<br>~~oe~~<br>~~Pot~~ ~~ft~~<br>~~a~~<br>~~es~~ eee ~~ee ee~~<br>~~a~~<br>~~ee~~ eee ~~ee ee~~<br>~~a~~<br>~~es es es es ee~~<br>~~a es~~<br>~~es es se~~<br>~~a~~<br>~~rs es~~<br>~~se~~|
|_Notes:_|
|_1._<br>_Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,_|
|_located in a lightly loaded row (single element is connected to the global net)._|
## _**Table 2-110 •**_ **A3P125 Global Resource**
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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**==> picture [467 x 171] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Power|Matters.”|
|Table 2-111 •|A3P250 Global Resource|
|Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V|
|–2|–1|Std.|
|Parameter|Description|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Units|
|oe|
|tRCKL|Input Low Delay for Global Clock|0.80|1.01|0.91|1.15|1.07|1.36|ns|
|a esPot|||
|tRCKH|Input High Delay for Global Clock|0.78|1.04|0.89|1.18|1.04|1.39|ns|
|a|Gs|es|
|tRCKMPWH|Minimum Pulse Width High for Global Clock|0.75|0.85|1.00|ns|
|a errs|es|Gs|es|es|
|tRCKMPWL|Minimum Pulse Width Low for Global Clock|0.85|0.96|1.13|ns|
|a|eeGs|es|
|tRCKSW|Maximum Skew for Global Clock|0.26|0.29|0.34|ns|
|ee|ee|ee|eeees|ee|s|ee|ee|ee|
**----- End of picture text -----**<br>
_**Table 2-111 •**_ **A3P250 Global Resource**
## _Notes:_
_1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net)._
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
## _**Table 2-112 •**_ **A3P400 Global Resource**
**Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [468 x 123] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|–2|–1|Std.|
|Parameter|Description|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Units|
|oe|
|tRCKL|Input Low Delay for Global Clock|0.87|1.09|0.99|1.24|1.17|1.46|ns|
|a|Pot|ft|
|tRCKH|Input High Delay for Global Clock|0.86|1.11|0.98|1.27|1.15|1.49|ns|
|a|es|eee|ee ee|
|tRCKMPWH|Minimum Pulse Width High for Global Clock|0.75|0.85|1.00|ns|
|a|ee|eee|ee|ee|
|tRCKMPWL|Minimum Pulse Width Low for Global Clock|0.85|0.96|1.13|ns|
|a eses|es|es|es|ee|
|tRCKSW|Maximum Skew for Global Clock|0.26|0.29|0.34|ns|
|a|es|es se|
|rs|es|se|
**----- End of picture text -----**<br>
## _Notes:_
_1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net)._
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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_**Table 2-113 •**_ **A3P600 Global Resource**
**==> picture [468 x 136] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V|
|–2|–1|Std.|
|Parameter|Description|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Units|
|ee|
|tRCKL|Input Low Delay for Global Clock|0.87|1.09|0.99|1.24|1.17|1.46|ns|
|a eePot|||
|tRCKH|Input High Delay for Global Clock|0.86|1.11|0.98|1.27|1.15|1.49|ns|
|a esre|ee|
|tRCKMPWH|Minimum Pulse Width High for Global Clock|0.75|0.85|1.00|ns|
|a|es|ee|ee|
|tRCKMPWL|Minimum Pulse Width Low for Global Clock|0.85|0.96|1.13|ns|
|a esrs|es|
|tRCKSW|Maximum Skew for Global Clock|0.26|0.29|0.34|ns|
|a|res|ee|es|es|es|ee|
|es|eres|eee|ee|es|es|ee|
**----- End of picture text -----**<br>
## _Notes:_
_1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net)._
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
## _**Table 2-114 •**_ **A3P1000 Global Resource**
**Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [470 x 154] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|–2|–1|Std.|
|Parameter|Description|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Min.|[1]|Max.|[2]|Units|
|oePot|
|tRCKL|Input Low Delay for Global Clock|0.94|1.16|1.07|1.32|1.26|1.55|ns|
|a ee|
|tRCKH|Input High Delay for Global Clock|0.93|1.19|1.06|1.35|1.24|1.59|ns|
|a|eees|ee|ee|
|tRCKMPWH|Minimum Pulse Width High for Global Clock|0.75|0.85|1.00|ns|
|a|ee|es ee|ee|
|tRCKMPWL|Minimum Pulse Width Low for Global Clock|0.85|0.96|1.13|ns|
|a esrs|es|es|ee|
|tRCKSW|Maximum Skew for Global Clock|0.26|0.29|0.35|ns|
|ee|
|es|es|e|s|eee|
|Notes:|
|1.|Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,|
|located in a lightly loaded row (single element is connected to the global net).|
**----- End of picture text -----**<br>
_2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row)._
_3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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## **Clock Conditioning Circuits**
## **CCC Electrical Specifications**
## _**Timing Characteristics**_
|**_Table 2-115 •_ProASIC3 CCC/PLL Specification**|||||
|---|---|---|---|---|
|**Parameter**<br>~~rs~~|**Minimum**<br>~~rs~~|**Typical**<br>~~rs~~|**Maximum**<br>~~rs~~|**Units**<br>~~rs~~|
|Clock Conditioning Circuitry Input Frequency fIN_CCC<br>~~es~~|1.5<br>~~es~~|~~es~~|350<br>~~es~~|MHz<br>~~es~~|
|Clock Conditioning Circuitry Output Frequency fOUT_CCC<br>~~rs~~|0.75<br>~~rs~~|~~rs~~|350<br>~~rs~~|MHz<br>~~rs~~|
|Serial Clock (SCLK) for Dynamic PLL1<br>~~rs~~|~~rs~~|~~rs~~|125<br>~~rs~~|MHz<br>~~rs~~|
|Delay Increments in Programmable Delay Blocks2, 3|~~ee~~|2004<br>~~ee~~|~~ee~~|ps<br>~~ee~~|
|Number of Programmable Values in Each Programmable<br>Delay Block<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|32<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|
|Input Period Jitter<br>~~rs~~<br>~~Ce~~|~~ee ~~<br>~~rs~~|~~ee~~<br>~~rs~~|1.5<br>~~ee~~<br>~~rs~~|ns<br>~~ee~~<br>~~rs~~|
|CCC Output Peak-to-Peak Period Jitter FCCC_OUT<br>~~Ce~~|Max Peak-to-Peak Period Jitter||||
||1 Global<br>Network<br>Used||3 Global<br>Networks<br>Used||
|0.75 MHz to 24 MHz<br>~~Ce~~<br>~~es~~|0.50%<br>~~es~~|~~es~~|0.70%<br>~~es~~|~~es~~|
|24 MHz to 100 MHz<br>~~es~~|1.00%<br>~~es~~|~~es~~|1.20%<br>~~es~~|~~es~~|
|100 MHz to 250 MHz<br>~~es~~|1.75%<br>~~es~~|~~es~~|2.00%<br>~~es~~|~~es~~|
|250 MHz to 350 MHz<br>~~es~~|2.50%<br>~~es~~|~~es~~|5.60%<br>~~es~~|~~es~~|
|Acquisition Time<br>~~es~~|~~es~~|~~es~~|~~es~~|~~es~~|
|(A3P250 and A3P1000 only)<br>LockControl = 0<br>~~es~~|~~es~~|~~es~~|300<br>~~es~~|µs<br>~~es~~|
|LockControl = 1<br>~~es~~|~~es~~|~~es~~|300<br>~~es~~|µs<br>~~es~~|
|(all other dies)<br>LockControl = 0<br>~~es~~|~~es~~|~~es~~|300<br>~~es~~|µs<br>~~es~~|
|LockControl = 1<br>~~es~~|~~es~~|~~es~~|6.0<br>~~es~~|ms<br>~~es~~|
|Tracking Jitter 5<br>~~es~~|~~es~~|~~es~~|~~es~~|~~es~~|
|(A3P250 and A3P1000 only)<br>LockControl = 0<br>~~es~~|~~es~~|~~es~~|1.6<br>~~es~~|ns<br>~~es~~|
|LockControl = 1<br>~~es~~|~~es~~|~~es~~|1.6<br>~~es~~|ns<br>~~es~~|
|(all other dies)<br>LockControl = 0<br>~~es~~|~~es~~|~~es~~|1.6<br>~~es~~|ns<br>~~es~~|
|LockControl = 1<br>~~es~~|~~es~~|~~es~~|0.8<br>~~es~~|ns<br>~~es~~|
|Output Duty Cycle<br>~~es~~|48.5<br>~~es~~|~~es~~|51.5<br>~~es~~|%<br>~~es~~|
|Delay Range in Block: Programmable Delay 12, 3<br>~~es~~|0.6<br>~~es~~|~~es~~|5.56<br>~~es~~|ns<br>~~es~~|
|Delay Range in Block: Programmable Delay 22, 3<br>~~es~~|0.225<br>~~es~~<br>~~rn~~|~~es~~|5.56<br>~~es~~|ns<br>~~es~~|
|Delay Range in Block: Fixed Delay2, 3<br>~~ns~~|~~ns~~<br>~~rn~~|2.2<br>~~ns~~|~~ns~~|ns<br>~~ns~~|
_Notes:_
_1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
_2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings._
_3. TJ = 25°C, VCC = 1.5 V_
_4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information._
_5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter._
_6. The A3P030 device does not contain a PLL._
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**----- Start of picture text -----**<br>
Output Signal<br>T T<br>period_max period_min<br>**----- End of picture text -----**<br>
_Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min._ _**Figure 2-29 •**_ **Peak-to-Peak Jitter Definition**
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## **Embedded SRAM and FIFO Characteristics**
## **SRAM**
**==> picture [243 x 439] intentionally omitted <==**
**----- Start of picture text -----**<br>
RAM4K9 RAM512X18<br>ADDRA11 DOUTA8 RADDR8 RD17<br>ADDRA10 DOUTA7 RADDR7 RD16<br>ADDRA0 DOUTA0 RADDR0 RD0<br>DINA8<br>DINA7<br>DINA0 RW1<br>RW0<br>WIDTHA1<br>WIDTHA0<br>PIPE<br>PIPEA<br>WMODEA<br>BLKA<br>REN<br>WENA<br>RCLK<br>CLKA<br>- 7<br>ADDRB11 DOUTB8 WADDR8<br>ADDRB10 DOUTB7 WADDR7<br>ADDRB0 DOUTB0<br>WADDR0<br>WD17<br>WD16<br>DINB8<br>DINB7<br>WD0<br>DINB0<br>WW1<br>WIDTHB1 WW0<br>WIDTHB0<br>PIPEB<br>WMODEB<br>BLKB<br>WEN<br>WENB<br>CLKB WCLK<br>RESET RESET<br>:- :-<br>**----- End of picture text -----**<br>
_**Figure 2-30 •**_ **RAM Models**
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## _**Timing Waveforms**_
**==> picture [404 x 500] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>[R|W]ADDR A0 A1 A2<br>tBKS<br>tBKH<br>BLK<br>elec mca<br>tENS tENH<br>ee ee<br>WEN<br>t<br>CKQ1<br>DOUT|RD Dn D0 D1 D2<br>Lone home<br>tDOH1<br>Figure 2-31 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.<br>tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>[R|W]ADDR A0 A1 A2<br>tBKS<br>tBKH<br>BLK<br>ee<br>tENS tENH<br>— = |<br>WEN<br>t<br>CKQ2<br>DOUT|RD Dn D0 D1<br>_ tat<br>tDOH2<br>**----- End of picture text -----**<br>
_**Figure 2-31 •**_ **RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.**
_**Figure 2-32 •**_ **RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.**
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**==> picture [412 x 561] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>[R|W]ADDR A0 A1 A2<br>tBKS<br>tBKH<br>BLK Sia m Samc oa<br>tENS tENH<br>WEN<br>tDS tDH<br>DIN|RD ener DI0 DI1 ee<br>DOUT|RD E—EEKEKEK Dn D2<br>Figure 2-33 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.<br>tCYC<br>tCKH tCKL<br>CLK<br>tAS tAH<br>ADDR A0 A1 A2<br>q o e e eee<br>tBKS<br>tBKH<br>BLK<br>tENS<br>WEN ——<br>tDS tDH<br>DIN a DI0 ose DI1 See DI2 oe<br>DOUT<br>KOR Dn DI0 DI1<br>(pass-through)<br>DOUT<br>(pipelined) >. Dn ..0.> Ga DI0 0.0. Gin DI1<br>**----- End of picture text -----**<br>
_**Figure 2-33 •**_ **RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.**
_**Figure 2-34 •**_ **RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.**
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**==> picture [303 x 122] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCYC<br>tCKH tCKL<br>CLK<br>RESET<br>t<br>RSTBQ<br>DOUT|RD Dm Dn<br>**----- End of picture text -----**<br>
_**Figure 2-35 •**_ **RAM Reset. Applicable to Both RAM4K9 and RAM512x18.**
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## _**Timing Characteristics**_
_**Table 2-116 •**_ **RAM4K9**
||**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**|||||
|---|---|---|---|---|---|
|**Parameter**<br>~~a~~|**Description**|**–2**|**–1**|**Std.**|**Units**|
|tAS<br>~~a~~|Address setup time|0.25|0.28|0.33|ns|
|tAH<br>~~a~~|Address hold time|0.00|0.00|0.00|ns|
|tENS<br>~~a~~|REN, WEN setup time|0.14|0.16|0.19|ns|
|tENH<br>~~a~~|REN, WEN hold time|0.10|0.11|0.13|ns|
|tBKS<br>~~a~~|BLK setup time|0.23|0.27|0.31|ns|
|tBKH<br>~~a~~|BLK hold time|0.02|0.02|0.02|ns|
|tDS<br>~~a~~|Input data (DIN) setup time|0.18|0.21|0.25|ns|
|tDH<br>~~a~~|Input data (DIN) hold time<br>|0.00<br>|0.00<br>|0.00<br>|ns<br>|
|tCKQ1<br>~~Se~~|Clock High to new data valid on DOUT (output retained, WMODE = 0)<br>~~Se~~|2.36<br>~~Se~~|2.68<br>~~Se~~|3.15<br>~~Se~~|ns<br>~~Se~~|
||Clock High to new data valid on DOUT (flow-through, WMODE = 1)<br>~~Se~~<br>~~a~~|1.79<br>~~Se~~<br>~~a~~|2.03<br>~~Se~~<br>~~a~~|2.39<br>~~Se~~<br>~~a~~|ns<br>~~Se~~<br>~~a~~|
|tCKQ2|Clock High to new data valid on DOUT (pipelined)|0.89|1.02|1.20|ns|
|tC2CWWL<br>1|Address collision clk-to-clk delay for reliable write after write on same<br>address—Applicable to Closing Edge|0.33|0.28|0.25|ns|
|tC2CWWH<br>1|Address collision clk-to-clk delay for reliable write after write on same<br>address—Applicable to Rising Edge|0.30|0.26|0.23|ns|
|tC2CRWH<br>1|Address collision clk-to-clk delay for reliable read access after write on same<br>address—Applicable to Opening Edge|0.45|0.38|0.34|ns|
|tC2CWRH<br>1|Address collision clk-to-clk delay for reliable write access after read on same<br>address— Applicable to Opening Edge|0.49|0.42|0.37|ns|
|tRSTBQ<br>~~Se~~|RESET Low to data out Low on DOUT (flow-through)<br>~~Se~~|0.92<br>~~Se~~|1.05<br>~~Se~~|1.23<br>~~Se~~|ns<br>~~Se~~|
||RESET Low to Data Out Low on DOUT (pipelined)<br>~~Se~~<br>~~a~~|0.92<br>~~Se~~<br>~~a~~|1.05<br>~~Se~~<br>~~a~~|1.23<br>~~Se~~<br>~~a~~|ns<br>~~Se~~<br>~~a~~|
|tREMRSTB<br>~~a~~|RESET removal|0.29|0.33|0.38|ns|
|tRECRSTB<br>~~a~~|RESET recovery<br>~~Ge~~|1.50<br>~~Ge~~|1.71<br>~~Ge~~|2.01<br>~~Ge~~|ns<br>~~Ge~~|
|tMPWRSTB<br>~~a~~|RESET minimum pulse width|0.21|0.24|0.29|ns|
|tCYC<br>~~a~~|Clock cycle time|3.23|3.68|4.32|ns|
|FMAX<br>~~a~~|Maximum frequency|310|272|231|MHz|
_Notes:_
_1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs._
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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_**Table 2-117 •**_ **RAM512X18**
|**Parameter**<br>~~ee~~<br>~~ee~~|**Description**<br>~~ee~~<br>|**–2**<br>~~ee~~<br>~~G~~~~**e**~~<br><br>~~ts~~|**–1**<br>~~ee~~<br>~~G~~~~**s**~~<br><br>~~t~~|**Std.**<br>~~ee~~<br>~~e~~~~**s**~~<br><br>~~G~~|**Units**<br>~~ee~~<br><br>~~Ge~~|
|---|---|---|---|---|---|
|tAS<br>~~ee~~<br>~~ee~~|Address setup time<br>~~ee~~<br>~~rs~~|0.25<br>~~ee~~<br>~~G~~~~**e**~~<br>~~rs~~<br>~~ts~~<br>~~tts~~|0.28<br>~~ee~~<br>~~G~~~~**s**~~<br>~~rs~~<br>~~t~~<br>~~ts~~|0.33<br>~~ee~~<br>~~e~~~~**s**~~<br>~~rs~~<br>~~G~~<br>~~Gs~~|ns<br>~~ee~~<br>~~rs~~<br>~~Ge~~<br>~~Ge~~|
|tAH<br>~~ee~~<br>~~es~~<br>~~a~~|Address hold time<br><br>~~es~~<br>|0.00<br>~~G~~~~**e** ~~<br><br>~~t s ~~<br>~~es~~<br>~~tts~~<br>Gttits<br>|0.00<br> ~~G~~~~**s** ~~<br><br> ~~t ~~<br>~~es~~<br>~~ts~~<br>~~tts Gs~~<br>|0.00<br> ~~e~~~~**s**~~<br><br> ~~G ~~<br>~~es~~<br>~~Gs~~<br>~~Gs~~<br>|ns<br><br> ~~Ge~~<br>~~es~~<br>~~Ge~~<br>|
|tENS<br>~~es~~<br>~~a~~<br>~~ee~~|REN, WEN setup time<br>~~es~~<br><br>|0.13<br>~~tts ~~<br>~~es~~<br>Gttits<br><br>~~Gs~~<br>|0.15<br> ~~ts ~~<br>~~es~~<br>~~tts Gs~~<br><br>~~ts~~<br>|0.17<br> ~~Gs ~~<br>~~es~~<br>~~Gs~~<br><br>~~ts~~<br>|ns<br> ~~Ge~~<br>~~es~~<br><br>|
|tENH<br>~~a ee~~<br>~~ee~~<br>~~ee~~|REN, WEN hold time<br>~~ee~~<br><br>|0.10<br>Gttits <br>~~ee~~<br>~~Gs~~<br><br>~~Gs~~<br>|0.11<br> ~~tts Gs~~<br>~~ee~~<br>~~ts~~<br><br>~~tes~~<br>|0.13<br>~~Gs~~<br>~~ee~~<br>~~ts~~<br><br>~~Gs~~<br>|ns<br>~~ee~~<br><br>|
|tDS<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input data (WD) setup time<br>~~es~~<br><br>|0.18<br>~~Gs~~<br>~~es~~<br>~~Gs~~<br><br>~~Ge~~<br>|0.21<br>~~ts~~<br>~~es~~<br>~~tes~~<br><br>~~es~~<br>|0.25<br>~~ts~~<br>~~es~~<br>~~Gs~~<br><br>~~es~~<br>|ns<br>~~es~~<br><br>|
|tDH<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Le~~|Input data (WD) hold time<br><br>~~ee~~<br>|0.00<br>~~Gs ~~<br><br>~~Gs~~<br>~~ee~~<br>~~Ge~~<br><br>~~Gt~~|0.00<br> ~~ts ~~<br><br>~~tes~~<br>~~ee~~<br>~~es~~<br><br>~~es~~|0.00<br> ~~ts~~<br><br>~~Gs~~<br>~~ee~~<br>~~es~~<br><br>~~es~~|ns<br><br>~~ee~~<br>|
|tCKQ1<br>~~ee~~<br>~~ee~~<br>~~Le~~|Clock High to new data valid on RD (output retained)<br><br>~~ee~~|2.16<br>~~Gs ~~<br><br>~~Ge~~<br>~~ee~~<br>~~Gt~~|2.46<br> ~~tes ~~<br><br>~~es~~<br>~~ee~~<br>~~es~~|2.89<br> ~~Gs~~<br><br>~~es~~<br>~~ee~~<br>~~es~~|ns<br><br>~~ee~~|
|tCKQ2<br>~~ee~~<br>~~Le~~|Clock High to new data valid on RD (pipelined)<br>|0.90<br>~~Ge ~~<br><br>~~Gt~~|1.02<br> ~~es ~~<br><br>~~es~~|1.20<br> ~~es~~<br><br>~~es~~|ns<br>|
|tC2CRWH<br>1<br>~~Le~~|Address collision clk-to-clk delay for reliable read access after write on same<br>address—Applicable to Opening Edge|0.50<br>~~Gt~~|0.43<br>~~es~~|0.38<br>~~es~~|ns|
|tC2CWRH<br>1<br>~~Le~~<br>~~——————eee~~|Address collision clk-to-clk delay for reliable write access after read on same<br>address—Applicable to Opening Edge<br>~~——————eee~~|0.59<br>~~Gt ~~<br>~~——————eee~~|0.50<br> ~~es ~~<br>~~——————eee~~|0.44<br> ~~es~~<br>~~——————eee~~|ns<br>~~——————eee~~|
|tRSTBQ<br>~~——————eee~~<br>~~a~~<br>~~a~~|RESET Low to data out Low on RD (flow-through)<br>~~——————eee~~<br>|0.92<br>~~——————eee~~<br>~~Gt~~<br>|1.05<br>~~——————eee~~<br>~~Ge~~<br>|1.23<br>~~——————eee~~<br>~~ee~~<br>|ns<br>~~——————eee~~<br>|
||RESET Low to data out Low on RD (pipelined)<br>~~——————eee~~<br>~~rn~~<br><br>|0.92<br>~~——————eee~~<br>~~rn~~<br>~~Gt~~<br><br>Gti<br>|1.05<br>~~——————eee~~<br>~~rn~~<br>~~Ge~~<br><br>~~tts Gs~~<br>|1.23<br>~~——————eee~~<br>~~rn~~<br>~~ee~~<br><br>~~Gs~~<br>|ns<br>~~——————eee~~<br>~~rn~~<br><br>|
|tREMRSTB<br>~~——————eee~~<br>~~a re~~<br>~~a~~<br>~~ee~~|RESET removal<br>~~——————eee~~<br>~~re~~<br><br>|0.29<br>~~——————eee~~<br>~~Gt ~~<br>~~re~~<br>Gti<br><br>~~Gs~~<br>|0.33<br>~~——————eee~~<br> ~~Ge~~ <br>~~re~~<br>~~tts Gs~~<br><br>~~ts~~<br>|0.38<br>~~——————eee~~<br> ~~ee~~<br>~~re~~<br>~~Gs~~<br><br>~~ts~~<br>|ns<br>~~——————eee~~<br>~~re~~<br><br>|
|tRECRSTB<br>~~a ee~~<br>~~ee~~<br>~~ee~~|RESET recovery<br>~~ee~~<br><br>|1.50<br>Gti <br>~~ee~~<br>~~Gs~~<br><br>~~Gs~~<br>|1.71<br> ~~tts Gs~~<br>~~ee~~<br>~~ts~~<br><br>~~tes~~<br>|2.01<br>~~Gs~~<br>~~ee~~<br>~~ts~~<br><br>~~Gs~~<br>|ns<br>~~ee~~<br><br>|
|tMPWRSTB<br>~~ee~~<br>~~ee~~<br>~~ee~~|RESET minimum pulse width<br>~~es~~<br><br>|0.21<br>~~Gs~~<br>~~es~~<br>~~Gs~~<br><br>~~**G**e~~<br>|0.24<br>~~ts~~<br>~~es~~<br>~~tes~~<br><br>~~**es**~~<br>|0.29<br>~~ts~~<br>~~es~~<br>~~Gs~~<br><br>~~**es**~~<br>|ns<br>~~es~~<br><br>|
|tCYC<br>~~ee~~<br>~~ee~~<br>~~ee~~|Clock cycle time<br><br>~~ee~~<br>|3.23<br>~~Gs ~~<br><br>~~Gs~~<br>~~ee~~<br>~~**G**e~~<br><br>~~t~~|3.68<br> ~~ts ~~<br><br>~~tes~~<br>~~ee~~<br>~~**es**~~<br>|4.32<br> ~~ts~~<br><br>~~Gs~~<br>~~ee~~<br>~~**es**~~<br>|ns<br><br>~~ee~~<br>|
|FMAX<br>~~ee~~<br>~~ee~~|Maximum frequency<br><br>~~es~~|310<br>~~Gs ~~<br><br>~~**G**e~~<br>~~es~~<br>~~t~~|272<br> ~~tes ~~<br><br>~~**es**~~<br>~~es~~|231<br> ~~Gs~~<br><br>~~**es**~~<br>~~es~~|MHz<br><br>~~es~~|
_2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
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_ProASIC3 Flash Family FPGAs_
## **FIFO**
**==> picture [113 x 434] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIFO4K18<br>RW2 RD17<br>RW1 RD16<br>RW0<br>WW2<br>WW1<br>WW0 RD0<br>ESTOP<br>FSTOP FULL<br> AFULL<br>EMPTY<br>AEVAL11<br>AEMPTY<br>AEVAL10<br>AEVAL0<br>AFVAL11<br>AFVAL10<br>AFVAL0<br>REN<br>RBLK<br>RCLK<br>WD17<br>WD16<br>WD0<br>WEN<br>WBLK<br>WCLK<br>RPIPE<br>RESET<br>**----- End of picture text -----**<br>
_**Figure 2-36 •**_ **FIFO Model**
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_ProASIC3 DC and Switching Characteristics_
## _**Timing Waveforms**_
**==> picture [459 x 501] intentionally omitted <==**
**----- Start of picture text -----**<br>
t<br>CYC<br>RCLK<br>tENS tENH<br>REN<br>tBKS tBKH<br>RBLK<br>t<br>CKQ1<br>(flow-through)RD Dn D0 D1 D2<br>t<br>CKQ2<br>(pipelined)RD Dn K KK D0 D1<br>Figure 2-37 • FIFO Read<br>t<br>CYC<br>WCLK<br>tENS tENH<br>WEN<br>tBKS tBKH<br>WBLK<br>tDS tDH<br>WD S DI0 O DI1 KOODOC OOK KKK KX<br>**----- End of picture text -----**<br>
_**Figure 2-37 •**_ **FIFO Read**
_**Figure 2-38 •**_ **FIFO Write**
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_ProASIC3 Flash Family FPGAs_
**==> picture [359 x 263] intentionally omitted <==**
**----- Start of picture text -----**<br>
RCLK/<br>WCLK<br>tMPWRSTB tRSTCK<br>RESET<br>tRSTFG<br>EMPTY POOKY<br>tRSTAF<br>AEMPTY POOQOQOOOOOOF<br>tRSTFG<br>FULL POOQKOOO'W.<br>tRSTAF<br>AFULL POQOOOOOOKXDOO'®N<br>WA/RA<br>(Address Counter) MATCH (A0)<br>**----- End of picture text -----**<br>
_**Figure 2-39 •**_ **FIFO Reset**
**==> picture [461 x 193] intentionally omitted <==**
**----- Start of picture text -----**<br>
t<br>CYC<br>RCLK<br>t<br>RCKEF<br>EMPTY<br>t<br>CKAF<br>AEMPTY<br>WA/RA<br>NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)<br>(Address Counter) >GeGe Ge<br>**----- End of picture text -----**<br>
_**Figure 2-40 •**_ **FIFO EMPTY Flag and AEMPTY Flag Assertion**
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**==> picture [458 x 349] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCYC<br>WCLK<br>tWCKFF<br>FULL<br>tCKAF<br>AFULL<br>(Address Counter)WA/RA KKK NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)<br>Figure 2-41 • FIFO FULL Flag and AFULL Flag Assertion<br>WCLK<br>WA/RA MATCH NO MATCH NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1<br>(Address Counter) (EMPTY)<br>Sr a Ga ee,<br>1st Rising 2nd Rising<br>Edge Edge<br>After 1st After 1st<br>RCLK Write a Write<br>tRCKEF<br>EMPTY<br>tCKAF<br>—<br>AEMPTY<br>**----- End of picture text -----**<br>
_**Figure 2-41 •**_ **FIFO FULL Flag and AFULL Flag Assertion**
_**Figure 2-42 •**_ **FIFO EMPTY Flag and AEMPTY Flag Deassertion**
**==> picture [468 x 132] intentionally omitted <==**
**----- Start of picture text -----**<br>
RCLK<br>WA/RA<br>MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH Dist = AFF_TH – 1<br>(Address Counter) Ce KKK dD<br>1st Rising 1st Rising<br>Edge Edge<br>After 1st After 2nd<br>WCLK Read Read<br>tWCKF<br>FULL<br>ax Y S<br>tCKAF<br>AFULL<br>**----- End of picture text -----**<br>
_**Figure 2-43 •**_ **FIFO FULL Flag and AFULL Flag Deassertion**
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_ProASIC3 Flash Family FPGAs_
## _**Timing Characteristics**_
_**Table 2-118 •**_ **FIFO (for all dies except A3P250)**
**Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [467 x 357] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|aee|
|tENS|REN, WEN Setup Time|1.34|1.52|1.79|ns|
|a|
|tENH|REN, WEN Hold Time|0.00|0.00|0.00|ns|
|a|ee|
|tBKS|BLK Setup Time|0.19|0.22|0.26|ns|
|ee|
|ee|ss|ee|
|tBKH|BLK Hold Time|0.00|0.00|0.00|ns|
|a eees|ee|ee|
|tDS|Input Data (WD) Setup Time|0.18|0.21|0.25|ns|
|a|es|se|
|tDH|Input Data (WD) Hold Time|0.00|0.00|0.00|ns|
|ee es|
|tCKQ1|Clock High to New Data Valid on RD (flow-through)|2.17|2.47|2.90|ns|
|esee|
|tCKQ2|Clock High to New Data Valid on RD (pipelined)|0.94|1.07|1.26|ns|
|a|ee|
|tRCKEF|RCLK High to Empty Flag Valid|1.72|1.96|2.30|ns|
|ee|
|ee|ss|ee|
|tWCKFF|WCLK High to Full Flag Valid|1.63|1.86|2.18|ns|
|a|eees|ee|ee|
|tCKAF|Clock High to Almost Empty/Full Flag Valid|6.19|7.05|8.29|ns|
|a|es|es|ee|
|tRSTFG|RESET Low to Empty/Full Flag Valid|1.69|1.93|2.27|ns|
|a|ee|
|tRSTAF|RESET Low to Almost Empty/Full Flag Valid|6.13|6.98|8.20|ns|
|esee|
|tRSTBQ|RESET Low to Data Out Low on RD (flow-through)|0.92|1.05|1.23|ns|
|RESET Low to Data Out Low on RD (pipelined)|0.92|1.05|1.23|ns|
|eees|
|tREMRSTB|RESET Removal|0.29|0.33|0.38|ns|
|a eeee ee|ee|
|tRECRSTB|RESET Recovery|1.50|1.71|2.01|ns|
|es|
|ee|es|se|
|tMPWRSTB|RESET Minimum Pulse Width|0.21|0.24|0.29|ns|
|a|ee|
|tCYC|Clock Cycle Time|3.23|3.68|4.32|ns|
|esee|
|FMAX|Maximum Frequency for FIFO|310|272|231|MHz|
|a a|
**----- End of picture text -----**<br>
_Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values._
**Revision 18**
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_ProASIC3 DC and Switching Characteristics_
_**Table 2-119 •**_ **FIFO (for A3P250 only, aspect-ratio-dependent)**
**Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [468 x 358] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|a es|
|tENS|REN, WEN Setup Time|3.26|3.71|4.36|ns|
|a|eses|es|
|tENH|REN, WEN Hold Time|0.00|0.00|0.00|ns|
|a|OG|
|tBKS|BLK Setup Time|0.19|0.22|0.26|ns|
|a|eG|
|tBKH|BLK Hold Time|0.00|0.00|0.00|ns|
|es|
|tDS|Input Data (WD) Setup Time|0.18|0.21|0.25|ns|
|a|ee|
|tDH|Input Data (WD) Hold Time|0.00|0.00|0.00|ns|
|ee|
|ee|es|es|ee|
|tCKQ1|Clock High to New Data Valid on RD (flow-through)|2.17|2.47|2.90|ns|
|a|eses ee|ee|
|tCKQ2|Clock High to New Data Valid on RD (pipelined)|0.94|1.07|1.26|ns|
|a|OGss|ee|
|tRCKEF|RCLK High to Empty Flag Valid|1.72|1.96|2.30|ns|
|a|eG|
|tWCKFF|WCLK High to Full Flag Valid|1.63|1.86|2.18|ns|
|es|
|tCKAF|Clock High to Almost Empty/Full Flag Valid|6.19|7.05|8.29|ns|
|a|ee|
|tRSTFG|RESET Low to Empty/Full Flag Valid|1.69|1.93|2.27|ns|
|ee|
|ee|es|es|ee|
|tRSTAF|RESET Low to Almost Empty/Full Flag Valid|6.13|6.98|8.20|ns|
|a aeses eees|ee|
|tRSTBQ|RESET Low to Data Out Low on RD (flow-through)|0.92|1.05|1.23|ns|
|RESET Low to Data Out Low on RD (pipelined)|0.92|1.05|1.23|ns|
|Sa|
|tREMRSTB|RESET Removal|0.29|0.33|0.38|ns|
|eses|
|tRECRSTB|RESET Recovery|1.50|1.71|2.01|ns|
|a|ee|
|tMPWRSTB|RESET Minimum Pulse Width|0.21|0.24|0.29|ns|
|ee|
|ee|es|es|ee|
|tCYC|Clock Cycle Time|3.23|3.68|4.32|ns|
|a|eses ee|ee|
|FMAX|Maximum Frequency for FIFO|310|272|231|MHz|
|a|eGss|ee|
**----- End of picture text -----**<br>
**2-103**
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_ProASIC3 Flash Family FPGAs_
_**Table 2-120 •**_ **A3P250 FIFO 512×8**
|~~ae~~||~~es~~<br>|~~es~~<br>|~~ee~~<br>||
|---|---|---|---|---|---|
|**Parameter**<br>~~a ~~<br>~~ae~~|**Description**<br> ~~ee~~<br>|**–2**<br>~~ee~~<br>~~es~~<br>|**–1**<br>~~ee~~<br>~~es~~<br>|**Std.**<br>~~ee~~<br>~~ee~~<br>|**Units**<br>~~ee~~<br>|
|tENS<br>~~ae~~|REN, WEN Setup Time<br>~~es~~|3.75<br>~~es~~<br>~~es~~|4.27<br>~~es~~<br>~~es~~|5.02<br>~~ee~~<br>~~es~~|ns<br>~~es~~|
|tENH<br>~~ae~~<br>~~a ~~<br>~~ee~~|REN, WEN Hold Time<br><br> ~~es~~|0.00<br>~~es ~~<br><br>~~es~~|0.00<br> ~~es ~~<br><br>~~es~~|0.00<br> ~~ee~~<br><br>~~es~~|ns<br><br>~~es~~|
|tBKS<br>~~ee~~<br>~~es~~|BLK Setup Time<br>~~ee~~|0.19<br>~~ee~~|0.22<br>~~ee~~|0.26<br>~~ee~~|ns<br>~~ee~~|
|tBKH<br>~~ee~~<br>~~es~~<br>~~ee~~|BLK Hold Time<br>~~ee~~<br>|0.00<br>~~ee~~<br>~~ss~~<br>|0.00<br>~~ee~~<br>~~ss~~<br>|0.00<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|tDS<br>~~es~~<br>~~a ~~<br>~~ee~~<br>~~a~~|Input Data (WD) Setup Time<br>~~ee~~<br> ~~ee~~<br><br>|0.18<br>~~ee~~<br>~~ee~~<br>~~ss~~<br><br>~~es~~<br>|0.21<br>~~ee~~<br>~~ee~~<br>~~ss~~<br><br>~~ee~~<br>|0.25<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br><br>|
|tDH<br>~~ee~~<br>~~a~~<br>~~a~~|Input Data (WD) Hold Time<br>~~ee~~<br><br>|0.00<br>~~ss~~<br>~~ee~~<br>~~es~~<br><br>~~es~~<br>|0.00<br>~~ss~~<br>~~ee~~<br>~~ee~~<br><br>~~se~~<br>|0.00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~se~~<br>|ns<br>~~ee~~<br><br>|
|tCKQ1<br>~~ee~~<br>~~a ee~~<br>~~a~~|Clock High to New Data Valid on RD (flow-through)<br><br>~~ee~~<br>|2.17<br>~~ss~~<br><br>~~es ~~<br>~~ee~~<br>~~es~~<br>|2.47<br>~~ss ~~<br><br> ~~ee ~~<br>~~ee~~<br>~~se~~<br>|2.90<br> ~~ee~~<br><br> ~~ee~~<br>~~ee~~<br>~~se~~<br>|ns<br><br>~~ee~~<br>|
|tCKQ2<br>~~a es~~<br>~~ee~~|Clock High to New Data Valid on RD (pipelined)<br>~~es~~|0.94<br>~~es ~~<br>~~es~~|1.07<br> ~~se~~<br>~~es~~|1.26<br>~~se~~<br>~~es~~|ns<br>~~es~~|
|tRCKEF<br>~~es~~<br>~~ee~~<br>~~es~~|RCLK High to Empty Flag Valid<br>~~es~~<br>~~ee~~|1.72<br>~~es~~<br>~~ee~~|1.96<br>~~es~~<br>~~ee~~|2.30<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|
|tWCKFF<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|WCLK High to Full Flag Valid<br>~~es~~<br>~~ee~~<br>|1.63<br>~~es~~<br>~~ee~~<br>~~ss~~<br>|1.86<br>~~es~~<br>~~ee~~<br>~~ss~~<br>|2.18<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~es~~<br>~~ee~~<br>|
|tCKAF<br>~~es~~<br>~~a ~~<br>~~ee~~<br>~~a~~|Clock High to Almost Empty/Full Flag Valid<br>~~ee~~<br> ~~ee~~<br><br>|6.19<br>~~ee~~<br>~~ee~~<br>~~ss~~<br><br>~~es~~<br>|7.05<br>~~ee~~<br>~~ee~~<br>~~ss~~<br><br>~~ee~~<br>|8.29<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br><br>|
|tRSTFG<br>~~ee~~<br>~~a~~|RESET Low to Empty/Full Flag Valid<br>~~ee~~<br>|1.69<br>~~ss~~<br>~~ee~~<br>~~es~~<br><br>~~es~~|1.93<br>~~ss~~<br>~~ee~~<br>~~ee~~<br><br>~~es~~|2.27<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|ns<br>~~ee~~<br>|
|tRSTAF<br>~~ee~~<br>~~a ~~|RESET Low to Almost Empty/Full Flag Valid<br><br> ~~ee~~|6.13<br>~~ss~~<br><br>~~es ~~<br>~~ee~~<br>~~es~~|6.98<br>~~ss ~~<br><br> ~~ee ~~<br>~~ee~~<br>~~es~~|8.20<br> ~~ee~~<br><br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br><br>~~ee~~|
|tRSTBQ<br>~~pp~~<br>~~es~~|RESET Low to Data Out Low on RD (flow-through)<br>~~pp~~<br>|0.92<br>~~es ~~<br>~~pp~~<br>~~ee~~<br>|1.05<br> ~~es ~~<br>~~pp~~<br>~~ee~~<br>|1.23<br> ~~ee~~<br>~~pp~~<br>|ns<br>~~pp~~<br>|
||RESET Low to Data Out Low on RD (pipelined)<br>~~pp~~<br>~~es~~<br>|0.92<br>~~pp~~<br>~~es~~<br>~~ee~~<br>|1.05<br>~~pp~~<br>~~es~~<br>~~ee~~<br>|1.23<br>~~pp~~<br>~~es~~<br>|ns<br>~~pp~~<br>~~es~~<br>|
|tREMRSTB<br>~~es~~<br>~~ee~~|RESET Removal<br>~~ee~~<br>|0.29<br>~~ee~~<br>~~ee~~<br>~~ss~~<br>|0.33<br>~~ee~~<br>~~ee~~<br>~~ss~~<br>|0.38<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|tRECRSTB<br>~~es~~<br>~~a ~~<br>~~ee~~<br>~~a~~|RESET Recovery<br><br> ~~ee~~<br><br>|1.50<br>~~ee~~<br><br>~~ee~~<br>~~ss~~<br><br>~~es~~<br>|1.71<br>~~ee~~<br><br>~~ee~~<br>~~ss~~<br><br>~~ee~~<br>|2.01<br><br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br><br>~~ee~~<br><br>|
|tMPWRSTB<br>~~ee~~<br>~~a~~<br>~~a~~|RESET Minimum Pulse Width<br>~~ee~~<br><br>|0.21<br>~~ss~~<br>~~ee~~<br>~~es~~<br><br>~~es~~<br>|0.24<br>~~ss~~<br>~~ee~~<br>~~ee~~<br><br>~~se~~<br>|0.29<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~se~~<br>|ns<br>~~ee~~<br><br>|
|tCYC<br>~~ee~~<br>~~a ee~~<br>~~a~~|Clock Cycle Time<br><br>~~ee~~<br>|3.23<br>~~ss~~<br><br>~~es ~~<br>~~ee~~<br>~~es~~<br>|3.68<br>~~ss ~~<br><br> ~~ee ~~<br>~~ee~~<br>~~se~~<br>|4.32<br> ~~ee~~<br><br> ~~ee~~<br>~~ee~~<br>~~se~~<br>|ns<br><br>~~ee~~<br>|
|FMAX<br>~~a ~~|Maximum Frequency for FIFO<br> ~~es~~|310<br>~~es ~~<br>~~es~~|272<br> ~~se~~<br>~~es~~|231<br>~~se~~<br>~~es~~|MHz<br>~~es~~|
**Revision 18**
**2-104**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-121 •**_ **A3P250 FIFO 1k×4**
|**Parameter**<br>~~ae~~<br>~~a~~<br>~~a~~|**Description**<br>~~es~~<br><br>|**–2**<br>~~es~~<br>~~ee~~<br><br>~~ss~~<br>|**–1**<br>~~es~~<br>~~ee~~<br><br>~~ss~~<br>|**Std.**<br>~~es~~<br>~~ee~~<br><br>|**Units**<br>~~es~~<br><br>|
|---|---|---|---|---|---|
|tENS<br>~~ae~~<br>~~a es~~<br>~~a~~|REN, WEN Setup Time<br>~~es~~<br>~~es~~<br>|4.05<br>~~es~~<br>~~ee ~~<br>~~es~~<br>~~ss~~<br>|4.61<br>~~es~~<br> ~~ee ~~<br>~~es~~<br>~~ss~~<br>|5.42<br>~~es~~<br> ~~ee~~<br>~~es~~<br>|ns<br>~~es~~<br>~~es~~<br>|
|tENH<br>~~a~~|REN, WEN Hold Time<br>~~es~~|0.00<br>~~ss~~<br>~~es~~|0.00<br>~~ss~~<br>~~es~~|0.00<br>~~es~~|ns<br>~~es~~|
|tBKS<br>~~a es~~|BLK Setup Time<br>~~es~~|0.19<br>~~es~~|0.22<br>~~es~~|0.26<br>~~es~~|ns<br>~~es~~|
|tBKH<br>~~a ~~<br>~~ae~~<br>~~ee~~|BLK Hold Time<br> ~~ee~~<br>~~es~~<br>|0.00<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|0.00<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|0.00<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~es~~<br>|
|tDS<br>~~ae~~<br>~~ee~~<br>~~ae~~|Input Data (WD) Setup Time<br>~~es~~<br><br>|0.18<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.21<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.25<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tDH<br>~~ae~~<br>~~ee~~<br>~~ae~~<br>~~a~~|Input Data (WD) Hold Time<br>~~es~~<br>~~es~~<br><br>|0.00<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.00<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.00<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br>~~es~~<br><br>|
|tCKQ1<br>~~ee~~<br>~~ae~~<br>~~a~~|Clock High to New Data Valid on RD (flow-through)<br><br>~~es~~<br>|2.36<br>~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|2.68<br> ~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|3.15<br> ~~ee~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|ns<br><br>~~es~~<br>|
|tCKQ2<br>~~ae~~<br>~~a~~|Clock High to New Data Valid on RD (pipelined)<br><br>~~es~~|0.89<br>~~ee ~~<br><br>~~ee ~~<br>~~es~~|1.02<br> ~~ee ~~<br><br> ~~ee ~~<br>~~es~~|1.20<br> ~~ee~~<br><br> ~~ee~~<br>~~es~~|ns<br><br>~~es~~|
|tRCKEF<br>~~a es~~|RCLK High to Empty Flag Valid<br>~~es~~|1.72<br>~~es~~|1.96<br>~~es~~|2.30<br>~~es~~|ns<br>~~es~~|
|tWCKFF<br>~~a ~~<br>~~ae~~<br>~~ee~~|WCLK High to Full Flag Valid<br> ~~ee~~<br>~~es~~<br>|1.63<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|1.86<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|2.18<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~es~~<br>|
|tCKAF<br>~~ae~~<br>~~ee~~<br>~~ae~~|Clock High to Almost Empty/Full Flag Valid<br>~~es~~<br><br>|6.19<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|7.05<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|8.29<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tRSTFG<br>~~ae~~<br>~~ee~~<br>~~ae~~<br>~~—__~~|RESET Low to Empty/Full Flag Valid<br>~~es~~<br>~~es~~<br><br>~~—__~~|1.69<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|1.93<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|2.27<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br>~~es~~<br><br>|
|tRSTAF<br>~~ee~~<br>~~ae~~<br>~~—__~~|RESET Low to Almost Empty/Full Flag Valid<br><br>~~es~~<br>~~—__~~|6.13<br>~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|6.98<br> ~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|8.20<br> ~~ee~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|ns<br><br>~~es~~<br>|
|tRSTBQ<br>~~ae~~<br>~~—__~~|RESET Low to Data Out Low on RD (flow-through)<br><br>~~—__~~|0.92<br>~~ee ~~<br><br>~~ee~~<br>|1.05<br> ~~ee ~~<br><br>~~ee~~<br>|1.23<br> ~~ee~~<br><br>~~ee~~<br>|ns<br><br>|
||RESET Low to Data Out Low on RD (pipelined)<br>~~—__es~~|0.92<br>~~ee~~<br>~~es~~|1.05<br>~~ee~~<br>~~es~~|1.23<br>~~ee~~<br>~~es~~|ns<br>~~es~~|
|tREMRSTB<br>~~—__~~<br>~~a ~~<br>~~ae~~<br>~~ee~~|RESET Removal<br>~~—__~~<br> ~~ee~~<br>~~es~~<br>|0.29<br>~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|0.33<br> ~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|0.38<br> ~~ee~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|ns<br><br>~~ee~~<br>~~es~~<br>|
|tRECRSTB<br>~~ae~~<br>~~ee~~<br>~~ae~~|RESET Recovery<br>~~es~~<br><br>|1.50<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|1.71<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|2.01<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br><br>|
|tMPWRSTB<br>~~ae~~<br>~~ee~~<br>~~ae~~<br>~~a~~|RESET Minimum Pulse Width<br>~~es~~<br>~~es~~<br><br>|0.21<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.24<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|0.29<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~es~~<br>~~es~~<br><br>|
|tCYC<br>~~ee~~<br>~~ae~~<br>~~a~~|Clock Cycle Time<br><br>~~es~~<br>|3.23<br>~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|3.68<br> ~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|4.32<br> ~~ee~~<br><br>~~ee~~<br>~~es~~<br>~~ee~~<br>|ns<br><br>~~es~~<br>|
|FMAX<br>~~ae~~<br>~~a es~~|Maximum Frequency for FIFO<br><br>~~es~~|310<br>~~ee ~~<br><br>~~ee ~~<br>~~es~~|272<br> ~~ee ~~<br><br> ~~ee ~~<br>~~es~~|231<br> ~~ee~~<br><br> ~~ee~~<br>~~es~~|MHz<br><br>~~es~~|
**2-105**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
_**Table 2-122 •**_ **A3P250 FIFO 2k×2**
**Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [468 x 615] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|a|es|
|tENS|REN, WEN Setup Time|4.39|5.00|5.88|ns|
|es|
|ee|ee|ee|
|tENH|REN, WEN Hold Time|0.00|0.00|0.00|ns|
|ee|es|es|es|
|tBKS|BLK Setup Time|0.19|0.22|0.26|ns|
|aees|
|tBKH|BLK Hold Time|0.00|0.00|0.00|ns|
|i|
|eses|
|tDS|Input Data (WD) Setup Time|0.18|0.21|0.25|ns|
|a|es|
|tDH|Input Data (WD) Hold Time|0.00|0.00|0.00|ns|
|es|
|ee|ee|ee|ee|
|tCKQ1|Clock High to New Data Valid on RD (flow-through)|2.36|2.68|3.15|ns|
|a aee ee|ee|
|tCKQ2|Clock High to New Data Valid on RD (pipelined)|0.89|1.02|1.20|ns|
|ee|ee|ee|
|tRCKEF|RCLK High to Empty Flag Valid|1.72|1.96|2.30|ns|
|aees|
|tWCKFF|WCLK High to Full Flag Valid|1.63|1.86|2.18|ns|
|i|
|eses|
|tCKAF|Clock High to Almost Empty/Full Flag Valid|6.19|7.05|8.29|ns|
|a|es|
|tRSTFG|RESET Low to Empty/Full Flag Valid|1.69|1.93|2.27|ns|
|es|
|ee|ee|ee|ee|
|tRSTAF|RESET Low to Almost Empty/Full Flag Valid|6.13|6.98|8.20|ns|
|a|eseeee eeee|eeee|
|tRSTBQ|RESET Low to Data Out Low on RD (flow-through)|0.92|1.05|1.23|ns|
|RESET Low to Data Out Low on RD (pipelined)|0.92|1.05|1.23|ns|
|ee|
|tREMRSTB|RESET Removal|0.29|0.33|0.38|ns|
|i|
|esee|
|tRECRSTB|RESET Recovery|1.50|1.71|2.01|ns|
|a|es|
|tMPWRSTB|RESET Minimum Pulse Width|0.21|0.24|0.29|ns|
|es|
|ee|ee|ee|ee|
|tCYC|Clock Cycle Time|3.23|3.68|4.32|ns|
|a aee ee|ee|
|FMAX|Maximum Frequency for FIFO|310|272|231|MHz|
|es|
|ee|eees|ee|
|Table 2-123 •|A3P250 FIFO 4k×1|
|Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V|
|Parameter|Description|–2|–1|Std.|Units|
|a a|
|tENS|REN, WEN Setup Time|4.86|5.53|6.50|ns|
|a|esee|
|tENH|REN, WEN Hold Time|0.00|0.00|0.00|ns|
|a|es|
|tBKS|BLK Setup Time|0.19|0.22|0.26|ns|
|a|
|tBKH|BLK Hold Time|0.00|0.00|0.00|ns|
|a es|
|tDS|Input Data (WD) Setup Time|0.18|0.21|0.25|ns|
|a|esee|
|tDH|Input Data (WD) Hold Time|0.00|0.00|0.00|ns|
|a aee|ee|ee|
|tCKQ1|Clock High to New Data Valid on RD (flow-through)|2.36|2.68|3.15|ns|
|a|ssee|
|tCKQ2|Clock High to New Data Valid on RD (pipelined)|0.89|1.02|1.20|ns|
|a|es|
|tRCKEF|RCLK High to Empty Flag Valid|1.72|1.96|2.30|ns|
|a|
|tWCKFF|WCLK High to Full Flag Valid|1.63|1.86|2.18|ns|
|a|ee|
|tCKAF|Clock High to Almost Empty/Full Flag Valid|6.19|7.05|8.29|ns|
|a es|
|tRSTFG|RESET Low to Empty/Full Flag Valid|1.69|1.93|2.27|ns|
|aaesee|
**----- End of picture text -----**<br>
**Revision 18**
**2-106**
_ProASIC3 DC and Switching Characteristics_
_**Table 2-123 •**_ **A3P250 FIFO 4k×1 (continued)**
**Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V**
**==> picture [468 x 153] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|a|ee|
|tRSTAF|RESET Low to Almost Empty/Full Flag Valid|6.13|6.98|8.20|ns|
|tRSTBQ|RESET Low to Data Out Low on DO (pass-through)|0.92|1.05|1.23|ns|
|a|
|RESET Low to Data Out Low on DO (pipelined)|0.92|1.05|1.23|ns|
|ees|ee|ne|es|
|tREMRSTB|RESET Removal|0.29|0.33|0.38|ns|
|a|
|tRECRSTB|RESET Recovery|1.50|1.71|2.01|ns|
|a|
|tMPWRSTB|RESET Minimum Pulse Width|0.21|0.24|0.29|ns|
|aes|
|tCYC|Clock Cycle Time|3.23|3.68|4.32|ns|
|a|es|
|FMAX|Maximum Frequency|310|272|231|MHz|
|aa|
**----- End of picture text -----**<br>
## **Embedded FlashROM Characteristics**
**==> picture [457 x 151] intentionally omitted <==**
**----- Start of picture text -----**<br>
tSU tSU tSU<br>CLK<br>tHOLD tHOLD tHOLD<br>Address A0 A1<br>1) AD GO ED 000000<br>t t t<br>CKQ2 CKQ2 CKQ2<br>Data D0 D0 D1<br>OOOO IKK<br>**----- End of picture text -----**<br>
_**Figure 2-44 •**_ **Timing Diagram**
## _**Timing Characteristics**_
_**Table 2-124 •**_ **Embedded FlashROM Access Time**
**==> picture [455 x 78] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|tSU|Address Setup Time|0.53|0.61|0.71|ns|
|tHOLD|Address Hold Time|0.00|0.00|0.00|ns|
|tCK2Q|Clock to Out|21.42|24.40|28.68|ns|
|FMAX|Maximum Clock Frequency|15|15|15|MHz|
**----- End of picture text -----**<br>
**2-107**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **JTAG 1532 Characteristics**
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-15 for more details.
## **Timing Characteristics**
_**Table 2-125 •**_ **JTAG 1532**
**Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V**
**==> picture [414 x 212] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Description|–2|–1|Std.|Units|
|eees|
|tDISU|Test Data Input Setup Time|0.50|0.57|0.67|ns|
|es|
|es|es|
|tDIHD|Test Data Input Hold Time|1.00|1.13|1.33|ns|
|a|ee|
|tTMSSU|Test Mode Select Setup Time|0.50|0.57|0.67|ns|
|a eeee|ee|ee|
|tTMDHD|Test Mode Select Hold Time|1.00|1.13|1.33|ns|
|a|eeee|ee|ee|
|tTCK2Q|Clock to Q (data out)|6.00|6.80|8.00|ns|
|es|
|ee|ee|ee|ee|
|tRSTB2Q|Reset to Q (data out)|20.00|22.67|26.67|ns|
|es|
|ee|ee|
|FTCKMAX|TCK Maximum Frequency|25.00|22.00|19.00|MHz|
|es|
|es|se|
|tTRSTREM|ResetB Removal Time|0.00|0.00|0.00|ns|
|a|ee|
|tTRSTREC|ResetB Recovery Time|0.20|0.23|0.27|ns|
|a eeee|ee|ee|
|tTRSTMPW|ResetB Minimum Pulse|TBD|TBD|TBD|ns|
|a|eeeeee|eeee|eeee|
|Note:|For specific junction temperature and voltage supply levels, refer to|Table 2-6 on page 2-6 for|
|derating values.|
**----- End of picture text -----**<br>
**Revision 18**
**2-108**
## **3 – Pin Descriptions**
## **Supply Pins**
## **GND**
## **Ground**
Ground supply voltage to the core, I/O outputs, and I/O logic.
## **GNDQ**
## **Ground (quiet)**
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board.
## **VCC**
## **Core Supply Voltage**
Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.
## **VCCIBx**
## **I/O Supply Voltage**
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. In general, unused I/O banks should have their corresponding VCCIX pins tied to GND. If an output pad is terminated to ground through any resistor and if the corresponding VCCIX is left floating, then the leakage current to ground is ~ 0uA. However, if an output pad is terminated to ground through any resistor and the corresponding VCCIX grounded, then the leakage current to ground is ~ 3 uA. For unused banks the aforementioned behavior is to be taken into account while deciding if it’s better to float VCCIX of unused bank or tie it to GND.
## **VMVx**
## **I/O Supply Voltage (quiet)**
Quiet supply voltage to the input buffers of each I/O bank. _x_ is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
## **VCCPLA/B/C/D/E/F PLL Supply Voltage**
Supply voltage to analog PLL, nominally 1.5 V.
When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the _ProASIC3 FPGA Fabric User’s Guide_ for a complete board solution for the PLL analog power supply and ground.
There is one VCCPLF pin on ProASIC3 devices.
## **VCOMPLA/B/C/D/E/F PLL Ground**
Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on ProASIC3 devices.
**Revision 18**
**3-1**
_ProASIC3 Flash Family FPGAs_
## **VJTAG**
## **JTAG Supply Voltage**
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design.
If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND.
It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail.
## **VPUMP Programming Supply Voltage**
ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail.
## **User Pins**
## **I/O User Input/Output**
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
- Output buffer is disabled (with tristate value of high impedance)
- Input buffer is disabled (with tristate value of high impedance)
- Weak pull-up is programmed
## **GL**
## **Globals**
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the _ProASIC3 FPGA Fabric User’s Guide_ . All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure section of the handbook for the device you are using for an explanation of the naming of global pins.
## **FF Flash*Freeze Mode Activation Pin**
Flash*Freeze is available on IGLOO, ProASIC3L, and RT ProASIC3 devices. It is not supported on ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active-low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze
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_Pin Descriptions_
mode is not used in the design, the FF pin is available as a regular I/O. For IGLOOe, ProASIC3EL, and RT ProASIC3 only, the FF pin can be configured as a Schmitt trigger input.
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signal. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required.
## **JTAG Pins**
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND.
## **TCK Test Clock**
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 1 for more information.
_**Table 1 •**_ **Recommended Tie-Off Values for the TCK and TRST Pins**
|**VJTAG**|**Tie-Off Resistance**|
|---|---|
|3.3 V|200–1 k|
|2.5 V|200–1 k|
|1.8 V|500–1 k|
|1.5 V|500–1 k|
_Notes:_
_1. Equivalent parallel resistance if more than one device is on the JTAG chain_
_2. The TCK pin can be pulled up/down._
_3. The TRST pin is pulled down._
## **TDI**
## **Test Data Input**
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin.
## **TDO Test Data Output**
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
## **TMS Test Mode Select**
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin.
## **TRST**
## **Boundary Scan Reset Pin**
The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 1 and must satisfy the parallel resistance value requirement. The values in Table 1 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain.
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In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
## **Special Function Pins**
## **NC**
## **No Connect**
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
## **DC**
## **Do Not Connect**
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
## **Related Documents**
## **User’s Guides**
_ProASIC FPGA Fabric User’s Guide_
_http://www.microsemi.com/soc/documents/PA3_UG.pdf_
## **Packaging**
The following documents provide packaging information and device selection for low power flash devices.
## _**Product Catalog**_
_http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf_
Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use.
## _**Package Mechanical Drawings**_
_http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf_
This document contains the package mechanical drawings for all packages currently or previously supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials are at _http://www.microsemi.com/products/solutions/package/docs.aspx._
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## **4 – Package Pin Assignments**
## **QN48 – Bottom View**
**==> picture [85 x 47] intentionally omitted <==**
**----- Start of picture text -----**<br>
Pin 1<br>48<br>a<br>1<br>**----- End of picture text -----**<br>
_Note: The die attach paddle center of the package is tied to ground (GND)._
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
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_Package Pin Assignments_
|**QN48**<br>~~Pe~~|||**QN48**|**QN48**|
|---|---|---|---|---|
|**Pin Number**<br>**A3P030 Function**<br>~~ee~~||**Pin Number**||**A3P030 Function**|
|1<br>IO82RSB1<br>~~a~~||37||IO24RSB0|
|2<br>GEC0/IO73RSB1<br>~~a~~||38||IO22RSB0|
|3<br>GEA0/IO72RSB1<br>4<br>GEB0/IO71RSB1<br>5<br>GND<br>6<br>VCCIB1<br>7<br>IO68RSB1<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~a~~||39<br>40<br>41<br>42<br>43||IO20RSB0<br>IO18RSB0<br>IO16RSB0<br>IO14RSB0<br>IO10RSB0|
|8<br>IO67RSB1<br>~~a~~||44||IO08RSB0|
|9<br>IO66RSB1<br>10<br>IO65RSB1<br>11<br>IO64RSB1<br>12<br>IO62RSB1<br>13<br>IO61RSB1<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~a~~||45<br>46<br>47<br>48||IO06RSB0<br>IO04RSB0<br>IO02RSB0<br>IO00RSB0|
|14<br>IO60RSB1<br>~~a~~|||||
|15<br>IO57RSB1<br>16<br>IO55RSB1<br>17<br>IO53RSB1<br>18<br>VCC<br>19<br>VCCIB1<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|||||
|20<br>IO46RSB1<br>~~a~~|||||
|21<br>IO42RSB1<br>22<br>TCK<br>23<br>TDI<br>24<br>TMS<br>25<br>VPUMP<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|||||
|26<br>TDO<br>~~a~~|||||
|27<br>TRST<br>28<br>VJTAG<br>29<br>IO38RSB0<br>30<br>GDB0/IO34RSB0<br>31<br>GDA0/IO33RSB0<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|||||
|32<br>GDC0/IO32RSB0<br>~~a~~|||||
|33<br>VCCIB0<br>34<br>GND<br>35<br>VCC<br>36<br>IO25RSB0<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeeee~~|||||
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_ProASIC3 Flash Family FPGAs_
## **QN68 – Bottom View**
**==> picture [249 x 201] intentionally omitted <==**
**----- Start of picture text -----**<br>
Pin A1 Mark<br>68<br>1<br>1 PLETEEL<br>**----- End of picture text -----**<br>
_Note: The die attach paddle center of the package is tied to ground (GND)._
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
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_Package Pin Assignments_
|**QN68**<br>**Pin Number**<br>**A3P015 Function**<br>1<br>IO82RSB1<br>2<br>IO80RSB1<br>3<br>IO78RSB1<br>4<br>IO76RSB1<br>5<br>GEC0/IO73RSB1<br>6<br>GEA0/IO72RSB1<br>7<br>GEB0/IO71RSB1<br>8<br>VCC<br>9<br>GND<br>10<br>VCCIB1<br>11<br>IO68RSB1<br>12<br>IO67RSB1<br>13<br>IO66RSB1<br>14<br>IO65RSB1<br>15<br>IO64RSB1<br>16<br>IO63RSB1<br>17<br>IO62RSB1<br>18<br>IO60RSB1<br>19<br>IO58RSB1<br>20<br>IO56RSB1<br>21<br>IO54RSB1<br>22<br>IO52RSB1<br>23<br>IO51RSB1<br>24<br>VCC<br>25<br>GND<br>26<br>VCCIB1<br>27<br>IO50RSB1<br>28<br>IO48RSB1<br>29<br>IO46RSB1<br>30<br>IO44RSB1<br>31<br>IO42RSB1<br>32<br>TCK<br>33<br>TDI<br>34<br>TMS<br>35<br>VPUMP<br>36<br>TDO<br>37<br>TRST<br>38<br>VJTAG<br>39<br>IO40RSB0<br>40<br>IO37RSB0<br>41<br>GDB0/IO34RSB0<br>42<br>GDA0/IO33RSB0<br>43<br>GDC0/IO32RSB0<br>44<br>VCCIB0<br>45<br>GND<br>46<br>VCC<br>47<br>IO31RSB0<br>48<br>IO29RSB0<br>49<br>IO28RSB0<br>50<br>IO27RSB0<br>51<br>IO25RSB0<br>52<br>IO24RSB0<br>53<br>IO22RSB0<br>54<br>IO21RSB0<br>55<br>IO19RSB0<br>56<br>IO17RSB0<br>57<br>IO15RSB0<br>58<br>IO14RSB0<br>59<br>VCCIB0<br>60<br>GND<br>61<br>VCC<br>62<br>IO12RSB0<br>63<br>IO10RSB0<br>64<br>IO08RSB0<br>65<br>IO06RSB0<br>66<br>IO04RSB0<br>67<br>IO02RSB0<br>68<br>IO00RSB0<br>**QN68**<br>**Pin Number**<br>**A3P015 Function**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~eeeee~~|
|---|
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_ProASIC3 Flash Family FPGAs_
|**QN68**<br>**Pin Number**<br>**A3P030 Function**<br>1<br>IO82RSB1<br>2<br>IO80RSB1<br>3<br>IO78RSB1<br>4<br>IO76RSB1<br>5<br>GEC0/IO73RSB1<br>6<br>GEA0/IO72RSB1<br>7<br>GEB0/IO71RSB1<br>8<br>VCC<br>9<br>GND<br>10<br>VCCIB1<br>11<br>IO68RSB1<br>12<br>IO67RSB1<br>13<br>IO66RSB1<br>14<br>IO65RSB1<br>15<br>IO64RSB1<br>16<br>IO63RSB1<br>17<br>IO62RSB1<br>18<br>IO60RSB1<br>19<br>IO58RSB1<br>20<br>IO56RSB1<br>21<br>IO54RSB1<br>22<br>IO52RSB1<br>23<br>IO51RSB1<br>24<br>VCC<br>25<br>GND<br>26<br>VCCIB1<br>27<br>IO50RSB1<br>28<br>IO48RSB1<br>29<br>IO46RSB1<br>30<br>IO44RSB1<br>31<br>IO42RSB1<br>32<br>TCK<br>33<br>TDI<br>34<br>TMS<br>35<br>VPUMP<br>36<br>TDO<br>37<br>TRST<br>38<br>VJTAG<br>39<br>IO40RSB0<br>40<br>IO37RSB0<br>41<br>GDB0/IO34RSB0<br>42<br>GDA0/IO33RSB0<br>43<br>GDC0/IO32RSB0<br>44<br>VCCIB0<br>45<br>GND<br>46<br>VCC<br>47<br>IO31RSB0<br>48<br>IO29RSB0<br>49<br>IO28RSB0<br>50<br>IO27RSB0<br>51<br>IO25RSB0<br>52<br>IO24RSB0<br>53<br>IO22RSB0<br>54<br>IO21RSB0<br>55<br>IO19RSB0<br>56<br>IO17RSB0<br>57<br>IO15RSB0<br>58<br>IO14RSB0<br>59<br>VCCIB0<br>60<br>GND<br>61<br>VCC<br>62<br>IO12RSB0<br>63<br>IO10RSB0<br>64<br>IO08RSB0<br>65<br>IO06RSB0<br>66<br>IO04RSB0<br>67<br>IO02RSB0<br>68<br>IO00RSB0<br>**QN68**<br>**Pin Number**<br>**A3P030 Function**<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eeee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eeee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eeee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eeee~~<br>~~a~~<br>~~ee ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|---|
**Revision 18**
**4-5**
_Package Pin Assignments_
## **QN132 – Bottom View**
**==> picture [339 x 290] intentionally omitted <==**
**----- Start of picture text -----**<br>
A37 A48<br>B34 B44<br>C31 C40<br>Pin A1Mark<br>D4 D1<br>Fl QUO OOOOOOOOM /o<br>A36 A1<br>B33 a e Apo ooo ony / B1<br>C30 er NOOOOOOOOO ee C1<br>oo ZL ==!<br>O40 oo<br>O,u O40<br>OU O40<br>O40 O_U<br>OU O40<br>O40 O,d0<br>oo O40<br>C21 C10<br>B23 =r of B11<br>A25 | HoOoOooOoooog PreGh A12<br>D3 Fl GFPOOOOOOOOOoOOKmoOoooooooom ‘oy--| D2<br>Optional<br>Corner Pad (4x)<br>C20 C11<br>B22 B12<br>A24 A13<br>**----- End of picture text -----**<br>
_Notes:_
_1. The die attach paddle center of the package is tied to ground (GND)._
_2. Option corner pads come with this device and package combination. It is optional to tie them to ground or leave them floating._
_3. The QN132 package is discontinued and is not available for ProASIC3 devices._
_4._ For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-6**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**==> picture [468 x 646] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|QN132|QN132|QN132|
|ee Os|
|Pin Number|A3P030 Function|Pin Number|A3P030 Function|Pin Number|A3P030 Function|
|a|ee|es|Os|
|A1|IO01RSB1|A37|IO26RSB0|B25|GND|
|a|ee|es|Oo|
|A2|IO81RSB1|A38|IO23RSB0|B26|NC|
|a|ee|es|Ooes|
|A3|NC|A39|NC|B27|IO41RSB0|
|a|ee|es|so|
|A4|IO80RSB1|A40|IO22RSB0|B28|GND|
|es|en|ie|nnOs|
|A5|GEC0/IO77RSB1|A41|IO20RSB0|B29|GDA0/IO37RSB0|
|a|ee Os|
|A6|NC|A42|IO18RSB0|B30|NC|
|a|ee|es|Oo|
|A7|GEB0/IO75RSB1|A43|VCC|B31|GND|
|a|ee|es|eo|
|A8|IO73RSB1|A44|IO15RSB0|B32|IO33RSB0|
|a|ee|es|Ooes|
|A9|NC|A45|IO12RSB0|B33|IO30RSB0|
|a|ee|es|so|
|A10|VCC|A46|IO10RSB0|B34|IO27RSB0|
|es|en|ie|nnOs|
|A11|IO71RSB1|A47|IO09RSB0|B35|IO24RSB0|
|a|ee Os|
|A12|IO68RSB1|A48|IO06RSB0|B36|GND|
|a|ee|es|Oo|
|A13|IO63RSB1|B1|IO02RSB1|B37|IO21RSB0|
|a|ee|es|0s|es|
|A14|IO60RSB1|B2|IO82RSB1|B38|IO19RSB0|
|ee|ee|Oo|
|A15|NC|B3|GND|B39|GND|
|a|ee|ie|enso es|
|A16|IO59RSB1|B4|IO79RSB1|B40|IO16RSB0|
|es|en|ie|nnOs|
|A17|IO57RSB1|B5|NC|B41|IO13RSB0|
|a|ee Os|
|A18|VCC|B6|GND|B42|GND|
|a|ee|es|Oo|
|A19|IO54RSB1|B7|IO74RSB1|B43|IO08RSB0|
|a|ee|es|eo|
|A20|IO52RSB1|B8|NC|B44|IO05RSB0|
|a|ee|es|Oo|
|A21|IO49RSB1|B9|GND|C1|IO03RSB1|
|a|ee|ie|enso es|
|A22|IO48RSB1|B10|IO70RSB1|C2|IO00RSB1|
|es|en|ie|nnOs|
|A23|IO47RSB1|B11|IO67RSB1|C3|NC|
|a|ee Os|
|A24|TDI|B12|IO64RSB1|C4|IO78RSB1|
|a|ee|es|Oo|
|A25|TRST|B13|IO61RSB1|C5|GEA0/IO76RSB1|
|a|ee|es|eo|
|A26|IO44RSB0|B14|GND|C6|NC|
|a|ee|es|Oo|
|A27|NC|B15|IO58RSB1|C7|NC|
|a|ee|ie|enso es|
|A28|IO43RSB0|B16|IO56RSB1|C8|VCCIB1|
|es|en|ie|nnOs|
|A29|IO42RSB0|B17|GND|C9|IO69RSB1|
|a|ee Os|
|A30|IO40RSB0|B18|IO53RSB1|C10|IO66RSB1|
|a|ee|es|Oo|
|A31|IO39RSB0|B19|IO50RSB1|C11|IO65RSB1|
|a|ee|es|eo|
|A32|GDC0/IO36RSB0|B20|GND|C12|IO62RSB1|
|a|ee|es|Oo|
|A33|NC|B21|IO46RSB1|C13|NC|
|a|ee|es|Oo|
|A34|VCC|B22|TMS|C14|NC|
|es|en|ie|nnOs|
|A35|IO34RSB0|B23|TDO|C15|IO55RSB1|
|a|ee|ie|Gs|Os|I|
|A36|IO31RSB0|B24|IO45RSB0|C16|VCCIB1|
|a|ee fo|
**----- End of picture text -----**<br>
**Revision 18**
**4-7**
_Package Pin Assignments_
**QN132 Pin Number A3P030 Function** ~~a~~ C17 IO51RSB1 ~~a~~ C18 NC ~~a~~ C19 TCK ~~a~~ C20 NC ~~ee eee~~ C21 VPUMP ~~a ee~~ C22 VJTAG ~~a ee~~ C23 NC ~~a~~ C24 NC ~~a~~ C25 NC ~~a~~ C26 GDB0/IO38RSB0 ~~ee eee~~ C27 NC ~~a ee~~ C28 VCCIB0 ~~a ee~~ C29 IO32RSB0 ~~a~~ C30 IO29RSB0 ~~a~~ C31 IO28RSB0 ~~a~~ C32 IO25RSB0 ~~ee eee~~ C33 NC ~~a ee~~ C34 NC ~~a ee~~ C35 VCCIB0 ~~a~~ C36 IO17RSB0 ~~a~~ C37 IO14RSB0 ~~a~~ C38 IO11RSB0 ~~ee eee~~ C39 IO07RSB0 ~~a ee~~ C40 IO04RSB0 ~~a ee~~ D1 GND ~~a~~ D2 GND ~~a~~ D3 GND ~~a~~ D4 GND ~~ee eee~~
**4-8**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**QN132**<br>**Pin Number**<br>**A3P060 Function**<br>A1<br>GAB2/IO00RSB1<br>A2<br>IO93RSB1<br>A3<br>VCCIB1<br>A4<br>GFC1/IO89RSB1<br>A5<br>GFB0/IO86RSB1<br>A6<br>VCCPLF<br>A7<br>GFA1/IO84RSB1<br>A8<br>GFC2/IO81RSB1<br>A9<br>IO78RSB1<br>A10<br>VCC<br>A11<br>GEB1/IO75RSB1<br>A12<br>GEA0/IO72RSB1<br>A13<br>GEC2/IO69RSB1<br>A14<br>IO65RSB1<br>A15<br>VCC<br>A16<br>IO64RSB1<br>A17<br>IO63RSB1<br>A18<br>IO62RSB1<br>A19<br>IO61RSB1<br>A20<br>IO58RSB1<br>A21<br>GDB2/IO55RSB1<br>A22<br>NC<br>A23<br>GDA2/IO54RSB1<br>A24<br>TDI<br>A25<br>TRST<br>A26<br>GDC1/IO48RSB0<br>A27<br>VCC<br>A28<br>IO47RSB0<br>A29<br>GCC2/IO46RSB0<br>A30<br>GCA2/IO44RSB0<br>A31<br>GCA0/IO43RSB0<br>A32<br>GCB1/IO40RSB0<br>A33<br>IO36RSB0<br>A34<br>VCC<br>A35<br>IO31RSB0<br>A36<br>GBA2/IO28RSB0<br>A37<br>GBB1/IO25RSB0<br>A38<br>GBC0/IO22RSB0<br>A39<br>VCCIB0<br>A40<br>IO21RSB0<br>A41<br>IO18RSB0<br>A42<br>IO15RSB0<br>A43<br>IO14RSB0<br>A44<br>IO11RSB0<br>A45<br>GAB1/IO08RSB0<br>A46<br>NC<br>A47<br>GAB0/IO07RSB0<br>A48<br>IO04RSB0<br>B1<br>IO01RSB1<br>B2<br>GAC2/IO94RSB1<br>B3<br>GND<br>B4<br>GFC0/IO88RSB1<br>B5<br>VCOMPLF<br>B6<br>GND<br>B7<br>GFB2/IO82RSB1<br>B8<br>IO79RSB1<br>B9<br>GND<br>B10<br>GEB0/IO74RSB1<br>B11<br>VMV1<br>B12<br>GEB2/IO70RSB1<br>B13<br>IO67RSB1<br>B14<br>GND<br>B15<br>NC<br>B16<br>NC<br>B17<br>GND<br>B18<br>IO59RSB1<br>B19<br>GDC2/IO56RSB1<br>B20<br>GND<br>B21<br>GNDQ<br>B22<br>TMS<br>B23<br>TDO<br>B24<br>GDC0/IO49RSB0<br>**QN132**<br>**Pin Number**<br>**A3P060 Function**<br>~~en eG ~~Os<br>~~es ee ~~ie~~Ps~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~ss~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~neOs~~<br>~~es ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es ee ~~ie~~Ps~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~neOs~~<br>~~es ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es~~<br>~~ee ~~i<br>~~esOo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~i<br>~~esOo~~<br>~~es~~<br>~~neOs~~<br>~~es ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es ee ~~ie~~Ps~~<br>~~Os~~<br>~~a ee es eo~~<br>~~es~~<br>~~ee ~~i<br>~~esOo~~<br>~~es~~<br>~~neOs~~<br>~~es ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es ee ~~ie~~Ps~~<br>~~Os~~<br>~~a ee es eo~~<br>~~es~~<br>~~ee ~~i<br>~~esOo~~<br>~~es~~<br>~~neOs~~<br>~~es ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es ee ~~ie~~Ps~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~ss~~<br>~~a ee es eo~~<br>~~es~~<br>~~neOs~~<br>~~es~~<br>~~ne ns~~<br>~~Os~~<br>~~es~~<br>~~eeRs~~<br>~~fo~~|B25<br>B26<br>B27<br>B28<br>B29<br>B30<br>B31<br>B32<br>B33<br>B34<br>B35<br>B36<br>B37<br>B38<br>B39<br>B40<br>B41<br>B42<br>B43<br>B44<br>C1<br>C2<br>C3<br>C4<br>C5<br>C6<br>C7<br>C8<br>C9<br>C10<br>C11<br>C12<br>C13<br>C14<br>C15<br>C16<br>**Pin Number**|GND<br>NC<br>GCB2/IO45RSB0<br>GND<br>GCB0/IO41RSB0<br>GCC1/IO38RSB0<br>GND<br>GBB2/IO30RSB0<br>VMV0<br>GBA0/IO26RSB0<br>GBC1/IO23RSB0<br>GND<br>IO20RSB0<br>IO17RSB0<br>GND<br>IO12RSB0<br>GAC0/IO09RSB0<br>GND<br>GAA1/IO06RSB0<br>GNDQ<br>GAA2/IO02RSB1<br>IO95RSB1<br>VCC<br>GFB1/IO87RSB1<br>GFA0/IO85RSB1<br>GFA2/IO83RSB1<br>IO80RSB1<br>VCCIB1<br>GEA1/IO73RSB1<br>GNDQ<br>GEA2/IO71RSB1<br>IO68RSB1<br>VCCIB1<br>NC<br>NC<br>IO60RSB1<br>**QN132**<br>**A3P060 Function**|
|---|---|---|
**Revision 18**
**4-9**
_Package Pin Assignments_
**QN132 Pin Number A3P060 Function** ~~a~~ C17 IO57RSB1 ~~a~~ C18 NC ~~a~~ C19 TCK ~~a~~ C20 VMV1 ~~ee ee~~ C21 VPUMP ~~ee ee~~ C22 VJTAG ~~a~~ C23 VCCIB0 ~~a~~ C24 NC ~~a~~ C25 NC ~~a~~ C26 GCA1/IO42RSB0 ~~ee ee~~ C27 GCC0/IO39RSB0 ~~ee ee~~ C28 VCCIB0 ~~a~~ C29 IO29RSB0 ~~a~~ C30 GNDQ ~~a~~ C31 GBA1/IO27RSB0 ~~a~~ C32 GBB0/IO24RSB0 ~~ee ee~~ C33 VCC ~~ee ee~~ C34 IO19RSB0 ~~a~~ C35 IO16RSB0 ~~a~~ C36 IO13RSB0 ~~a~~ C37 GAC1/IO10RSB0 ~~a~~ C38 NC ~~ee ee~~ C39 GAA0/IO05RSB0 ~~ee ee~~ C40 VMV0 ~~a~~ D1 GND ~~a~~ D2 GND ~~a~~ D3 GND ~~a~~ D4 GND ~~ee ee~~
**4-10**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**QN132**<br>**Pin Number**<br>**A3P125 Function**<br>A1<br>GAB2/IO69RSB1<br>A2<br>IO130RSB1<br>A3<br>VCCIB1<br>A4<br>GFC1/IO126RSB1<br>A5<br>GFB0/IO123RSB1<br>A6<br>VCCPLF<br>A7<br>GFA1/IO121RSB1<br>A8<br>GFC2/IO118RSB1<br>A9<br>IO115RSB1<br>A10<br>VCC<br>A11<br>GEB1/IO110RSB1<br>A12<br>GEA0/IO107RSB1<br>A13<br>GEC2/IO104RSB1<br>A14<br>IO100RSB1<br>A15<br>VCC<br>A16<br>IO99RSB1<br>A17<br>IO96RSB1<br>A18<br>IO94RSB1<br>A19<br>IO91RSB1<br>A20<br>IO85RSB1<br>A21<br>IO79RSB1<br>A22<br>VCC<br>A23<br>GDB2/IO71RSB1<br>A24<br>TDI<br>A25<br>TRST<br>A26<br>GDC1/IO61RSB0<br>A27<br>VCC<br>A28<br>IO60RSB0<br>A29<br>GCC2/IO59RSB0<br>A30<br>GCA2/IO57RSB0<br>A31<br>GCA0/IO56RSB0<br>A32<br>GCB1/IO53RSB0<br>A33<br>IO49RSB0<br>A34<br>VCC<br>A35<br>IO44RSB0<br>A36<br>GBA2/IO41RSB0<br>A37<br>GBB1/IO38RSB0<br>A38<br>GBC0/IO35RSB0<br>A39<br>VCCIB0<br>A40<br>IO28RSB0<br>A41<br>IO22RSB0<br>A42<br>IO18RSB0<br>A43<br>IO14RSB0<br>A44<br>IO11RSB0<br>A45<br>IO07RSB0<br>A46<br>VCC<br>A47<br>GAC1/IO05RSB0<br>A48<br>GAB0/IO02RSB0<br>B1<br>IO68RSB1<br>B2<br>GAC2/IO131RSB1<br>B3<br>GND<br>B4<br>GFC0/IO125RSB1<br>B5<br>VCOMPLF<br>B6<br>GND<br>B7<br>GFB2/IO119RSB1<br>B8<br>IO116RSB1<br>B9<br>GND<br>B10<br>GEB0/IO109RSB1<br>B11<br>VMV1<br>B12<br>GEB2/IO105RSB1<br>B13<br>IO101RSB1<br>B14<br>GND<br>B15<br>IO98RSB1<br>B16<br>IO95RSB1<br>B17<br>GND<br>B18<br>IO87RSB1<br>B19<br>IO81RSB1<br>B20<br>GND<br>B21<br>GNDQ<br>B22<br>TMS<br>B23<br>TDO<br>B24<br>GDC0/IO62RSB0<br>**QN132**<br>**Pin Number**<br>**A3P125 Function**<br>~~en eG ~~Os<br>~~a ee ~~ie~~ee~~<br>~~Os~~<br>~~a ee ee~~<br>~~so~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~ee~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~nnOs~~<br>~~es~~<br>~~ee ~~ie~~en~~<br>~~Oo~~<br>~~a ee ee~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~ee~~<br>~~Os~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~ee~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~nnOs~~<br>~~es~~<br>~~ee ~~ie~~en~~<br>~~Oo~~<br>~~a ee ee~~<br>~~Oo~~<br>~~ee~~<br>~~ee ee~~<br>~~0s~~<br>~~ee~~<br>~~ee ee~~<br>~~Oo~~<br>~~a ee eees~~<br>~~es~~<br>~~ee~~<br>~~nnOs~~<br>~~es~~<br>~~ee ~~ie~~en~~<br>~~Oo~~<br>~~a ee ee~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~ee~~<br>~~Os~~<br>~~a ee eeeo~~<br>~~a ee eees~~<br>~~es~~<br>~~ee~~<br>~~nnOs~~<br>~~es~~<br>~~ee ~~ie~~en~~<br>~~Oo~~<br>~~a ee ee~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~ee~~<br>~~Os~~<br>~~a ee eeeo~~<br>~~a ee eees~~<br>~~es~~<br>~~ee~~<br>~~nnOs~~<br>~~es~~<br>~~ee ~~ie~~en~~<br>~~Oo~~<br>~~a ee ee~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~ee~~<br>~~Os~~<br>~~a ee ee~~<br>~~so~~<br>~~a ee eeeo~~<br>~~es~~<br>~~ee~~<br>~~nnOs~~<br>~~es~~<br>~~ee ~~ie~~Gn~~<br>~~Os~~<br>~~es~~<br>~~eeen~~<br>~~Os~~|B25<br>B26<br>B27<br>B28<br>B29<br>B30<br>B31<br>B32<br>B33<br>B34<br>B35<br>B36<br>B37<br>B38<br>B39<br>B40<br>B41<br>B42<br>B43<br>B44<br>C1<br>C2<br>C3<br>C4<br>C5<br>C6<br>C7<br>C8<br>C9<br>C10<br>C11<br>C12<br>C13<br>C14<br>C15<br>C16<br>**Pin Number**|GND<br>NC<br>GCB2/IO58RSB0<br>GND<br>GCB0/IO54RSB0<br>GCC1/IO51RSB0<br>GND<br>GBB2/IO43RSB0<br>VMV0<br>GBA0/IO39RSB0<br>GBC1/IO36RSB0<br>GND<br>IO26RSB0<br>IO21RSB0<br>GND<br>IO13RSB0<br>IO08RSB0<br>GND<br>GAC0/IO04RSB0<br>GNDQ<br>GAA2/IO67RSB1<br>IO132RSB1<br>VCC<br>GFB1/IO124RSB1<br>GFA0/IO122RSB1<br>GFA2/IO120RSB1<br>IO117RSB1<br>VCCIB1<br>GEA1/IO108RSB1<br>GNDQ<br>GEA2/IO106RSB1<br>IO103RSB1<br>VCCIB1<br>IO97RSB1<br>IO93RSB1<br>IO89RSB1<br>**QN132**<br>**A3P125 Function**|
|---|---|---|
**Revision 18**
**4-11**
_Package Pin Assignments_
|~~pe~~|~~pe~~|
|---|---|
|**QN132**<br>~~pea~~<br>~~eee~~||
|**Pin Number**<br>~~pea~~|**A3P125 Function**<br>~~eee~~|
|C17<br>~~a~~<br>~~a~~|IO83RSB1<br>~~eee~~<br>~~a~~|
|C18<br>~~a~~|VCCIB1<br>~~a~~|
|C19<br>~~a~~<br>~~ee~~|TCK<br>~~a~~<br>~~eee~~|
|C20<br>~~ee~~<br>~~ee~~|VMV1<br>~~eee~~<br>~~ee~~|
|C21<br>~~ee ~~<br>~~ee~~<br>~~ee~~|VPUMP<br> ~~eee~~<br>~~ee~~<br>~~eee~~|
|C22<br>~~ee~~<br>~~ee~~<br>~~es~~|VJTAG<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|C23<br>~~ee ~~<br>~~es~~|VCCIB0<br> ~~eee~~<br>~~eee~~|
|C24<br>~~es ~~<br>~~a~~|NC<br> ~~eee~~<br>~~a~~|
|C25<br>~~a~~<br>~~ee~~|NC<br>~~a~~<br>~~eee~~|
|C26<br>~~ee~~<br>~~ee~~|GCA1/IO55RSB0<br>~~eee~~<br>~~ee~~|
|C27<br>~~ee ~~<br>~~ee~~<br>~~ee~~|GCC0/IO52RSB0<br> ~~eee~~<br>~~ee~~<br>~~eee~~|
|C28<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIB0<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|C29<br>~~ee ~~<br>~~ee~~|IO42RSB0<br> ~~eee~~<br>~~ee~~|
|C30<br>~~ee~~<br>~~a~~|GNDQ<br>~~ee~~<br>~~a~~|
|C31<br>~~a~~<br>~~ee~~|GBA1/IO40RSB0<br>~~a~~<br>~~eee~~|
|C32<br>~~ee~~<br>~~ee~~|GBB0/IO37RSB0<br>~~eee~~<br>~~ee~~|
|C33<br>~~ee ~~<br>~~ee~~<br>~~ee~~|VCC<br> ~~eee~~<br>~~ee~~<br>~~eee~~|
|C34<br>~~ee~~<br>~~ee~~<br>~~es~~|IO24RSB0<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|C35<br>~~ee ~~<br>~~es~~|IO19RSB0<br> ~~eee~~<br>~~eee~~|
|C36<br>~~es ~~<br>~~a~~|IO16RSB0<br> ~~eee~~<br>~~a~~|
|C37<br>~~a~~<br>~~ee~~|IO10RSB0<br>~~a~~<br>~~eee~~|
|C38<br>~~ee~~<br>~~ee~~|VCCIB0<br>~~eee~~<br>~~ee~~|
|C39<br>~~ee ~~<br>~~ee~~<br>~~ee~~|GAB1/IO03RSB0<br> ~~eee~~<br>~~ee~~<br>~~eee~~|
|C40<br>~~ee~~<br>~~ee~~<br>~~es~~|VMV0<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|D1<br>~~ee ~~<br>~~es~~|GND<br> ~~eee~~<br>~~eee~~|
|D2<br>~~es ~~<br>~~a~~|GND<br> ~~eee~~<br>~~a~~|
|D3<br>~~a~~<br>~~ee~~|GND<br>~~a~~<br>~~ee~~|
|D4<br>~~ee~~|GND<br>~~ee~~|
**4-12**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**QN132**<br>**Pin Number**<br>**A3P250 Function**<br>A1<br>GAB2/IO117UPB3<br>A2<br>IO117VPB3<br>A3<br>VCCIB3<br>A4<br>GFC1/IO110PDB3<br>A5<br>GFB0/IO109NPB3<br>A6<br>VCCPLF<br>A7<br>GFA1/IO108PPB3<br>A8<br>GFC2/IO105PPB3<br>A9<br>IO103NDB3<br>A10<br>VCC<br>A11<br>GEA1/IO98PPB3<br>A12<br>GEA0/IO98NPB3<br>A13<br>GEC2/IO95RSB2<br>A14<br>IO91RSB2<br>A15<br>VCC<br>A16<br>IO90RSB2<br>A17<br>IO87RSB2<br>A18<br>IO85RSB2<br>A19<br>IO82RSB2<br>A20<br>IO76RSB2<br>A21<br>IO70RSB2<br>A22<br>VCC<br>A23<br>GDB2/IO62RSB2<br>A24<br>TDI<br>A25<br>TRST<br>A26<br>GDC1/IO58UDB1<br>A27<br>VCC<br>A28<br>IO54NDB1<br>A29<br>IO52NDB1<br>A30<br>GCA2/IO51PPB1<br>A31<br>GCA0/IO50NPB1<br>A32<br>GCB1/IO49PDB1<br>A33<br>IO47NSB1<br>A34<br>VCC<br>A35<br>IO41NPB1<br>A36<br>GBA2/IO41PPB1<br>A37<br>GBB1/IO38RSB0<br>A38<br>GBC0/IO35RSB0<br>A39<br>VCCIB0<br>A40<br>IO28RSB0<br>A41<br>IO22RSB0<br>A42<br>IO18RSB0<br>A43<br>IO14RSB0<br>A44<br>IO11RSB0<br>A45<br>IO07RSB0<br>A46<br>VCC<br>A47<br>GAC1/IO05RSB0<br>A48<br>GAB0/IO02RSB0<br>B1<br>IO118VDB3<br>B2<br>GAC2/IO116UDB3<br>B3<br>GND<br>B4<br>GFC0/IO110NDB3<br>B5<br>VCOMPLF<br>B6<br>GND<br>B7<br>GFB2/IO106PSB3<br>B8<br>IO103PDB3<br>B9<br>GND<br>B10<br>GEB0/IO99NDB3<br>B11<br>VMV3<br>B12<br>GEB2/IO96RSB2<br>B13<br>IO92RSB2<br>B14<br>GND<br>B15<br>IO89RSB2<br>B16<br>IO86RSB2<br>B17<br>GND<br>B18<br>IO78RSB2<br>B19<br>IO72RSB2<br>B20<br>GND<br>B21<br>GNDQ<br>B22<br>TMS<br>B23<br>TDO<br>B24<br>GDC0/IO58VDB1<br>**QN132**<br>**Pin Number**<br>**A3P250 Function**<br>B25<br>GND<br>B26<br>IO54PDB1<br>B27<br>GCB2/IO52PDB1<br>B28<br>GND<br>B29<br>GCB0/IO49NDB1<br>B30<br>GCC1/IO48PDB1<br>B31<br>GND<br>B32<br>GBB2/IO42PDB1<br>B33<br>VMV1<br>B34<br>GBA0/IO39RSB0<br>B35<br>GBC1/IO36RSB0<br>B36<br>GND<br>B37<br>IO26RSB0<br>B38<br>IO21RSB0<br>B39<br>GND<br>B40<br>IO13RSB0<br>B41<br>IO08RSB0<br>B42<br>GND<br>B43<br>GAC0/IO04RSB0<br>B44<br>GNDQ<br>C1<br>GAA2/IO118UDB3<br>C2<br>IO116VDB3<br>C3<br>VCC<br>C4<br>GFB1/IO109PPB3<br>C5<br>GFA0/IO108NPB3<br>C6<br>GFA2/IO107PSB3<br>C7<br>IO105NPB3<br>C8<br>VCCIB3<br>C9<br>GEB1/IO99PDB3<br>C10<br>GNDQ<br>C11<br>GEA2/IO97RSB2<br>C12<br>IO94RSB2<br>C13<br>VCCIB2<br>C14<br>IO88RSB2<br>C15<br>IO84RSB2<br>C16<br>IO80RSB2<br>**QN132**<br>**Pin Number**<br>**A3P250 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**Revision 18**
**4-13**
_Package Pin Assignments_
**QN132 Pin Number A3P250 Function** ~~a~~ C17 IO74RSB2 ~~a~~ C18 VCCIB2 ~~a~~ C19 TCK ~~a~~ C20 VMV2 ~~ee ee~~ C21 VPUMP ~~a eee~~ C22 VJTAG ~~a ee~~ C23 VCCIB1 ~~a~~ C24 IO53NSB1 ~~a~~ C25 IO51NPB1 ~~a~~ C26 GCA1/IO50PPB1 ~~ee ee~~ C27 GCC0/IO48NDB1 ~~a eee~~ C28 VCCIB1 ~~a ee~~ C29 IO42NDB1 ~~a~~ C30 GNDQ ~~a~~ C31 GBA1/IO40RSB0 ~~a~~ C32 GBB0/IO37RSB0 ~~ee ee~~ C33 VCC ~~a eee~~ C34 IO24RSB0 ~~a ee~~ C35 IO19RSB0 ~~a~~ C36 IO16RSB0 ~~a~~ C37 IO10RSB0 ~~a~~ C38 VCCIB0 ~~ee ee~~ C39 GAB1/IO03RSB0 ~~a eee~~ C40 VMV0 ~~a ee~~ D1 GND ~~a~~ D2 GND ~~a~~ D3 GND ~~a~~ D4 GND ~~ee eee~~
**4-14**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **CS121 – Bottom View**
|11 10<br>1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9||
|---|---|
|OOOOOOOCO00O|A|
|OOOOOCOOC0O0O|B|
|OOOOOOOOC0O0O0O|C|
|OOOOOCOOC0O0CO|D|
|OOOOOCOOC0O0O0O|E|
|OODOOQOOO0O0O00O|F|
|OOOOOCOOOCO00O|G|
|OOOOOOOOC0O0O0O|H|
|OOOOOCOOC0O0O|J|
|OOOOOOOC0O0CO|K|
|OOOOOCOOCO0O|L|
_Note: The die attach paddle center of the package is tied to ground (GND)._
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**Revision 18**
**4-15**
_Package Pin Assignments_
|**CS121**<br>**Pin Number**<br>**A3P060 Function**<br>A1<br>GNDQ<br>A2<br>IO01RSB0<br>A3<br>GAA1/IO03RSB0<br>A4<br>GAC1/IO07RSB0<br>A5<br>IO15RSB0<br>A6<br>IO13RSB0<br>A7<br>IO17RSB0<br>A8<br>GBB1/IO22RSB0<br>A9<br>GBA1/IO24RSB0<br>A10<br>GNDQ<br>A11<br>VMV0<br>B1<br>GAA2/IO95RSB1<br>B2<br>IO00RSB0<br>B3<br>GAA0/IO02RSB0<br>B4<br>GAC0/IO06RSB0<br>B5<br>IO08RSB0<br>B6<br>IO12RSB0<br>B7<br>IO16RSB0<br>B8<br>GBC1/IO20RSB0<br>B9<br>GBB0/IO21RSB0<br>B10<br>GBB2/IO27RSB0<br>B11<br>GBA2/IO25RSB0<br>C1<br>IO89RSB1<br>C2<br>GAC2/IO91RSB1<br>C3<br>GAB1/IO05RSB0<br>C4<br>GAB0/IO04RSB0<br>C5<br>IO09RSB0<br>C6<br>IO14RSB0<br>C7<br>GBA0/IO23RSB0<br>C8<br>GBC0/IO19RSB0<br>C9<br>IO26RSB0<br>C10<br>IO28RSB0<br>C11<br>GBC2/IO29RSB0<br>D1<br>IO88RSB1<br>D2<br>IO90RSB1<br>D3<br>GAB2/IO93RSB1<br>D4<br>IO10RSB0<br>D5<br>IO11RSB0<br>D6<br>IO18RSB0<br>D7<br>IO32RSB0<br>D8<br>IO31RSB0<br>D9<br>GCA2/IO41RSB0<br>D10<br>IO30RSB0<br>D11<br>IO33RSB0<br>E1<br>IO87RSB1<br>E2<br>GFC0/IO85RSB1<br>E3<br>IO92RSB1<br>E4<br>IO94RSB1<br>E5<br>VCC<br>E6<br>VCCIB0<br>E7<br>GND<br>E8<br>GCC0/IO36RSB0<br>E9<br>IO34RSB0<br>E10<br>GCB1/IO37RSB0<br>E11<br>GCC1/IO35RSB0<br>F1<br>VCOMPLF<br>F2<br>GFB0/IO83RSB1<br>F3<br>GFA0/IO82RSB1<br>F4<br>GFC1/IO86RSB1<br>F5<br>VCCIB1<br>F6<br>VCC<br>F7<br>VCCIB0<br>F8<br>GCB2/IO42RSB0<br>F9<br>GCC2/IO43RSB0<br>F10<br>GCB0/IO38RSB0<br>F11<br>GCA1/IO39RSB0<br>G1<br>VCCPLF<br>G2<br>GFB2/IO79RSB1<br>G3<br>GFA1/IO81RSB1<br>G4<br>GFB1/IO84RSB1<br>G5<br>GND<br>G6<br>VCCIB1<br>**CS121**<br>**Pin Number**<br>**A3P060 Function**<br>~~es0~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~ae~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~0~~<br>~~a~~<br>~~es es ee~~<br>~~ee~~<br>~~soRs~~<br>~~0~~<br>~~ee~~<br>~~se~~<br>~~ns0~~<br>~~ee~~<br>~~eses~~<br>~~0~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~0~~<br>~~a~~<br>~~es es ee~~<br>~~ee~~<br>~~soRs~~<br>~~0~~<br>~~ee~~<br>~~se~~<br>~~ns0~~<br>~~ee~~<br>~~eses~~<br>~~0~~<br>~~ee~~<br>~~es es~~<br>~~0~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~re~~<br>~~ee~~<br>~~es~~<br>~~0~~<br>~~ee~~<br>~~soRs~~<br>~~0~~<br>~~ee~~<br>~~se~~<br>~~ns0~~<br>~~ee~~<br>~~eses~~<br>~~0~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~ae~~<br>~~es~~<br>~~es~~<br>~~0 ee~~<br>~~re~~<br>~~ee~~<br>~~es~~<br>~~0~~<br>~~ee~~<br>~~soRs~~<br>~~0~~<br>~~ee~~<br>~~se~~<br>~~ns0~~<br>~~ee~~<br>~~eses~~<br>~~0~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~ae~~<br>~~es~~<br>~~es~~<br>~~0 ee~~<br>~~re~~<br>~~ee~~<br>~~es~~<br>~~0~~<br>~~ee~~<br>~~soRs~~<br>~~0~~<br>~~ee~~<br>~~se~~<br>~~ns0~~<br>~~ee~~<br>~~eses~~<br>~~0~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~ae~~<br>~~es~~<br>~~es~~<br>~~0~~<br>~~ae~~<br>~~es~~<br>~~es~~<br>~~0 ee~~<br>~~ee~~<br>~~soRs~~<br>~~0~~<br>~~ee~~<br>~~eses~~<br>~~0~~<br>~~ee~~<br>~~sees~~|0<br>0<br>~~ee~~<br>~~ee~~<br>~~ee~~|G7<br>VCC<br>G8<br>GDC0/IO46RSB0<br>G9<br>GDA1/IO49RSB0<br>G10<br>GDB0/IO48RSB0<br>G11<br>GCA0/IO40RSB0<br>H1<br>IO75RSB1<br>H2<br>IO76RSB1<br>H3<br>GFC2/IO78RSB1<br>H4<br>GFA2/IO80RSB1<br>H5<br>IO77RSB1<br>H6<br>GEC2/IO66RSB1<br>H7<br>IO54RSB1<br>H8<br>GDC2/IO53RSB1<br>H9<br>VJTAG<br>H10<br>TRST<br>H11<br>IO44RSB0<br>J1<br>GEC1/IO74RSB1<br>J2<br>GEC0/IO73RSB1<br>J3<br>GEB1/IO72RSB1<br>J4<br>GEA0/IO69RSB1<br>J5<br>GEB2/IO67RSB1<br>J6<br>IO62RSB1<br>J7<br>GDA2/IO51RSB1<br>J8<br>GDB2/IO52RSB1<br>J9<br>TDI<br>J10<br>TDO<br>J11<br>GDC1/IO45RSB0<br>K1<br>GEB0/IO71RSB1<br>K2<br>GEA1/IO70RSB1<br>K3<br>GEA2/IO68RSB1<br>K4<br>IO64RSB1<br>K5<br>IO60RSB1<br>K6<br>IO59RSB1<br>K7<br>IO56RSB1<br>K8<br>TCK<br>K9<br>TMS<br>**CS121**<br>**Pin Number**<br>**A3P060 Function**<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|---|---|---|
**4-16**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**CS121**|**CS121**|
|---|---|
|**Pin Number**|**A3P060 Function**|
|K10|VPUMP|
|K11|GDB1/IO47RSB0|
|L1|VMV1|
|L2|GNDQ|
|L3|IO65RSB1|
|L4|IO63RSB1|
|L5|IO61RSB1|
|L6|IO58RSB1|
|L7|IO57RSB1|
|L8|IO55RSB1|
|L9|GNDQ|
|L10|GDA0/IO50RSB0|
|L11|VMV1|
**Revision 18**
**4-17**
_Package Pin Assignments_
## **VQ100 – Top View**
|||||100|100|100|
|---|---|---|---|---|---|---|
|1|||~~_~~|~~_~~|~~TOU~~<br>~~POLE~~<br>~~_~~|~~TOU~~<br>~~POLE~~<br>~~_~~|
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-18**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**VQ100**<br>**Pin Number**<br>**A3P030 Function**<br>1<br>GND<br>2<br>IO82RSB1<br>3<br>IO81RSB1<br>4<br>IO80RSB1<br>5<br>IO79RSB1<br>6<br>IO78RSB1<br>7<br>IO77RSB1<br>8<br>IO76RSB1<br>9<br>GND<br>10<br>IO75RSB1<br>11<br>IO74RSB1<br>12<br>GEC0/IO73RSB1<br>13<br>GEA0/IO72RSB1<br>14<br>GEB0/IO71RSB1<br>15<br>IO70RSB1<br>16<br>IO69RSB1<br>17<br>VCC<br>18<br>VCCIB1<br>19<br>IO68RSB1<br>20<br>IO67RSB1<br>21<br>IO66RSB1<br>22<br>IO65RSB1<br>23<br>IO64RSB1<br>24<br>IO63RSB1<br>25<br>IO62RSB1<br>26<br>IO61RSB1<br>27<br>IO60RSB1<br>28<br>IO59RSB1<br>29<br>IO58RSB1<br>30<br>IO57RSB1<br>31<br>IO56RSB1<br>32<br>IO55RSB1<br>33<br>IO54RSB1<br>34<br>IO53RSB1<br>35<br>IO52RSB1<br>36<br>IO51RSB1<br>37<br>VCC<br>38<br>GND<br>39<br>VCCIB1<br>40<br>IO49RSB1<br>41<br>IO47RSB1<br>42<br>IO46RSB1<br>43<br>IO45RSB1<br>44<br>IO44RSB1<br>45<br>IO43RSB1<br>46<br>IO42RSB1<br>47<br>TCK<br>48<br>TDI<br>49<br>TMS<br>50<br>NC<br>51<br>GND<br>52<br>VPUMP<br>53<br>NC<br>54<br>TDO<br>55<br>TRST<br>56<br>VJTAG<br>57<br>IO41RSB0<br>58<br>IO40RSB0<br>59<br>IO39RSB0<br>60<br>IO38RSB0<br>61<br>IO37RSB0<br>62<br>IO36RSB0<br>63<br>GDB0/IO34RSB0<br>64<br>GDA0/IO33RSB0<br>65<br>GDC0/IO32RSB0<br>66<br>VCCIB0<br>67<br>GND<br>68<br>VCC<br>69<br>IO31RSB0<br>70<br>IO30RSB0<br>71<br>IO29RSB0<br>72<br>IO28RSB0<br>**VQ100**<br>**Pin Number**<br>**A3P030 Function**<br>~~es0~~<br>~~ee~~<br>~~es Re~~<br>~~0~~<br>~~ae~~<br>~~es0~~<br>~~a es ee~~<br>~~0 es~~<br>~~a es ee~~<br>~~0~~<br>~~es~~<br>~~es eR 0~~<br>~~es~~<br>~~se Pe 0~~<br>~~ee~~<br>~~es0~~<br>~~ee~~<br>~~es0~~<br>~~a es ee~~<br>~~0 es~~<br>~~a es ee~~<br>~~0~~<br>~~es~~<br>~~es eR 0~~<br>~~es~~<br>~~se Pe 0~~<br>~~ee~~<br>~~es0~~<br>~~a~~<br>~~es0~~<br>~~a es Re~~<br>~~0~~<br>~~a~~<br>~~ee Pe 0 es~~<br>~~es~~<br>~~es eR 0~~<br>~~es~~<br>~~se Pe 0~~<br>~~ee~~<br>~~es0~~<br>~~ee~~<br>~~es0~~<br>~~a~~<br>~~es ee~~<br>~~0 es~~<br>~~a~~<br>~~ee Pe 0 es~~<br>~~es~~<br>~~es eR 0~~<br>~~es~~<br>~~se Pe 0~~<br>~~ee~~<br>~~es0~~<br>~~ee~~<br>~~es0~~<br>~~a~~<br>~~es ee~~<br>~~0 es~~<br>~~a~~<br>~~ee Pe 0 es~~<br>~~es~~<br>~~se0~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee es~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~<br>~~ee~~<br>~~es~~<br>~~ee ee~~<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|73<br>IO27RSB0<br>74<br>IO26RSB0<br>75<br>IO25RSB0<br>76<br>IO24RSB0<br>77<br>IO23RSB0<br>78<br>IO22RSB0<br>79<br>IO21RSB0<br>80<br>IO20RSB0<br>81<br>IO19RSB0<br>82<br>IO18RSB0<br>83<br>IO17RSB0<br>84<br>IO16RSB0<br>85<br>IO15RSB0<br>86<br>IO14RSB0<br>87<br>VCCIB0<br>88<br>GND<br>89<br>VCC<br>90<br>IO12RSB0<br>91<br>IO10RSB0<br>92<br>IO08RSB0<br>93<br>IO07RSB0<br>94<br>IO06RSB0<br>95<br>IO05RSB0<br>96<br>IO04RSB0<br>97<br>IO03RSB0<br>98<br>IO02RSB0<br>99<br>IO01RSB0<br>100<br>IO00RSB0<br>**VQ100**<br>**Pin Number**<br>**A3P030 Function**<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|
|---|---|---|
**Revision 18**
**4-19**
_Package Pin Assignments_
|**VQ100**<br>**Pin Number**<br>**A3P060 Function**<br>1<br>GND<br>2<br>GAA2/IO51RSB1<br>3<br>IO52RSB1<br>4<br>GAB2/IO53RSB1<br>5<br>IO95RSB1<br>6<br>GAC2/IO94RSB1<br>7<br>IO93RSB1<br>8<br>IO92RSB1<br>9<br>GND<br>10<br>GFB1/IO87RSB1<br>11<br>GFB0/IO86RSB1<br>12<br>VCOMPLF<br>13<br>GFA0/IO85RSB1<br>14<br>VCCPLF<br>15<br>GFA1/IO84RSB1<br>16<br>GFA2/IO83RSB1<br>17<br>VCC<br>18<br>VCCIB1<br>19<br>GEC1/IO77RSB1<br>20<br>GEB1/IO75RSB1<br>21<br>GEB0/IO74RSB1<br>22<br>GEA1/IO73RSB1<br>23<br>GEA0/IO72RSB1<br>24<br>VMV1<br>25<br>GNDQ<br>26<br>GEA2/IO71RSB1<br>27<br>GEB2/IO70RSB1<br>28<br>GEC2/IO69RSB1<br>29<br>IO68RSB1<br>30<br>IO67RSB1<br>31<br>IO66RSB1<br>32<br>IO65RSB1<br>33<br>IO64RSB1<br>34<br>IO63RSB1<br>35<br>IO62RSB1<br>36<br>IO61RSB1<br>37<br>VCC<br>38<br>GND<br>39<br>VCCIB1<br>40<br>IO60RSB1<br>41<br>IO59RSB1<br>42<br>IO58RSB1<br>43<br>IO57RSB1<br>44<br>GDC2/IO56RSB1<br>45<br>GDB2/IO55RSB1<br>46<br>GDA2/IO54RSB1<br>47<br>TCK<br>48<br>TDI<br>49<br>TMS<br>50<br>VMV1<br>51<br>GND<br>52<br>VPUMP<br>53<br>NC<br>54<br>TDO<br>55<br>TRST<br>56<br>VJTAG<br>57<br>GDA1/IO49RSB0<br>58<br>GDC0/IO46RSB0<br>59<br>GDC1/IO45RSB0<br>60<br>GCC2/IO43RSB0<br>61<br>GCB2/IO42RSB0<br>62<br>GCA0/IO40RSB0<br>63<br>GCA1/IO39RSB0<br>64<br>GCC0/IO36RSB0<br>65<br>GCC1/IO35RSB0<br>66<br>VCCIB0<br>67<br>GND<br>68<br>VCC<br>69<br>IO31RSB0<br>70<br>GBC2/IO29RSB0<br>71<br>GBB2/IO27RSB0<br>72<br>IO26RSB0<br>**VQ100**<br>**Pin Number**<br>**A3P060 Function**<br>~~es ~~ie~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~es~~<br>~~Os~~<br>~~es ee ~~ie<br>~~es~~<br>~~ss~~<br>~~es~~<br>~~ee es~~<br>~~ss~~<br>~~es~~<br>~~ee ~~ie ~~es~~<br>~~so~~<br>~~es~~<br>~~ees(n~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie~~Ds~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~ss~~<br>~~es~~<br>~~ee ~~ie ~~es~~<br>~~so~~<br>~~es~~<br>~~ees(n~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie~~Ds~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~ss~~<br>~~es~~<br>~~ee ~~ie~~Ps es~~<br>~~es~~<br>~~ees(n~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie~~Ds~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~es~~<br>~~Os~~<br>~~es~~<br>~~ee esGo~~<br>~~es~~<br>~~ee ~~ie~~Ps es~~<br>~~es~~<br>~~ees(n~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie~~Ds~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~es~~<br>~~Os~~<br>~~es~~<br>~~ee esGo~~<br>~~es~~<br>~~ee ~~ie~~Ps es~~<br>~~es~~<br>~~ne~~<br>~~ns~~<br>~~Os~~<br>~~es~~<br>~~eeee~~<br>~~ee~~<br>~~eeee~~<br>~~a~~<br>~~eeee~~<br>~~ee~~<br>~~ee es~~<br>~~ee~~<br>~~eeee~~<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~eeee~~|73<br>74<br>75<br>76<br>77<br>78<br>79<br>80<br>81<br>82<br>83<br>84<br>85<br>86<br>87<br>88<br>89<br>90<br>91<br>92<br>93<br>94<br>95<br>96<br>97<br>98<br>99<br>100<br>**Pin Number**|GBA2/IO25RSB0<br>VMV0<br>GNDQ<br>GBA1/IO24RSB0<br>GBA0/IO23RSB0<br>GBB1/IO22RSB0<br>GBB0/IO21RSB0<br>GBC1/IO20RSB0<br>GBC0/IO19RSB0<br>IO18RSB0<br>IO17RSB0<br>IO15RSB0<br>IO13RSB0<br>IO11RSB0<br>VCCIB0<br>GND<br>VCC<br>IO10RSB0<br>IO09RSB0<br>IO08RSB0<br>GAC1/IO07RSB0<br>GAC0/IO06RSB0<br>GAB1/IO05RSB0<br>GAB0/IO04RSB0<br>GAA1/IO03RSB0<br>GAA0/IO02RSB0<br>IO01RSB0<br>IO00RSB0<br>**VQ100**<br>**A3P060 Function**|
|---|---|---|
**4-20**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**VQ100**<br>**Pin Number**<br>**A3P125 Function**<br>1<br>GND<br>2<br>GAA2/IO67RSB1<br>3<br>IO68RSB1<br>4<br>GAB2/IO69RSB1<br>5<br>IO132RSB1<br>6<br>GAC2/IO131RSB1<br>7<br>IO130RSB1<br>8<br>IO129RSB1<br>9<br>GND<br>10<br>GFB1/IO124RSB1<br>11<br>GFB0/IO123RSB1<br>12<br>VCOMPLF<br>13<br>GFA0/IO122RSB1<br>14<br>VCCPLF<br>15<br>GFA1/IO121RSB1<br>16<br>GFA2/IO120RSB1<br>17<br>VCC<br>18<br>VCCIB1<br>19<br>GEC0/IO111RSB1<br>20<br>GEB1/IO110RSB1<br>21<br>GEB0/IO109RSB1<br>22<br>GEA1/IO108RSB1<br>23<br>GEA0/IO107RSB1<br>24<br>VMV1<br>25<br>GNDQ<br>26<br>GEA2/IO106RSB1<br>27<br>GEB2/IO105RSB1<br>28<br>GEC2/IO104RSB1<br>29<br>IO102RSB1<br>30<br>IO100RSB1<br>31<br>IO99RSB1<br>32<br>IO97RSB1<br>33<br>IO96RSB1<br>34<br>IO95RSB1<br>35<br>IO94RSB1<br>36<br>IO93RSB1<br>37<br>VCC<br>38<br>GND<br>39<br>VCCIB1<br>40<br>IO87RSB1<br>41<br>IO84RSB1<br>42<br>IO81RSB1<br>43<br>IO75RSB1<br>44<br>GDC2/IO72RSB1<br>45<br>GDB2/IO71RSB1<br>46<br>GDA2/IO70RSB1<br>47<br>TCK<br>48<br>TDI<br>49<br>TMS<br>50<br>VMV1<br>51<br>GND<br>52<br>VPUMP<br>53<br>NC<br>54<br>TDO<br>55<br>TRST<br>56<br>VJTAG<br>57<br>GDA1/IO65RSB0<br>58<br>GDC0/IO62RSB0<br>59<br>GDC1/IO61RSB0<br>60<br>GCC2/IO59RSB0<br>61<br>GCB2/IO58RSB0<br>62<br>GCA0/IO56RSB0<br>63<br>GCA1/IO55RSB0<br>64<br>GCC0/IO52RSB0<br>65<br>GCC1/IO51RSB0<br>66<br>VCCIB0<br>67<br>GND<br>68<br>VCC<br>69<br>IO47RSB0<br>70<br>GBC2/IO45RSB0<br>71<br>GBB2/IO43RSB0<br>72<br>IO42RSB0<br>**VQ100**<br>**Pin Number**<br>**A3P125 Function**<br>73<br>GBA2/IO41RSB0<br>74<br>VMV0<br>75<br>GNDQ<br>76<br>GBA1/IO40RSB0<br>77<br>GBA0/IO39RSB0<br>78<br>GBB1/IO38RSB0<br>79<br>GBB0/IO37RSB0<br>80<br>GBC1/IO36RSB0<br>81<br>GBC0/IO35RSB0<br>82<br>IO32RSB0<br>83<br>IO28RSB0<br>84<br>IO25RSB0<br>85<br>IO22RSB0<br>86<br>IO19RSB0<br>87<br>VCCIB0<br>88<br>GND<br>89<br>VCC<br>90<br>IO15RSB0<br>91<br>IO13RSB0<br>92<br>IO11RSB0<br>93<br>IO09RSB0<br>94<br>IO07RSB0<br>95<br>GAC1/IO05RSB0<br>96<br>GAC0/IO04RSB0<br>97<br>GAB1/IO03RSB0<br>98<br>GAB0/IO02RSB0<br>99<br>GAA1/IO01RSB0<br>100<br>GAA0/IO00RSB0<br>**VQ100**<br>**Pin Number**<br>**A3P125 Function**<br>~~ee ~~ie~~Os~~<br>~~a ee es~~<br>~~Os~~<br>~~a ee ~~ie~~es~~<br>~~Os~~<br>~~a~~<br>~~ee eeeo~~<br>~~ee ~~ie~~es~~<br>~~Oses~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~a ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a~~<br>~~ee eeeo~~<br>~~ee ~~ie~~es~~<br>~~Oses~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~a ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee eseo~~<br>~~ee ~~ie~~eses ~~Oo<br>~~a ee ee~~<br>~~so~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~a ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ee~~<br>~~so~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~a ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ee~~<br>~~so~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eeee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~|
|---|
**Revision 18**
**4-21**
_Package Pin Assignments_
|**VQ100**<br>**Pin Number**<br>**A3P250 Function**<br>1<br>GND<br>2<br>GAA2/IO118UDB3<br>3<br>IO118VDB3<br>4<br>GAB2/IO117UDB3<br>5<br>IO117VDB3<br>6<br>GAC2/IO116UDB3<br>7<br>IO116VDB3<br>8<br>IO112PSB3<br>9<br>GND<br>10<br>GFB1/IO109PDB3<br>11<br>GFB0/IO109NDB3<br>12<br>VCOMPLF<br>13<br>GFA0/IO108NPB3<br>14<br>VCCPLF<br>15<br>GFA1/IO108PPB3<br>16<br>GFA2/IO107PSB3<br>17<br>VCC<br>18<br>VCCIB3<br>19<br>GFC2/IO105PSB3<br>20<br>GEC1/IO100PDB3<br>21<br>GEC0/IO100NDB3<br>22<br>GEA1/IO98PDB3<br>23<br>GEA0/IO98NDB3<br>24<br>VMV3<br>25<br>GNDQ<br>26<br>GEA2/IO97RSB2<br>27<br>GEB2/IO96RSB2<br>28<br>GEC2/IO95RSB2<br>29<br>IO93RSB2<br>30<br>IO92RSB2<br>31<br>IO91RSB2<br>32<br>IO90RSB2<br>33<br>IO88RSB2<br>34<br>IO86RSB2<br>35<br>IO85RSB2<br>36<br>IO84RSB2<br>37<br>VCC<br>38<br>GND<br>39<br>VCCIB2<br>40<br>IO77RSB2<br>41<br>IO74RSB2<br>42<br>IO71RSB2<br>43<br>GDC2/IO63RSB2<br>44<br>GDB2/IO62RSB2<br>45<br>GDA2/IO61RSB2<br>46<br>GNDQ<br>47<br>TCK<br>48<br>TDI<br>49<br>TMS<br>50<br>VMV2<br>51<br>GND<br>52<br>VPUMP<br>53<br>NC<br>54<br>TDO<br>55<br>TRST<br>56<br>VJTAG<br>57<br>GDA1/IO60USB1<br>58<br>GDC0/IO58VDB1<br>59<br>GDC1/IO58UDB1<br>60<br>IO52NDB1<br>61<br>GCB2/IO52PDB1<br>62<br>GCA1/IO50PDB1<br>63<br>GCA0/IO50NDB1<br>64<br>GCC0/IO48NDB1<br>65<br>GCC1/IO48PDB1<br>66<br>VCCIB1<br>67<br>GND<br>68<br>VCC<br>69<br>IO43NDB1<br>70<br>GBC2/IO43PDB1<br>71<br>GBB2/IO42PSB1<br>72<br>IO41NDB1<br>**VQ100**<br>**Pin Number**<br>**A3P250 Function**<br>~~re ~~ie~~Os~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~ee~~<br>~~ee es~~<br>~~ss~~<br>~~ee~~<br>~~ee ~~i<br>~~es~~<br>~~so~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~ss~~<br>~~ee~~<br>~~ee ~~i<br>~~es~~<br>~~so~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~re~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~eeeses ~~Oo<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~so~~<br>~~ee~~<br>~~eeeses ~~Oo<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~so~~<br>~~ee~~<br>~~eeeses ~~Oo<br>~~ee~~<br>~~eeGs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~a ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~|73<br>74<br>75<br>76<br>77<br>78<br>79<br>80<br>81<br>82<br>83<br>84<br>85<br>86<br>87<br>88<br>89<br>90<br>91<br>92<br>93<br>94<br>95<br>96<br>97<br>98<br>99<br>100<br>**Pin Number**<br>~~I~~<br>~~I~~<br>~~I~~<br>~~I~~|GBA2/IO41PDB1<br>VMV1<br>GNDQ<br>GBA1/IO40RSB0<br>GBA0/IO39RSB0<br>GBB1/IO38RSB0<br>GBB0/IO37RSB0<br>GBC1/IO36RSB0<br>GBC0/IO35RSB0<br>IO29RSB0<br>IO27RSB0<br>IO25RSB0<br>IO23RSB0<br>IO21RSB0<br>VCCIB0<br>GND<br>VCC<br>IO15RSB0<br>IO13RSB0<br>IO11RSB0<br>GAC1/IO05RSB0<br>GAC0/IO04RSB0<br>GAB1/IO03RSB0<br>GAB0/IO02RSB0<br>GAA1/IO01RSB0<br>GAA0/IO00RSB0<br>GNDQ<br>VMV0<br>**VQ100**<br>**A3P250 Function**|
|---|---|---|
**4-22**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **TQ144 – Top View**
**==> picture [174 x 166] intentionally omitted <==**
**----- Start of picture text -----**<br>
144<br>1<br>144-Pin<br>TQFP<br>**----- End of picture text -----**<br>
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**Revision 18**
**4-23**
_Package Pin Assignments_
**==> picture [465 x 650] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|TQ144|TQ144|TQ144|
|es|ie|Os|
|Pin Number|A3P060 Function|Pin Number|A3P060 Function|Pin Number|A3P060 Function|
|es|ee|ie|es|Os|
|1|GAA2/IO51RSB1|37|NC|73|VPUMP|
|es|ee|ie|es|ss|
|2|IO52RSB1|38|GEA2/IO71RSB1|74|NC|
|es|ee es|ss|
|3|GAB2/IO53RSB1|39|GEB2/IO70RSB1|75|TDO|
|es|ee|ie|es|so|
|4|IO95RSB1|40|GEC2/IO69RSB1|76|TRST|
|es|ees(n|
|5|GAC2/IO94RSB1|41|IO68RSB1|77|VJTAG|
|es|ee es|Os|
|6|IO93RSB1|42|IO67RSB1|78|GDA0/IO50RSB0|
|es|ee|ie|Ds|Os|
|7|IO92RSB1|43|IO66RSB1|79|GDB0/IO48RSB0|
|es|ee|ie|es|Os|
|8|IO91RSB1|44|IO65RSB1|80|GDB1/IO47RSB0|
|es|ee es|ss|
|9|VCC|45|VCC|81|VCCIB0|
|es|ee|ie|es|so|
|10|GND|46|GND|82|GND|
|es|ees(n|
|11|VCCIB1|47|VCCIB1|83|IO44RSB0|
|es|ee es|Os|
|12|IO90RSB1|48|NC|84|GCC2/IO43RSB0|
|es|ee|ie|Ds|Os|
|13|GFC1/IO89RSB1|49|IO64RSB1|85|GCB2/IO42RSB0|
|es|ee|ie|es|Oo|
|14|GFC0/IO88RSB1|50|NC|86|GCA2/IO41RSB0|
|es|ee|ie|es|ss|
|15|GFB1/IO87RSB1|51|IO63RSB1|87|GCA0/IO40RSB0|
|es|ee|ie|Ps es|
|16|GFB0/IO86RSB1|52|NC|88|GCA1/IO39RSB0|
|es|ees(n|
|17|VCOMPLF|53|IO62RSB1|89|GCB0/IO38RSB0|
|es|ee es|Os|
|18|GFA0/IO85RSB1|54|NC|90|GCB1/IO37RSB0|
|es|ee|ie|Ds|Os|
|19|VCCPLF|55|IO61RSB1|91|GCC0/IO36RSB0|
|es|ee|ie|es|Os|
|20|GFA1/IO84RSB1|56|NC|92|GCC1/IO35RSB0|
|es|ee es|Go|
|21|GFA2/IO83RSB1|57|NC|93|IO34RSB0|
|es|ee|ie|Ps es|
|22|GFB2/IO82RSB1|58|IO60RSB1|94|IO33RSB0|
|es|ees(n|
|23|GFC2/IO81RSB1|59|IO59RSB1|95|NC|
|es|ee es|Os|
|24|IO80RSB1|60|IO58RSB1|96|NC|
|es|ee|ie|Ds|Os|
|25|IO79RSB1|61|IO57RSB1|97|NC|
|es|ee|ie|es|Os|
|26|IO78RSB1|62|NC|98|VCCIB0|
|es|ee es|Go|
|27|GND|63|GND|99|GND|
|es|ee|ie|Ps es|
|28|VCCIB1|64|NC|100|VCC|
|es|ees(n|
|29|GEC1/IO77RSB1|65|GDC2/IO56RSB1|101|IO30RSB0|
|es|ee es|Os|
|30|GEC0/IO76RSB1|66|GDB2/IO55RSB1|102|GBC2/IO29RSB0|
|es|ee|ie|Ds|Os|
|31|GEB1/IO75RSB1|67|GDA2/IO54RSB1|103|IO28RSB0|
|es|ee|ie|es|Os|
|32|GEB0/IO74RSB1|68|GNDQ|104|GBB2/IO27RSB0|
|es|ee|ie|es|ss|
|33|GEA1/IO73RSB1|69|TCK|105|IO26RSB0|
|es|ee es|Go|
|34|GEA0/IO72RSB1|70|TDI|106|GBA2/IO25RSB0|
|es|ees(n|
|35|VMV1|71|TMS|107|VMV0|
|es|ne ns|Os|
|36|GNDQ|72|VMV1|108|GNDQ|
|es|ee|Rs Rn|
**----- End of picture text -----**<br>
**4-24**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**TQ144 Pin Number A3P060 Function** ~~a~~ 109 NC ~~a~~ 110 NC ~~a~~ 111 GBA1/IO24RSB0 ~~a~~ 112 GBA0/IO23RSB0 ~~ee ee~~ 113 GBB1/IO22RSB0 ~~ee eee~~ 114 GBB0/IO21RSB0 ~~re~~ 115 GBC1/IO20RSB0 ~~a~~ 116 GBC0/IO19RSB0 ~~a~~ 117 VCCIB0 ~~a~~ 118 GND ~~ee ee~~ 119 VCC ~~ee eee~~ 120 IO18RSB0 ~~re~~ 121 IO17RSB0 ~~ee ee~~ 122 IO16RSB0 ~~a~~ 123 IO15RSB0 ~~a~~ 124 IO14RSB0 ~~ee ee~~ 125 IO13RSB0 ~~ee eee~~ 126 IO12RSB0 ~~re~~ 127 IO11RSB0 ~~a~~ 128 NC ~~a~~ 129 IO10RSB0 ~~a~~ 130 IO09RSB0 ~~ee ee~~ 131 IO08RSB0 ~~ee eee~~ 132 GAC1/IO07RSB0 ~~re~~ 133 GAC0/IO06RSB0 ~~a~~ 134 NC ~~a~~ 135 GND ~~a~~ 136 NC ~~ee ee~~ 137 GAB1/IO05RSB0 ~~ee eee~~ 138 GAB0/IO04RSB0 ~~re~~ 139 GAA1/IO03RSB0 ~~a~~ 140 GAA0/IO02RSB0 ~~a~~ 141 IO01RSB0 ~~a~~ 142 IO00RSB0 ~~ee ee~~ 143 GNDQ ~~ee eee~~ 144 VMV0 ~~ee ee~~
**Revision 18**
**4-25**
_Package Pin Assignments_
|**TQ144**<br>**Pin Number**<br>**A3P125 Function**<br>1<br>GAA2/IO67RSB1<br>2<br>IO68RSB1<br>3<br>GAB2/IO69RSB1<br>4<br>IO132RSB1<br>5<br>GAC2/IO131RSB1<br>6<br>IO130RSB1<br>7<br>IO129RSB1<br>8<br>IO128RSB1<br>9<br>VCC<br>10<br>GND<br>11<br>VCCIB1<br>12<br>IO127RSB1<br>13<br>GFC1/IO126RSB1<br>14<br>GFC0/IO125RSB1<br>15<br>GFB1/IO124RSB1<br>16<br>GFB0/IO123RSB1<br>17<br>VCOMPLF<br>18<br>GFA0/IO122RSB1<br>19<br>VCCPLF<br>20<br>GFA1/IO121RSB1<br>21<br>GFA2/IO120RSB1<br>22<br>GFB2/IO119RSB1<br>23<br>GFC2/IO118RSB1<br>24<br>IO117RSB1<br>25<br>IO116RSB1<br>26<br>IO115RSB1<br>27<br>GND<br>28<br>VCCIB1<br>29<br>GEC1/IO112RSB1<br>30<br>GEC0/IO111RSB1<br>31<br>GEB1/IO110RSB1<br>32<br>GEB0/IO109RSB1<br>33<br>GEA1/IO108RSB1<br>34<br>GEA0/IO107RSB1<br>35<br>VMV1<br>36<br>GNDQ<br>37<br>NC<br>38<br>GEA2/IO106RSB1<br>39<br>GEB2/IO105RSB1<br>40<br>GEC2/IO104RSB1<br>41<br>IO103RSB1<br>42<br>IO102RSB1<br>43<br>IO101RSB1<br>44<br>IO100RSB1<br>45<br>VCC<br>46<br>GND<br>47<br>VCCIB1<br>48<br>IO99RSB1<br>49<br>IO97RSB1<br>50<br>IO95RSB1<br>51<br>IO93RSB1<br>52<br>IO92RSB1<br>53<br>IO90RSB1<br>54<br>IO88RSB1<br>55<br>IO86RSB1<br>56<br>IO84RSB1<br>57<br>IO83RSB1<br>58<br>IO82RSB1<br>59<br>IO81RSB1<br>60<br>IO80RSB1<br>61<br>IO79RSB1<br>62<br>VCC<br>63<br>GND<br>64<br>VCCIB1<br>65<br>GDC2/IO72RSB1<br>66<br>GDB2/IO71RSB1<br>67<br>GDA2/IO70RSB1<br>68<br>GNDQ<br>69<br>TCK<br>70<br>TDI<br>71<br>TMS<br>72<br>VMV1<br>**TQ144**<br>**Pin Number**<br>**A3P125 Function**<br>~~ee ~~ie~~Os~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ae~~<br>~~ee~~<br>~~esOs~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~so~~<br>~~ee~~<br>~~ee es~~<br>~~ss~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es eo~~<br>~~ee~~<br>~~ee es~~<br>~~ss~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es eo~~<br>~~ee~~<br>~~ee es~~<br>~~ss~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~eees~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ae~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee es eo~~<br>~~ee~~<br>~~ee~~<br>~~nsOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee~~ie~~Rs~~<br>~~fn~~|73<br>74<br>75<br>76<br>77<br>78<br>79<br>80<br>81<br>82<br>83<br>84<br>85<br>86<br>87<br>88<br>89<br>90<br>91<br>92<br>93<br>94<br>95<br>96<br>97<br>98<br>99<br>100<br>101<br>102<br>103<br>104<br>105<br>106<br>107<br>108<br>**Pin Number**|VPUMP<br>NC<br>TDO<br>TRST<br>VJTAG<br>GDA0/IO66RSB0<br>GDB0/IO64RSB0<br>GDB1/IO63RSB0<br>VCCIB0<br>GND<br>IO60RSB0<br>GCC2/IO59RSB0<br>GCB2/IO58RSB0<br>GCA2/IO57RSB0<br>GCA0/IO56RSB0<br>GCA1/IO55RSB0<br>GCB0/IO54RSB0<br>GCB1/IO53RSB0<br>GCC0/IO52RSB0<br>GCC1/IO51RSB0<br>IO50RSB0<br>IO49RSB0<br>NC<br>NC<br>NC<br>VCCIB0<br>GND<br>VCC<br>IO47RSB0<br>GBC2/IO45RSB0<br>IO44RSB0<br>GBB2/IO43RSB0<br>IO42RSB0<br>GBA2/IO41RSB0<br>VMV0<br>GNDQ<br>**TQ144**<br>**A3P125 Function**|
|---|---|---|
**4-26**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**TQ144 Pin Number A3P125 Function** ~~a~~ 109 GBA1/IO40RSB0 ~~a~~ 110 GBA0/IO39RSB0 ~~a~~ 111 GBB1/IO38RSB0 ~~a~~ 112 GBB0/IO37RSB0 ~~ee ee~~ 113 GBC1/IO36RSB0 ~~a~~ 114 GBC0/IO35RSB0 ~~a~~ 115 IO34RSB0 ~~a~~ 116 IO33RSB0 ~~a~~ 117 VCCIB0 ~~a~~ 118 GND ~~ee ee~~ 119 VCC ~~a~~ 120 IO29RSB0 ~~a~~ 121 IO28RSB0 ~~a~~ 122 IO27RSB0 ~~a~~ 123 IO25RSB0 ~~a~~ 124 IO23RSB0 ~~ee ee~~ 125 IO21RSB0 ~~a~~ 126 IO19RSB0 ~~a~~ 127 IO17RSB0 ~~a~~ 128 IO16RSB0 ~~a~~ 129 IO14RSB0 ~~a~~ 130 IO12RSB0 ~~ee ee~~ 131 IO10RSB0 ~~a~~ 132 IO08RSB0 ~~a~~ 133 IO06RSB0 ~~a~~ 134 VCCIB0 ~~a~~ 135 GND ~~a~~ 136 VCC ~~ee ee~~ 137 GAC1/IO05RSB0 ~~a~~ 138 GAC0/IO04RSB0 ~~a~~ 139 GAB1/IO03RSB0 ~~a~~ 140 GAB0/IO02RSB0 ~~a~~ 141 GAA1/IO01RSB0 ~~a~~ 142 GAA0/IO00RSB0 ~~ee ee~~ 143 GNDQ ~~ee~~ 144 VMV0 ~~ee ee~~
**Revision 18**
**4-27**
_Package Pin Assignments_
## **PQ208 – Top View**
**==> picture [191 x 167] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 [208]<br>208-Pin PQFP<br>**----- End of picture text -----**<br>
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-28**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**PQ208**<br>**Pin Number**<br>**A3P125 Function**<br>1<br>GND<br>2<br>GAA2/IO67RSB1<br>3<br>IO68RSB1<br>4<br>GAB2/IO69RSB1<br>5<br>IO132RSB1<br>6<br>GAC2/IO131RSB1<br>7<br>NC<br>8<br>NC<br>9<br>IO130RSB1<br>10<br>IO129RSB1<br>11<br>NC<br>12<br>IO128RSB1<br>13<br>NC<br>14<br>NC<br>15<br>NC<br>16<br>VCC<br>17<br>GND<br>18<br>VCCIB1<br>19<br>IO127RSB1<br>20<br>NC<br>21<br>GFC1/IO126RSB1<br>22<br>GFC0/IO125RSB1<br>23<br>GFB1/IO124RSB1<br>24<br>GFB0/IO123RSB1<br>25<br>VCOMPLF<br>26<br>GFA0/IO122RSB1<br>27<br>VCCPLF<br>28<br>GFA1/IO121RSB1<br>29<br>GND<br>30<br>GFA2/IO120RSB1<br>31<br>NC<br>32<br>GFB2/IO119RSB1<br>33<br>NC<br>34<br>GFC2/IO118RSB1<br>35<br>IO117RSB1<br>36<br>NC<br>37<br>IO116RSB1<br>38<br>IO115RSB1<br>39<br>NC<br>40<br>VCCIB1<br>41<br>GND<br>42<br>IO114RSB1<br>43<br>IO113RSB1<br>44<br>GEC1/IO112RSB1<br>45<br>GEC0/IO111RSB1<br>46<br>GEB1/IO110RSB1<br>47<br>GEB0/IO109RSB1<br>48<br>GEA1/IO108RSB1<br>49<br>GEA0/IO107RSB1<br>50<br>VMV1<br>51<br>GNDQ<br>52<br>GND<br>53<br>NC<br>54<br>NC<br>55<br>GEA2/IO106RSB1<br>56<br>GEB2/IO105RSB1<br>57<br>GEC2/IO104RSB1<br>58<br>IO103RSB1<br>59<br>IO102RSB1<br>60<br>IO101RSB1<br>61<br>IO100RSB1<br>62<br>VCCIB1<br>63<br>IO99RSB1<br>64<br>IO98RSB1<br>65<br>GND<br>66<br>IO97RSB1<br>67<br>IO96RSB1<br>68<br>IO95RSB1<br>69<br>IO94RSB1<br>70<br>IO93RSB1<br>71<br>VCC<br>72<br>VCCIB1<br>**PQ208**<br>**Pin Number**<br>**A3P125 Function**<br>73<br>IO92RSB1<br>74<br>IO91RSB1<br>75<br>IO90RSB1<br>76<br>IO89RSB1<br>77<br>IO88RSB1<br>78<br>IO87RSB1<br>79<br>IO86RSB1<br>80<br>IO85RSB1<br>81<br>GND<br>82<br>IO84RSB1<br>83<br>IO83RSB1<br>84<br>IO82RSB1<br>85<br>IO81RSB1<br>86<br>IO80RSB1<br>87<br>IO79RSB1<br>88<br>VCC<br>89<br>VCCIB1<br>90<br>IO78RSB1<br>91<br>IO77RSB1<br>92<br>IO76RSB1<br>93<br>IO75RSB1<br>94<br>IO74RSB1<br>95<br>IO73RSB1<br>96<br>GDC2/IO72RSB1<br>97<br>GND<br>98<br>GDB2/IO71RSB1<br>99<br>GDA2/IO70RSB1<br>100<br>GNDQ<br>101<br>TCK<br>102<br>TDI<br>103<br>TMS<br>104<br>VMV1<br>105<br>GND<br>106<br>VPUMP<br>107<br>NC<br>108<br>TDO<br>**PQ208**<br>**Pin Number**<br>**A3P125 Function**<br>~~ee ~~Oe~~Go~~<br>~~ee Pe no~~<br>~~a~~<br>~~ee ~~be~~ee no~~<br>~~ee ~~be~~ee no~~<br>~~a ee Re eo~~<br>~~es~~<br>~~OePn~~<br>~~no~~<br>~~a~~<br>~~eeno~~<br>~~ee~~<br>~~ee ee~~<br>~~no~~<br>~~a ee ~~be ~~ee~~<br>~~no~~<br>~~ee ~~be~~ee no~~<br>~~a ee Re eo~~<br>~~es~~<br>~~OePn~~<br>~~no~~<br>~~a~~<br>~~eeno~~<br>~~ee~~<br>~~ee ee~~<br>~~no~~<br>~~a ee ~~be~~ee~~<br>~~no~~<br>~~a~~<br>~~ee ~~be~~Pe~~<br>~~noes~~<br>~~a ee ~~be~~Ree en~~<br>~~es~~<br>~~OePn~~<br>~~no~~<br>~~a~~<br>~~eeno~~<br>~~ee~~<br>~~ee ee~~<br>~~no~~<br>~~a ee ~~be ~~ee~~<br>~~no~~<br>~~ee~~<br>~~ee ~~be~~Me no~~<br>~~a ee ~~be~~Ree en~~<br>~~es~~<br>~~OePn~~<br>~~no~~<br>~~a~~<br>~~eeno~~<br>~~ee~~<br>~~ee ee~~<br>~~no~~<br>~~a ee ~~be ~~ee~~<br>~~no~~<br>~~ee~~<br>~~ee ~~be~~Me no~~<br>~~a ee ~~be~~Ree en~~<br>~~es~~<br>~~OePn~~<br>~~no~~<br>~~a~~<br>~~eeno~~<br>~~ee~~<br>~~ee ee~~<br>~~no~~<br>~~a ee ~~be ~~ee~~<br>~~no~~<br>~~a~~<br>~~ee ~~be~~ee no~~<br>~~ee~~<br>~~ee ~~be~~Me no~~<br>~~es~~<br>~~OePn~~<br>~~no~~<br>~~ee~~<br>~~Oeno~~<br>~~ee~~<br>~~feen~~<br>~~no~~|
|---|
**Revision 18**
**4-29**
_Package Pin Assignments_
**==> picture [469 x 650] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|PQ208|PQ208|PQ208|
|ee|Oe|Go|
|Pin Number|A3P125 Function|Pin Number|A3P125 Function|Pin Number|A3P125 Function|
|ee|Pe|no|
|109|TRST|145|IO46RSB0|181|IO21RSB0|
|a|ee|be|ee|no|
|110|VJTAG|146|NC|182|IO20RSB0|
|ee|be|ee|no|
|111|GDA0/IO66RSB0|147|NC|183|IO19RSB0|
|a|ee|Re|eo|
|112|GDA1/IO65RSB0|148|NC|184|IO18RSB0|
|es|Oe|Pn|no|
|113|GDB0/IO64RSB0|149|GBC2/IO45RSB0|185|IO17RSB0|
|a|eeno|
|114|GDB1/IO63RSB0|150|IO44RSB0|186|VCCIB0|
|ee|ee|ee|no|
|115|GDC0/IO62RSB0|151|GBB2/IO43RSB0|187|VCC|
|a|ee|be|ee|no|
|116|GDC1/IO61RSB0|152|IO42RSB0|188|IO16RSB0|
|ee|be|ee|no|
|117|NC|153|GBA2/IO41RSB0|189|IO15RSB0|
|a|ee|Re|eo|
|118|NC|154|VMV0|190|IO14RSB0|
|es|Oe|Pn|no|
|119|NC|155|GNDQ|191|IO13RSB0|
|a|eeno|
|120|NC|156|GND|192|IO12RSB0|
|ee|ee|ee|no|
|121|NC|157|NC|193|IO11RSB0|
|a|ee|be|ee|no|
|122|GND|158|GBA1/IO40RSB0|194|IO10RSB0|
|a|ee|be|Pe|noes|
|123|VCCIB0|159|GBA0/IO39RSB0|195|GND|
|a|ee|be|Ree en|
|124|NC|160|GBB1/IO38RSB0|196|IO09RSB0|
|es|Oe|Pn|no|
|125|NC|161|GBB0/IO37RSB0|197|IO08RSB0|
|a|eeno|
|126|VCC|162|GND|198|IO07RSB0|
|ee|ee|ee|no|
|127|IO60RSB0|163|GBC1/IO36RSB0|199|IO06RSB0|
|a|ee|be|ee|no|
|128|GCC2/IO59RSB0|164|GBC0/IO35RSB0|200|VCCIB0|
|ee|ee|be|Me|no|
|129|GCB2/IO58RSB0|165|IO34RSB0|201|GAC1/IO05RSB0|
|a|ee|be|Ree en|
|130|GND|166|IO33RSB0|202|GAC0/IO04RSB0|
|es|Oe|Pn|no|
|131|GCA2/IO57RSB0|167|IO32RSB0|203|GAB1/IO03RSB0|
|a|eeno|
|132|GCA0/IO56RSB0|168|IO31RSB0|204|GAB0/IO02RSB0|
|ee|ee|ee|no|
|133|GCA1/IO55RSB0|169|IO30RSB0|205|GAA1/IO01RSB0|
|a|ee|be|ee|no|
|134|GCB0/IO54RSB0|170|VCCIB0|206|GAA0/IO00RSB0|
|ee|ee|be|Me|no|
|135|GCB1/IO53RSB0|171|VCC|207|GNDQ|
|a|ee|be|Ree en|
|136|GCC0/IO52RSB0|172|IO29RSB0|208|VMV0|
|es|Oe|Rn|no|
|137|GCC1/IO51RSB0|173|IO28RSB0|
|ee|ee|es|
|138|IO50RSB0|174|IO27RSB0|
|ee|ee|es|
|139|IO49RSB0|175|IO26RSB0|
|ee|ee|ee|
|140|VCCIB0|176|IO25RSB0|
|ee|ee|ee|
|141|GND|177|IO24RSB0|
|ee|ee|es|
|142|VCC|178|GND|
|ee|ee ee|
|143|IO48RSB0|179|IO23RSB0|
|ee|ee|
|144|IO47RSB0|180|IO22RSB0|
|ee|ee es|
**----- End of picture text -----**<br>
**4-30**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**PQ208**<br>**Pin Number**<br>**A3P250 Function**<br>1<br>GND<br>2<br>GAA2/IO118UDB3<br>3<br>IO118VDB3<br>4<br>GAB2/IO117UDB3<br>5<br>IO117VDB3<br>6<br>GAC2/IO116UDB3<br>7<br>IO116VDB3<br>8<br>IO115UDB3<br>9<br>IO115VDB3<br>10<br>IO114UDB3<br>11<br>IO114VDB3<br>12<br>IO113PDB3<br>13<br>IO113NDB3<br>14<br>IO112PDB3<br>15<br>IO112NDB3<br>16<br>VCC<br>17<br>GND<br>18<br>VCCIB3<br>19<br>IO111PDB3<br>20<br>IO111NDB3<br>21<br>GFC1/IO110PDB3<br>22<br>GFC0/IO110NDB3<br>23<br>GFB1/IO109PDB3<br>24<br>GFB0/IO109NDB3<br>25<br>VCOMPLF<br>26<br>GFA0/IO108NPB3<br>27<br>VCCPLF<br>28<br>GFA1/IO108PPB3<br>29<br>GND<br>30<br>GFA2/IO107PDB3<br>31<br>IO107NDB3<br>32<br>GFB2/IO106PDB3<br>33<br>IO106NDB3<br>34<br>GFC2/IO105PDB3<br>35<br>IO105NDB3<br>36<br>NC<br>37<br>IO104PDB3<br>38<br>IO104NDB3<br>39<br>IO103PSB3<br>40<br>VCCIB3<br>41<br>GND<br>42<br>IO101PDB3<br>43<br>IO101NDB3<br>44<br>GEC1/IO100PDB3<br>45<br>GEC0/IO100NDB3<br>46<br>GEB1/IO99PDB3<br>47<br>GEB0/IO99NDB3<br>48<br>GEA1/IO98PDB3<br>49<br>GEA0/IO98NDB3<br>50<br>VMV3<br>51<br>GNDQ<br>52<br>GND<br>53<br>NC<br>54<br>NC<br>55<br>GEA2/IO97RSB2<br>56<br>GEB2/IO96RSB2<br>57<br>GEC2/IO95RSB2<br>58<br>IO94RSB2<br>59<br>IO93RSB2<br>60<br>IO92RSB2<br>61<br>IO91RSB2<br>62<br>VCCIB2<br>63<br>IO90RSB2<br>64<br>IO89RSB2<br>65<br>GND<br>66<br>IO88RSB2<br>67<br>IO87RSB2<br>68<br>IO86RSB2<br>69<br>IO85RSB2<br>70<br>IO84RSB2<br>71<br>VCC<br>72<br>VCCIB2<br>**PQ208**<br>**Pin Number**<br>**A3P250 Function**<br>~~ee ~~ie~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~a ee~~<br>~~esGo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~so~~<br>~~a ee ~~ie~~ee es~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es~~<br>~~ee eseo~~<br>~~a ee ~~ie~~ee es~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es~~<br>~~ee eseo~~<br>~~a ee ~~ie~~ee es~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~esGo~~<br>~~es~~<br>~~ee eseo~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~ee ~~ie~~Os~~<br>~~es~~<br>~~eees~~<br>~~fn~~|73<br>74<br>75<br>76<br>77<br>78<br>79<br>80<br>81<br>82<br>83<br>84<br>85<br>86<br>87<br>88<br>89<br>90<br>91<br>92<br>93<br>94<br>95<br>96<br>97<br>98<br>99<br>100<br>101<br>102<br>103<br>104<br>105<br>106<br>107<br>108<br>**Pin Number**|IO83RSB2<br>IO82RSB2<br>IO81RSB2<br>IO80RSB2<br>IO79RSB2<br>IO78RSB2<br>IO77RSB2<br>IO76RSB2<br>GND<br>IO75RSB2<br>IO74RSB2<br>IO73RSB2<br>IO72RSB2<br>IO71RSB2<br>IO70RSB2<br>VCC<br>VCCIB2<br>IO69RSB2<br>IO68RSB2<br>IO67RSB2<br>IO66RSB2<br>IO65RSB2<br>IO64RSB2<br>GDC2/IO63RSB2<br>GND<br>GDB2/IO62RSB2<br>GDA2/IO61RSB2<br>GNDQ<br>TCK<br>TDI<br>TMS<br>VMV2<br>GND<br>VPUMP<br>NC<br>TDO<br>**PQ208**<br>**A3P250 Function**|
|---|---|---|
**Revision 18**
**4-31**
_Package Pin Assignments_
|109<br>TRST<br>110<br>VJTAG<br>111<br>GDA0/IO60VDB1<br>112<br>GDA1/IO60UDB1<br>113<br>GDB0/IO59VDB1<br>114<br>GDB1/IO59UDB1<br>115<br>GDC0/IO58VDB1<br>116<br>GDC1/IO58UDB1<br>117<br>IO57VDB1<br>118<br>IO57UDB1<br>119<br>IO56NDB1<br>120<br>IO56PDB1<br>121<br>IO55RSB1<br>122<br>GND<br>123<br>VCCIB1<br>124<br>NC<br>125<br>NC<br>126<br>VCC<br>127<br>IO53NDB1<br>128<br>GCC2/IO53PDB1<br>129<br>GCB2/IO52PSB1<br>130<br>GND<br>131<br>GCA2/IO51PSB1<br>132<br>GCA1/IO50PDB1<br>133<br>GCA0/IO50NDB1<br>134<br>GCB0/IO49NDB1<br>135<br>GCB1/IO49PDB1<br>136<br>GCC0/IO48NDB1<br>137<br>GCC1/IO48PDB1<br>138<br>IO47NDB1<br>139<br>IO47PDB1<br>140<br>VCCIB1<br>141<br>GND<br>142<br>VCC<br>143<br>IO46RSB1<br>144<br>IO45NDB1<br>**PQ208**<br>**Pin Number**<br>**A3P250 Function**<br>145<br>IO45PDB1<br>146<br>IO44NDB1<br>147<br>IO44PDB1<br>148<br>IO43NDB1<br>149<br>GBC2/IO43PDB1<br>150<br>IO42NDB1<br>151<br>GBB2/IO42PDB1<br>152<br>IO41NDB1<br>153<br>GBA2/IO41PDB1<br>154<br>VMV1<br>155<br>GNDQ<br>156<br>GND<br>157<br>NC<br>158<br>GBA1/IO40RSB0<br>159<br>GBA0/IO39RSB0<br>160<br>GBB1/IO38RSB0<br>161<br>GBB0/IO37RSB0<br>162<br>GND<br>163<br>GBC1/IO36RSB0<br>164<br>GBC0/IO35RSB0<br>165<br>IO34RSB0<br>166<br>IO33RSB0<br>167<br>IO32RSB0<br>168<br>IO31RSB0<br>169<br>IO30RSB0<br>170<br>VCCIB0<br>171<br>VCC<br>172<br>IO29RSB0<br>173<br>IO28RSB0<br>174<br>IO27RSB0<br>175<br>IO26RSB0<br>176<br>IO25RSB0<br>177<br>IO24RSB0<br>178<br>GND<br>179<br>IO23RSB0<br>180<br>IO22RSB0<br>**PQ208**<br>**Pin Number**<br>**A3P250 Function**<br>~~ee ~~ie~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~a ee~~<br>~~esGo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Os~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~so~~<br>~~a ee ~~ie~~ee es~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es~~<br>~~ee eseo~~<br>~~a ee ~~ie~~ee es~~<br>~~es~~<br>~~eeOs~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esOo~~<br>~~es~~<br>~~ee ~~ie<br>~~esOo~~<br>~~es~~<br>~~ee eseo~~<br>~~a ee ~~ie~~ee es~~<br>~~es~~<br>~~eeOs~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a ee~~<br>~~ee~~<br>~~a ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a es~~<br>~~aee~~<br>~~ee~~|181<br>182<br>183<br>184<br>185<br>186<br>187<br>188<br>189<br>190<br>191<br>192<br>193<br>194<br>195<br>196<br>197<br>198<br>199<br>200<br>201<br>202<br>203<br>204<br>205<br>206<br>207<br>208<br>**Pin Number**|IO21RSB0<br>IO20RSB0<br>IO19RSB0<br>IO18RSB0<br>IO17RSB0<br>VCCIB0<br>VCC<br>IO16RSB0<br>IO15RSB0<br>IO14RSB0<br>IO13RSB0<br>IO12RSB0<br>IO11RSB0<br>IO10RSB0<br>GND<br>IO09RSB0<br>IO08RSB0<br>IO07RSB0<br>IO06RSB0<br>VCCIB0<br>GAC1/IO05RSB0<br>GAC0/IO04RSB0<br>GAB1/IO03RSB0<br>GAB0/IO02RSB0<br>GAA1/IO01RSB0<br>GAA0/IO00RSB0<br>GNDQ<br>VMV0<br>**PQ208**<br>**A3P250 Function**|
|---|---|---|
**4-32**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**PQ208**<br>**Pin Number**<br>**A3P400 Function**<br>1<br>GND<br>2<br>GAA2/IO155UDB3<br>3<br>IO155VDB3<br>4<br>GAB2/IO154UDB3<br>5<br>IO154VDB3<br>6<br>GAC2/IO153UDB3<br>7<br>IO153VDB3<br>8<br>IO152UDB3<br>9<br>IO152VDB3<br>10<br>IO151UDB3<br>11<br>IO151VDB3<br>12<br>IO150PDB3<br>13<br>IO150NDB3<br>14<br>IO149PDB3<br>15<br>IO149NDB3<br>16<br>VCC<br>17<br>GND<br>18<br>VCCIB3<br>19<br>IO148PDB3<br>20<br>IO148NDB3<br>21<br>GFC1/IO147PDB3<br>22<br>GFC0/IO147NDB3<br>23<br>GFB1/IO146PDB3<br>24<br>GFB0/IO146NDB3<br>25<br>VCOMPLF<br>26<br>GFA0/IO145NPB3<br>27<br>VCCPLF<br>28<br>GFA1/IO145PPB3<br>29<br>GND<br>30<br>GFA2/IO144PDB3<br>31<br>IO144NDB3<br>32<br>GFB2/IO143PDB3<br>33<br>IO143NDB3<br>34<br>GFC2/IO142PDB3<br>35<br>IO142NDB3<br>36<br>NC<br>37<br>IO141PSB3<br>38<br>IO140PDB3<br>39<br>IO140NDB3<br>40<br>VCCIB3<br>41<br>GND<br>42<br>IO138PDB3<br>43<br>IO138NDB3<br>44<br>GEC1/IO137PDB3<br>45<br>GEC0/IO137NDB3<br>46<br>GEB1/IO136PDB3<br>47<br>GEB0/IO136NDB3<br>48<br>GEA1/IO135PDB3<br>49<br>GEA0/IO135NDB3<br>50<br>VMV3<br>51<br>GNDQ<br>52<br>GND<br>53<br>VMV2<br>54<br>NC<br>55<br>GEA2/IO134RSB2<br>56<br>GEB2/IO133RSB2<br>57<br>GEC2/IO132RSB2<br>58<br>IO131RSB2<br>59<br>IO130RSB2<br>60<br>IO129RSB2<br>61<br>IO128RSB2<br>62<br>VCCIB2<br>63<br>IO125RSB2<br>64<br>IO123RSB2<br>65<br>GND<br>66<br>IO121RSB2<br>67<br>IO119RSB2<br>68<br>IO117RSB2<br>69<br>IO115RSB2<br>70<br>IO113RSB2<br>71<br>VCC<br>72<br>VCCIB2<br>**PQ208**<br>**Pin Number**<br>**A3P400 Function**<br>~~re ~~ie~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~es0s~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~i~~es eo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~i~~es eo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~esOs~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esso~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esso~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee~~<br>~~esso~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~en ~~ie~~ns~~<br>~~Os~~<br>~~es~~<br>~~eees~~<br>~~fn~~|73<br>74<br>75<br>76<br>77<br>78<br>79<br>80<br>81<br>82<br>83<br>84<br>85<br>86<br>87<br>88<br>89<br>90<br>91<br>92<br>93<br>94<br>95<br>96<br>97<br>98<br>99<br>100<br>101<br>102<br>103<br>104<br>105<br>106<br>107<br>108<br>**Pin Number**|IO112RSB2<br>IO111RSB2<br>IO110RSB2<br>IO109RSB2<br>IO108RSB2<br>IO107RSB2<br>IO106RSB2<br>IO104RSB2<br>GND<br>IO102RSB2<br>IO101RSB2<br>IO100RSB2<br>IO99RSB2<br>IO98RSB2<br>IO97RSB2<br>VCC<br>VCCIB2<br>IO94RSB2<br>IO92RSB2<br>IO90RSB2<br>IO88RSB2<br>IO86RSB2<br>IO84RSB2<br>GDC2/IO82RSB2<br>GND<br>GDB2/IO81RSB2<br>GDA2/IO80RSB2<br>GNDQ<br>TCK<br>TDI<br>TMS<br>VMV2<br>GND<br>VPUMP<br>NC<br>TDO<br>**PQ208**<br>**A3P400 Function**|
|---|---|---|
**Revision 18**
**4-33**
_Package Pin Assignments_
|109<br>TRST<br>110<br>VJTAG<br>111<br>GDA0/IO79VDB1<br>112<br>GDA1/IO79UDB1<br>113<br>GDB0/IO78VDB1<br>114<br>GDB1/IO78UDB1<br>115<br>GDC0/IO77VDB1<br>116<br>GDC1/IO77UDB1<br>117<br>IO76VDB1<br>118<br>IO76UDB1<br>119<br>IO75NDB1<br>120<br>IO75PDB1<br>121<br>IO74RSB1<br>122<br>GND<br>123<br>VCCIB1<br>124<br>NC<br>125<br>NC<br>126<br>VCC<br>127<br>IO72NDB1<br>128<br>GCC2/IO72PDB1<br>129<br>GCB2/IO71PSB1<br>130<br>GND<br>131<br>GCA2/IO70PSB1<br>132<br>GCA1/IO69PDB1<br>133<br>GCA0/IO69NDB1<br>134<br>GCB0/IO68NDB1<br>135<br>GCB1/IO68PDB1<br>136<br>GCC0/IO67NDB1<br>137<br>GCC1/IO67PDB1<br>138<br>IO66NDB1<br>139<br>IO66PDB1<br>140<br>VCCIB1<br>141<br>GND<br>142<br>VCC<br>143<br>IO65RSB1<br>144<br>IO64NDB1<br>**PQ208**<br>**Pin Number**<br>**A3P400 Function**<br>145<br>IO64PDB1<br>146<br>IO63NDB1<br>147<br>IO63PDB1<br>148<br>IO62NDB1<br>149<br>GBC2/IO62PDB1<br>150<br>IO61NDB1<br>151<br>GBB2/IO61PDB1<br>152<br>IO60NDB1<br>153<br>GBA2/IO60PDB1<br>154<br>VMV1<br>155<br>GNDQ<br>156<br>GND<br>157<br>VMV0<br>158<br>GBA1/IO59RSB0<br>159<br>GBA0/IO58RSB0<br>160<br>GBB1/IO57RSB0<br>161<br>GBB0/IO56RSB0<br>162<br>GND<br>163<br>GBC1/IO55RSB0<br>164<br>GBC0/IO54RSB0<br>165<br>IO52RSB0<br>166<br>IO49RSB0<br>167<br>IO46RSB0<br>168<br>IO43RSB0<br>169<br>IO40RSB0<br>170<br>VCCIB0<br>171<br>VCC<br>172<br>IO36RSB0<br>173<br>IO35RSB0<br>174<br>IO34RSB0<br>175<br>IO33RSB0<br>176<br>IO32RSB0<br>177<br>IO31RSB0<br>178<br>GND<br>179<br>IO29RSB0<br>180<br>IO28RSB0<br>**PQ208**<br>**Pin Number**<br>**A3P400 Function**<br>~~re ~~ie~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~es0s~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~i~~es eo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~i~~es eo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~esOs~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esso~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~ee~~<br>~~eeRs~~<br>~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee es~~<br>~~Os~~<br>~~es~~<br>~~ee~~<br>~~esso~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~en ~~ie~~s(n~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~eeee~~<br>~~a~~<br>~~ee ee~~<br>~~a~~<br>~~eeee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~es~~|181<br>182<br>183<br>184<br>185<br>186<br>187<br>188<br>189<br>190<br>191<br>192<br>193<br>194<br>195<br>196<br>197<br>198<br>199<br>200<br>201<br>202<br>203<br>204<br>205<br>206<br>207<br>208<br>**Pin Number**|IO27RSB0<br>IO26RSB0<br>IO25RSB0<br>IO24RSB0<br>IO23RSB0<br>VCCIB0<br>VCC<br>IO21RSB0<br>IO20RSB0<br>IO19RSB0<br>IO18RSB0<br>IO17RSB0<br>IO16RSB0<br>IO15RSB0<br>GND<br>IO13RSB0<br>IO11RSB0<br>IO09RSB0<br>IO07RSB0<br>VCCIB0<br>GAC1/IO05RSB0<br>GAC0/IO04RSB0<br>GAB1/IO03RSB0<br>GAB0/IO02RSB0<br>GAA1/IO01RSB0<br>GAA0/IO00RSB0<br>GNDQ<br>VMV0<br>**PQ208**<br>**A3P400 Function**|
|---|---|---|
**4-34**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**==> picture [468 x 650] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|PQ208|PQ208|PQ208|
|ee Os|
|Pin Number|A3P600 Function|Pin Number|A3P600 Function|Pin Number|A3P600 Function|
|a|ee|ie|ee|sses|
|1|GND|37|IO152PDB3|73|IO120RSB2|
|ee|ees|0s|
|2|GAA2/IO174PDB3|38|IO152NDB3|74|IO119RSB2|
|ee|es eo|
|3|IO174NDB3|39|IO150PSB3|75|IO118RSB2|
|i|ee|es es|
|4|GAB2/IO173PDB3|40|VCCIB3|76|IO117RSB2|
|ee|ee ee|es|fo|es|
|5|IO173NDB3|41|GND|77|IO116RSB2|
|ee|ee|ie|es|so|
|6|GAC2/IO172PDB3|42|IO147PDB3|78|IO115RSB2|
|ee|ee|es|ssee|
|7|IO172NDB3|43|IO147NDB3|79|IO114RSB2|
|ee|es|Os|
|8|IO171PDB3|44|GEC1/IO146PDB3|80|IO112RSB2|
|ee ee|es es|
|9|IO171NDB3|45|GEC0/IO146NDB3|81|GND|
|i|ee|es es|
|10|IO170PDB3|46|GEB1/IO145PDB3|82|IO111RSB2|
|ee|ee ee|es|fo|es|
|11|IO170NDB3|47|GEB0/IO145NDB3|83|IO110RSB2|
|ee|ee|ie|es|so|
|12|IO169PDB3|48|GEA1/IO144PDB3|84|IO109RSB2|
|ee|ee|es|ssee|
|13|IO169NDB3|49|GEA0/IO144NDB3|85|IO108RSB2|
|ee|es|Os|
|14|IO168PDB3|50|VMV3|86|IO107RSB2|
|ee ee|es es|
|15|IO168NDB3|51|GNDQ|87|IO106RSB2|
|i|ee|es es|
|16|VCC|52|GND|88|VCC|
|ee|ee ee|es|fo|es|
|17|GND|53|VMV2|89|VCCIB2|
|ee|ee|ie|es|so|
|18|VCCIB3|54|GEA2/IO143RSB2|90|IO104RSB2|
|ee|ee|es|ssee|
|19|IO166PDB3|55|GEB2/IO142RSB2|91|IO102RSB2|
|ee|es|Os|
|20|IO166NDB3|56|GEC2/IO141RSB2|92|IO100RSB2|
|ee ee|es es|
|21|GFC1/IO164PDB3|57|IO140RSB2|93|IO98RSB2|
|i|ee|es es|
|22|GFC0/IO164NDB3|58|IO139RSB2|94|IO96RSB2|
|ee|ee ee|es|fo|es|
|23|GFB1/IO163PDB3|59|IO138RSB2|95|IO92RSB2|
|ee|ee|ie|es|so|
|24|GFB0/IO163NDB3|60|IO137RSB2|96|GDC2/IO91RSB2|
|ee|ee|es|ssee|
|25|VCOMPLF|61|IO136RSB2|97|GND|
|ee|es|Os|
|26|GFA0/IO162NPB3|62|VCCIB2|98|GDB2/IO90RSB2|
|ee ee|es es|
|27|VCCPLF|63|IO135RSB2|99|GDA2/IO89RSB2|
|i|ee|es es|
|28|GFA1/IO162PPB3|64|IO133RSB2|100|GNDQ|
|ee|ee ee|es|fo|es|
|29|GND|65|GND|101|TCK|
|ee|ee|ie|es|so|
|30|GFA2/IO161PDB3|66|IO131RSB2|102|TDI|
|ee|ee|es|ssee|
|31|IO161NDB3|67|IO129RSB2|103|TMS|
|ee|es|Os|
|32|GFB2/IO160PDB3|68|IO127RSB2|104|VMV2|
|es ee|es|0s|
|33|IO160NDB3|69|IO125RSB2|105|GND|
|ee ee|es es|
|34|GFC2/IO159PDB3|70|IO123RSB2|106|VPUMP|
|ee|ee ee|es|fo|es|
|35|IO159NDB3|71|VCC|107|GNDQ|
|ee|se|es|so|
|36|VCC|72|VCCIB2|108|TDO|
|ee|ee|ie|ees|fo|
**----- End of picture text -----**<br>
**Revision 18**
**4-35**
_Package Pin Assignments_
|109<br>TRST<br>110<br>VJTAG<br>111<br>GDA0/IO88NDB1<br>112<br>GDA1/IO88PDB1<br>113<br>GDB0/IO87NDB1<br>114<br>GDB1/IO87PDB1<br>115<br>GDC0/IO86NDB1<br>116<br>GDC1/IO86PDB1<br>117<br>IO84NDB1<br>118<br>IO84PDB1<br>119<br>IO82NDB1<br>120<br>IO82PDB1<br>121<br>IO81PSB1<br>122<br>GND<br>123<br>VCCIB1<br>124<br>IO77NDB1<br>125<br>IO77PDB1<br>126<br>NC<br>127<br>IO74NDB1<br>128<br>GCC2/IO74PDB1<br>129<br>GCB2/IO73PSB1<br>130<br>GND<br>131<br>GCA2/IO72PSB1<br>132<br>GCA1/IO71PDB1<br>133<br>GCA0/IO71NDB1<br>134<br>GCB0/IO70NDB1<br>135<br>GCB1/IO70PDB1<br>136<br>GCC0/IO69NDB1<br>137<br>GCC1/IO69PDB1<br>138<br>IO67NDB1<br>139<br>IO67PDB1<br>140<br>VCCIB1<br>141<br>GND<br>142<br>VCC<br>143<br>IO65PSB1<br>144<br>IO64NDB1<br>**PQ208**<br>**Pin Number**<br>**A3P600 Function**<br>145<br>IO64PDB1<br>146<br>IO63NDB1<br>147<br>IO63PDB1<br>148<br>IO62NDB1<br>149<br>GBC2/IO62PDB1<br>150<br>IO61NDB1<br>151<br>GBB2/IO61PDB1<br>152<br>IO60NDB1<br>153<br>GBA2/IO60PDB1<br>154<br>VMV1<br>155<br>GNDQ<br>156<br>GND<br>157<br>VMV0<br>158<br>GBA1/IO59RSB0<br>159<br>GBA0/IO58RSB0<br>160<br>GBB1/IO57RSB0<br>161<br>GBB0/IO56RSB0<br>162<br>GND<br>163<br>GBC1/IO55RSB0<br>164<br>GBC0/IO54RSB0<br>165<br>IO52RSB0<br>166<br>IO50RSB0<br>167<br>IO48RSB0<br>168<br>IO46RSB0<br>169<br>IO44RSB0<br>170<br>VCCIB0<br>171<br>VCC<br>172<br>IO36RSB0<br>173<br>IO35RSB0<br>174<br>IO34RSB0<br>175<br>IO33RSB0<br>176<br>IO32RSB0<br>177<br>IO31RSB0<br>178<br>GND<br>179<br>IO29RSB0<br>180<br>IO28RSB0<br>**PQ208**<br>**Pin Number**<br>**A3P600 Function**<br>181<br>IO27RSB0<br>182<br>IO26RSB0<br>183<br>IO25RSB0<br>184<br>IO24RSB0<br>185<br>IO23RSB0<br>186<br>VCCIB0<br>187<br>VCC<br>188<br>IO20RSB0<br>189<br>IO19RSB0<br>190<br>IO18RSB0<br>191<br>IO17RSB0<br>192<br>IO16RSB0<br>193<br>IO14RSB0<br>194<br>IO12RSB0<br>195<br>GND<br>196<br>IO10RSB0<br>197<br>IO09RSB0<br>198<br>IO08RSB0<br>199<br>IO07RSB0<br>200<br>VCCIB0<br>201<br>GAC1/IO05RSB0<br>202<br>GAC0/IO04RSB0<br>203<br>GAB1/IO03RSB0<br>204<br>GAB0/IO02RSB0<br>205<br>GAA1/IO01RSB0<br>206<br>GAA0/IO00RSB0<br>207<br>GNDQ<br>208<br>VMV0<br>**PQ208**<br>**Pin Number**<br>**A3P600 Function**<br>~~ee Os~~<br>~~a ee ~~ie~~ee~~<br>~~sses~~<br>~~ee ees~~<br>~~0s~~<br>~~ee es eo~~<br>~~i~~<br>~~ee es es~~<br>~~ee ee ee es ~~fo~~es~~<br>~~ee ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eees~~<br>~~ssee~~<br>~~ee es~~<br>~~Os~~<br>~~ee eees es~~<br>~~i~~<br>~~ee es es~~<br>~~ee ee ee es ~~fo~~es~~<br>~~ee ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eees~~<br>~~ssee~~<br>~~ee es~~<br>~~Os~~<br>~~ee eees es~~<br>~~i~~<br>~~ee es es~~<br>~~ee ee ee es ~~fo~~es~~<br>~~ee ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eees~~<br>~~ssee~~<br>~~ee es~~<br>~~Os~~<br>~~ee eees es~~<br>~~i~~<br>~~ee es es~~<br>~~ee ee ee es ~~fo~~es~~<br>~~ee ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eees~~<br>~~ssee~~<br>~~ee es~~<br>~~Os~~<br>~~ee eees es~~<br>~~i~~<br>~~ee es es~~<br>~~ee ee ~~ie~~ee~~<br>~~es os~~<br>~~ee eeee~~<br>~~ee~~<br>~~eeee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~eeeeee~~|
|---|
**4-36**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**PQ208**<br>**Pin Number**<br>**A3P1000 Function**<br>1<br>GND<br>2<br>GAA2/IO225PDB3<br>3<br>IO225NDB3<br>4<br>GAB2/IO224PDB3<br>5<br>IO224NDB3<br>6<br>GAC2/IO223PDB3<br>7<br>IO223NDB3<br>8<br>IO222PDB3<br>9<br>IO222NDB3<br>10<br>IO220PDB3<br>11<br>IO220NDB3<br>12<br>IO218PDB3<br>13<br>IO218NDB3<br>14<br>IO216PDB3<br>15<br>IO216NDB3<br>16<br>VCC<br>17<br>GND<br>18<br>VCCIB3<br>19<br>IO212PDB3<br>20<br>IO212NDB3<br>21<br>GFC1/IO209PDB3<br>22<br>GFC0/IO209NDB3<br>23<br>GFB1/IO208PDB3<br>24<br>GFB0/IO208NDB3<br>25<br>VCOMPLF<br>26<br>GFA0/IO207NPB3<br>27<br>VCCPLF<br>28<br>GFA1/IO207PPB3<br>29<br>GND<br>30<br>GFA2/IO206PDB3<br>31<br>IO206NDB3<br>32<br>GFB2/IO205PDB3<br>33<br>IO205NDB3<br>34<br>GFC2/IO204PDB3<br>35<br>IO204NDB3<br>36<br>VCC<br>37<br>IO199PDB3<br>38<br>IO199NDB3<br>39<br>IO197PSB3<br>40<br>VCCIB3<br>41<br>GND<br>42<br>IO191PDB3<br>43<br>IO191NDB3<br>44<br>GEC1/IO190PDB3<br>45<br>GEC0/IO190NDB3<br>46<br>GEB1/IO189PDB3<br>47<br>GEB0/IO189NDB3<br>48<br>GEA1/IO188PDB3<br>49<br>GEA0/IO188NDB3<br>50<br>VMV3<br>51<br>GNDQ<br>52<br>GND<br>53<br>VMV2<br>54<br>GEA2/IO187RSB2<br>55<br>GEB2/IO186RSB2<br>56<br>GEC2/IO185RSB2<br>57<br>IO184RSB2<br>58<br>IO183RSB2<br>59<br>IO182RSB2<br>60<br>IO181RSB2<br>61<br>IO180RSB2<br>62<br>VCCIB2<br>63<br>IO178RSB2<br>64<br>IO176RSB2<br>65<br>GND<br>66<br>IO174RSB2<br>67<br>IO172RSB2<br>68<br>IO170RSB2<br>69<br>IO168RSB2<br>70<br>IO166RSB2<br>71<br>VCC<br>72<br>VCCIB2<br>**PQ208**<br>**Pin Number**<br>**A3P1000 Function**<br>73<br>IO162RSB2<br>74<br>IO160RSB2<br>75<br>IO158RSB2<br>76<br>IO156RSB2<br>77<br>IO154RSB2<br>78<br>IO152RSB2<br>79<br>IO150RSB2<br>80<br>IO148RSB2<br>81<br>GND<br>82<br>IO143RSB2<br>83<br>IO141RSB2<br>84<br>IO139RSB2<br>85<br>IO137RSB2<br>86<br>IO135RSB2<br>87<br>IO133RSB2<br>88<br>VCC<br>89<br>VCCIB2<br>90<br>IO128RSB2<br>91<br>IO126RSB2<br>92<br>IO124RSB2<br>93<br>IO122RSB2<br>94<br>IO120RSB2<br>95<br>IO118RSB2<br>96<br>GDC2/IO116RSB2<br>97<br>GND<br>98<br>GDB2/IO115RSB2<br>99<br>GDA2/IO114RSB2<br>100<br>GNDQ<br>101<br>TCK<br>102<br>TDI<br>103<br>TMS<br>104<br>VMV2<br>105<br>GND<br>106<br>VPUMP<br>107<br>GNDQ<br>108<br>TDO<br>**PQ208**<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee ~~ie~~Os~~<br>~~a ee ~~ie~~es~~<br>~~Oo~~<br>~~es~~<br>~~a ee ~~ie~~es~~<br>~~sses~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~i~~Rseoes~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~ee~~<br>~~ee es~~<br>~~Ooes~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~i~~Rseoes~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~a ee es~~<br>~~Ooes~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~es~~<br>~~a ee ~~ie~~es eo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~ee~~<br>~~ee es~~<br>~~Ooes~~<br>~~a~~<br>~~ee eseo~~<br>~~es~~<br>~~a ee ~~ie~~es eo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~ee~~<br>~~ee es~~<br>~~Ooes~~<br>~~a~~<br>~~ee eseo~~<br>~~es~~<br>~~a ee ~~ie~~es eo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~ee~~<br>~~ee es~~<br>~~Ooes~~<br>~~a ee ~~ie~~es~~<br>~~sses~~<br>~~a~~<br>~~ee eseo~~<br>~~es~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~a ee ~~ie~~es~~<br>~~Oo~~<br>~~aeees~~<br>~~fs~~|
|---|
**Revision 18**
**4-37**
_Package Pin Assignments_
|109<br>TRST<br>110<br>VJTAG<br>111<br>GDA0/IO113NDB1<br>112<br>GDA1/IO113PDB1<br>113<br>GDB0/IO112NDB1<br>114<br>GDB1/IO112PDB1<br>115<br>GDC0/IO111NDB1<br>116<br>GDC1/IO111PDB1<br>117<br>IO109NDB1<br>118<br>IO109PDB1<br>119<br>IO106NDB1<br>120<br>IO106PDB1<br>121<br>IO104PSB1<br>122<br>GND<br>123<br>VCCIB1<br>124<br>IO99NDB1<br>125<br>IO99PDB1<br>126<br>NC<br>127<br>IO96NDB1<br>128<br>GCC2/IO96PDB1<br>129<br>GCB2/IO95PSB1<br>130<br>GND<br>131<br>GCA2/IO94PSB1<br>132<br>GCA1/IO93PDB1<br>133<br>GCA0/IO93NDB1<br>134<br>GCB0/IO92NDB1<br>135<br>GCB1/IO92PDB1<br>136<br>GCC0/IO91NDB1<br>137<br>GCC1/IO91PDB1<br>138<br>IO88NDB1<br>139<br>IO88PDB1<br>140<br>VCCIB1<br>141<br>GND<br>142<br>VCC<br>143<br>IO86PSB1<br>144<br>IO84NDB1<br>**PQ208**<br>**Pin Number**<br>**A3P1000 Function**<br>145<br>IO84PDB1<br>146<br>IO82NDB1<br>147<br>IO82PDB1<br>148<br>IO80NDB1<br>149<br>GBC2/IO80PDB1<br>150<br>IO79NDB1<br>151<br>GBB2/IO79PDB1<br>152<br>IO78NDB1<br>153<br>GBA2/IO78PDB1<br>154<br>VMV1<br>155<br>GNDQ<br>156<br>GND<br>157<br>VMV0<br>158<br>GBA1/IO77RSB0<br>159<br>GBA0/IO76RSB0<br>160<br>GBB1/IO75RSB0<br>161<br>GBB0/IO74RSB0<br>162<br>GND<br>163<br>GBC1/IO73RSB0<br>164<br>GBC0/IO72RSB0<br>165<br>IO70RSB0<br>166<br>IO67RSB0<br>167<br>IO63RSB0<br>168<br>IO60RSB0<br>169<br>IO57RSB0<br>170<br>VCCIB0<br>171<br>VCC<br>172<br>IO54RSB0<br>173<br>IO51RSB0<br>174<br>IO48RSB0<br>175<br>IO45RSB0<br>176<br>IO42RSB0<br>177<br>IO40RSB0<br>178<br>GND<br>179<br>IO38RSB0<br>180<br>IO35RSB0<br>**PQ208**<br>**Pin Number**<br>**A3P1000 Function**<br>181<br>IO33RSB0<br>182<br>IO31RSB0<br>183<br>IO29RSB0<br>184<br>IO27RSB0<br>185<br>IO25RSB0<br>186<br>VCCIB0<br>187<br>VCC<br>188<br>IO22RSB0<br>189<br>IO20RSB0<br>190<br>IO18RSB0<br>191<br>IO16RSB0<br>192<br>IO15RSB0<br>193<br>IO14RSB0<br>194<br>IO13RSB0<br>195<br>GND<br>196<br>IO12RSB0<br>197<br>IO11RSB0<br>198<br>IO10RSB0<br>199<br>IO09RSB0<br>200<br>VCCIB0<br>201<br>GAC1/IO05RSB0<br>202<br>GAC0/IO04RSB0<br>203<br>GAB1/IO03RSB0<br>204<br>GAB0/IO02RSB0<br>205<br>GAA1/IO01RSB0<br>206<br>GAA0/IO00RSB0<br>207<br>GNDQ<br>208<br>VMV0<br>**PQ208**<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee ~~ie~~Os~~<br>~~a ee ~~ie~~es~~<br>~~Oo~~<br>~~es~~<br>~~a ee ~~ie~~es~~<br>~~sses~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~i~~Rseoes~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~ee~~<br>~~ee es~~<br>~~Ooes~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~i~~Rseoes~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~a ee es~~<br>~~Ooes~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~es~~<br>~~a ee ~~ie~~es eo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~ee~~<br>~~ee es~~<br>~~Ooes~~<br>~~a~~<br>~~ee eseo~~<br>~~es~~<br>~~a ee ~~ie~~es eo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo es~~<br>~~ee~~<br>~~ee es~~<br>~~Ooes~~<br>~~a~~<br>~~ee eseo~~<br>~~es~~<br>~~a ee ~~ie~~es eo~~<br>~~ee~~<br>~~ee ~~ie~~Os~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~a ee~~<br>~~ee~~<br>~~a ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~|
|---|
**4-38**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **FG144 – Bottom View**
|A1 Ball Pad Corner||
|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12||
|ORORORORONORORONONONONO)|A|
|OOO0000000000|B|
|OOO0000000000|C|
|CROROROROROROROTORORONO|D|
|OO0O000000000|E|
|OOO0000000000|F|
|ORORORORONOROROTORORONO|G|
|CROROROROROROROTORORON©|H|
|OO0O000000000|J|
|OOO0000000000|K|
|CROROROROROROROTORORONO|L|
|ORONORORORORORONORORONO|M|
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**Revision 18**
**4-39**
_Package Pin Assignments_
**==> picture [465 x 650] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|FG144|FG144|FG144|
|es|ie|Os|
|Pin Number|A3P060 Function|Pin Number|A3P060 Function|Pin Number|A3P060 Function|
|es|ee|ie|es|Os|
|A1|GNDQ|D1|IO91RSB1|G1|GFA1/IO84RSB1|
|es|ee|ie|es|ss|
|A2|VMV0|D2|IO92RSB1|G2|GND|
|es|ee es|ss|
|A3|GAB0/IO04RSB0|D3|IO93RSB1|G3|VCCPLF|
|es|ee|ie|es|so|
|A4|GAB1/IO05RSB0|D4|GAA2/IO51RSB1|G4|GFA0/IO85RSB1|
|es|ees(n|
|A5|IO08RSB0|D5|GAC0/IO06RSB0|G5|GND|
|es|ee es|Os|
|A6|GND|D6|GAC1/IO07RSB0|G6|GND|
|es|ee|ie|Ds|Os|
|A7|IO11RSB0|D7|GBC0/IO19RSB0|G7|GND|
|es|ee|ie|es|Os|
|A8|VCC|D8|GBC1/IO20RSB0|G8|GDC1/IO45RSB0|
|es|ee es|ss|
|A9|IO16RSB0|D9|GBB2/IO27RSB0|G9|IO32RSB0|
|es|ee|ie|es|so|
|A10|GBA0/IO23RSB0|D10|IO18RSB0|G10|GCC2/IO43RSB0|
|es|ees(n|
|A11|GBA1/IO24RSB0|D11|IO28RSB0|G11|IO31RSB0|
|es|ee es|Os|
|A12|GNDQ|D12|GCB1/IO37RSB0|G12|GCB2/IO42RSB0|
|es|ee|ie|Ds|Os|
|B1|GAB2/IO53RSB1|E1|VCC|H1|VCC|
|es|ee|ie|es|Oo|
|B2|GND|E2|GFC0/IO88RSB1|H2|GFB2/IO82RSB1|
|es|ee|ie|es|ss|
|B3|GAA0/IO02RSB0|E3|GFC1/IO89RSB1|H3|GFC2/IO81RSB1|
|es|ee|ie|Ps es|
|B4|GAA1/IO03RSB0|E4|VCCIB1|H4|GEC1/IO77RSB1|
|es|ees(n|
|B5|IO00RSB0|E5|IO52RSB1|H5|VCC|
|es|ee es|Os|
|B6|IO10RSB0|E6|VCCIB0|H6|IO34RSB0|
|es|ee|ie|Ds|Os|
|B7|IO12RSB0|E7|VCCIB0|H7|IO44RSB0|
|es|ee|ie|es|Os|
|B8|IO14RSB0|E8|GCC1/IO35RSB0|H8|GDB2/IO55RSB1|
|es|ee es|Go|
|B9|GBB0/IO21RSB0|E9|VCCIB0|H9|GDC0/IO46RSB0|
|es|ee|ie|Ps es|
|B10|GBB1/IO22RSB0|E10|VCC|H10|VCCIB0|
|es|ees(n|
|B11|GND|E11|GCA0/IO40RSB0|H11|IO33RSB0|
|es|ee es|Os|
|B12|VMV0|E12|IO30RSB0|H12|VCC|
|es|ee|ie|Ds|Os|
|C1|IO95RSB1|F1|GFB0/IO86RSB1|J1|GEB1/IO75RSB1|
|es|ee|ie|es|Os|
|C2|GFA2/IO83RSB1|F2|VCOMPLF|J2|IO78RSB1|
|es|ee es|Go|
|C3|GAC2/IO94RSB1|F3|GFB1/IO87RSB1|J3|VCCIB1|
|es|ee|ie|Ps es|
|C4|VCC|F4|IO90RSB1|J4|GEC0/IO76RSB1|
|es|ees(n|
|C5|IO01RSB0|F5|GND|J5|IO79RSB1|
|es|ee es|Os|
|C6|IO09RSB0|F6|GND|J6|IO80RSB1|
|es|ee|ie|Ds|Os|
|C7|IO13RSB0|F7|GND|J7|VCC|
|es|ee|ie|es|Os|
|C8|IO15RSB0|F8|GCC0/IO36RSB0|J8|TCK|
|es|ee|ie|es|ss|
|C9|IO17RSB0|F9|GCB0/IO38RSB0|J9|GDA2/IO54RSB1|
|es|ee es|Go|
|C10|GBA2/IO25RSB0|F10|GND|J10|TDO|
|es|ees(n|
|C11|IO26RSB0|F11|GCA1/IO39RSB0|J11|GDA1/IO49RSB0|
|es|ne ns|Os|
|C12|GBC2/IO29RSB0|F12|GCA2/IO41RSB0|J12|GDB1/IO47RSB0|
|es|ee|Rs Rn|
**----- End of picture text -----**<br>
**4-40**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**FG144 Pin Number A3P060 Function** ~~a~~ K1 GEB0/IO74RSB1 ~~a~~ K2 GEA1/IO73RSB1 ~~a~~ K3 GEA0/IO72RSB1 ~~a~~ K4 GEA2/IO71RSB1 ~~ee ee~~ K5 IO65RSB1 ~~ee eee~~ K6 IO64RSB1 ~~re~~ K7 GND ~~a~~ K8 IO57RSB1 ~~a~~ K9 GDC2/IO56RSB1 ~~a~~ K10 GND ~~ee ee~~ K11 GDA0/IO50RSB0 ~~ee eee~~ K12 GDB0/IO48RSB0 ~~re~~ L1 GND ~~ee ee~~ L2 VMV1 ~~a~~ L3 GEB2/IO70RSB1 ~~a~~ L4 IO67RSB1 ~~ee ee~~ L5 VCCIB1 ~~ee eee~~ L6 IO62RSB1 ~~re~~ L7 IO59RSB1 ~~a~~ L8 IO58RSB1 ~~a~~ L9 TMS ~~a~~ L10 VJTAG ~~ee ee~~ L11 VMV1 ~~ee eee~~ L12 TRST ~~re~~ M1 GNDQ ~~a~~ M2 GEC2/IO69RSB1 ~~a~~ M3 IO68RSB1 ~~a~~ M4 IO66RSB1 ~~ee ee~~ M5 IO63RSB1 ~~ee eee~~ M6 IO61RSB1 ~~re~~ M7 IO60RSB1 ~~a~~ M8 NC ~~a~~ M9 TDI ~~a~~ M10 VCCIB1 ~~ee ee~~ M11 VPUMP ~~ee eee~~ M12 GNDQ ~~ee ee~~
**Revision 18**
**4-41**
_Package Pin Assignments_
|**FG144**<br>**Pin Number**<br>**A3P125 Function**<br>A1<br>GNDQ<br>A2<br>VMV0<br>A3<br>GAB0/IO02RSB0<br>A4<br>GAB1/IO03RSB0<br>A5<br>IO11RSB0<br>A6<br>GND<br>A7<br>IO18RSB0<br>A8<br>VCC<br>A9<br>IO25RSB0<br>A10<br>GBA0/IO39RSB0<br>A11<br>GBA1/IO40RSB0<br>A12<br>GNDQ<br>B1<br>GAB2/IO69RSB1<br>B2<br>GND<br>B3<br>GAA0/IO00RSB0<br>B4<br>GAA1/IO01RSB0<br>B5<br>IO08RSB0<br>B6<br>IO14RSB0<br>B7<br>IO19RSB0<br>B8<br>IO22RSB0<br>B9<br>GBB0/IO37RSB0<br>B10<br>GBB1/IO38RSB0<br>B11<br>GND<br>B12<br>VMV0<br>C1<br>IO132RSB1<br>C2<br>GFA2/IO120RSB1<br>C3<br>GAC2/IO131RSB1<br>C4<br>VCC<br>C5<br>IO10RSB0<br>C6<br>IO12RSB0<br>C7<br>IO21RSB0<br>C8<br>IO24RSB0<br>C9<br>IO27RSB0<br>C10<br>GBA2/IO41RSB0<br>C11<br>IO42RSB0<br>C12<br>GBC2/IO45RSB0<br>D1<br>IO128RSB1<br>D2<br>IO129RSB1<br>D3<br>IO130RSB1<br>D4<br>GAA2/IO67RSB1<br>D5<br>GAC0/IO04RSB0<br>D6<br>GAC1/IO05RSB0<br>D7<br>GBC0/IO35RSB0<br>D8<br>GBC1/IO36RSB0<br>D9<br>GBB2/IO43RSB0<br>D10<br>IO28RSB0<br>D11<br>IO44RSB0<br>D12<br>GCB1/IO53RSB0<br>E1<br>VCC<br>E2<br>GFC0/IO125RSB1<br>E3<br>GFC1/IO126RSB1<br>E4<br>VCCIB1<br>E5<br>IO68RSB1<br>E6<br>VCCIB0<br>E7<br>VCCIB0<br>E8<br>GCC1/IO51RSB0<br>E9<br>VCCIB0<br>E10<br>VCC<br>E11<br>GCA0/IO56RSB0<br>E12<br>IO46RSB0<br>F1<br>GFB0/IO123RSB1<br>F2<br>VCOMPLF<br>F3<br>GFB1/IO124RSB1<br>F4<br>IO127RSB1<br>F5<br>GND<br>F6<br>GND<br>F7<br>GND<br>F8<br>GCC0/IO52RSB0<br>F9<br>GCB0/IO54RSB0<br>F10<br>GND<br>F11<br>GCA1/IO55RSB0<br>F12<br>GCA2/IO57RSB0<br>**FG144**<br>**Pin Number**<br>**A3P125 Function**<br>~~ee ~~ie~~Gs~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es~~<br>~~so~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~ss~~<br>~~ee~~<br>~~ees(n~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~es0s~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~ss~~<br>~~ee~~<br>~~ees(n~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~ss~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~so~~<br>~~ee~~<br>~~ees(n~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~es0s~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~so~~<br>~~ee~~<br>~~ees(n~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~es0s~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~so~~<br>~~ee~~<br>~~ees(n~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~eees~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~es0s~~<br>~~ee~~<br>~~ee es~~<br>~~so~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ees(n~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~ie~~Rs~~<br>~~fn~~|G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11<br>G12<br>H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>H12<br>J1<br>J2<br>J3<br>J4<br>J5<br>J6<br>J7<br>J8<br>J9<br>J10<br>J11<br>J12<br>**Pin Number**|GFA1/IO121RSB1<br>GND<br>VCCPLF<br>GFA0/IO122RSB1<br>GND<br>GND<br>GND<br>GDC1/IO61RSB0<br>IO48RSB0<br>GCC2/IO59RSB0<br>IO47RSB0<br>GCB2/IO58RSB0<br>VCC<br>GFB2/IO119RSB1<br>GFC2/IO118RSB1<br>GEC1/IO112RSB1<br>VCC<br>IO50RSB0<br>IO60RSB0<br>GDB2/IO71RSB1<br>GDC0/IO62RSB0<br>VCCIB0<br>IO49RSB0<br>VCC<br>GEB1/IO110RSB1<br>IO115RSB1<br>VCCIB1<br>GEC0/IO111RSB1<br>IO116RSB1<br>IO117RSB1<br>VCC<br>TCK<br>GDA2/IO70RSB1<br>TDO<br>GDA1/IO65RSB0<br>GDB1/IO63RSB0<br>**FG144**<br>**A3P125 Function**|
|---|---|---|
**4-42**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**FG144 Pin Number A3P125 Function** ~~a~~ K1 GEB0/IO109RSB1 ~~a~~ K2 GEA1/IO108RSB1 ~~a~~ K3 GEA0/IO107RSB1 ~~a~~ K4 GEA2/IO106RSB1 ~~ee ee~~ K5 IO100RSB1 ~~ee~~ K6 IO98RSB1 ~~a~~ K7 GND ~~a~~ K8 IO73RSB1 ~~a~~ K9 GDC2/IO72RSB1 ~~a~~ K10 GND ~~ee ee~~ K11 GDA0/IO66RSB0 ~~ee~~ K12 GDB0/IO64RSB0 ~~a~~ L1 GND ~~a~~ L2 VMV1 ~~a~~ L3 GEB2/IO105RSB1 ~~a~~ L4 IO102RSB1 ~~ee ee~~ L5 VCCIB1 ~~ee~~ L6 IO95RSB1 ~~a~~ L7 IO85RSB1 ~~a~~ L8 IO74RSB1 ~~a~~ L9 TMS ~~a~~ L10 VJTAG ~~ee ee~~ L11 VMV1 ~~ee~~ L12 TRST ~~a~~ M1 GNDQ ~~a~~ M2 GEC2/IO104RSB1 ~~a~~ M3 IO103RSB1 ~~a~~ M4 IO101RSB1 ~~ee ee~~ M5 IO97RSB1 ~~ee~~ M6 IO94RSB1 ~~a~~ M7 IO86RSB1 ~~a~~ M8 IO75RSB1 ~~a~~ M9 TDI ~~a~~ M10 VCCIB1 ~~ee ee~~ M11 VPUMP ~~a~~ M12 GNDQ ~~ee ee~~
**Revision 18**
**4-43**
_Package Pin Assignments_
**==> picture [465 x 650] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|FG144|FG144|FG144|
|ee|ie|Os|
|Pin Number|A3P250 Function|Pin Number|A3P250 Function|Pin Number|A3P250 Function|
|es|ee es|Os|
|A1|GNDQ|D1|IO112NDB3|G1|GFA1/IO108PPB3|
|es|ee|i|es eo|
|A2|VMV0|D2|IO112PDB3|G2|GND|
|es|ee es|Oo|
|A3|GAB0/IO02RSB0|D3|IO116VDB3|G3|VCCPLF|
|es|ee es|Oo|
|A4|GAB1/IO03RSB0|D4|GAA2/IO118UPB3|G4|GFA0/IO108NPB3|
|ee|en|ie|Gs|Os|
|A5|IO16RSB0|D5|GAC0/IO04RSB0|G5|GND|
|es|ee|ie|es|Oo|
|A6|GND|D6|GAC1/IO05RSB0|G6|GND|
|ee|ee|ie|es|Oo|
|A7|IO29RSB0|D7|GBC0/IO35RSB0|G7|GND|
|es|ee es|Os|
|A8|VCC|D8|GBC1/IO36RSB0|G8|GDC1/IO58UPB1|
|es|ee es|Oo|
|A9|IO33RSB0|D9|GBB2/IO42PDB1|G9|IO53NDB1|
|es|ee es|Oo|
|A10|GBA0/IO39RSB0|D10|IO42NDB1|G10|GCC2/IO53PDB1|
|ee|en|ie|Gs|Os|
|A11|GBA1/IO40RSB0|D11|IO43NPB1|G11|IO52NDB1|
|es|ee|ie|es|Oo|
|A12|GNDQ|D12|GCB1/IO49PPB1|G12|GCB2/IO52PDB1|
|ee|ee|ie|es|Oo|
|B1|GAB2/IO117UDB3|E1|VCC|H1|VCC|
|es|ee|Ps|Oo|
|B2|GND|E2|GFC0/IO110NDB3|H2|GFB2/IO106PDB3|
|ee|ee es es|Oo|
|B3|GAA0/IO00RSB0|E3|GFC1/IO110PDB3|H3|GFC2/IO105PSB3|
|ee|ee es|Os|
|B4|GAA1/IO01RSB0|E4|VCCIB3|H4|GEC1/IO100PDB3|
|ee|en|ie|Gs|Os|
|B5|IO14RSB0|E5|IO118VPB3|H5|VCC|
|es|ee|ie|es|Oo|
|B6|IO19RSB0|E6|VCCIB0|H6|IO79RSB2|
|ee|ee|ie|es|Oo|
|B7|IO22RSB0|E7|VCCIB0|H7|IO65RSB2|
|es|ee es|Os|
|B8|IO30RSB0|E8|GCC1/IO48PDB1|H8|GDB2/IO62RSB2|
|ee|ee|ie|es|Oo|
|B9|GBB0/IO37RSB0|E9|VCCIB1|H9|GDC0/IO58VPB1|
|ee|ee es|Os|
|B10|GBB1/IO38RSB0|E10|VCC|H10|VCCIB1|
|ee|en|ie|Gs|Os|
|B11|GND|E11|GCA0/IO50NDB1|H11|IO54PSB1|
|es|ee|ie|es|Oo|
|B12|VMV1|E12|IO51NDB1|H12|VCC|
|ee|ee|ie|es|Oo|
|C1|IO117VDB3|F1|GFB0/IO109NPB3|J1|GEB1/IO99PDB3|
|es|ee es|Os|
|C2|GFA2/IO107PPB3|F2|VCOMPLF|J2|IO106NDB3|
|ee|ee|ie|es|Oo|
|C3|GAC2/IO116UDB3|F3|GFB1/IO109PPB3|J3|VCCIB3|
|ee|ee es|Os|
|C4|VCC|F4|IO107NPB3|J4|GEC0/IO100NDB3|
|ee|en|ie|Gs|Os|
|C5|IO12RSB0|F5|GND|J5|IO88RSB2|
|es|ee|ie|es|Oo|
|C6|IO17RSB0|F6|GND|J6|IO81RSB2|
|ee|ee|ie|es|Oo|
|C7|IO24RSB0|F7|GND|J7|VCC|
|es|ee es|Os|
|C8|IO31RSB0|F8|GCC0/IO48NDB1|J8|TCK|
|es|ee|i|es eo|
|C9|IO34RSB0|F9|GCB0/IO49NPB1|J9|GDA2/IO61RSB2|
|ee|ee|ie|es|Oo|
|C10|GBA2/IO41PDB1|F10|GND|J10|TDO|
|ee|en|ie|Gs|Os|
|C11|IO41NDB1|F11|GCA1/IO50PDB1|J11|GDA1/IO60UDB1|
|ee|en|ie|Gs|Os|
|C12|GBC2/IO43PPB1|F12|GCA2/IO51PDB1|J12|GDB1/IO59UDB1|
|ee|ee es|fo|
**----- End of picture text -----**<br>
**4-44**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**FG144 Pin Number A3P250 Function** ~~a~~ K1 GEB0/IO99NDB3 ~~a~~ K2 GEA1/IO98PDB3 ~~a~~ K3 GEA0/IO98NDB3 ~~a~~ K4 GEA2/IO97RSB2 ~~ee eee~~ K5 IO90RSB2 ~~ee~~ K6 IO84RSB2 ~~a~~ K7 GND ~~a~~ K8 IO66RSB2 ~~a~~ K9 GDC2/IO63RSB2 ~~a~~ K10 GND ~~ee eee~~ K11 GDA0/IO60VDB1 ~~ee~~ K12 GDB0/IO59VDB1 ~~a~~ L1 GND ~~a~~ L2 VMV3 ~~a~~ L3 GEB2/IO96RSB2 ~~a~~ L4 IO91RSB2 ~~ee eee~~ L5 VCCIB2 ~~ee~~ L6 IO82RSB2 ~~a~~ L7 IO80RSB2 ~~a~~ L8 IO72RSB2 ~~a~~ L9 TMS ~~a~~ L10 VJTAG ~~ee eee~~ L11 VMV2 ~~ee~~ L12 TRST ~~a~~ M1 GNDQ ~~a~~ M2 GEC2/IO95RSB2 ~~a~~ M3 IO92RSB2 ~~a~~ M4 IO89RSB2 ~~ee eee~~ M5 IO87RSB2 ~~ee~~ M6 IO85RSB2 ~~a~~ M7 IO78RSB2 ~~a~~ M8 IO76RSB2 ~~a~~ M9 TDI ~~a~~ M10 VCCIB2 ~~ee eee~~ M11 VPUMP ~~ee eee~~ M12 GNDQ ~~ee ee~~
**Revision 18**
**4-45**
_Package Pin Assignments_
|**FG144**<br>**Pin Number**<br>**A3P400 Function**<br>A1<br>GNDQ<br>A2<br>VMV0<br>A3<br>GAB0/IO02RSB0<br>A4<br>GAB1/IO03RSB0<br>A5<br>IO16RSB0<br>A6<br>GND<br>A7<br>IO30RSB0<br>A8<br>VCC<br>A9<br>IO34RSB0<br>A10<br>GBA0/IO58RSB0<br>A11<br>GBA1/IO59RSB0<br>A12<br>GNDQ<br>B1<br>GAB2/IO154UDB3<br>B2<br>GND<br>B3<br>GAA0/IO00RSB0<br>B4<br>GAA1/IO01RSB0<br>B5<br>IO14RSB0<br>B6<br>IO19RSB0<br>B7<br>IO23RSB0<br>B8<br>IO31RSB0<br>B9<br>GBB0/IO56RSB0<br>B10<br>GBB1/IO57RSB0<br>B11<br>GND<br>B12<br>VMV1<br>C1<br>IO154VDB3<br>C2<br>GFA2/IO144PPB3<br>C3<br>GAC2/IO153UDB3<br>C4<br>VCC<br>C5<br>IO12RSB0<br>C6<br>IO17RSB0<br>C7<br>IO25RSB0<br>C8<br>IO32RSB0<br>C9<br>IO53RSB0<br>C10<br>GBA2/IO60PDB1<br>C11<br>IO60NDB1<br>C12<br>GBC2/IO62PPB1<br>D1<br>IO149NDB3<br>D2<br>IO149PDB3<br>D3<br>IO153VDB3<br>D4<br>GAA2/IO155UPB3<br>D5<br>GAC0/IO04RSB0<br>D6<br>GAC1/IO05RSB0<br>D7<br>GBC0/IO54RSB0<br>D8<br>GBC1/IO55RSB0<br>D9<br>GBB2/IO61PDB1<br>D10<br>IO61NDB1<br>D11<br>IO62NPB1<br>D12<br>GCB1/IO68PPB1<br>E1<br>VCC<br>E2<br>GFC0/IO147NDB3<br>E3<br>GFC1/IO147PDB3<br>E4<br>VCCIB3<br>E5<br>IO155VPB3<br>E6<br>VCCIB0<br>E7<br>VCCIB0<br>E8<br>GCC1/IO67PDB1<br>E9<br>VCCIB1<br>E10<br>VCC<br>E11<br>GCA0/IO69NDB1<br>E12<br>IO70NDB1<br>F1<br>GFB0/IO146NPB3<br>F2<br>VCOMPLF<br>F3<br>GFB1/IO146PPB3<br>F4<br>IO144NPB3<br>F5<br>GND<br>F6<br>GND<br>F7<br>GND<br>F8<br>GCC0/IO67NDB1<br>F9<br>GCB0/IO68NPB1<br>F10<br>GND<br>F11<br>GCA1/IO69PDB1<br>F12<br>GCA2/IO70PDB1<br>**FG144**<br>**Pin Number**<br>**A3P400 Function**<br>G1<br>GFA1/IO145PPB3<br>G2<br>GND<br>G3<br>VCCPLF<br>G4<br>GFA0/IO145NPB3<br>G5<br>GND<br>G6<br>GND<br>G7<br>GND<br>G8<br>GDC1/IO77UPB1<br>G9<br>IO72NDB1<br>G10<br>GCC2/IO72PDB1<br>G11<br>IO71NDB1<br>G12<br>GCB2/IO71PDB1<br>H1<br>VCC<br>H2<br>GFB2/IO143PDB3<br>H3<br>GFC2/IO142PSB3<br>H4<br>GEC1/IO137PDB3<br>H5<br>VCC<br>H6<br>IO75PDB1<br>H7<br>IO75NDB1<br>H8<br>GDB2/IO81RSB2<br>H9<br>GDC0/IO77VPB1<br>H10<br>VCCIB1<br>H11<br>IO73PSB1<br>H12<br>VCC<br>J1<br>GEB1/IO136PDB3<br>J2<br>IO143NDB3<br>J3<br>VCCIB3<br>J4<br>GEC0/IO137NDB3<br>J5<br>IO125RSB2<br>J6<br>IO116RSB2<br>J7<br>VCC<br>J8<br>TCK<br>J9<br>GDA2/IO80RSB2<br>J10<br>TDO<br>J11<br>GDA1/IO79UDB1<br>J12<br>GDB1/IO78UDB1<br>**FG144**<br>**Pin Number**<br>**A3P400 Function**<br>~~ee ~~ie~~Os~~<br>~~es~~<br>~~eePs~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Ooes~~<br>~~es ee ~~ie~~es~~<br>~~Ooes~~<br>~~a ee Re es es~~<br>~~es~~<br>~~ne ns~~<br>~~Os~~<br>~~es~~<br>~~eees~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es ee ~~ie~~es~~<br>~~Ooes~~<br>~~a ee Re es es~~<br>~~es~~<br>~~ne ns~~<br>~~Os~~<br>~~es~~<br>~~eees~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~so~~<br>~~a ee eses~~<br>~~es~~<br>~~ne ns~~<br>~~Os~~<br>~~es~~<br>~~eees~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~eeee~~<br>~~Oo~~<br>~~a ee eses~~<br>~~es~~<br>~~ne ns~~<br>~~Os~~<br>~~es~~<br>~~eees~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~eeee~~<br>~~Oo~~<br>~~a ee eses~~<br>~~es~~<br>~~ne ns~~<br>~~Os~~<br>~~es~~<br>~~eees~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~Oo~~<br>~~es~~<br>~~ee es~~<br>~~Oo~~<br>~~es~~<br>~~ee ~~ie~~es~~<br>~~Ooes~~<br>~~es~~<br>~~eeee~~<br>~~Oo~~<br>~~es~~<br>~~ne ns~~<br>~~Os~~<br>~~es~~<br>~~ee ~~ie<br>~~nsOn~~<br>~~es~~<br>~~eefn~~|
|---|
**4-46**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**FG144 Pin Number A3P400 Function** ~~a~~ K1 GEB0/IO136NDB3 ~~a~~ K2 GEA1/IO135PDB3 ~~a~~ K3 GEA0/IO135NDB3 ~~a~~ K4 GEA2/IO134RSB2 ~~ee ee~~ K5 IO127RSB2 ~~a~~ K6 IO121RSB2 ~~a~~ K7 GND ~~a~~ K8 IO104RSB2 ~~a~~ K9 GDC2/IO82RSB2 ~~a~~ K10 GND ~~ee ee~~ K11 GDA0/IO79VDB1 ~~a~~ K12 GDB0/IO78VDB1 ~~a~~ L1 GND ~~a~~ L2 VMV3 ~~a~~ L3 GEB2/IO133RSB2 ~~a~~ L4 IO128RSB2 ~~ee ee~~ L5 VCCIB2 ~~a~~ L6 IO119RSB2 ~~a~~ L7 IO114RSB2 ~~a~~ L8 IO110RSB2 ~~a~~ L9 TMS ~~a~~ L10 VJTAG ~~ee ee~~ L11 VMV2 ~~a~~ L12 TRST ~~a~~ M1 GNDQ ~~a~~ M2 GEC2/IO132RSB2 ~~a~~ M3 IO129RSB2 ~~a~~ M4 IO126RSB2 ~~ee ee~~ M5 IO124RSB2 ~~a~~ M6 IO122RSB2 ~~a~~ M7 IO117RSB2 ~~a~~ M8 IO115RSB2 ~~a~~ M9 TDI ~~a~~ M10 VCCIB2 ~~ee ee~~ M11 VPUMP ~~a eee~~ M12 GNDQ ~~a ee~~
**Revision 18**
**4-47**
_Package Pin Assignments_
|**FG144**<br>**Pin Number**<br>**A3P600 Function**<br>A1<br>GNDQ<br>A2<br>VMV0<br>A3<br>GAB0/IO02RSB0<br>A4<br>GAB1/IO03RSB0<br>A5<br>IO10RSB0<br>A6<br>GND<br>A7<br>IO34RSB0<br>A8<br>VCC<br>A9<br>IO50RSB0<br>A10<br>GBA0/IO58RSB0<br>A11<br>GBA1/IO59RSB0<br>A12<br>GNDQ<br>B1<br>GAB2/IO173PDB3<br>B2<br>GND<br>B3<br>GAA0/IO00RSB0<br>B4<br>GAA1/IO01RSB0<br>B5<br>IO13RSB0<br>B6<br>IO19RSB0<br>B7<br>IO31RSB0<br>B8<br>IO39RSB0<br>B9<br>GBB0/IO56RSB0<br>B10<br>GBB1/IO57RSB0<br>B11<br>GND<br>B12<br>VMV1<br>C1<br>IO173NDB3<br>C2<br>GFA2/IO161PPB3<br>C3<br>GAC2/IO172PDB3<br>C4<br>VCC<br>C5<br>IO16RSB0<br>C6<br>IO25RSB0<br>C7<br>IO28RSB0<br>C8<br>IO42RSB0<br>C9<br>IO45RSB0<br>C10<br>GBA2/IO60PDB1<br>C11<br>IO60NDB1<br>C12<br>GBC2/IO62PPB1<br>D1<br>IO169PDB3<br>D2<br>IO169NDB3<br>D3<br>IO172NDB3<br>D4<br>GAA2/IO174PPB3<br>D5<br>GAC0/IO04RSB0<br>D6<br>GAC1/IO05RSB0<br>D7<br>GBC0/IO54RSB0<br>D8<br>GBC1/IO55RSB0<br>D9<br>GBB2/IO61PDB1<br>D10<br>IO61NDB1<br>D11<br>IO62NPB1<br>D12<br>GCB1/IO70PPB1<br>E1<br>VCC<br>E2<br>GFC0/IO164NDB3<br>E3<br>GFC1/IO164PDB3<br>E4<br>VCCIB3<br>E5<br>IO174NPB3<br>E6<br>VCCIB0<br>E7<br>VCCIB0<br>E8<br>GCC1/IO69PDB1<br>E9<br>VCCIB1<br>E10<br>VCC<br>E11<br>GCA0/IO71NDB1<br>E12<br>IO72NDB1<br>F1<br>GFB0/IO163NPB3<br>F2<br>VCOMPLF<br>F3<br>GFB1/IO163PPB3<br>F4<br>IO161NPB3<br>F5<br>GND<br>F6<br>GND<br>F7<br>GND<br>F8<br>GCC0/IO69NDB1<br>F9<br>GCB0/IO70NPB1<br>F10<br>GND<br>F11<br>GCA1/IO71PDB1<br>F12<br>GCA2/IO72PDB1<br>**FG144**<br>**Pin Number**<br>**A3P600 Function**<br>~~ee ~~ie~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee eseo~~<br>~~ee~~<br>~~ee~~<br>~~esso~~<br>~~a ee~~<br>~~eseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Oo~~<br>~~a ee~~<br>~~eseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Oo~~<br>~~a ee~~<br>~~eseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~Gs~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~ie<br>~~esfn~~|G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11<br>G12<br>H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>H12<br>J1<br>J2<br>J3<br>J4<br>J5<br>J6<br>J7<br>J8<br>J9<br>J10<br>J11<br>J12<br>**Pin Number**|GFA1/IO162PPB3<br>GND<br>VCCPLF<br>GFA0/IO162NPB3<br>GND<br>GND<br>GND<br>GDC1/IO86PPB1<br>IO74NDB1<br>GCC2/IO74PDB1<br>IO73NDB1<br>GCB2/IO73PDB1<br>VCC<br>GFB2/IO160PDB3<br>GFC2/IO159PSB3<br>GEC1/IO146PDB3<br>VCC<br>IO80PDB1<br>IO80NDB1<br>GDB2/IO90RSB2<br>GDC0/IO86NPB1<br>VCCIB1<br>IO84PSB1<br>VCC<br>GEB1/IO145PDB3<br>IO160NDB3<br>VCCIB3<br>GEC0/IO146NDB3<br>IO129RSB2<br>IO131RSB2<br>VCC<br>TCK<br>GDA2/IO89RSB2<br>TDO<br>GDA1/IO88PDB1<br>GDB1/IO87PDB1<br>**FG144**<br>**A3P600 Function**|
|---|---|---|
**4-48**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**FG144 Pin Number A3P600 Function** ~~a~~ K1 GEB0/IO145NDB3 ~~a~~ K2 GEA1/IO144PDB3 ~~a~~ K3 GEA0/IO144NDB3 ~~a~~ K4 GEA2/IO143RSB2 ~~ee ee~~ K5 IO119RSB2 ~~a~~ K6 IO111RSB2 ~~a~~ K7 GND ~~a~~ K8 IO94RSB2 ~~a~~ K9 GDC2/IO91RSB2 ~~a~~ K10 GND ~~ee ee~~ K11 GDA0/IO88NDB1 ~~a~~ K12 GDB0/IO87NDB1 ~~a~~ L1 GND ~~a~~ L2 VMV3 ~~a~~ L3 GEB2/IO142RSB2 ~~a~~ L4 IO136RSB2 ~~ee ee~~ L5 VCCIB2 ~~a~~ L6 IO115RSB2 ~~a~~ L7 IO103RSB2 ~~a~~ L8 IO97RSB2 ~~a~~ L9 TMS ~~a~~ L10 VJTAG ~~ee ee~~ L11 VMV2 ~~a~~ L12 TRST ~~a~~ M1 GNDQ ~~a~~ M2 GEC2/IO141RSB2 ~~a~~ M3 IO138RSB2 ~~a~~ M4 IO123RSB2 ~~ee ee~~ M5 IO126RSB2 ~~a~~ M6 IO134RSB2 ~~a~~ M7 IO108RSB2 ~~a~~ M8 IO99RSB2 ~~a~~ M9 TDI ~~a~~ M10 VCCIB2 ~~ee ee~~ M11 VPUMP ~~a~~ M12 GNDQ ~~aee~~
**Revision 18**
**4-49**
_Package Pin Assignments_
|**FG144**<br>**Pin Number**<br>**A3P1000 Function**<br>A1<br>GNDQ<br>A2<br>VMV0<br>A3<br>GAB0/IO02RSB0<br>A4<br>GAB1/IO03RSB0<br>A5<br>IO10RSB0<br>A6<br>GND<br>A7<br>IO44RSB0<br>A8<br>VCC<br>A9<br>IO69RSB0<br>A10<br>GBA0/IO76RSB0<br>A11<br>GBA1/IO77RSB0<br>A12<br>GNDQ<br>B1<br>GAB2/IO224PDB3<br>B2<br>GND<br>B3<br>GAA0/IO00RSB0<br>B4<br>GAA1/IO01RSB0<br>B5<br>IO13RSB0<br>B6<br>IO26RSB0<br>B7<br>IO35RSB0<br>B8<br>IO60RSB0<br>B9<br>GBB0/IO74RSB0<br>B10<br>GBB1/IO75RSB0<br>B11<br>GND<br>B12<br>VMV1<br>C1<br>IO224NDB3<br>C2<br>GFA2/IO206PPB3<br>C3<br>GAC2/IO223PDB3<br>C4<br>VCC<br>C5<br>IO16RSB0<br>C6<br>IO29RSB0<br>C7<br>IO32RSB0<br>C8<br>IO63RSB0<br>C9<br>IO66RSB0<br>C10<br>GBA2/IO78PDB1<br>C11<br>IO78NDB1<br>C12<br>GBC2/IO80PPB1<br>D1<br>IO213PDB3<br>D2<br>IO213NDB3<br>D3<br>IO223NDB3<br>D4<br>GAA2/IO225PPB3<br>D5<br>GAC0/IO04RSB0<br>D6<br>GAC1/IO05RSB0<br>D7<br>GBC0/IO72RSB0<br>D8<br>GBC1/IO73RSB0<br>D9<br>GBB2/IO79PDB1<br>D10<br>IO79NDB1<br>D11<br>IO80NPB1<br>D12<br>GCB1/IO92PPB1<br>E1<br>VCC<br>E2<br>GFC0/IO209NDB3<br>E3<br>GFC1/IO209PDB3<br>E4<br>VCCIB3<br>E5<br>IO225NPB3<br>E6<br>VCCIB0<br>E7<br>VCCIB0<br>E8<br>GCC1/IO91PDB1<br>E9<br>VCCIB1<br>E10<br>VCC<br>E11<br>GCA0/IO93NDB1<br>E12<br>IO94NDB1<br>F1<br>GFB0/IO208NPB3<br>F2<br>VCOMPLF<br>F3<br>GFB1/IO208PPB3<br>F4<br>IO206NPB3<br>F5<br>GND<br>F6<br>GND<br>F7<br>GND<br>F8<br>GCC0/IO91NDB1<br>F9<br>GCB0/IO92NPB1<br>F10<br>GND<br>F11<br>GCA1/IO93PDB1<br>F12<br>GCA2/IO94PDB1<br>**FG144**<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee ~~ie~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee eseo~~<br>~~ee~~<br>~~ee~~<br>~~esso~~<br>~~a ee~~<br>~~eseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Oo~~<br>~~a ee~~<br>~~eseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Oo~~<br>~~a ee~~<br>~~eseo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie<br>~~esOo~~<br>~~a ee~~<br>~~es0s~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~Gs~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~ie<br>~~esfn~~|G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11<br>G12<br>H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>H12<br>J1<br>J2<br>J3<br>J4<br>J5<br>J6<br>J7<br>J8<br>J9<br>J10<br>J11<br>J12<br>**Pin Number**|GFA1/IO207PPB3<br>GND<br>VCCPLF<br>GFA0/IO207NPB3<br>GND<br>GND<br>GND<br>GDC1/IO111PPB1<br>IO96NDB1<br>GCC2/IO96PDB1<br>IO95NDB1<br>GCB2/IO95PDB1<br>VCC<br>GFB2/IO205PDB3<br>GFC2/IO204PSB3<br>GEC1/IO190PDB3<br>VCC<br>IO105PDB1<br>IO105NDB1<br>GDB2/IO115RSB2<br>GDC0/IO111NPB1<br>VCCIB1<br>IO101PSB1<br>VCC<br>GEB1/IO189PDB3<br>IO205NDB3<br>VCCIB3<br>GEC0/IO190NDB3<br>IO160RSB2<br>IO157RSB2<br>VCC<br>TCK<br>GDA2/IO114RSB2<br>TDO<br>GDA1/IO113PDB1<br>GDB1/IO112PDB1<br>**FG144**<br>**A3P1000 Function**|
|---|---|---|
**4-50**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**FG144 Pin Number A3P1000 Function** ~~a~~ K1 GEB0/IO189NDB3 ~~a~~ K2 GEA1/IO188PDB3 ~~a~~ K3 GEA0/IO188NDB3 ~~a~~ K4 GEA2/IO187RSB2 ~~ee ee~~ K5 IO169RSB2 ~~a~~ K6 IO152RSB2 ~~a~~ K7 GND ~~a~~ K8 IO117RSB2 ~~a~~ K9 GDC2/IO116RSB2 ~~a~~ K10 GND ~~ee ee~~ K11 GDA0/IO113NDB1 ~~a~~ K12 GDB0/IO112NDB1 ~~a~~ L1 GND ~~a~~ L2 VMV3 ~~a~~ L3 GEB2/IO186RSB2 ~~a~~ L4 IO172RSB2 ~~ee ee~~ L5 VCCIB2 ~~a~~ L6 IO153RSB2 ~~a~~ L7 IO144RSB2 ~~a~~ L8 IO140RSB2 ~~a~~ L9 TMS ~~a~~ L10 VJTAG ~~ee ee~~ L11 VMV2 ~~a~~ L12 TRST ~~a~~ M1 GNDQ ~~a~~ M2 GEC2/IO185RSB2 ~~a~~ M3 IO173RSB2 ~~a~~ M4 IO168RSB2 ~~ee ee~~ M5 IO161RSB2 ~~a~~ M6 IO156RSB2 ~~a~~ M7 IO145RSB2 ~~a~~ M8 IO141RSB2 ~~a~~ M9 TDI ~~a~~ M10 VCCIB2 ~~ee ee~~ M11 VPUMP ~~a~~ M12 GNDQ ~~aee~~
**Revision 18**
**4-51**
_Package Pin Assignments_
## **FG256 – Bottom View**
|A1 Ball Pad Corner||
|---|---|
|1<br>3<br>5<br>7<br>9<br>11<br>13<br>15<br>2<br>4<br>6<br>8<br>10<br>12<br>14<br>16||
|OOOO000000000000%|A|
|OOQOOCOOQOOOCOO0O0C0C0OO|B|
|OOQOOCOOQOOOCOO0OC0C0OO|C|
|OOQOOCOOQOOCOO0QO0C0C0OO|D|
|OOQOCOOQOOCOOO0C0C0OO|E|
|OOQOOCOOOOCOO0O0C0C0OO|F|
|COOOODDOOOCOO000000|G|
|OOQOOCQOOQOOOCOOO0C0C0OO|H|
|OOQOOCOOQOOCOOOC0C0OO|J|
|OOQOOCOOQOOOCOOOQOC0C0OO|K|
|OOQOOCOOQOOCOOOQOC0C0OO|L|
|OOQOOCOOQOOQCOOOC0C0OO|M|
|OCOOOODDOOOOOQ000000|N|
|OOQOOCOOQOOCCOO0O0C0C0OO|P|
|OOQOOCOOQOOCOCOO0O0C0C0OO|R|
|OOQOOCOOQOOOCOO0QO0C0C0OO|T|
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**4-52**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**FG256**<br>**Pin Number**<br>**A3P250 Function**<br>A1<br>GND<br>A2<br>GAA0/IO00RSB0<br>A3<br>GAA1/IO01RSB0<br>A4<br>GAB0/IO02RSB0<br>A5<br>IO07RSB0<br>A6<br>IO10RSB0<br>A7<br>IO11RSB0<br>A8<br>IO15RSB0<br>A9<br>IO20RSB0<br>A10<br>IO25RSB0<br>A11<br>IO29RSB0<br>A12<br>IO33RSB0<br>A13<br>GBB1/IO38RSB0<br>A14<br>GBA0/IO39RSB0<br>A15<br>GBA1/IO40RSB0<br>A16<br>GND<br>B1<br>GAB2/IO117UDB3<br>B2<br>GAA2/IO118UDB3<br>B3<br>NC<br>B4<br>GAB1/IO03RSB0<br>B5<br>IO06RSB0<br>B6<br>IO09RSB0<br>B7<br>IO12RSB0<br>B8<br>IO16RSB0<br>B9<br>IO21RSB0<br>B10<br>IO26RSB0<br>B11<br>IO30RSB0<br>B12<br>GBC1/IO36RSB0<br>B13<br>GBB0/IO37RSB0<br>B14<br>NC<br>B15<br>GBA2/IO41PDB1<br>B16<br>IO41NDB1<br>C1<br>IO117VDB3<br>C2<br>IO118VDB3<br>C3<br>NC<br>C4<br>NC<br>C5<br>GAC0/IO04RSB0<br>C6<br>GAC1/IO05RSB0<br>C7<br>IO13RSB0<br>C8<br>IO17RSB0<br>C9<br>IO22RSB0<br>C10<br>IO27RSB0<br>C11<br>IO31RSB0<br>C12<br>GBC0/IO35RSB0<br>C13<br>IO34RSB0<br>C14<br>NC<br>C15<br>IO42NPB1<br>C16<br>IO44PDB1<br>D1<br>IO114VDB3<br>D2<br>IO114UDB3<br>D3<br>GAC2/IO116UDB3<br>D4<br>NC<br>D5<br>GNDQ<br>D6<br>IO08RSB0<br>D7<br>IO14RSB0<br>D8<br>IO18RSB0<br>D9<br>IO23RSB0<br>D10<br>IO28RSB0<br>D11<br>IO32RSB0<br>D12<br>GNDQ<br>D13<br>NC<br>D14<br>GBB2/IO42PPB1<br>D15<br>NC<br>D16<br>IO44NDB1<br>E1<br>IO113PDB3<br>E2<br>NC<br>E3<br>IO116VDB3<br>E4<br>IO115UDB3<br>E5<br>VMV0<br>E6<br>VCCIB0<br>E7<br>VCCIB0<br>E8<br>IO19RSB0<br>**FG256**<br>**Pin Number**<br>**A3P250 Function**<br>E9<br>IO24RSB0<br>E10<br>VCCIB0<br>E11<br>VCCIB0<br>E12<br>VMV1<br>E13<br>GBC2/IO43PDB1<br>E14<br>IO46RSB1<br>E15<br>NC<br>E16<br>IO45PDB1<br>F1<br>IO113NDB3<br>F2<br>IO112PPB3<br>F3<br>NC<br>F4<br>IO115VDB3<br>F5<br>VCCIB3<br>F6<br>GND<br>F7<br>VCC<br>F8<br>VCC<br>F9<br>VCC<br>F10<br>VCC<br>F11<br>GND<br>F12<br>VCCIB1<br>F13<br>IO43NDB1<br>F14<br>NC<br>F15<br>IO47PPB1<br>F16<br>IO45NDB1<br>G1<br>IO111NDB3<br>G2<br>IO111PDB3<br>G3<br>IO112NPB3<br>G4<br>GFC1/IO110PPB3<br>G5<br>VCCIB3<br>G6<br>VCC<br>G7<br>GND<br>G8<br>GND<br>G9<br>GND<br>G10<br>GND<br>G11<br>VCC<br>G12<br>VCCIB1<br>**FG256**<br>**Pin Number**<br>**A3P250 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**Revision 18**
**4-53**
_Package Pin Assignments_
|G13<br>GCC1/IO48PPB1<br>G14<br>IO47NPB1<br>G15<br>IO54PDB1<br>G16<br>IO54NDB1<br>H1<br>GFB0/IO109NPB3<br>H2<br>GFA0/IO108NDB3<br>H3<br>GFB1/IO109PPB3<br>H4<br>VCOMPLF<br>H5<br>GFC0/IO110NPB3<br>H6<br>VCC<br>H7<br>GND<br>H8<br>GND<br>H9<br>GND<br>H10<br>GND<br>H11<br>VCC<br>H12<br>GCC0/IO48NPB1<br>H13<br>GCB1/IO49PPB1<br>H14<br>GCA0/IO50NPB1<br>H15<br>NC<br>H16<br>GCB0/IO49NPB1<br>J1<br>GFA2/IO107PPB3<br>J2<br>GFA1/IO108PDB3<br>J3<br>VCCPLF<br>J4<br>IO106NDB3<br>J5<br>GFB2/IO106PDB3<br>J6<br>VCC<br>J7<br>GND<br>J8<br>GND<br>J9<br>GND<br>J10<br>GND<br>J11<br>VCC<br>J12<br>GCB2/IO52PPB1<br>J13<br>GCA1/IO50PPB1<br>J14<br>GCC2/IO53PPB1<br>J15<br>NC<br>J16<br>GCA2/IO51PDB1<br>**FG256**<br>**Pin Number**<br>**A3P250 Function**<br>K1<br>GFC2/IO105PDB3<br>K2<br>IO107NPB3<br>K3<br>IO104PPB3<br>K4<br>NC<br>K5<br>VCCIB3<br>K6<br>VCC<br>K7<br>GND<br>K8<br>GND<br>K9<br>GND<br>K10<br>GND<br>K11<br>VCC<br>K12<br>VCCIB1<br>K13<br>IO52NPB1<br>K14<br>IO55RSB1<br>K15<br>IO53NPB1<br>K16<br>IO51NDB1<br>L1<br>IO105NDB3<br>L2<br>IO104NPB3<br>L3<br>NC<br>L4<br>IO102RSB3<br>L5<br>VCCIB3<br>L6<br>GND<br>L7<br>VCC<br>L8<br>VCC<br>L9<br>VCC<br>L10<br>VCC<br>L11<br>GND<br>L12<br>VCCIB1<br>L13<br>GDB0/IO59VPB1<br>L14<br>IO57VDB1<br>L15<br>IO57UDB1<br>L16<br>IO56PDB1<br>M1<br>IO103PDB3<br>M2<br>NC<br>M3<br>IO101NPB3<br>M4<br>GEC0/IO100NPB3<br>**FG256**<br>**Pin Number**<br>**A3P250 Function**<br>M5<br>VMV3<br>M6<br>VCCIB2<br>M7<br>VCCIB2<br>M8<br>NC<br>M9<br>IO74RSB2<br>M10<br>VCCIB2<br>M11<br>VCCIB2<br>M12<br>VMV2<br>M13<br>NC<br>M14<br>GDB1/IO59UPB1<br>M15<br>GDC1/IO58UDB1<br>M16<br>IO56NDB1<br>N1<br>IO103NDB3<br>N2<br>IO101PPB3<br>N3<br>GEC1/IO100PPB3<br>N4<br>NC<br>N5<br>GNDQ<br>N6<br>GEA2/IO97RSB2<br>N7<br>IO86RSB2<br>N8<br>IO82RSB2<br>N9<br>IO75RSB2<br>N10<br>IO69RSB2<br>N11<br>IO64RSB2<br>N12<br>GNDQ<br>N13<br>NC<br>N14<br>VJTAG<br>N15<br>GDC0/IO58VDB1<br>N16<br>GDA1/IO60UDB1<br>P1<br>GEB1/IO99PDB3<br>P2<br>GEB0/IO99NDB3<br>P3<br>NC<br>P4<br>NC<br>P5<br>IO92RSB2<br>P6<br>IO89RSB2<br>P7<br>IO85RSB2<br>P8<br>IO81RSB2<br>**FG256**<br>**Pin Number**<br>**A3P250 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**4-54**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|~~Pe~~|||||
|---|---|---|---|---|
|**FG256**<br>**Pin Number**<br>**A3P250 Function**<br>~~Pea~~||**Pin Number**|**FG256**<br>**A3P250 Function**||
|P9<br>IO76RSB2<br>~~a~~||T13||IO67RSB2|
|P10<br>IO71RSB2<br>~~a~~||T14||GDA2/IO61RSB2|
|P11<br>IO66RSB2<br>P12<br>NC<br>P13<br>TCK<br>P14<br>VPUMP<br>P15<br>TRST<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~||T15<br>T16||TMS<br>GND|
|P16<br>GDA0/IO60VDB1<br>~~a~~|||||
|R1<br>GEA1/IO98PDB3<br>R2<br>GEA0/IO98NDB3<br>R3<br>NC<br>R4<br>GEC2/IO95RSB2<br>R5<br>IO91RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|R6<br>IO88RSB2<br>~~a~~|||||
|R7<br>IO84RSB2<br>R8<br>IO80RSB2<br>R9<br>IO77RSB2<br>R10<br>IO72RSB2<br>R11<br>IO68RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|R12<br>IO65RSB2<br>~~a~~|||||
|R13<br>GDB2/IO62RSB2<br>R14<br>TDI<br>R15<br>NC<br>R16<br>TDO<br>T1<br>GND<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|T2<br>IO94RSB2<br>~~a~~|||||
|T3<br>GEB2/IO96RSB2<br>T4<br>IO93RSB2<br>T5<br>IO90RSB2<br>T6<br>IO87RSB2<br>T7<br>IO83RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|T8<br>IO79RSB2<br>~~a~~|||||
|T9<br>IO78RSB2<br>T10<br>IO73RSB2<br>T11<br>IO70RSB2<br>T12<br>GDC2/IO63RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~a~~<br>~~ee~~|||||
**Revision 18**
**4-55**
_Package Pin Assignments_
|**FG256**<br>**Pin Number**<br>**A3P400 Function**<br>A1<br>GND<br>A2<br>GAA0/IO00RSB0<br>A3<br>GAA1/IO01RSB0<br>A4<br>GAB0/IO02RSB0<br>A5<br>IO16RSB0<br>A6<br>IO17RSB0<br>A7<br>IO22RSB0<br>A8<br>IO28RSB0<br>A9<br>IO34RSB0<br>A10<br>IO37RSB0<br>A11<br>IO41RSB0<br>A12<br>IO43RSB0<br>A13<br>GBB1/IO57RSB0<br>A14<br>GBA0/IO58RSB0<br>A15<br>GBA1/IO59RSB0<br>A16<br>GND<br>B1<br>GAB2/IO154UDB3<br>B2<br>GAA2/IO155UDB3<br>B3<br>IO12RSB0<br>B4<br>GAB1/IO03RSB0<br>B5<br>IO13RSB0<br>B6<br>IO14RSB0<br>B7<br>IO21RSB0<br>B8<br>IO27RSB0<br>B9<br>IO32RSB0<br>B10<br>IO38RSB0<br>B11<br>IO42RSB0<br>B12<br>GBC1/IO55RSB0<br>B13<br>GBB0/IO56RSB0<br>B14<br>IO44RSB0<br>B15<br>GBA2/IO60PDB1<br>B16<br>IO60NDB1<br>C1<br>IO154VDB3<br>C2<br>IO155VDB3<br>C3<br>IO11RSB0<br>C4<br>IO07RSB0<br>C5<br>GAC0/IO04RSB0<br>C6<br>GAC1/IO05RSB0<br>C7<br>IO20RSB0<br>C8<br>IO24RSB0<br>C9<br>IO33RSB0<br>C10<br>IO39RSB0<br>C11<br>IO45RSB0<br>C12<br>GBC0/IO54RSB0<br>C13<br>IO48RSB0<br>C14<br>VMV0<br>C15<br>IO61NPB1<br>C16<br>IO63PDB1<br>D1<br>IO151VDB3<br>D2<br>IO151UDB3<br>D3<br>GAC2/IO153UDB3<br>D4<br>IO06RSB0<br>D5<br>GNDQ<br>D6<br>IO10RSB0<br>D7<br>IO19RSB0<br>D8<br>IO26RSB0<br>D9<br>IO30RSB0<br>D10<br>IO40RSB0<br>D11<br>IO46RSB0<br>D12<br>GNDQ<br>D13<br>IO47RSB0<br>D14<br>GBB2/IO61PPB1<br>D15<br>IO53RSB0<br>D16<br>IO63NDB1<br>E1<br>IO150PDB3<br>E2<br>IO08RSB0<br>E3<br>IO153VDB3<br>E4<br>IO152VDB3<br>E5<br>VMV0<br>E6<br>VCCIB0<br>E7<br>VCCIB0<br>E8<br>IO25RSB0<br>**FG256**<br>**Pin Number**<br>**A3P400 Function**<br>E9<br>IO31RSB0<br>E10<br>VCCIB0<br>E11<br>VCCIB0<br>E12<br>VMV1<br>E13<br>GBC2/IO62PDB1<br>E14<br>IO65RSB1<br>E15<br>IO52RSB0<br>E16<br>IO66PDB1<br>F1<br>IO150NDB3<br>F2<br>IO149NPB3<br>F3<br>IO09RSB0<br>F4<br>IO152UDB3<br>F5<br>VCCIB3<br>F6<br>GND<br>F7<br>VCC<br>F8<br>VCC<br>F9<br>VCC<br>F10<br>VCC<br>F11<br>GND<br>F12<br>VCCIB1<br>F13<br>IO62NDB1<br>F14<br>IO49RSB0<br>F15<br>IO64PPB1<br>F16<br>IO66NDB1<br>G1<br>IO148NDB3<br>G2<br>IO148PDB3<br>G3<br>IO149PPB3<br>G4<br>GFC1/IO147PPB3<br>G5<br>VCCIB3<br>G6<br>VCC<br>G7<br>GND<br>G8<br>GND<br>G9<br>GND<br>G10<br>GND<br>G11<br>VCC<br>G12<br>VCCIB1<br>**FG256**<br>**Pin Number**<br>**A3P400 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**4-56**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|G13<br>GCC1/IO67PPB1<br>G14<br>IO64NPB1<br>G15<br>IO73PDB1<br>G16<br>IO73NDB1<br>H1<br>GFB0/IO146NPB3<br>H2<br>GFA0/IO145NDB3<br>H3<br>GFB1/IO146PPB3<br>H4<br>VCOMPLF<br>H5<br>GFC0/IO147NPB3<br>H6<br>VCC<br>H7<br>GND<br>H8<br>GND<br>H9<br>GND<br>H10<br>GND<br>H11<br>VCC<br>H12<br>GCC0/IO67NPB1<br>H13<br>GCB1/IO68PPB1<br>H14<br>GCA0/IO69NPB1<br>H15<br>NC<br>H16<br>GCB0/IO68NPB1<br>J1<br>GFA2/IO144PPB3<br>J2<br>GFA1/IO145PDB3<br>J3<br>VCCPLF<br>J4<br>IO143NDB3<br>J5<br>GFB2/IO143PDB3<br>J6<br>VCC<br>J7<br>GND<br>J8<br>GND<br>J9<br>GND<br>J10<br>GND<br>J11<br>VCC<br>J12<br>GCB2/IO71PPB1<br>J13<br>GCA1/IO69PPB1<br>J14<br>GCC2/IO72PPB1<br>J15<br>NC<br>J16<br>GCA2/IO70PDB1<br>**FG256**<br>**Pin Number**<br>**A3P400 Function**<br>K1<br>GFC2/IO142PDB3<br>K2<br>IO144NPB3<br>K3<br>IO141PPB3<br>K4<br>IO120RSB2<br>K5<br>VCCIB3<br>K6<br>VCC<br>K7<br>GND<br>K8<br>GND<br>K9<br>GND<br>K10<br>GND<br>K11<br>VCC<br>K12<br>VCCIB1<br>K13<br>IO71NPB1<br>K14<br>IO74RSB1<br>K15<br>IO72NPB1<br>K16<br>IO70NDB1<br>L1<br>IO142NDB3<br>L2<br>IO141NPB3<br>L3<br>IO125RSB2<br>L4<br>IO139RSB3<br>L5<br>VCCIB3<br>L6<br>GND<br>L7<br>VCC<br>L8<br>VCC<br>L9<br>VCC<br>L10<br>VCC<br>L11<br>GND<br>L12<br>VCCIB1<br>L13<br>GDB0/IO78VPB1<br>L14<br>IO76VDB1<br>L15<br>IO76UDB1<br>L16<br>IO75PDB1<br>M1<br>IO140PDB3<br>M2<br>IO130RSB2<br>M3<br>IO138NPB3<br>M4<br>GEC0/IO137NPB3<br>**FG256**<br>**Pin Number**<br>**A3P400 Function**<br>M5<br>VMV3<br>M6<br>VCCIB2<br>M7<br>VCCIB2<br>M8<br>IO108RSB2<br>M9<br>IO101RSB2<br>M10<br>VCCIB2<br>M11<br>VCCIB2<br>M12<br>VMV2<br>M13<br>IO83RSB2<br>M14<br>GDB1/IO78UPB1<br>M15<br>GDC1/IO77UDB1<br>M16<br>IO75NDB1<br>N1<br>IO140NDB3<br>N2<br>IO138PPB3<br>N3<br>GEC1/IO137PPB3<br>N4<br>IO131RSB2<br>N5<br>GNDQ<br>N6<br>GEA2/IO134RSB2<br>N7<br>IO117RSB2<br>N8<br>IO111RSB2<br>N9<br>IO99RSB2<br>N10<br>IO94RSB2<br>N11<br>IO87RSB2<br>N12<br>GNDQ<br>N13<br>IO93RSB2<br>N14<br>VJTAG<br>N15<br>GDC0/IO77VDB1<br>N16<br>GDA1/IO79UDB1<br>P1<br>GEB1/IO136PDB3<br>P2<br>GEB0/IO136NDB3<br>P3<br>VMV2<br>P4<br>IO129RSB2<br>P5<br>IO128RSB2<br>P6<br>IO122RSB2<br>P7<br>IO115RSB2<br>P8<br>IO110RSB2<br>**FG256**<br>**Pin Number**<br>**A3P400 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**Revision 18**
**4-57**
_Package Pin Assignments_
|~~Pe~~|||||
|---|---|---|---|---|
|**FG256**<br>**Pin Number**<br>**A3P400 Function**<br>~~Pea~~||**Pin Number**|**FG256**<br>**A3P400 Function**||
|P9<br>IO98RSB2<br>~~a~~||T13||IO86RSB2|
|P10<br>IO95RSB2<br>~~a~~||T14||GDA2/IO80RSB2|
|P11<br>IO88RSB2<br>P12<br>IO84RSB2<br>P13<br>TCK<br>P14<br>VPUMP<br>P15<br>TRST<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~||T15<br>T16||TMS<br>GND|
|P16<br>GDA0/IO79VDB1<br>~~a~~|||||
|R1<br>GEA1/IO135PDB3<br>R2<br>GEA0/IO135NDB3<br>R3<br>IO127RSB2<br>R4<br>GEC2/IO132RSB2<br>R5<br>IO123RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|R6<br>IO118RSB2<br>~~a~~|||||
|R7<br>IO112RSB2<br>R8<br>IO106RSB2<br>R9<br>IO100RSB2<br>R10<br>IO96RSB2<br>R11<br>IO89RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|R12<br>IO85RSB2<br>~~a~~|||||
|R13<br>GDB2/IO81RSB2<br>R14<br>TDI<br>R15<br>NC<br>R16<br>TDO<br>T1<br>GND<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|T2<br>IO126RSB2<br>~~a~~|||||
|T3<br>GEB2/IO133RSB2<br>T4<br>IO124RSB2<br>T5<br>IO116RSB2<br>T6<br>IO113RSB2<br>T7<br>IO107RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|T8<br>IO105RSB2<br>~~a~~|||||
|T9<br>IO102RSB2<br>T10<br>IO97RSB2<br>T11<br>IO92RSB2<br>T12<br>GDC2/IO82RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~a~~<br>~~ee~~|||||
**4-58**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**==> picture [468 x 651] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||
|---|---|---|---|---|---|---|
|FG256|FG256|FG256|
|ee|ie|Os|
|Pin Number|A3P600 Function|Pin Number|A3P600 Function|Pin Number|A3P600 Function|
|a|ee|ie|ee|eoes|
|A1|GND|C5|GAC0/IO04RSB0|E9|IO31RSB0|
|ee|ee es es|
|A2|GAA0/IO00RSB0|C6|GAC1/IO05RSB0|E10|VCCIB0|
|ee|ee es|es|
|A3|GAA1/IO01RSB0|C7|IO20RSB0|E11|VCCIB0|
|i|ee es|es|
|A4|GAB0/IO02RSB0|C8|IO24RSB0|E12|VMV1|
|ee|es|ie|ees es (os|
|A5|IO11RSB0|C9|IO33RSB0|E13|GBC2/IO62PDB1|
|re|ee|ie|eres es|fo|
|A6|IO16RSB0|C10|IO39RSB0|E14|IO67PPB1|
|ee|ee es|es|
|A7|IO18RSB0|C11|IO44RSB0|E15|IO64PPB1|
|i|ee es|es|
|A8|IO28RSB0|C12|GBC0/IO54RSB0|E16|IO66PDB1|
|ee|eees|
|A9|IO34RSB0|C13|IO51RSB0|F1|IO166NDB3|
|i|ee es|es|
|A10|IO37RSB0|C14|VMV0|F2|IO168NPB3|
|ee|es|ie|ees es (os|
|A11|IO41RSB0|C15|IO61NPB1|F3|IO167PPB3|
|re|ee|ie|eres es|fo|
|A12|IO43RSB0|C16|IO63PDB1|F4|IO169PDB3|
|ee|ee es|es|
|A13|GBB1/IO57RSB0|D1|IO171NDB3|F5|VCCIB3|
|i|ee es|es|
|A14|GBA0/IO58RSB0|D2|IO171PDB3|F6|GND|
|ee|eees|
|A15|GBA1/IO59RSB0|D3|GAC2/IO172PDB3|F7|VCC|
|i|ee es|es|
|A16|GND|D4|IO06RSB0|F8|VCC|
|ee|es|ie|ees es (os|
|B1|GAB2/IO173PDB3|D5|GNDQ|F9|VCC|
|re|ee|ie|eres es|fo|
|B2|GAA2/IO174PDB3|D6|IO10RSB0|F10|VCC|
|ee|ee es|es|
|B3|GNDQ|D7|IO19RSB0|F11|GND|
|i|ee es|es|
|B4|GAB1/IO03RSB0|D8|IO26RSB0|F12|VCCIB1|
|ee|eees|
|B5|IO13RSB0|D9|IO30RSB0|F13|IO62NDB1|
|i|ee es|es|
|B6|IO14RSB0|D10|IO40RSB0|F14|IO64NPB1|
|ee|es|ie|ees es (os|
|B7|IO21RSB0|D11|IO45RSB0|F15|IO65PPB1|
|re|ee|ie|eres es|fo|
|B8|IO27RSB0|D12|GNDQ|F16|IO66NDB1|
|ee|ee es|es|
|B9|IO32RSB0|D13|IO50RSB0|G1|IO165NDB3|
|i|ee es|es|
|B10|IO38RSB0|D14|GBB2/IO61PPB1|G2|IO165PDB3|
|ee|eees|
|B11|IO42RSB0|D15|IO53RSB0|G3|IO168PPB3|
|i|ee es|es|
|B12|GBC1/IO55RSB0|D16|IO63NDB1|G4|GFC1/IO164PPB3|
|ee|es|ie|ees es (os|
|B13|GBB0/IO56RSB0|E1|IO166PDB3|G5|VCCIB3|
|re|ee|ie|eres es|fo|
|B14|IO52RSB0|E2|IO167NPB3|G6|VCC|
|ee|ee es|es|
|B15|GBA2/IO60PDB1|E3|IO172NDB3|G7|GND|
|i|ee es|es|
|B16|IO60NDB1|E4|IO169NDB3|G8|GND|
|ee|ee es es|
|C1|IO173NDB3|E5|VMV0|G9|GND|
|ee|eees|
|C2|IO174NDB3|E6|VCCIB0|G10|GND|
|ee|es|ie|ees es (os|
|C3|VMV3|E7|VCCIB0|G11|VCC|
|ee|ee|ie|eee|es|fo|es|
|C4|IO07RSB0|E8|IO25RSB0|G12|VCCIB1|
|i|ee|ie|ees es os|
**----- End of picture text -----**<br>
**Revision 18**
**4-59**
_Package Pin Assignments_
**==> picture [468 x 651] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||
|---|---|---|---|---|---|---|
|FG256|FG256|FG256|
|ee|ie|Os|
|Pin Number|A3P600 Function|Pin Number|A3P600 Function|Pin Number|A3P600 Function|
|a|ee|ie|ee|eoes|
|G13|GCC1/IO69PPB1|K1|GFC2/IO159PDB3|M5|VMV3|
|ee|ee es es|
|G14|IO65NPB1|K2|IO161NPB3|M6|VCCIB2|
|ee|ee es|es|
|G15|IO75PDB1|K3|IO156PPB3|M7|VCCIB2|
|i|ee es|es|
|G16|IO75NDB1|K4|IO129RSB2|M8|IO117RSB2|
|ee|es|ie|ees es (os|
|H1|GFB0/IO163NPB3|K5|VCCIB3|M9|IO110RSB2|
|re|ee|ie|eres es|fo|
|H2|GFA0/IO162NDB3|K6|VCC|M10|VCCIB2|
|ee|ee es|es|
|H3|GFB1/IO163PPB3|K7|GND|M11|VCCIB2|
|i|ee es|es|
|H4|VCOMPLF|K8|GND|M12|VMV2|
|ee|eees|
|H5|GFC0/IO164NPB3|K9|GND|M13|IO94RSB2|
|i|ee es|es|
|H6|VCC|K10|GND|M14|GDB1/IO87PPB1|
|ee|es|ie|ees es (os|
|H7|GND|K11|VCC|M15|GDC1/IO86PDB1|
|re|ee|ie|eres es|fo|
|H8|GND|K12|VCCIB1|M16|IO84NDB1|
|ee|ee es|es|
|H9|GND|K13|IO73NPB1|N1|IO150NDB3|
|i|ee es|es|
|H10|GND|K14|IO80NPB1|N2|IO147PPB3|
|ee|eees|
|H11|VCC|K15|IO74NPB1|N3|GEC1/IO146PPB3|
|i|ee es|es|
|H12|GCC0/IO69NPB1|K16|IO72NDB1|N4|IO140RSB2|
|ee|es|ie|ees es (os|
|H13|GCB1/IO70PPB1|L1|IO159NDB3|N5|GNDQ|
|re|ee|ie|eres es|fo|
|H14|GCA0/IO71NPB1|L2|IO156NPB3|N6|GEA2/IO143RSB2|
|ee|ee es|es|
|H15|IO67NPB1|L3|IO151PPB3|N7|IO126RSB2|
|i|ee es|es|
|H16|GCB0/IO70NPB1|L4|IO158PSB3|N8|IO120RSB2|
|ee|eees|
|J1|GFA2/IO161PPB3|L5|VCCIB3|N9|IO108RSB2|
|i|ee es|es|
|J2|GFA1/IO162PDB3|L6|GND|N10|IO103RSB2|
|ee|es|ie|ees es (os|
|J3|VCCPLF|L7|VCC|N11|IO99RSB2|
|re|ee|ie|eres es|fo|
|J4|IO160NDB3|L8|VCC|N12|GNDQ|
|ee|ee es|es|
|J5|GFB2/IO160PDB3|L9|VCC|N13|IO92RSB2|
|i|ee es|es|
|J6|VCC|L10|VCC|N14|VJTAG|
|ee|eees|
|J7|GND|L11|GND|N15|GDC0/IO86NDB1|
|i|ee es|es|
|J8|GND|L12|VCCIB1|N16|GDA1/IO88PDB1|
|ee|es|ie|ees es (os|
|J9|GND|L13|GDB0/IO87NPB1|P1|GEB1/IO145PDB3|
|re|ee|ie|eres es|fo|
|J10|GND|L14|IO85NDB1|P2|GEB0/IO145NDB3|
|ee|ee es|es|
|J11|VCC|L15|IO85PDB1|P3|VMV2|
|i|ee es|es|
|J12|GCB2/IO73PPB1|L16|IO84PDB1|P4|IO138RSB2|
|ee|ee es es|
|J13|GCA1/IO71PPB1|M1|IO150PDB3|P5|IO136RSB2|
|ee|eees|
|J14|GCC2/IO74PPB1|M2|IO151NPB3|P6|IO131RSB2|
|ee|es|ie|ees es (os|
|J15|IO80PPB1|M3|IO147NPB3|P7|IO124RSB2|
|ee|ee|ie|eee|es|fo|es|
|J16|GCA2/IO72PDB1|M4|GEC0/IO146NPB3|P8|IO119RSB2|
|i|ee|ie|ees es os|
**----- End of picture text -----**<br>
**4-60**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**FG256**|||**FG256**|
|---|---|---|---|
|P9<br>IO107RSB2<br>P10<br>IO104RSB2<br>P11<br>IO97RSB2<br>P12<br>VMV1<br>P13<br>TCK<br>P14<br>VPUMP<br>P15<br>TRST<br>P16<br>GDA0/IO88NDB1<br>R1<br>GEA1/IO144PDB3<br>R2<br>GEA0/IO144NDB3<br>R3<br>IO139RSB2<br>R4<br>GEC2/IO141RSB2<br>R5<br>IO132RSB2<br>R6<br>IO127RSB2<br>R7<br>IO121RSB2<br>R8<br>IO114RSB2<br>R9<br>IO109RSB2<br>R10<br>IO105RSB2<br>R11<br>IO98RSB2<br>R12<br>IO96RSB2<br>R13<br>GDB2/IO90RSB2<br>R14<br>TDI<br>R15<br>GNDQ<br>R16<br>TDO<br>T1<br>GND<br>T2<br>IO137RSB2<br>T3<br>GEB2/IO142RSB2<br>T4<br>IO134RSB2<br>T5<br>IO125RSB2<br>T6<br>IO123RSB2<br>T7<br>IO118RSB2<br>T8<br>IO115RSB2<br>T9<br>IO111RSB2<br>T10<br>IO106RSB2<br>T11<br>IO102RSB2<br>T12<br>GDC2/IO91RSB2<br>**Pin Number**<br>**A3P600 Function**<br>~~a~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~eeee~~||T13<br>T14<br>T15<br>T16<br>**Pin Number**|IO93RSB2<br>GDA2/IO89RSB2<br>TMS<br>GND<br>**A3P600 Function**|
**Revision 18**
**4-61**
_Package Pin Assignments_
||**FG256**|**FG256**|||**FG256**|
|---|---|---|---|---|---|
|**Pin Number**<br>A1<br>~~a~~|**A3P1000 Function**<br>GND<br>~~ee~~|C7<br>IO25RSB0<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee~~||E13<br>**Pin Number**<br>~~es~~|GBC2/IO80PDB1<br>**A3P1000 Function**<br>~~ee~~|
|A2<br>A3<br>A4<br>A5<br>~~a ~~<br>~~a~~<br>~~a ~~<br>~~ee~~|GAA0/IO00RSB0<br>GAA1/IO01RSB0<br>GAB0/IO02RSB0<br>IO16RSB0<br>C8<br>IO36RSB0<br>C9<br>IO42RSB0<br>C10<br>IO49RSB0<br>C11<br>IO56RSB0<br>E14<br>E15<br>E16<br>F1<br> ~~ee Os~~<br>~~ee ~~ie~~Os~~<br> ~~ee Os~~<br>~~eees~~<br>~~Os~~||||IO83PPB1<br>IO86PPB1<br>IO87PDB1<br>IO217NDB3|
|A6|IO22RSB0|C12<br>GBC0/IO72RSB0||F2|IO218NDB3|
|A7<br>A8<br>A9<br>~~ee~~<br>~~ee~~<br>~~a ~~|IO28RSB0<br>IO35RSB0<br>IO45RSB0<br>C13<br>IO62RSB0<br>C14<br>VMV0<br>C15<br>IO78NDB1<br>F3<br>F4<br>F5<br>~~ee~~<br>~~es~~<br>~~ee ee~~<br>~~**e**ees~~<br>~~Os~~<br> ~~e~~<br>~~nsOs~~||||IO216PDB3<br>IO216NDB3<br>VCCIB3<br>~~ee~~|
|A10|IO50RSB0|C16<br>IO81NDB1||F6|GND|
|A11<br>A12<br>~~ee~~|IO55RSB0<br>IO61RSB0<br>~~ee~~|D1<br>IO222NDB3<br>D2<br>IO222PDB3<br>~~ee~~||F7<br>F8<br>~~es~~|VCC<br>VCC<br>~~ee~~|
|A13<br>A14<br>~~ee~~|GBB1/IO75RSB0<br>GBA0/IO76RSB0<br>~~ee~~|D3<br>GAC2/IO223PDB3<br>D4<br>IO223NDB3<br>~~ee ee~~||F9<br>F10<br>~~ee~~|VCC<br>VCC<br>~~ee~~|
|A15<br>A16<br>~~ee~~|GBA1/IO77RSB0<br>GND<br>~~ee~~|D5<br>GNDQ<br>D6<br>IO23RSB0<br>~~ee~~<br>~~ee~~||F11<br>GND<br>F12<br>VCCIB1<br>~~a~~||
|B1<br>B2<br>~~ee~~|GAB2/IO224PDB3<br>GAA2/IO225PDB3<br>~~ee~~|D7<br>IO29RSB0<br>D8<br>IO33RSB0<br>~~ee~~||F13<br>F14<br>~~es~~|IO83NPB1<br>IO86NPB1<br>~~ee~~|
|B3<br>B4<br>B5<br>B6<br>~~a ~~<br>~~ee~~|GNDQ<br>GAB1/IO03RSB0<br>IO17RSB0<br>IO21RSB0<br> ~~ee ~~<br>~~ee~~|D9<br>IO46RSB0<br>D10<br>IO52RSB0<br>D11<br>IO60RSB0<br>D12<br>GNDQ<br>F15<br>IO90PPB1<br>F16<br>IO87NDB1<br>G1<br>IO210PSB3<br>G2<br>IO213NDB3<br> Oe~~Osa~~<br>~~ee~~<br>~~ee~~||||
|B7<br>B8<br>~~ee~~|IO27RSB0<br>IO34RSB0<br>~~ee~~|D13<br>IO80NDB1<br>D14<br>GBB2/IO79PDB1<br>~~es~~<br>~~ee~~||G3<br>G4|IO213PDB3<br>GFC1/IO209PPB3|
|B9<br>B10<br>B11<br>~~ee~~<br>~~a ~~<br>~~ee~~|IO44RSB0<br>IO51RSB0<br>IO57RSB0<br>D15<br>IO79NDB1<br>D16<br>IO82NSB1<br>E1<br>IO217PDB3<br>G5<br>G6<br>G7<br>~~eees~~<br>~~Os~~<br> ~~ee ~~Oe~~Os~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||||VCCIB3<br>VCC<br>GND|
|B12|GBC1/IO73RSB0|E2<br>IO218PDB3||G8|GND|
|B13<br>B14<br>~~ee~~<br>~~a ~~|GBB0/IO74RSB0<br>IO71RSB0<br>E3<br>IO221NDB3<br>E4<br>IO221PDB3<br>G9<br>G10<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~||||GND<br>GND|
|B15|GBA2/IO78PDB1|E5<br>VMV0||G11|VCC|
|B16<br>C1<br>~~ee~~|IO81PDB1<br>IO224NDB3<br>~~ee~~|E6<br>VCCIB0<br>E7<br>VCCIB0<br>~~ee~~||G12<br>G13<br>~~es~~|VCCIB1<br>GCC1/IO91PPB1<br>~~ee~~|
|C2<br>C3<br>~~ee~~|IO225NDB3<br>VMV3<br>~~ee~~|E8<br>IO38RSB0<br>E9<br>IO47RSB0<br>~~ee ee~~||G14<br>G15<br>~~ee~~|IO90NPB1<br>IO88PDB1<br>~~ee~~|
|C4<br>~~a~~|IO11RSB0|E10<br>VCCIB0<br>~~ee~~||G16<br>IO88NDB1<br>~~a~~||
|C5|GAC0/IO04RSB0|E11<br>VCCIB0||H1|GFB0/IO208NPB3|
|C6<br>~~es~~|GAC1/IO05RSB0<br>~~ee~~|E12<br>VMV1<br>~~eseee~~||H2<br>~~es~~|GFA0/IO207NDB3<br>~~ee~~|
**4-62**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
||**FG256**<br>**FG256**|**FG256**|
|---|---|---|
|H3<br>GFB1/IO208PPB3<br>**Pin Number**<br>**A3P1000 Function**<br>K9<br>GND<br>**Pin Number**<br>**A3P1000 Function**<br>M15<br>**Pin Number**<br>~~ee ~~ie<br>~~nsOs~~<br>~~a ee Os~~||GDC1/IO111PDB1<br>**A3P1000 Function**|
|H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>H12<br>H13<br>H14<br>H15<br>H16<br>J1<br>J2<br>J3<br>J4<br>J5<br>J6<br>J7<br>J8<br>J9<br>J10<br>J11<br>J12<br>J13<br>J14<br>J15<br>J16<br>K1<br>K2<br>K3<br>K4<br>K5<br>K6<br>K7<br>K8<br>~~a ~~<br>~~a~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~ee~~<br>~~a ~~<br>~~a ~~<br>~~a~~|VCOMPLF<br>GFC0/IO209NPB3<br>VCC<br>GND<br>GND<br>GND<br>GND<br>VCC<br>GCC0/IO91NPB1<br>GCB1/IO92PPB1<br>GCA0/IO93NPB1<br>IO96NPB1<br>GCB0/IO92NPB1<br>GFA2/IO206PSB3<br>GFA1/IO207PDB3<br>VCCPLF<br>IO205NDB3<br>GFB2/IO205PDB3<br>VCC<br>GND<br>GND<br>GND<br>GND<br>VCC<br>GCB2/IO95PPB1<br>GCA1/IO93PPB1<br>GCC2/IO96PPB1<br>IO100PPB1<br>GCA2/IO94PSB1<br>GFC2/IO204PDB3<br>IO204NDB3<br>IO203NDB3<br>IO203PDB3<br>VCCIB3<br>VCC<br>GND<br>GND<br>K10<br>GND<br>K11<br>VCC<br>K12<br>VCCIB1<br>K13<br>IO95NPB1<br>K14<br>IO100NPB1<br>K15<br>IO102NDB1<br>K16<br>IO102PDB1<br>L1<br>IO202NDB3<br>L2<br>IO202PDB3<br>L3<br>IO196PPB3<br>L4<br>IO193PPB3<br>L5<br>VCCIB3<br>L6<br>GND<br>L7<br>VCC<br>L8<br>VCC<br>L9<br>VCC<br>L10<br>VCC<br>L11<br>GND<br>L12<br>VCCIB1<br>L13<br>GDB0/IO112NPB1<br>L14<br>IO106NDB1<br>L15<br>IO106PDB1<br>L16<br>IO107PDB1<br>M1<br>IO197NSB3<br>M2<br>IO196NPB3<br>M3<br>IO193NPB3<br>M4<br>GEC0/IO190NPB3<br>M5<br>VMV3<br>M6<br>VCCIB2<br>M7<br>VCCIB2<br>M8<br>IO147RSB2<br>M9<br>IO136RSB2<br>M10<br>VCCIB2<br>M11<br>VCCIB2<br>M12<br>VMV2<br>M13<br>IO110NDB1<br>M14<br>GDB1/IO112PPB1<br>M16<br>N1<br>N2<br>N3<br>N4<br>N5<br>N6<br>N7<br>N8<br>N9<br>N10<br>N11<br>N12<br>N13<br>N14<br>N15<br>N16<br>P1<br>P2<br>P3<br>P4<br>P5<br>P6<br>P7<br>P8<br>P9<br>P10<br>P11<br>P12<br>P13<br>P14<br>P15<br>P16<br>R1<br>R2<br>R3<br>R4<br> ~~ee Os~~<br>~~ee ~~ie~~Os~~<br> ~~ee Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOs~~<br> ~~ee Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOs~~<br> ~~ee Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~ee~~<br>~~nsOo~~<br> ~~ee ~~Oe~~Os~~<br>~~eees~~<br>~~Os~~<br> ~~eees~~<br>~~Os~~<br> ~~ee Os OO~~<br>~~ee~~<br>~~nsOs~~|IO107NDB1<br>IO194PSB3<br>IO192PPB3<br>GEC1/IO190PPB3<br>IO192NPB3<br>GNDQ<br>GEA2/IO187RSB2<br>IO161RSB2<br>IO155RSB2<br>IO141RSB2<br>IO129RSB2<br>IO124RSB2<br>GNDQ<br>IO110PDB1<br>VJTAG<br>GDC0/IO111NDB1<br>GDA1/IO113PDB1<br>GEB1/IO189PDB3<br>GEB0/IO189NDB3<br>VMV2<br>IO179RSB2<br>IO171RSB2<br>IO165RSB2<br>IO159RSB2<br>IO151RSB2<br>IO137RSB2<br>IO134RSB2<br>IO128RSB2<br>VMV1<br>TCK<br>VPUMP<br>TRST<br>GDA0/IO113NDB1<br>GEA1/IO188PDB3<br>GEA0/IO188NDB3<br>IO184RSB2<br>GEC2/IO185RSB2|
**Revision 18**
**4-63**
_Package Pin Assignments_
**FG256 Pin Number A3P1000 Function** ~~a ee~~ R5 IO168RSB2 ~~ee ee~~ R6 IO163RSB2 ~~es ee a~~ R7 IO157RSB2 R8 IO149RSB2 ~~ee ee~~ R9 IO143RSB2 ~~ee ee es~~ R10 IO138RSB2 R11 IO131RSB2 ~~ee ee~~ R12 IO125RSB2 ~~ee ee es~~ R13 GDB2/IO115RSB2 R14 TDI ~~ee ee~~ R15 GNDQ ~~ee ee~~ R16 TDO ~~ee ee~~ T1 GND ~~ee ee~~ T2 IO183RSB2 ~~ee ee~~ T3 GEB2/IO186RSB2 ~~ee ee~~ T4 IO172RSB2 ~~ee ee~~ T5 IO170RSB2 ~~ee ee~~ T6 IO164RSB2 ~~ee ee~~ T7 IO158RSB2 ~~ee ee~~ T8 IO153RSB2 ~~ee ee~~ T9 IO142RSB2 ~~ee ee~~ T10 IO135RSB2 ~~ee ee~~ T11 IO130RSB2 ~~ee ee~~ T12 GDC2/IO116RSB2 ~~ee ee~~ T13 IO120RSB2 ~~ee ee~~ T14 GDA2/IO114RSB2 ~~ee ee~~ T15 TMS ~~ee ee~~ T16 GND ~~es ee~~
**4-64**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
## **FG484 – Bottom View**
|**A1 Ball Pad Corner**|**A1 Ball Pad Corner**|
|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14<br>15<br>16<br>17<br>18<br>19<br>20<br>21<br>22||
|(OXONOROROROROROROROROROROROROMOROROROLONONG)|A|
|(OROROROROROROROROROROROROROROMOROROOLONONG)|B|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|C|
|(ORORORONONORORORORORORORORORONOROROROIORONG)|D|
|OXONORORORORORONO OROROROROROMOROROROIONONG)|E|
|(ORO**RO**RORO**R**OR<br>O ON<br>OROROROROROMORO OOLONONG)|F|
|OROROROROROROROROROROROROROROMOROROROLONONG)|G|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|H|
|OXONOROROROROROROROROROROROROMOROROROIONONG)|J|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|K|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|L|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|M|
|OROROROROROROROROROROROROROROMOROROROLONONG)|N|
|(OXONORONO OROROROROROROROROROMOROROROIONONG)|P|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|R|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|T|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|U|
|(ORORORORONORORORORORORORORORONOROROROIONONG)|V|
|(OROROROROROROROROROROROROROROMOROROROIONONG)|W|
|OXONOROROROROROROROROROROROROMOROROROLONONG)|Y|
|(OROROROROROROROROROROROROROROMOROROROLONONG)|AA|
|OROROROROROROROROROROROROROROMOROROROLONONG)|AB|
## _**Note**_
For more information on package drawings, see _PD3068: Package Mechanical Drawings_ .
**Revision 18**
**4-65**
_Package Pin Assignments_
|**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>A1<br>GND<br>A2<br>GND<br>A3<br>VCCIB0<br>A4<br>NC<br>A5<br>NC<br>A6<br>IO15RSB0<br>A7<br>IO18RSB0<br>A8<br>NC<br>A9<br>NC<br>A10<br>IO23RSB0<br>A11<br>IO29RSB0<br>A12<br>IO35RSB0<br>A13<br>IO36RSB0<br>A14<br>NC<br>A15<br>NC<br>A16<br>IO50RSB0<br>A17<br>IO51RSB0<br>A18<br>NC<br>A19<br>NC<br>A20<br>VCCIB0<br>A21<br>GND<br>A22<br>GND<br>B1<br>GND<br>B2<br>VCCIB3<br>B3<br>NC<br>B4<br>NC<br>B5<br>NC<br>B6<br>NC<br>B7<br>NC<br>B8<br>NC<br>B9<br>NC<br>B10<br>NC<br>B11<br>NC<br>B12<br>NC<br>B13<br>NC<br>B14<br>NC<br>B15<br>NC<br>B16<br>NC<br>B17<br>NC<br>B18<br>NC<br>B19<br>NC<br>B20<br>NC<br>B21<br>VCCIB1<br>B22<br>GND<br>C1<br>VCCIB3<br>C2<br>NC<br>C3<br>NC<br>C4<br>NC<br>C5<br>GND<br>C6<br>NC<br>C7<br>NC<br>C8<br>VCC<br>C9<br>VCC<br>C10<br>NC<br>C11<br>NC<br>C12<br>NC<br>C13<br>NC<br>C14<br>VCC<br>C15<br>VCC<br>C16<br>NC<br>C17<br>NC<br>C18<br>GND<br>C19<br>NC<br>C20<br>NC<br>C21<br>NC<br>C22<br>VCCIB1<br>D1<br>NC<br>D2<br>NC<br>D3<br>NC<br>D4<br>GND<br>D5<br>GAA0/IO00RSB0<br>D6<br>GAA1/IO01RSB0<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>D7<br>GAB0/IO02RSB0<br>D8<br>IO16RSB0<br>D9<br>IO17RSB0<br>D10<br>IO22RSB0<br>D11<br>IO28RSB0<br>D12<br>IO34RSB0<br>D13<br>IO37RSB0<br>D14<br>IO41RSB0<br>D15<br>IO43RSB0<br>D16<br>GBB1/IO57RSB0<br>D17<br>GBA0/IO58RSB0<br>D18<br>GBA1/IO59RSB0<br>D19<br>GND<br>D20<br>NC<br>D21<br>NC<br>D22<br>NC<br>E1<br>NC<br>E2<br>NC<br>E3<br>GND<br>E4<br>GAB2/IO154UDB3<br>E5<br>GAA2/IO155UDB3<br>E6<br>IO12RSB0<br>E7<br>GAB1/IO03RSB0<br>E8<br>IO13RSB0<br>E9<br>IO14RSB0<br>E10<br>IO21RSB0<br>E11<br>IO27RSB0<br>E12<br>IO32RSB0<br>E13<br>IO38RSB0<br>E14<br>IO42RSB0<br>E15<br>GBC1/IO55RSB0<br>E16<br>GBB0/IO56RSB0<br>E17<br>IO44RSB0<br>E18<br>GBA2/IO60PDB1<br>E19<br>IO60NDB1<br>E20<br>GND<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**4-66**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|E21<br>NC<br>E22<br>NC<br>F1<br>NC<br>F2<br>NC<br>F3<br>NC<br>F4<br>IO154VDB3<br>F5<br>IO155VDB3<br>F6<br>IO11RSB0<br>F7<br>IO07RSB0<br>F8<br>GAC0/IO04RSB0<br>F9<br>GAC1/IO05RSB0<br>F10<br>IO20RSB0<br>F11<br>IO24RSB0<br>F12<br>IO33RSB0<br>F13<br>IO39RSB0<br>F14<br>IO45RSB0<br>F15<br>GBC0/IO54RSB0<br>F16<br>IO48RSB0<br>F17<br>VMV0<br>F18<br>IO61NPB1<br>F19<br>IO63PDB1<br>F20<br>NC<br>F21<br>NC<br>F22<br>NC<br>G1<br>NC<br>G2<br>NC<br>G3<br>NC<br>G4<br>IO151VDB3<br>G5<br>IO151UDB3<br>G6<br>GAC2/IO153UDB3<br>G7<br>IO06RSB0<br>G8<br>GNDQ<br>G9<br>IO10RSB0<br>G10<br>IO19RSB0<br>G11<br>IO26RSB0<br>G12<br>IO30RSB0<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>G13<br>IO40RSB0<br>G14<br>IO46RSB0<br>G15<br>GNDQ<br>G16<br>IO47RSB0<br>G17<br>GBB2/IO61PPB1<br>G18<br>IO53RSB0<br>G19<br>IO63NDB1<br>G20<br>NC<br>G21<br>NC<br>G22<br>NC<br>H1<br>NC<br>H2<br>NC<br>H3<br>VCC<br>H4<br>IO150PDB3<br>H5<br>IO08RSB0<br>H6<br>IO153VDB3<br>H7<br>IO152VDB3<br>H8<br>VMV0<br>H9<br>VCCIB0<br>H10<br>VCCIB0<br>H11<br>IO25RSB0<br>H12<br>IO31RSB0<br>H13<br>VCCIB0<br>H14<br>VCCIB0<br>H15<br>VMV1<br>H16<br>GBC2/IO62PDB1<br>H17<br>IO65RSB1<br>H18<br>IO52RSB0<br>H19<br>IO66PDB1<br>H20<br>VCC<br>H21<br>NC<br>H22<br>NC<br>J1<br>NC<br>J2<br>NC<br>J3<br>NC<br>J4<br>IO150NDB3<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>J5<br>IO149NPB3<br>J6<br>IO09RSB0<br>J7<br>IO152UDB3<br>J8<br>VCCIB3<br>J9<br>GND<br>J10<br>VCC<br>J11<br>VCC<br>J12<br>VCC<br>J13<br>VCC<br>J14<br>GND<br>J15<br>VCCIB1<br>J16<br>IO62NDB1<br>J17<br>IO49RSB0<br>J18<br>IO64PPB1<br>J19<br>IO66NDB1<br>J20<br>NC<br>J21<br>NC<br>J22<br>NC<br>K1<br>NC<br>K2<br>NC<br>K3<br>NC<br>K4<br>IO148NDB3<br>K5<br>IO148PDB3<br>K6<br>IO149PPB3<br>K7<br>GFC1/IO147PPB3<br>K8<br>VCCIB3<br>K9<br>VCC<br>K10<br>GND<br>K11<br>GND<br>K12<br>GND<br>K13<br>GND<br>K14<br>VCC<br>K15<br>VCCIB1<br>K16<br>GCC1/IO67PPB1<br>K17<br>IO64NPB1<br>K18<br>IO73PDB1<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**Revision 18**
**4-67**
_Package Pin Assignments_
|K19<br>IO73NDB1<br>K20<br>NC<br>K21<br>NC<br>K22<br>NC<br>L1<br>NC<br>L2<br>NC<br>L3<br>NC<br>L4<br>GFB0/IO146NPB3<br>L5<br>GFA0/IO145NDB3<br>L6<br>GFB1/IO146PPB3<br>L7<br>VCOMPLF<br>L8<br>GFC0/IO147NPB3<br>L9<br>VCC<br>L10<br>GND<br>L11<br>GND<br>L12<br>GND<br>L13<br>GND<br>L14<br>VCC<br>L15<br>GCC0/IO67NPB1<br>L16<br>GCB1/IO68PPB1<br>L17<br>GCA0/IO69NPB1<br>L18<br>NC<br>L19<br>GCB0/IO68NPB1<br>L20<br>NC<br>L21<br>NC<br>L22<br>NC<br>M1<br>NC<br>M2<br>NC<br>M3<br>NC<br>M4<br>GFA2/IO144PPB3<br>M5<br>GFA1/IO145PDB3<br>M6<br>VCCPLF<br>M7<br>IO143NDB3<br>M8<br>GFB2/IO143PDB3<br>M9<br>VCC<br>M10<br>GND<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>M11<br>GND<br>M12<br>GND<br>M13<br>GND<br>M14<br>VCC<br>M15<br>GCB2/IO71PPB1<br>M16<br>GCA1/IO69PPB1<br>M17<br>GCC2/IO72PPB1<br>M18<br>NC<br>M19<br>GCA2/IO70PDB1<br>M20<br>NC<br>M21<br>NC<br>M22<br>NC<br>N1<br>NC<br>N2<br>NC<br>N3<br>NC<br>N4<br>GFC2/IO142PDB3<br>N5<br>IO144NPB3<br>N6<br>IO141PPB3<br>N7<br>IO120RSB2<br>N8<br>VCCIB3<br>N9<br>VCC<br>N10<br>GND<br>N11<br>GND<br>N12<br>GND<br>N13<br>GND<br>N14<br>VCC<br>N15<br>VCCIB1<br>N16<br>IO71NPB1<br>N17<br>IO74RSB1<br>N18<br>IO72NPB1<br>N19<br>IO70NDB1<br>N20<br>NC<br>N21<br>NC<br>N22<br>NC<br>P1<br>NC<br>P2<br>NC<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>P3<br>NC<br>P4<br>IO142NDB3<br>P5<br>IO141NPB3<br>P6<br>IO125RSB2<br>P7<br>IO139RSB3<br>P8<br>VCCIB3<br>P9<br>GND<br>P10<br>VCC<br>P11<br>VCC<br>P12<br>VCC<br>P13<br>VCC<br>P14<br>GND<br>P15<br>VCCIB1<br>P16<br>GDB0/IO78VPB1<br>P17<br>IO76VDB1<br>P18<br>IO76UDB1<br>P19<br>IO75PDB1<br>P20<br>NC<br>P21<br>NC<br>P22<br>NC<br>R1<br>NC<br>R2<br>NC<br>R3<br>VCC<br>R4<br>IO140PDB3<br>R5<br>IO130RSB2<br>R6<br>IO138NPB3<br>R7<br>GEC0/IO137NPB3<br>R8<br>VMV3<br>R9<br>VCCIB2<br>R10<br>VCCIB2<br>R11<br>IO108RSB2<br>R12<br>IO101RSB2<br>R13<br>VCCIB2<br>R14<br>VCCIB2<br>R15<br>VMV2<br>R16<br>IO83RSB2<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**4-68**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|R17<br>GDB1/IO78UPB1<br>R18<br>GDC1/IO77UDB1<br>R19<br>IO75NDB1<br>R20<br>VCC<br>R21<br>NC<br>R22<br>NC<br>T1<br>NC<br>T2<br>NC<br>T3<br>NC<br>T4<br>IO140NDB3<br>T5<br>IO138PPB3<br>T6<br>GEC1/IO137PPB3<br>T7<br>IO131RSB2<br>T8<br>GNDQ<br>T9<br>GEA2/IO134RSB2<br>T10<br>IO117RSB2<br>T11<br>IO111RSB2<br>T12<br>IO99RSB2<br>T13<br>IO94RSB2<br>T14<br>IO87RSB2<br>T15<br>GNDQ<br>T16<br>IO93RSB2<br>T17<br>VJTAG<br>T18<br>GDC0/IO77VDB1<br>T19<br>GDA1/IO79UDB1<br>T20<br>NC<br>T21<br>NC<br>T22<br>NC<br>U1<br>NC<br>U2<br>NC<br>U3<br>NC<br>U4<br>GEB1/IO136PDB3<br>U5<br>GEB0/IO136NDB3<br>U6<br>VMV2<br>U7<br>IO129RSB2<br>U8<br>IO128RSB2<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>U9<br>IO122RSB2<br>U10<br>IO115RSB2<br>U11<br>IO110RSB2<br>U12<br>IO98RSB2<br>U13<br>IO95RSB2<br>U14<br>IO88RSB2<br>U15<br>IO84RSB2<br>U16<br>TCK<br>U17<br>VPUMP<br>U18<br>TRST<br>U19<br>GDA0/IO79VDB1<br>U20<br>NC<br>U21<br>NC<br>U22<br>NC<br>V1<br>NC<br>V2<br>NC<br>V3<br>GND<br>V4<br>GEA1/IO135PDB3<br>V5<br>GEA0/IO135NDB3<br>V6<br>IO127RSB2<br>V7<br>GEC2/IO132RSB2<br>V8<br>IO123RSB2<br>V9<br>IO118RSB2<br>V10<br>IO112RSB2<br>V11<br>IO106RSB2<br>V12<br>IO100RSB2<br>V13<br>IO96RSB2<br>V14<br>IO89RSB2<br>V15<br>IO85RSB2<br>V16<br>GDB2/IO81RSB2<br>V17<br>TDI<br>V18<br>NC<br>V19<br>TDO<br>V20<br>GND<br>V21<br>NC<br>V22<br>NC<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>W1<br>NC<br>W2<br>NC<br>W3<br>NC<br>W4<br>GND<br>W5<br>IO126RSB2<br>W6<br>GEB2/IO133RSB2<br>W7<br>IO124RSB2<br>W8<br>IO116RSB2<br>W9<br>IO113RSB2<br>W10<br>IO107RSB2<br>W11<br>IO105RSB2<br>W12<br>IO102RSB2<br>W13<br>IO97RSB2<br>W14<br>IO92RSB2<br>W15<br>GDC2/IO82RSB2<br>W16<br>IO86RSB2<br>W17<br>GDA2/IO80RSB2<br>W18<br>TMS<br>W19<br>GND<br>W20<br>NC<br>W21<br>NC<br>W22<br>NC<br>Y1<br>VCCIB3<br>Y2<br>NC<br>Y3<br>NC<br>Y4<br>NC<br>Y5<br>GND<br>Y6<br>NC<br>Y7<br>NC<br>Y8<br>VCC<br>Y9<br>VCC<br>Y10<br>NC<br>Y11<br>NC<br>Y12<br>NC<br>Y13<br>NC<br>Y14<br>VCC<br>**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>~~ee ~~ie~~Rs~~<br>~~a ee es~~<br>~~so~~<br>~~a ee es~~<br>~~sses~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie~~De so~~<br>~~a ee ~~ie~~es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~a ee ee so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~so~~<br>~~a ee ~~ie~~Ps~~<br>~~soes~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~es ee ~~ie~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee es~~<br>~~Oo~~<br>~~a~~<br>~~ee es~~<br>~~Oo~~<br>~~a ee es~~<br>~~sses~~<br>~~a ee es~~<br>~~so~~<br>~~ee~~<br>~~eeOs~~<br>~~I~~<br>~~ee~~<br>~~ee ns~~<br>~~Os~~<br>~~ee~~<br>~~eess~~|
|---|
**Revision 18**
**4-69**
_Package Pin Assignments_
|~~Pe~~||||
|---|---|---|---|
|**FG484**<br>**Pin Number**<br>**A3P400 Function**<br>~~Pea~~||**Pin Number**|**FG484**<br>**A3P400 Function**|
|Y15<br>VCC<br>~~a~~||AB7|IO119RSB2|
|Y16<br>NC<br>~~a~~||AB8|IO114RSB2|
|Y17<br>NC<br>Y18<br>GND<br>Y19<br>NC<br>Y20<br>NC<br>Y21<br>NC<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~||AB9<br>AB10<br>AB11<br>AB12<br>AB13|IO109RSB2<br>NC<br>NC<br>IO104RSB2<br>IO103RSB2|
|Y22<br>VCCIB1<br>~~a~~||AB14|NC|
|AA1<br>GND<br>AA2<br>VCCIB3<br>AA3<br>NC<br>AA4<br>NC<br>AA5<br>NC<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~||AB15<br>AB16<br>AB17<br>AB18<br>AB19|NC<br>IO91RSB2<br>IO90RSB2<br>NC<br>NC|
|AA6<br>NC<br>~~a~~||AB20|VCCIB2|
|AA7<br>NC<br>AA8<br>NC<br>AA9<br>NC<br>AA10<br>NC<br>AA11<br>NC<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~||AB21<br>AB22|GND<br>GND|
|AA12<br>NC<br>~~a~~||||
|AA13<br>NC<br>AA14<br>NC<br>AA15<br>NC<br>AA16<br>NC<br>AA17<br>NC<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~||||
|AA18<br>NC<br>~~a~~||||
|AA19<br>NC<br>AA20<br>NC<br>AA21<br>VCCIB1<br>AA22<br>GND<br>AB1<br>GND<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~a~~||||
|AB2<br>GND<br>~~a~~||||
|AB3<br>VCCIB2<br>AB4<br>NC<br>AB5<br>NC<br>AB6<br>IO121RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~a~~<br>~~ee~~||||
**4-70**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**==> picture [468 x 651] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|FG484|FG484|FG484|
|ee|ie|Os|
|Pin Number|A3P600 Function|Pin Number|A3P600 Function|Pin Number|A3P600 Function|
|a|ee|ie|ee|eo|es|
|A1|GND|B15|NC|D7|GAB0/IO02RSB0|
|ee|ee ees|es|
|A2|GND|B16|IO47RSB0|D8|IO11RSB0|
|ee|ee es eo|
|A3|VCCIB0|B17|IO49RSB0|D9|IO16RSB0|
|ee|ee es eo|
|A4|NC|B18|NC|D10|IO18RSB0|
|ee|ees es|fo|es|
|A5|NC|B19|NC|D11|IO28RSB0|
|es|ee|ie|ee|es|fo|
|A6|IO09RSB0|B20|NC|D12|IO34RSB0|
|ee|ee es|eesee|
|A7|IO15RSB0|B21|VCCIB1|D13|IO37RSB0|
|i|ee|es|es|
|A8|NC|B22|GND|D14|IO41RSB0|
|ee|ee es es|
|A9|NC|C1|VCCIB3|D15|IO43RSB0|
|ee|ee es eo|
|A10|IO22RSB0|C2|NC|D16|GBB1/IO57RSB0|
|ee|ees es|fo|es|
|A11|IO23RSB0|C3|NC|D17|GBA0/IO58RSB0|
|es|ee|ie|ee|es|fo|
|A12|IO29RSB0|C4|NC|D18|GBA1/IO59RSB0|
|ee|ee es|eesee|
|A13|IO35RSB0|C5|GND|D19|GND|
|i|ee|es|es|
|A14|NC|C6|NC|D20|NC|
|ee|ee es es|
|A15|NC|C7|NC|D21|NC|
|ee|ee es eo|
|A16|IO46RSB0|C8|VCC|D22|NC|
|ee|ees es|fo|es|
|A17|IO48RSB0|C9|VCC|E1|NC|
|es|ee|ie|ee|es|fo|
|A18|NC|C10|NC|E2|NC|
|ee|ee es|eesee|
|A19|NC|C11|NC|E3|GND|
|i|ee|es|es|
|A20|VCCIB0|C12|NC|E4|GAB2/IO173PDB3|
|ee|ee es es|
|A21|GND|C13|NC|E5|GAA2/IO174PDB3|
|ee|ee es eo|
|A22|GND|C14|VCC|E6|GNDQ|
|ee|ees es|fo|es|
|B1|GND|C15|VCC|E7|GAB1/IO03RSB0|
|es|ee|ie|ee|es|fo|
|B2|VCCIB3|C16|NC|E8|IO13RSB0|
|ee|ee es|eesee|
|B3|NC|C17|NC|E9|IO14RSB0|
|i|ee|es|es|
|B4|NC|C18|GND|E10|IO21RSB0|
|ee|ee es es|
|B5|NC|C19|NC|E11|IO27RSB0|
|ee|ee es eo|
|B6|IO08RSB0|C20|NC|E12|IO32RSB0|
|ee|ees es|fo|es|
|B7|IO12RSB0|C21|NC|E13|IO38RSB0|
|es|ee|ie|ee|es|fo|
|B8|NC|C22|VCCIB1|E14|IO42RSB0|
|ee|ee es|eesee|
|B9|NC|D1|NC|E15|GBC1/IO55RSB0|
|i|ee|es|es|
|B10|IO17RSB0|D2|NC|E16|GBB0/IO56RSB0|
|ee ee es eo|
|B11|NC|D3|NC|E17|IO52RSB0|
|ee|ee es es|
|B12|NC|D4|GND|E18|GBA2/IO60PDB1|
|ee|ees es|fo|es|
|B13|IO36RSB0|D5|GAA0/IO00RSB0|E19|IO60NDB1|
|i|ee|ie|ees es|fo|es|
|B14|NC|D6|GAA1/IO01RSB0|E20|GND|
|es|ee|ie|eee|es oe|
**----- End of picture text -----**<br>
**Revision 18**
**4-71**
_Package Pin Assignments_
**==> picture [468 x 651] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|FG484|FG484|FG484|
|ee|ie|Os|
|Pin Number|A3P600 Function|Pin Number|A3P600 Function|Pin Number|A3P600 Function|
|a|ee|ie|ee|eo|es|
|E21|NC|G13|IO40RSB0|J5|IO168NPB3|
|ee|ee ees|es|
|E22|NC|G14|IO45RSB0|J6|IO167PPB3|
|ee|ee es eo|
|F1|NC|G15|GNDQ|J7|IO169PDB3|
|ee|ee es eo|
|F2|NC|G16|IO50RSB0|J8|VCCIB3|
|ee|ees es|fo|es|
|F3|NC|G17|GBB2/IO61PPB1|J9|GND|
|es|ee|ie|ee|es|fo|
|F4|IO173NDB3|G18|IO53RSB0|J10|VCC|
|ee|ee es|eesee|
|F5|IO174NDB3|G19|IO63NDB1|J11|VCC|
|i|ee|es|es|
|F6|VMV3|G20|NC|J12|VCC|
|ee|ee es es|
|F7|IO07RSB0|G21|NC|J13|VCC|
|ee|ee es eo|
|F8|GAC0/IO04RSB0|G22|NC|J14|GND|
|ee|ees es|fo|es|
|F9|GAC1/IO05RSB0|H1|NC|J15|VCCIB1|
|es|ee|ie|ee|es|fo|
|F10|IO20RSB0|H2|NC|J16|IO62NDB1|
|ee|ee es|eesee|
|F11|IO24RSB0|H3|VCC|J17|IO64NPB1|
|i|ee|es|es|
|F12|IO33RSB0|H4|IO166PDB3|J18|IO65PPB1|
|ee|ee es es|
|F13|IO39RSB0|H5|IO167NPB3|J19|IO66NDB1|
|ee|ee es eo|
|F14|IO44RSB0|H6|IO172NDB3|J20|NC|
|ee|ees es|fo|es|
|F15|GBC0/IO54RSB0|H7|IO169NDB3|J21|IO68PDB1|
|es|ee|ie|ee|es|fo|
|F16|IO51RSB0|H8|VMV0|J22|IO68NDB1|
|ee|ee es|eesee|
|F17|VMV0|H9|VCCIB0|K1|IO157PDB3|
|i|ee|es|es|
|F18|IO61NPB1|H10|VCCIB0|K2|IO157NDB3|
|ee|ee es es|
|F19|IO63PDB1|H11|IO25RSB0|K3|NC|
|ee|ee es eo|
|F20|NC|H12|IO31RSB0|K4|IO165NDB3|
|ee|ees es|fo|es|
|F21|NC|H13|VCCIB0|K5|IO165PDB3|
|es|ee|ie|ee|es|fo|
|F22|NC|H14|VCCIB0|K6|IO168PPB3|
|ee|ee es|eesee|
|G1|IO170NDB3|H15|VMV1|K7|GFC1/IO164PPB3|
|i|ee|es|es|
|G2|IO170PDB3|H16|GBC2/IO62PDB1|K8|VCCIB3|
|ee|ee es es|
|G3|NC|H17|IO67PPB1|K9|VCC|
|ee|ee es eo|
|G4|IO171NDB3|H18|IO64PPB1|K10|GND|
|ee|ees es|fo|es|
|G5|IO171PDB3|H19|IO66PDB1|K11|GND|
|es|ee|ie|ee|es|fo|
|G6|GAC2/IO172PDB3|H20|VCC|K12|GND|
|ee|ee es|eesee|
|G7|IO06RSB0|H21|NC|K13|GND|
|i|ee|es|es|
|G8|GNDQ|H22|NC|K14|VCC|
|ee ee es eo|
|G9|IO10RSB0|J1|NC|K15|VCCIB1|
|ee|ee es es|
|G10|IO19RSB0|J2|NC|K16|GCC1/IO69PPB1|
|ee|ees es|fo|es|
|G11|IO26RSB0|J3|NC|K17|IO65NPB1|
|i|ee|ie|ees es|fo|es|
|G12|IO30RSB0|J4|IO166NDB3|K18|IO75PDB1|
|es|ee|ie|eee|es oe|
**----- End of picture text -----**<br>
**4-72**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
**==> picture [468 x 651] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|FG484|FG484|FG484|
|ee|ie|Os|
|Pin Number|A3P600 Function|Pin Number|A3P600 Function|Pin Number|A3P600 Function|
|a|ee|ie|ee|eo|es|
|K19|IO75NDB1|M11|GND|P3|IO153NDB3|
|ee|ee ees|es|
|K20|NC|M12|GND|P4|IO159NDB3|
|ee|ee es eo|
|K21|IO76NDB1|M13|GND|P5|IO156NPB3|
|ee|ee es eo|
|K22|IO76PDB1|M14|VCC|P6|IO151PPB3|
|ee|ees es|fo|es|
|L1|NC|M15|GCB2/IO73PPB1|P7|IO158PPB3|
|es|ee|ie|ee|es|fo|
|L2|IO155PDB3|M16|GCA1/IO71PPB1|P8|VCCIB3|
|ee|ee es|eesee|
|L3|NC|M17|GCC2/IO74PPB1|P9|GND|
|i|ee|es|es|
|L4|GFB0/IO163NPB3|M18|IO80PPB1|P10|VCC|
|ee|ee es es|
|L5|GFA0/IO162NDB3|M19|GCA2/IO72PDB1|P11|VCC|
|ee|ee es eo|
|L6|GFB1/IO163PPB3|M20|IO79PPB1|P12|VCC|
|ee|ees es|fo|es|
|L7|VCOMPLF|M21|IO78PPB1|P13|VCC|
|es|ee|ie|ee|es|fo|
|L8|GFC0/IO164NPB3|M22|NC|P14|GND|
|ee|ee es|eesee|
|L9|VCC|N1|IO154NDB3|P15|VCCIB1|
|i|ee|es|es|
|L10|GND|N2|IO154PDB3|P16|GDB0/IO87NPB1|
|ee|ee es es|
|L11|GND|N3|NC|P17|IO85NDB1|
|ee|ee es eo|
|L12|GND|N4|GFC2/IO159PDB3|P18|IO85PDB1|
|ee|ees es|fo|es|
|L13|GND|N5|IO161NPB3|P19|IO84PDB1|
|es|ee|ie|ee|es|fo|
|L14|VCC|N6|IO156PPB3|P20|NC|
|ee|ee es|eesee|
|L15|GCC0/IO69NPB1|N7|IO129RSB2|P21|IO81PDB1|
|i|ee|es|es|
|L16|GCB1/IO70PPB1|N8|VCCIB3|P22|NC|
|ee|ee es es|
|L17|GCA0/IO71NPB1|N9|VCC|R1|NC|
|ee|ee es eo|
|L18|IO67NPB1|N10|GND|R2|NC|
|ee|ees es|fo|es|
|L19|GCB0/IO70NPB1|N11|GND|R3|VCC|
|es|ee|ie|ee|es|fo|
|L20|IO77PDB1|N12|GND|R4|IO150PDB3|
|ee|ee es|eesee|
|L21|IO77NDB1|N13|GND|R5|IO151NPB3|
|i|ee|es|es|
|L22|IO78NPB1|N14|VCC|R6|IO147NPB3|
|ee|ee es es|
|M1|NC|N15|VCCIB1|R7|GEC0/IO146NPB3|
|ee|ee es eo|
|M2|IO155NDB3|N16|IO73NPB1|R8|VMV3|
|ee|ees es|fo|es|
|M3|IO158NPB3|N17|IO80NPB1|R9|VCCIB2|
|es|ee|ie|ee|es|fo|
|M4|GFA2/IO161PPB3|N18|IO74NPB1|R10|VCCIB2|
|ee|ee es|eesee|
|M5|GFA1/IO162PDB3|N19|IO72NDB1|R11|IO117RSB2|
|i|ee|es|es|
|M6|VCCPLF|N20|NC|R12|IO110RSB2|
|ee ee es eo|
|M7|IO160NDB3|N21|IO79NPB1|R13|VCCIB2|
|ee|ee es es|
|M8|GFB2/IO160PDB3|N22|NC|R14|VCCIB2|
|ee|ees es|fo|es|
|M9|VCC|P1|NC|R15|VMV2|
|i|ee|ie|ees es|fo|es|
|M10|GND|P2|IO153PDB3|R16|IO94RSB2|
|es|ee|ie|eee|es oe|
**----- End of picture text -----**<br>
**Revision 18**
**4-73**
_Package Pin Assignments_
**==> picture [468 x 651] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|FG484|FG484|FG484|
|ee|ie|Os|
|Pin Number|A3P600 Function|Pin Number|A3P600 Function|Pin Number|A3P600 Function|
|a|ee|ie|ee|eo|es|
|R17|GDB1/IO87PPB1|U9|IO131RSB2|W1|NC|
|ee|ee ees|es|
|R18|GDC1/IO86PDB1|U10|IO124RSB2|W2|IO148PDB3|
|ee|ee es eo|
|R19|IO84NDB1|U11|IO119RSB2|W3|NC|
|ee|ee es eo|
|R20|VCC|U12|IO107RSB2|W4|GND|
|ee|ees es|fo|es|
|R21|IO81NDB1|U13|IO104RSB2|W5|IO137RSB2|
|es|ee|ie|ee|es|fo|
|R22|IO82PDB1|U14|IO97RSB2|W6|GEB2/IO142RSB2|
|ee|ee es|eesee|
|T1|IO152PDB3|U15|VMV1|W7|IO134RSB2|
|i|ee|es|es|
|T2|IO152NDB3|U16|TCK|W8|IO125RSB2|
|ee|ee es es|
|T3|NC|U17|VPUMP|W9|IO123RSB2|
|ee|ee es eo|
|T4|IO150NDB3|U18|TRST|W10|IO118RSB2|
|ee|ees es|fo|es|
|T5|IO147PPB3|U19|GDA0/IO88NDB1|W11|IO115RSB2|
|es|ee|ie|ee|es|fo|
|T6|GEC1/IO146PPB3|U20|NC|W12|IO111RSB2|
|ee|ee es|eesee|
|T7|IO140RSB2|U21|IO83NDB1|W13|IO106RSB2|
|i|ee|es|es|
|T8|GNDQ|U22|NC|W14|IO102RSB2|
|ee|ee es es|
|T9|GEA2/IO143RSB2|V1|NC|W15|GDC2/IO91RSB2|
|ee|ee es eo|
|T10|IO126RSB2|V2|NC|W16|IO93RSB2|
|ee|ees es|fo|es|
|T11|IO120RSB2|V3|GND|W17|GDA2/IO89RSB2|
|es|ee|ie|ee|es|fo|
|T12|IO108RSB2|V4|GEA1/IO144PDB3|W18|TMS|
|ee|ee es|eesee|
|T13|IO103RSB2|V5|GEA0/IO144NDB3|W19|GND|
|i|ee|es|es|
|T14|IO99RSB2|V6|IO139RSB2|W20|NC|
|ee|ee es es|
|T15|GNDQ|V7|GEC2/IO141RSB2|W21|NC|
|ee|ee es eo|
|T16|IO92RSB2|V8|IO132RSB2|W22|NC|
|ee|ees es|fo|es|
|T17|VJTAG|V9|IO127RSB2|Y1|VCCIB3|
|es|ee|ie|ee|es|fo|
|T18|GDC0/IO86NDB1|V10|IO121RSB2|Y2|IO148NDB3|
|ee|ee es|eesee|
|T19|GDA1/IO88PDB1|V11|IO114RSB2|Y3|NC|
|i|ee|es|es|
|T20|NC|V12|IO109RSB2|Y4|NC|
|ee|ee es es|
|T21|IO83PDB1|V13|IO105RSB2|Y5|GND|
|ee|ee es eo|
|T22|IO82NDB1|V14|IO98RSB2|Y6|NC|
|ee|ees es|fo|es|
|U1|IO149PDB3|V15|IO96RSB2|Y7|NC|
|es|ee|ie|ee|es|fo|
|U2|IO149NDB3|V16|GDB2/IO90RSB2|Y8|VCC|
|ee|ee es|eesee|
|U3|NC|V17|TDI|Y9|VCC|
|i|ee|es|es|
|U4|GEB1/IO145PDB3|V18|GNDQ|Y10|NC|
|ee ee es eo|
|U5|GEB0/IO145NDB3|V19|TDO|Y11|NC|
|ee|ee es es|
|U6|VMV2|V20|GND|Y12|NC|
|ee|ees es|fo|es|
|U7|IO138RSB2|V21|NC|Y13|NC|
|i|ee|ie|ees es|fo|es|
|U8|IO136RSB2|V22|NC|Y14|VCC|
|es|ee|ie|eee|es oe|
**----- End of picture text -----**<br>
**4-74**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**FG484**|||**FG484**|
|---|---|---|---|
|Y15<br>VCC<br>Y16<br>NC<br>Y17<br>NC<br>Y18<br>GND<br>Y19<br>NC<br>Y20<br>NC<br>Y21<br>NC<br>Y22<br>VCCIB1<br>AA1<br>GND<br>AA2<br>VCCIB3<br>AA3<br>NC<br>AA4<br>NC<br>AA5<br>NC<br>AA6<br>IO135RSB2<br>AA7<br>IO133RSB2<br>AA8<br>NC<br>AA9<br>NC<br>AA10<br>NC<br>AA11<br>NC<br>AA12<br>NC<br>AA13<br>NC<br>AA14<br>NC<br>AA15<br>NC<br>AA16<br>IO101RSB2<br>AA17<br>NC<br>AA18<br>NC<br>AA19<br>NC<br>AA20<br>NC<br>AA21<br>VCCIB1<br>AA22<br>GND<br>AB1<br>GND<br>AB2<br>GND<br>AB3<br>VCCIB2<br>AB4<br>NC<br>AB5<br>NC<br>AB6<br>IO130RSB2<br>**Pin Number**<br>**A3P600 Function**<br>~~a~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee eee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~eeee~~||AB7<br>AB8<br>AB9<br>AB10<br>AB11<br>AB12<br>AB13<br>AB14<br>AB15<br>AB16<br>AB17<br>AB18<br>AB19<br>AB20<br>AB21<br>AB22<br>**Pin Number**|IO128RSB2<br>IO122RSB2<br>IO116RSB2<br>NC<br>NC<br>IO113RSB2<br>IO112RSB2<br>NC<br>NC<br>IO100RSB2<br>IO95RSB2<br>NC<br>NC<br>VCCIB2<br>GND<br>GND<br>**A3P600 Function**|
**Revision 18**
**4-75**
_Package Pin Assignments_
|**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>A1<br>GND<br>A2<br>GND<br>A3<br>VCCIB0<br>A4<br>IO07RSB0<br>A5<br>IO09RSB0<br>A6<br>IO13RSB0<br>A7<br>IO18RSB0<br>A8<br>IO20RSB0<br>A9<br>IO26RSB0<br>A10<br>IO32RSB0<br>A11<br>IO40RSB0<br>A12<br>IO41RSB0<br>A13<br>IO53RSB0<br>A14<br>IO59RSB0<br>A15<br>IO64RSB0<br>A16<br>IO65RSB0<br>A17<br>IO67RSB0<br>A18<br>IO69RSB0<br>A19<br>NC<br>A20<br>VCCIB0<br>A21<br>GND<br>A22<br>GND<br>B1<br>GND<br>B2<br>VCCIB3<br>B3<br>NC<br>B4<br>IO06RSB0<br>B5<br>IO08RSB0<br>B6<br>IO12RSB0<br>B7<br>IO15RSB0<br>B8<br>IO19RSB0<br>B9<br>IO24RSB0<br>B10<br>IO31RSB0<br>B11<br>IO39RSB0<br>B12<br>IO48RSB0<br>B13<br>IO54RSB0<br>B14<br>IO58RSB0<br>B15<br>IO63RSB0<br>B16<br>IO66RSB0<br>B17<br>IO68RSB0<br>B18<br>IO70RSB0<br>B19<br>NC<br>B20<br>NC<br>B21<br>VCCIB1<br>B22<br>GND<br>C1<br>VCCIB3<br>C2<br>IO220PDB3<br>C3<br>NC<br>C4<br>NC<br>C5<br>GND<br>C6<br>IO10RSB0<br>C7<br>IO14RSB0<br>C8<br>VCC<br>C9<br>VCC<br>C10<br>IO30RSB0<br>C11<br>IO37RSB0<br>C12<br>IO43RSB0<br>C13<br>NC<br>C14<br>VCC<br>C15<br>VCC<br>C16<br>NC<br>C17<br>NC<br>C18<br>GND<br>C19<br>NC<br>C20<br>NC<br>C21<br>NC<br>C22<br>VCCIB1<br>D1<br>IO219PDB3<br>D2<br>IO220NDB3<br>D3<br>NC<br>D4<br>GND<br>D5<br>GAA0/IO00RSB0<br>D6<br>GAA1/IO01RSB0<br>**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee Os~~<br>~~a ee es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~a ee es es ~~Oo<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee es es~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esfo~~|D7<br>D8<br>D9<br>D10<br>D11<br>D12<br>D13<br>D14<br>D15<br>D16<br>D17<br>D18<br>D19<br>D20<br>D21<br>D22<br>E1<br>E2<br>E3<br>E4<br>E5<br>E6<br>E7<br>E8<br>E9<br>E10<br>E11<br>E12<br>E13<br>E14<br>E15<br>E16<br>E17<br>E18<br>E19<br>E20<br>**Pin Number**|GAB0/IO02RSB0<br>IO16RSB0<br>IO22RSB0<br>IO28RSB0<br>IO35RSB0<br>IO45RSB0<br>IO50RSB0<br>IO55RSB0<br>IO61RSB0<br>GBB1/IO75RSB0<br>GBA0/IO76RSB0<br>GBA1/IO77RSB0<br>GND<br>NC<br>NC<br>NC<br>IO219NDB3<br>NC<br>GND<br>GAB2/IO224PDB3<br>GAA2/IO225PDB3<br>GNDQ<br>GAB1/IO03RSB0<br>IO17RSB0<br>IO21RSB0<br>IO27RSB0<br>IO34RSB0<br>IO44RSB0<br>IO51RSB0<br>IO57RSB0<br>GBC1/IO73RSB0<br>GBB0/IO74RSB0<br>IO71RSB0<br>GBA2/IO78PDB1<br>IO81PDB1<br>GND<br>**FG484**<br>**A3P1000 Function**|
|---|---|---|
**4-76**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|E21<br>NC<br>E22<br>IO84PDB1<br>F1<br>NC<br>F2<br>IO215PDB3<br>F3<br>IO215NDB3<br>F4<br>IO224NDB3<br>F5<br>IO225NDB3<br>F6<br>VMV3<br>F7<br>IO11RSB0<br>F8<br>GAC0/IO04RSB0<br>F9<br>GAC1/IO05RSB0<br>F10<br>IO25RSB0<br>F11<br>IO36RSB0<br>F12<br>IO42RSB0<br>F13<br>IO49RSB0<br>F14<br>IO56RSB0<br>F15<br>GBC0/IO72RSB0<br>F16<br>IO62RSB0<br>F17<br>VMV0<br>F18<br>IO78NDB1<br>F19<br>IO81NDB1<br>F20<br>IO82PPB1<br>F21<br>NC<br>F22<br>IO84NDB1<br>G1<br>IO214NDB3<br>G2<br>IO214PDB3<br>G3<br>NC<br>G4<br>IO222NDB3<br>G5<br>IO222PDB3<br>G6<br>GAC2/IO223PDB3<br>G7<br>IO223NDB3<br>G8<br>GNDQ<br>G9<br>IO23RSB0<br>G10<br>IO29RSB0<br>G11<br>IO33RSB0<br>G12<br>IO46RSB0<br>**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>G13<br>IO52RSB0<br>G14<br>IO60RSB0<br>G15<br>GNDQ<br>G16<br>IO80NDB1<br>G17<br>GBB2/IO79PDB1<br>G18<br>IO79NDB1<br>G19<br>IO82NPB1<br>G20<br>IO85PDB1<br>G21<br>IO85NDB1<br>G22<br>NC<br>H1<br>NC<br>H2<br>NC<br>H3<br>VCC<br>H4<br>IO217PDB3<br>H5<br>IO218PDB3<br>H6<br>IO221NDB3<br>H7<br>IO221PDB3<br>H8<br>VMV0<br>H9<br>VCCIB0<br>H10<br>VCCIB0<br>H11<br>IO38RSB0<br>H12<br>IO47RSB0<br>H13<br>VCCIB0<br>H14<br>VCCIB0<br>H15<br>VMV1<br>H16<br>GBC2/IO80PDB1<br>H17<br>IO83PPB1<br>H18<br>IO86PPB1<br>H19<br>IO87PDB1<br>H20<br>VCC<br>H21<br>NC<br>H22<br>NC<br>J1<br>IO212NDB3<br>J2<br>IO212PDB3<br>J3<br>NC<br>J4<br>IO217NDB3<br>**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee Os~~<br>~~a ee es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~a ee es es ~~Oo<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee es es~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esfo~~|J5<br>J6<br>J7<br>J8<br>J9<br>J10<br>J11<br>J12<br>J13<br>J14<br>J15<br>J16<br>J17<br>J18<br>J19<br>J20<br>J21<br>J22<br>K1<br>K2<br>K3<br>K4<br>K5<br>K6<br>K7<br>K8<br>K9<br>K10<br>K11<br>K12<br>K13<br>K14<br>K15<br>K16<br>K17<br>K18<br>**Pin Number**|IO218NDB3<br>IO216PDB3<br>IO216NDB3<br>VCCIB3<br>GND<br>VCC<br>VCC<br>VCC<br>VCC<br>GND<br>VCCIB1<br>IO83NPB1<br>IO86NPB1<br>IO90PPB1<br>IO87NDB1<br>NC<br>IO89PDB1<br>IO89NDB1<br>IO211PDB3<br>IO211NDB3<br>NC<br>IO210PPB3<br>IO213NDB3<br>IO213PDB3<br>GFC1/IO209PPB3<br>VCCIB3<br>VCC<br>GND<br>GND<br>GND<br>GND<br>VCC<br>VCCIB1<br>GCC1/IO91PPB1<br>IO90NPB1<br>IO88PDB1<br>**FG484**<br>**A3P1000 Function**|
|---|---|---|
**Revision 18**
**4-77**
_Package Pin Assignments_
|K19<br>IO88NDB1<br>K20<br>IO94NPB1<br>K21<br>IO98NDB1<br>K22<br>IO98PDB1<br>L1<br>NC<br>L2<br>IO200PDB3<br>L3<br>IO210NPB3<br>L4<br>GFB0/IO208NPB3<br>L5<br>GFA0/IO207NDB3<br>L6<br>GFB1/IO208PPB3<br>L7<br>VCOMPLF<br>L8<br>GFC0/IO209NPB3<br>L9<br>VCC<br>L10<br>GND<br>L11<br>GND<br>L12<br>GND<br>L13<br>GND<br>L14<br>VCC<br>L15<br>GCC0/IO91NPB1<br>L16<br>GCB1/IO92PPB1<br>L17<br>GCA0/IO93NPB1<br>L18<br>IO96NPB1<br>L19<br>GCB0/IO92NPB1<br>L20<br>IO97PDB1<br>L21<br>IO97NDB1<br>L22<br>IO99NPB1<br>M1<br>NC<br>M2<br>IO200NDB3<br>M3<br>IO206NDB3<br>M4<br>GFA2/IO206PDB3<br>M5<br>GFA1/IO207PDB3<br>M6<br>VCCPLF<br>M7<br>IO205NDB3<br>M8<br>GFB2/IO205PDB3<br>M9<br>VCC<br>M10<br>GND<br>**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>M11<br>GND<br>M12<br>GND<br>M13<br>GND<br>M14<br>VCC<br>M15<br>GCB2/IO95PPB1<br>M16<br>GCA1/IO93PPB1<br>M17<br>GCC2/IO96PPB1<br>M18<br>IO100PPB1<br>M19<br>GCA2/IO94PPB1<br>M20<br>IO101PPB1<br>M21<br>IO99PPB1<br>M22<br>NC<br>N1<br>IO201NDB3<br>N2<br>IO201PDB3<br>N3<br>NC<br>N4<br>GFC2/IO204PDB3<br>N5<br>IO204NDB3<br>N6<br>IO203NDB3<br>N7<br>IO203PDB3<br>N8<br>VCCIB3<br>N9<br>VCC<br>N10<br>GND<br>N11<br>GND<br>N12<br>GND<br>N13<br>GND<br>N14<br>VCC<br>N15<br>VCCIB1<br>N16<br>IO95NPB1<br>N17<br>IO100NPB1<br>N18<br>IO102NDB1<br>N19<br>IO102PDB1<br>N20<br>NC<br>N21<br>IO101NPB1<br>N22<br>IO103PDB1<br>P1<br>NC<br>P2<br>IO199PDB3<br>**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee Os~~<br>~~a ee es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~a ee es es ~~Oo<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee es es~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esfo~~|P3<br>P4<br>P5<br>P6<br>P7<br>P8<br>P9<br>P10<br>P11<br>P12<br>P13<br>P14<br>P15<br>P16<br>P17<br>P18<br>P19<br>P20<br>P21<br>P22<br>R1<br>R2<br>R3<br>R4<br>R5<br>R6<br>R7<br>R8<br>R9<br>R10<br>R11<br>R12<br>R13<br>R14<br>R15<br>R16<br>**Pin Number**|IO199NDB3<br>IO202NDB3<br>IO202PDB3<br>IO196PPB3<br>IO193PPB3<br>VCCIB3<br>GND<br>VCC<br>VCC<br>VCC<br>VCC<br>GND<br>VCCIB1<br>GDB0/IO112NPB1<br>IO106NDB1<br>IO106PDB1<br>IO107PDB1<br>NC<br>IO104PDB1<br>IO103NDB1<br>NC<br>IO197PPB3<br>VCC<br>IO197NPB3<br>IO196NPB3<br>IO193NPB3<br>GEC0/IO190NPB3<br>VMV3<br>VCCIB2<br>VCCIB2<br>IO147RSB2<br>IO136RSB2<br>VCCIB2<br>VCCIB2<br>VMV2<br>IO110NDB1<br>**FG484**<br>**A3P1000 Function**|
|---|---|---|
**4-78**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|R17<br>GDB1/IO112PPB1<br>R18<br>GDC1/IO111PDB1<br>R19<br>IO107NDB1<br>R20<br>VCC<br>R21<br>IO104NDB1<br>R22<br>IO105PDB1<br>T1<br>IO198PDB3<br>T2<br>IO198NDB3<br>T3<br>NC<br>T4<br>IO194PPB3<br>T5<br>IO192PPB3<br>T6<br>GEC1/IO190PPB3<br>T7<br>IO192NPB3<br>T8<br>GNDQ<br>T9<br>GEA2/IO187RSB2<br>T10<br>IO161RSB2<br>T11<br>IO155RSB2<br>T12<br>IO141RSB2<br>T13<br>IO129RSB2<br>T14<br>IO124RSB2<br>T15<br>GNDQ<br>T16<br>IO110PDB1<br>T17<br>VJTAG<br>T18<br>GDC0/IO111NDB1<br>T19<br>GDA1/IO113PDB1<br>T20<br>NC<br>T21<br>IO108PDB1<br>T22<br>IO105NDB1<br>U1<br>IO195PDB3<br>U2<br>IO195NDB3<br>U3<br>IO194NPB3<br>U4<br>GEB1/IO189PDB3<br>U5<br>GEB0/IO189NDB3<br>U6<br>VMV2<br>U7<br>IO179RSB2<br>U8<br>IO171RSB2<br>**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>U9<br>IO165RSB2<br>U10<br>IO159RSB2<br>U11<br>IO151RSB2<br>U12<br>IO137RSB2<br>U13<br>IO134RSB2<br>U14<br>IO128RSB2<br>U15<br>VMV1<br>U16<br>TCK<br>U17<br>VPUMP<br>U18<br>TRST<br>U19<br>GDA0/IO113NDB1<br>U20<br>NC<br>U21<br>IO108NDB1<br>U22<br>IO109PDB1<br>V1<br>NC<br>V2<br>NC<br>V3<br>GND<br>V4<br>GEA1/IO188PDB3<br>V5<br>GEA0/IO188NDB3<br>V6<br>IO184RSB2<br>V7<br>GEC2/IO185RSB2<br>V8<br>IO168RSB2<br>V9<br>IO163RSB2<br>V10<br>IO157RSB2<br>V11<br>IO149RSB2<br>V12<br>IO143RSB2<br>V13<br>IO138RSB2<br>V14<br>IO131RSB2<br>V15<br>IO125RSB2<br>V16<br>GDB2/IO115RSB2<br>V17<br>TDI<br>V18<br>GNDQ<br>V19<br>TDO<br>V20<br>GND<br>V21<br>NC<br>V22<br>IO109NDB1<br>**FG484**<br>**Pin Number**<br>**A3P1000 Function**<br>~~ee Os~~<br>~~a ee es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie~~es~~<br>~~Oo~~<br>~~a ee ~~ie~~Rs~~<br>~~Oo~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~ae~~<br>~~ee ~~ie ~~es~~<br>~~Os~~<br>~~a ee es es ~~Oo<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~ee~~<br>~~ee es es~~<br>~~a ee ~~ie<br>~~esOs~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee~~<br>~~esOs~~<br>~~ee~~<br>~~ee~~<br>~~esOo~~<br>~~a ee ~~i~~es~~<br>~~Os~~<br>~~a ee~~<br>~~esss~~<br>~~ee~~<br>~~ee es es~~<br>~~ee ee ~~ie~~Gs~~<br>~~Os~~<br>~~ee~~<br>~~ee ~~ie ~~es~~<br>~~Oo~~<br>~~ee~~<br>~~ee~~<br>~~esfo~~|W1<br>W2<br>W3<br>W4<br>W5<br>W6<br>W7<br>W8<br>W9<br>W10<br>W11<br>W12<br>W13<br>W14<br>W15<br>W16<br>W17<br>W18<br>W19<br>W20<br>W21<br>W22<br>Y1<br>Y2<br>Y3<br>Y4<br>Y5<br>Y6<br>Y7<br>Y8<br>Y9<br>Y10<br>Y11<br>Y12<br>Y13<br>Y14<br>**Pin Number**|NC<br>IO191PDB3<br>NC<br>GND<br>IO183RSB2<br>GEB2/IO186RSB2<br>IO172RSB2<br>IO170RSB2<br>IO164RSB2<br>IO158RSB2<br>IO153RSB2<br>IO142RSB2<br>IO135RSB2<br>IO130RSB2<br>GDC2/IO116RSB2<br>IO120RSB2<br>GDA2/IO114RSB2<br>TMS<br>GND<br>NC<br>NC<br>NC<br>VCCIB3<br>IO191NDB3<br>NC<br>IO182RSB2<br>GND<br>IO177RSB2<br>IO174RSB2<br>VCC<br>VCC<br>IO154RSB2<br>IO148RSB2<br>IO140RSB2<br>NC<br>VCC<br>**FG484**<br>**A3P1000 Function**|
|---|---|---|
**Revision 18**
**4-79**
_Package Pin Assignments_
|**FG484**|||**FG484**|
|---|---|---|---|
|**Pin Number**<br>**A3P1000 Function**<br>~~a~~||**Pin Number**|**A3P1000 Function**|
|Y15<br>VCC<br>~~a~~||AB7|IO167RSB2|
|Y16<br>NC<br>~~a~~||AB8|IO162RSB2|
|Y17<br>NC<br>Y18<br>GND<br>Y19<br>NC<br>Y20<br>NC<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~||AB9<br>AB10<br>AB11<br>AB12|IO156RSB2<br>IO150RSB2<br>IO145RSB2<br>IO144RSB2|
|Y21<br>NC<br>~~a~~||AB13|IO132RSB2|
|Y22<br>VCCIB1<br>~~a~~||AB14|IO127RSB2|
|AA1<br>GND<br>AA2<br>VCCIB3<br>AA3<br>NC<br>AA4<br>IO181RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~||AB15<br>AB16<br>AB17<br>AB18|IO126RSB2<br>IO123RSB2<br>IO121RSB2<br>IO118RSB2|
|AA5<br>IO178RSB2<br>~~a~~||AB19|NC|
|AA6<br>IO175RSB2<br>~~a~~||AB20|VCCIB2|
|AA7<br>IO169RSB2<br>AA8<br>IO166RSB2<br>AA9<br>IO160RSB2<br>AA10<br>IO152RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~||AB21<br>AB22|GND<br>GND|
|AA11<br>IO146RSB2<br>~~a~~||||
|AA12<br>IO139RSB2<br>~~a~~||||
|AA13<br>IO133RSB2<br>AA14<br>NC<br>AA15<br>NC<br>AA16<br>IO122RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~||||
|AA17<br>IO119RSB2<br>~~a~~||||
|AA18<br>IO117RSB2<br>~~a~~||||
|AA19<br>NC<br>AA20<br>NC<br>AA21<br>VCCIB1<br>AA22<br>GND<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~||||
|AB1<br>GND<br>~~a~~||||
|AB2<br>GND<br>~~a~~||||
|AB3<br>VCCIB2<br>AB4<br>IO180RSB2<br>AB5<br>IO176RSB2<br>AB6<br>IO173RSB2<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||||
**4-80**
**Revision 18**
## **5 – Datasheet Information**
## **List of Changes**
The following table lists critical changes that were made in each version of the ProASIC3 datasheet.
|**Revision**|**Changes**|**Page**|
|---|---|---|
|Revision 18<br>(March 2016)|Updated 3.3 V DC supply voltage's maximum Commercial and Industrial values<br>from 3.3 V to 3.6 V inTable 2-2(SAR 72693).|2-2|
||Added reference of Package Mechanical Drawings document in all package pin<br>assignment notes (76833).|NA|
|Revision 17<br>(June 2015)|Removed PQFP embedded heat spreader info. fromTable 2-5(SAR 52320).|2-6|
||Updated"VCCIBx I/O Supply Voltage"(SAR 43323).|3-1|
|Revision 16<br>(December 2014)|Updated"ProASIC3 Ordering Information". Interchanged the positions of<br>Y- Security Feature and I- Application (Temperature Range) (SAR 61079).<br>Added Note "Only devices with package size greater than or equal to 5x5 are<br>supported".|1-IV|
||Updated Table Note (2) inTable 2-3 • Flash Programming Limits – Retention,<br>Storage and Operating Temperatureso that the Table Note is not applicable for<br>Maximum Storage Temperature TSTG(SAR 54297).|2-3|
||Added values for Drive strength 2 mA inTable 2-41 • 3.3 V LVTTL / 3.3 V<br>LVCMOS High Slew,Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew,<br>Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew, andTable 2-44 • 3.3 V<br>LVTTL / 3.3 V LVCMOS Low Slew(SAR 57184).|2-34,2-35,<br>2-36,2-37|
||AddedFigure 2-1 • High-Temperature Data Retention (HTR)(SAR 45466).|2-3|
||Updates made to maintain the style and consistency of the document.|NA|
|Revision 15<br>(July 2014)|Added corner pad table note (3) to"QN132 – Bottom View"(SAR 47442).|4-6|
||Ambient temperature removed inTable 2-2, table notes and"ProASIC3<br>Ordering Information"figure were modified (SAR 48343).|2-2<br>1-IV|
||Other updates were made to maintain the style and consistency of the<br>datasheet.|NA|
|Revision 14<br>(April 2014)|Note added for the discontinuance of QN132 package to the following tables<br>and section:"ProASIC3 Devices","I/Os Per Package 1","ProASIC3 FPGAs<br>Package Sizes Dimensions"and"QN132 – Bottom View" section(SAR 55118).|I,III,4-6|
**Revision 18**
**5-1**
_ProASIC3 Flash Family FPGAs_
|**Revision**|**Changes**|**Page**|
|---|---|---|
|Revision 13<br>(January 2013)|The"ProASIC3 Ordering Information" sectionhas been updated to mention "Y"<br>as "Blank" mentioning "Device Does Not Include License to Implement IP<br>Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43104).|1-IV|
||Added a note toTable 2-2 • Recommended Operating Conditions 1(SAR<br>43644): The programming temperature range supported is Tambient= 0°C to<br>85°C.|2-2|
||The note inTable 2-115 • ProASIC3 CCC/PLL Specificationreferring the reader<br>to SmartGen was revised to refer instead to the online help associated with the<br>core (SAR 42569).|2-90|
||Libero Integrated Design Environment (IDE) was changed to Libero System-on-<br>Chip (SoC) throughout the document (SAR 40284).<br>Live at Power-Up (LAPU) has been replaced with ’Instant On’.|NA|
|Revision 12<br>(September 2012)|The Security section was modified to clarify that Microsemi does not support<br>read-back of programmed data.|1-1|
||Added a Note stating "VMV pins must be connected to the corresponding VCCI<br>pins. See the"VMVx I/O Supply Voltage (quiet)" section on page 3-1for further<br>information" toTable 2-1 • Absolute Maximum RatingsandTable 2-2 •<br>Recommended Operating Conditions 1(SAR 38321).|2-1<br>2-2|
||Table 2-35 • Duration of Short Circuit Event Before Failurewas revised to<br>change the maximum temperature from 110°C to 100°C, with an example of six<br>months instead of three months (SAR 37933).|2-31|
||InTable 2-93 • Minimum and Maximum DC Input and Output Levels, VIL and<br>VIH were revised so that the maximum is 3.6 V for all listed values of VCCI<br>(SAR 28549).|2-68|
||Figure 2-37 • FIFO ReadandFigure 2-38 • FIFO Writeare new (SAR 28371).|2-99|
||The following sentence was removed from the"VMVx I/O Supply Voltage<br>(quiet)" sectionin the"Pin Descriptions"chapter: "Within the package, the VMV<br>plane is decoupled from the simultaneous switching noise originating from the<br>output buffer VCCI domain" and replaced with “Within the package, the VMV<br>plane biases the input stage of the I/Os in the I/O banks” (SAR 38321). The<br>datasheet mentions that "VMV pins must be connected to the corresponding<br>VCCI pins" for an ESD enhancement.|3-1|
**Revision 18**
**5-2**
_Datasheet Information_
|**Revision**|**Changes**|**Page**|
|---|---|---|
|Revision 11<br>(March 2012)|Note indicating that A3P015 is not recommended for new designs has been<br>added. The"Devices Not Recommended For New Designs" sectionis new<br>(SAR 36760).|ItoIV|
||The following sentence was removed from the Advanced Architecture section:<br>"In addition, extensive on-chip programming circuitry allows for rapid, single-<br>voltage (3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG<br>interface" (SAR 34687).|NA|
||The reference to guidelines for global spines and VersaTile rows, given in the<br>"Global Clock Contribution—PCLOCK" section, was corrected to the "Spine<br>Architecture" section of the Global Resources chapter in the_ProASIC3 FPGA_<br>_Fabric User's Guide_(SAR 34734).|2-12|
||Figure 2-4 • Input Buffer Timing Model and Delays (Example)has been modified<br>for the DIN waveform; the Rise and Fall time label has been changed to tDIN<br>(35430).|2-16|
||The AC Loading figures in the"Single-Ended I/O Characteristics" sectionwere<br>updated to match tables in the"Summary of I/O Timing Characteristics – Default<br>I/O Software Settings" section(SAR 34883).|2-32|
||Added values for minimum pulse width and removed the FRMAX row from<br>Table 2-107throughTable 2-114in the"Global Tree Timing Characteristics"<br>section. Use the software to determine the FRMAX for the device you are using<br>(SARs 37279, 29269).|2-85|
**5-3**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**Revision**|**Changes**|**Page**|
|---|---|---|
|Revision 10<br>(September 2011)|The"In-System Programming (ISP) and Security" sectionand Security section<br>were revised to clarify that although no existing security measures can give an<br>absolute guarantee, Microsemi FPGAs implement the best security available in<br>the industry (SAR 32865).|I|
||The value of 34 I/Os for the QN48 package in A3P030 was added to the"I/Os<br>Per Package 1" section(SAR 33907).|III|
||The Y security option and Licensed DPA Logo were added to the"ProASIC3<br>Ordering Information" section. The trademarked Licensed DPA Logo identifies<br>that a product is covered by a DPA counter-measures license from<br>Cryptography Research (SAR 32151).|IV|
||The "Specifying I/O States During Programming" section is new (SAR 21281).|1-7|
||InTable 2-2 • Recommended Operating Conditions 1, VPUMP programming<br>voltage in programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45"<br>(SAR 30666). It was corrected in v2.0 of this datasheet in April 2007 but<br>inadvertently changed back to “3.0 to 3.6 V” in v1.4 in August 2009. The<br>following changes were made toTable 2-2 • Recommended Operating<br>Conditions 1:<br>VCCPLL analog power supply (PLL) was changed from "1.4 to 1.6" to "1.425 to<br>1.575" (SAR 33850).<br>For VCCI and VMV, values for 3.3 V DC and 3.3 V DC Wide Range were<br>corrected. The correct value for 3.3 V DC is "3.0 to 3.6 V" and the correct value<br>for 3.3 V Wide Range is "2.7 to 3.6" (SAR 33848).|2-2|
||Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings<br>was update to restore values to the correct columns. Previously the Slew Rate<br>column was missing and data were aligned incorrectly (SAR 34034).|2-24|
||The notes regarding drive strength in the"Summary of I/O Timing<br>Characteristics – Default I/O Software Settings" sectionand"3.3 V LVCMOS<br>Wide Range" sectiontables were revised for clarification. They now state that<br>the minimum drive strength for the default software configuration when run in<br>wide range is ±100 µA. The drive strength displayed in software is supported in<br>normal range only. For a detailed I/V curve, refer to the IBIS models (SAR<br>25700).|2-22,2-39|
**Revision 18**
**5-4**
_Datasheet Information_
|**Revision**|**Changes**|**Page**|
|---|---|---|
|Revision 10<br>(continued)|"TBD" for 3.3 V LVCMOS Wide Range inTable 2-28 • I/O Output Buffer<br>Maximum Resistances1throughTable 2-30 • I/O Output Buffer Maximum<br>Resistances1was replaced by "Same as regular 3.3 V" (SAR 33852).|2-26to2-28|
||The equations in the notes forTable 2-31 • I/O Weak Pull-Up/Pull-Down<br>Resistanceswere corrected (SAR 32470).|2-28|
||"TBD" for 3.3 V LVCMOS Wide Range inTable 2-32 • I/O Short Currents<br>IOSH/IOSLthroughTable 2-34 • I/O Short Currents IOSH/IOSLwas replaced<br>by "Same as regular 3.3 V LVCMOS" (SAR 33852).|2-29to2-31|
||In the"3.3 V LVCMOS Wide Range" section, values were added toTable 2-47<br>throughTable 2-49for IOSL and IOSH, replacing "TBD" (SAR 33852).|2-39to2-40|
||The following sentence was deleted from the"2.5 V LVCMOS" section(SAR<br>24916): "It uses a 5 V–tolerant input buffer and push-pull output buffer."|2-47|
||The table notes were revised forTable 2-90 • LVDS Minimum and Maximum DC<br>Input and Output Levels(SAR 33859).|2-66|
||Values were added for FDDRIMAXand FDDOMAXinTable 2-102 • Input DDR<br>Propagation DelaysandTable 2-104 • Output DDR Propagation Delays(SAR<br>23919).|2-78,2-80|
||Table 2-115 • ProASIC3 CCC/PLL Specificationwas updated. A note was<br>added to indicate that when the CCC/PLL core is generated by Microsemi core<br>generator software, not all delay values of the specified delay increments are<br>available (SAR 25705).|2-90|
||The following figures were deleted (SAR 29991). Reference was made to a new<br>application note,_Simultaneous Read-Write Operations in Dual-Port SRAM for_<br>_Flash-Based cSoCs and FPGAs_,which covers these cases in detail (SAR<br>21770).<br>Figure 2-34 • Write Access after Write onto Same Address<br>Figure 2-35 • Read Access after Write onto Same Address<br>Figure 2-35 • Read Access after Write onto Same Address<br>The port names in the SRAM"Timing Waveforms", SRAM"Timing<br>Characteristics"tables,Figure 2-39 • FIFO Reset, and the FIFO"Timing<br>Characteristics"tables were revised to ensure consistency with the software<br>names (SARs 29991, 30510).|2-92,<br>2-94,<br>2-992-102|
||The"Pin Descriptions"chapter has been added (SAR 21642).|3-1|
||Package names used in the"Package Pin Assignments" sectionwere revised<br>to match standards given in_Package Mechanical Drawings_(SAR 27395).|4-1|
|July 2010|The versioning system for datasheets has been changed. Datasheets are<br>assigned a revision number that increments each time the datasheet is revised.<br>The"ProASIC3 Device Status" table on page IVindicates the status for each<br>device in the device family.|N/A|
**Revision 18**
**5-5**
_ProASIC3 Flash Family FPGAs_
|**Revision**<br>~~aEEE~~|**Changes**<br>~~EEE~~|**Page**<br>~~EEE~~|
|---|---|---|
|**Revision 9 (Oct 2009)**<br>Product Brief v1.3<br>Packaging v1.5<br>~~EEE~~|The CS121 package was added to table under"Features and Benefits" section,<br>the"I/Os Per Package 1"table,Table 1 • ProASIC3 FPGAs Package Sizes<br>Dimensions,"ProASIC3 Ordering Information", and the"Temperature Grade<br>Offerings"table.<br>~~EEE~~|I–IV<br>~~EEE~~|
||"ProASIC3 Ordering Information"was revised to include the fact that some RoHS<br>compliant packages are halogen-free.<br>~~EEE~~|IV<br>~~EEE~~|
||The"CS121 – Bottom View"figure and pin table for A3P060 are new.<br>~~EEE~~|4-15<br>~~EEE~~|
|**Revision 8 (Aug 2009)**<br>Product Brief v1.2<br>DC and Switching<br>Characteristics v1.4<br>~~EEE~~<br>~~a~~|All references to M7 devices (CoreMP7) and speed grade –F were removed from<br>this document.<br>~~EEE~~|N/A<br>~~EEE~~|
||Table 1-1 I/O Standards supported is new.|1-7<br>~~ee~~|
||The I/Os with Advanced I/O Standards section was revised to add definitions of<br>hot-swap and cold-sparing.<br>~~ee~~|1-7<br>~~ee~~<br>~~ee~~|
||3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the<br>datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V<br>LVCMOS data.|N/A<br>~~ee~~|
||IILand IIHinput leakage current information was added to all "Minimum and<br>Maximum DC Input and Output Levels" tables.|N/A|
||–F was removed from the datasheet. The speed grade is no longer supported.<br>~~a~~<br>~~a~~|N/A<br>~~a~~<br>|
||The notes inTable 2-2 • Recommended Operating Conditions 1were updated.<br>~~a~~|2-2<br>|
||Table 2-4 • Overshoot and Undershoot Limits 1was updated.<br>~~a~~|2-3<br><br>~~ee~~|
||Table 2-6 • Temperature and Voltage Derating Factors for Timing Delayswas<br>updated.<br>~~ee~~|2-6<br>~~ee~~<br>~~ee~~|
||InTable 2-116 • RAM4K9, the following specifications were removed:<br>tWRO<br>tCCKH|2-96<br>~~ee~~|
||InTable 2-117 • RAM512X18, the following specifications were removed:<br>tWRO<br>tCCKH|2-97|
||In the title ofTable 2-74 • 1.8 V LVCMOS High Slew, VCCI had a typo. It was<br>changed from 3.0 V to 1.7 V.|2-58|
|**Revision 7 (Feb 2009)**<br>Product Brief v1.1<br>||The"Advanced I/O"section was revised to add a bullet regarding wide range<br>power supply voltage support.<br>|I<br>|
||The table under"Features and Benefits" section, was updated to include a value<br>for typical equivalent macrocells for A3P250.<br>|I<br>|
||The QN48 package was added to the following tables: the table under"Features<br>and Benefits" section,"I/Os Per Package 1" "ProASIC3 FPGAs Package Sizes<br>Dimensions", and"Temperature Grade Offerings".<br>The number of singled-ended I/Os for QN68 was added to the"I/Os Per<br>Package 1"table.<br>|N/A<br>|
||The Wide Range I/O Support section is new.<br>|1-7<br>|
|**Revision 6 (Dec 2008)**<br>Packaging v1.4<br>~~BR~~|The"QN48 – Bottom View"section is new.<br>~~BR~~|4-1<br>~~BR~~|
||The"QN68"pin table for A3P030 is new.<br>~~BR~~<br>~~a~~|4-5<br>~~BR~~<br>~~a~~|
**Revision 18**
**5-6**
_Datasheet Information_
|**Revision**|**Changes**|**Page**|
|---|---|---|
|**Revision 5 (Aug 2008)**<br>DC and Switching<br>Characteristics v1.3|TJ, Maximum Junction Temperature, was changed to 100° from 110º in the<br>"Thermal Characteristics" sectionandEQ 1. The calculated result of Maximum<br>Power Allowed has thus changed to 1.463 W from 1.951 W.|2-6|
||Values for the A3P015 device were added toTable 2-7 • Quiescent Supply<br>Current Characteristics.|2-7|
||Values for the A3P015 device were added toTable 2-14 • Different Components<br>Contributing to Dynamic Power Consumption in ProASIC3 Devices. PAC14was<br>removed.Table 2-15 • Different Components Contributing to the Static Power<br>Consumption in ProASIC3 Devicesis new.|2-11,2-12|
||The"PLL Contribution—PPLL" sectionwas updated to change the PPLLformula<br>from PAC13+ PAC14* FCLKOUTto PDC4+ PAC13* FCLKOUT.|2-14|
||Both fall and rise values were included for tDDRISUDand tDDRIHDinTable 2-102 •<br>Input DDR Propagation Delays.|2-78|
||Table 2-107 • A3P015 Global Resourceis new.|2-86|
||The typical value for Delay Increments in Programmable Delay Blocks was<br>changed from 160 to 200 inTable 2-115 • ProASIC3 CCC/PLL Specification.|2-90|
|**Revision 4 (Jun 2008)**<br>DC and Switching<br>Characteristics v1.2|Table note references were added toTable 2-2 • Recommended Operating<br>Conditions 1, and the order of the table notes was changed.|2-2|
||The title forTable 2-4 • Overshoot and Undershoot Limits 1was modified to<br>remove "as measured on quiet I/Os." Table note 1 was revised to remove<br>"estimated SSO density over cycles." Table note 2 was revised to remove "refers<br>only to overshoot/undershoot limits for simultaneous switching I/Os."|2-3|
||The"Power per I/O Pin" sectionwas updated to include 3 additional tables<br>pertaining to input buffer power and output buffer power.|2-7|
||Table 2-29 • I/O Output Buffer Maximum Resistances 1was revised to include<br>values for 3.3 V PCI/PCI-X.|2-27|
||Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levelswas<br>updated.|2-66|
|**Revision 3 (Jun 2008)**<br>Packaging v1.3|Pin numbers were added to the"QN68 – Bottom View"package diagram. Note 2<br>was added below the diagram.|4-3|
||The"QN132 – Bottom View"package diagram was updated to include D1 to D4.<br>In addition, note 1 was changed from top view to bottom view, and note 2 is new.|4-6|
|**Revision 2 (Feb 2008)**<br>Product Brief v1.0|This document was divided into two sections and given a version number, starting<br>at v1.0. The first section of the document includes features, benefits, ordering<br>information, and temperature and speed grade offerings. The second section is a<br>device family overview.|N/A|
||This document was updated to include A3P015 device information. QN68 is a<br>new package that was added because it is offered in the A3P015. The following<br>sections were updated:<br>"Features and Benefits"<br>"ProASIC3 Ordering Information"<br>"Temperature Grade Offerings"<br>"ProASIC3 Flash Family FPGAs"<br>"A3P015 and A3P030"note<br>Introduction and Overview (NA)|N/A|
**Revision 18**
**5-7**
_ProASIC3 Flash Family FPGAs_
|**Revision**<br>~~a~~|**Changes**<br>|**Page**|
|---|---|---|
|**Revision 2 (cont’d)**<br>Packaging v1.2<br>~~——~~|The"ProASIC3 FPGAs Package Sizes Dimensions"table is new.<br>~~——~~|III|
||In the"ProASIC3 Ordering Information", the QN package measurements were<br>updated to include both 0.4 mm and 0.5 mm.<br>~~——~~|IV|
||In the General Description section the number of I/Os was updated from 288 to<br>300.<br>~~——~~|1-1|
||The"QN68 – Bottom View" sectionis new.<br>~~——~~|4-3|
|**Revision 1 (Feb 2008)**<br>DC and Switching<br>Characteristics v1.1<br>Packaging v1.1<br>~~=~~|InTable 2-2 • Recommended Operating Conditions 1, TJwas listed in the symbol<br>column and was incorrect. It was corrected and changed to TA.<br>~~Se~~<br>~~=~~|2-2<br>~~Se~~<br>~~=~~|
||InTable 2-3 • Flash Programming Limits – Retention, Storage and Operating<br>Temperature, Maximum Operating Junction Temperature was changed from<br>110°C to 100°C for both commercial and industrial grades.<br>~~=~~|2-3<br>~~=~~|
||The"PLL Behavior at Brownout Condition" sectionis new.<br>~~=~~|2-4<br>~~=~~|
||In the"PLL Contribution—PPLL" section, the following was deleted:<br>FCLKIN is the input clock frequency.<br>~~=~~|2-14<br>~~=~~|
||InTable 2-21 • Summary of Maximum and Minimum DC Input Levels, the note<br>was incorrect. It previously said TJand it was corrected and changed to TA.<br>~~=~~|2-21<br>~~=~~|
||InTable 2-115 • ProASIC3 CCC/PLL Specification, the SCLK parameter and note<br>1 are new.<br>~~=~~|2-90<br>~~=~~|
||Table 2-125 • JTAG 1532was populated with the parameter data, which was not<br>in the previous version of the document.<br>~~=~~|2-108<br>~~=~~|
||In the"VQ100"A3P030 pin table, the function of pin 63 was incorrect and<br>changed from IO39RSB0 to GDB0/IO38RSB0.<br>~~=~~|4-19<br>~~=~~|
|**Revision 0 (Jan 2008)**|This document was previously in datasheet v2.2. As a result of moving to the<br>handbook format, Actel has restarted the version numbers.|N/A|
|v2.2<br>(July 2007)|The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3<br>Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering<br>Information", "Temperature Grade Offerings", and "Speed Grade and<br>Temperature Grade Matrix".|i, ii, iii,<br>iii, iv|
||The words "ambient temperature" were added to the temperature range in the<br>"Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings",<br>and "Speed Grade and Temperature Grade Matrix" sections.|iii, iv|
||The TJparameter in Table 3-2 • Recommended Operating Conditions was<br>changed to TA, ambient temperature, and table notes 4–6 were added.|3-2|
|v2.1<br>(May 2007)<br>~~a~~|In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input<br>Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).<br>~~a~~|i<br>~~a~~|
||The "Clock Conditioning Circuit (CCC) and PLL" section was updated.<br>~~a~~|i<br>~~a~~|
||In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and<br>A3P600 device I/Os were updated.<br>~~a~~|ii<br>~~a~~|
||Table 3-5 • Package Thermal Resistivities was updated with A3P1000<br>information. The note below the table is also new.<br>~~a~~|3-5<br>~~a~~|
_Datasheet Information_
|**Revision**<br>~~a ~~|**Changes**<br>|**Page**<br>|
|---|---|---|
|v2.0<br>(April 2007)<br> <br>~~a~~<br>~~a~~<br>~~a~~|In the "Packaging Tables", Ambient was deleted.<br>|ii<br>|
||The timing characteristics tables were updated.<br> ~~a~~|N/A<br>~~a~~|
||The "PLL Macro" section was updated to add information on the VCO and PLL<br>outputs during power-up.|2-15|
||The "PLL Macro" section was updated to include power-up information.<br>~~a~~<br>~~a~~|2-15<br>~~a~~|
||Table 2-11 • ProASIC3 CCC/PLL Specification was updated.<br>~~a~~<br>~~a~~|2-29|
||Figure 2-19 • Peak-to-Peak Jitter Definition is new.<br>~~a~~<br>~~a~~|2-18|
||The "SRAM and FIFO" section was updated with operation and timing<br>requirement information.<br>~~a~~<br>~~a~~|2-21<br>|
||The "RESET" section was updated with read and write information.<br>~~a~~|2-25<br>|
||The "RESET" section was updated with read and write information.<br>~~a~~|2-25<br><br>~~ee~~|
||The "Introduction" in the "Advanced I/Os" section was updated to include<br>information on input and output buffers being disabled.<br>~~ee~~|2-28<br>~~ee~~<br>~~ee~~|
||PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible<br>Standards.|2-29<br>~~ee~~|
||In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance<br>descriptions were updated for levels 3 and 4.|2-34|
||Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3<br>Devices was updated.|2-64|
||Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–<br>Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum<br>current was updated from 4 x 52.7 to 5 x 52.7.|2-40|
||The "VCCPLF PLL Supply Voltage" section was updated.<br>~~a~~|2-50<br>~~a~~|
||The "VPUMP Programming Supply Voltage" section was updated.|2-50<br>~~ee~~|
||The "GL Globals" section was updated to include information about direct input<br>into quadrant clocks.<br>~~ee~~|2-51<br>~~ee~~<br>~~ee~~|
||VJTAGwas deleted from the "TCK Test Clock" section.|2-51<br>~~ee~~<br>~~ee~~|
||In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK<br>was changed to TCK in note 2. Note 3 was also updated.<br>~~ee~~|2-51<br>~~ee~~<br>~~ee~~|
||Ambient was deleted from Table 3-2 • Recommended Operating Conditions.<br>VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".|3-2<br>~~ee~~|
||Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on<br>quiet I/Os)1.|3-2|
||In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.|3-5<br>~~ee~~|
||Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was<br>updated.<br>~~ee~~|3-6<br>~~ee~~<br>~~ee~~|
||Table 3-5 • Package Thermal Resistivities was updated.|3-5<br>~~ee~~|
||Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels<br>Applicable to Commercial and Industrial Conditions—Software Default Settings<br>(Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input<br>Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were<br>updated.<br>~~Pf~~|3-17 to 3-<br>17<br>~~Pf~~|
**5-9 Revision 18**
_ProASIC3 Flash Family FPGAs_
|**Revision**<br>~~a~~|**Changes**|**Page**|
|---|---|---|
|v2.0<br>(continued)<br>~~a~~<br>~~a~~<br>~~a~~|Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings<br>(Advanced) and Table 3-21 • Summary of I/O Timing Characteristics—Software<br>Default Settings (Standard Plus) were updated.|3-20 to<br>3-20|
||Table 3-11 • Different Components Contributing to Dynamic Power Consumption<br>in ProASIC3 Devices was updated.|3-9|
||Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-<br>25 • I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.|3-22 to<br>3-22|
||Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to<br>Commercial and Industrial Conditions was updated.|3-18|
||Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O<br>Short Currents IOSH/IOSL (Standard Plus) were updated.|3-24 to<br>3-26|
||The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O<br>Reliability was updated.|3-27|
||Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read<br>Access After Write onto Same Address, and Figure 3-35 • Write Access After<br>Read onto Same Address are new.<br>~~a~~|3-82 to<br>3-84<br>|
||Figure 3-43 • Timing Diagram was updated.<br>~~a~~|3-96<br>|
||Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".<br>~~a~~|iv<br><br>~~ee~~|
||Notes were added to the package diagrams identifying if they were top or bottom<br>view.<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|
||The A3P030 "132-Pin QFN" table is new.<br>~~a~~|4-2<br>~~ee~~<br>~~a~~|
||The A3P060 "132-Pin QFN" table is new.<br>~~a~~<br>~~a~~|4-4<br>~~a~~<br>|
||The A3P125 "132-Pin QFN" table is new.<br>~~a~~|4-6<br>|
||The A3P250 "132-Pin QFN" table is new.<br>~~aa~~<br>~~a~~|4-8<br>~~a~~|
||The A3P030 "100-Pin VQFP" table is new.<br>~~a~~|4-11|
|Advance v0.7<br>(January 2007)<br>~~a~~|In the "I/Os Per Package" table, the I/O numbers were added for A3P060,<br>A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77.<br>~~a~~|ii|
|Advance v0.6<br>(April 2006)<br>~~a~~<br>~~a~~|The term flow-through was changed to pass-through.|N/A|
||Table 1 was updated to include the QN132.|ii<br>~~ee~~|
||The "I/Os Per Package" table was updated with the QN132. The footnotes were<br>also updated. The A3P400-FG144 I/O count was updated.<br>~~ee~~|ii<br>~~ee~~<br>~~ee~~|
||"Automotive ProASIC3 Ordering Information" was updated with the QN132.<br>~~a~~|iii<br>~~ee~~<br>~~a~~|
||"Temperature Grade Offerings" was updated with the QN132.<br>~~a~~<br>~~a~~|iii<br>~~a~~<br>|
||B-LVDS and M-LDVS are new I/O standards added to the datasheet.<br>~~a~~|N/A<br>|
||The term flow-through was changed to pass-through.<br>~~aa~~<br>~~a~~|N/A<br>~~a~~<br>~~a~~|
||Figure 2-7 • Efficient Long-Line Resources was updated.<br>~~a~~|2-7<br>~~a~~|
||The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF,<br>CLKBUF_LVDS/LVPECL, and CLKINT were updated.<br>~~a~~|2-16<br>~~a~~|
||The Delay Increments in the Programmable Delay Blocks specification in Figure<br>2-24 • ProASIC3E CCC Options.|2-24|
||The "SRAM and FIFO" section was updated.<br>~~a~~|2-21<br>~~a~~|
**Revision 18**
**5-10**
_Datasheet Information_
|**Revision**<br>~~a~~<br>~~a~~|**Changes**<br>~~a~~|**Page**<br>|
|---|---|---|
|Advance v0.6<br>(continued)<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|The "RESET" section was updated.<br>~~a~~|2-25<br>|
||The "WCLK and RCLK" section was updated.<br>~~aa~~|2-25<br>~~a~~|
||The "RESET" section was updated.<br>~~a~~|2-25<br>~~a~~|
||The "RESET" section was updated.<br>~~es~~<br>~~a~~|2-27<br>~~es~~|
||The "Introduction" of the "Advanced I/Os" section was updated.<br>~~a~~|2-28|
||The "I/O Banks" section is new. This section explains the following types of I/Os:<br>Advanced<br>Standard+<br>Standard<br>Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is<br>new. This table describes the standards listed above.<br>~~a~~|2-29|
||PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-<br>11 • VCCI Voltages and Compatible Standards|2-29|
||Table 2-13 • ProASIC3 I/O Features was updated.|2-30<br>~~ee~~|
||The "Double Data Rate (DDR) Support" section was updated to include<br>information concerning implementation of the feature.<br>~~ee~~|2-32<br>~~ee~~<br>~~ee~~|
||The "Electrostatic Discharge (ESD) Protection" section was updated to include<br>testing information.|2-35<br>~~ee~~|
||Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V<br>Input Tolerance Capabilities in ProASIC3 Devices.|2-64|
||The notes in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in<br>ProASIC3 Devices were updated.|2-64|
||The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"<br>section is new.|2-41|
||A footnote was added to Table 2-14 • Maximum I/O Frequency for Single-Ended<br>and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum<br>drive strength and high slew selected).|2-30|
||Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications<br>~~a~~|2-45<br>~~ee~~|
||Table 2-50 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type<br>(A3P030 device)<br>~~ee~~<br>~~a~~|2-83<br>~~ee~~<br>~~ee~~|
||Table 2-51 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated.<br>~~a~~<br>~~a~~|2-84<br>~~ee~~<br>|
||Table 2-54 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated.<br>~~a~~<br>~~a~~|2-84<br>~~ee~~<br>|
||The "x" was updated in the "User I/O Naming Convention" section.<br>~~aa~~|2-48<br>~~a~~|
||The "VCC Core Supply Voltage" pin description was updated.<br>~~a~~|2-50<br>~~a~~|
||The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include<br>information concerning leaving the pin unconnected.|2-50|
||The "VJTAG JTAG Supply Voltage" pin description was updated.|2-50<br>~~ee~~|
||The "VPUMP Programming Supply Voltage" pin description was updated to<br>include information on what happens when the pin is tied to ground.<br>~~ee~~|2-50<br>~~ee~~<br>~~ee~~|
||The "I/O User Input/Output" pin description was updated to include information on<br>what happens when the pin is unused.|2-50<br>~~ee~~|
||The "JTAG Pins" section was updated to include information on what happens<br>when the pin is unused.|2-51|
**5-11**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**Revision**<br>~~ee~~|**Changes**<br>~~Re~~|**Page**<br>~~Re~~|
|---|---|---|
|Advance v0.6<br>(continued)<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~a~~|The "Programming" section was updated to include information concerning<br>serialization.<br>~~Re~~|2-53<br>~~Re~~|
||The "JTAG 1532" section was updated to include SAMPLE/PRELOAD<br>information.|2-54|
||"DC and Switching Characteristics" chapter was updated with new information.<br>~~ee~~|3-1<br>~~ee~~|
||The A3P060 "100-Pin VQFP" pin table was updated.<br>~~ee~~|4-13<br>~~ee~~|
||The A3P125 "100-Pin VQFP" pin table was updated.<br>~~ee~~|4-13<br>~~ee~~|
||The A3P060 "144-Pin TQFP" pin table was updated.<br>~~ee~~|4-16<br>~~ee~~|
||The A3P125 "144-Pin TQFP" pin table was updated.<br>~~ee~~|4-18<br>~~ee~~|
||The A3P125 "208-Pin PQFP" pin table was updated.<br>~~ee~~<br>~~a~~|4-21<br>~~ee~~<br>|
||The A3P400 "208-Pin PQFP" pin table was updated.<br>~~a~~|4-25<br>|
||The A3P060 "144-Pin FBGA" pin table was updated.<br>~~aee~~|4-32<br>~~ee~~|
||The A3P125 "144-Pin FBGA" pin table is new.<br>~~ee~~|4-34<br>~~ee~~|
||The A3P400 "144-Pin FBGA" is new.<br>~~ee~~|4-38<br>~~ee~~|
||The A3P400 "256-Pin FBGA" was updated.<br>~~ee~~|4-48<br>~~ee~~|
||The A3P1000 "256-Pin FBGA" was updated.<br>~~ee~~<br>~~a~~|4-54<br>~~ee~~<br>|
||The A3P400 "484-Pin FBGA" was updated.<br>~~a~~|4-58<br>|
||The A3P1000 "484-Pin FBGA" was updated.<br>~~aee~~|4-68<br>~~ee~~|
||The A3P250 "100-Pin VQFP*" pin table was updated.<br>~~ee~~|4-14<br>~~ee~~|
||The A3P250 "208-Pin PQFP*" pin table was updated.<br>~~ee~~|4-23<br>~~ee~~|
||The A3P1000 "208-Pin PQFP*" pin table was updated.<br>~~ee~~|4-29<br>~~ee~~|
||The A3P250 "144-Pin FBGA*" pin table was updated.<br>~~ee~~<br>~~a~~|4-36<br>~~ee~~<br>|
||The A3P1000 "144-Pin FBGA*" pin table was updated.<br>~~a~~|4-32<br>|
||The A3P250 "256-Pin FBGA*" pin table was updated.<br>~~aee~~|4-45<br>~~ee~~|
||The A3P1000 "256-Pin FBGA*" pin table was updated.<br>~~ee~~|4-54<br>~~ee~~|
||The A3P1000 "484-Pin FBGA*" pin table was updated.<br>~~ee~~|4-68<br>~~ee~~|
|Advance v0.5<br>(November 2005)<br>~~BR~~|The "I/Os Per Package" table was updated for the following devices and<br>packages:<br>Device<br>Package<br>A3P250/M7ACP250<br>VQ100<br>A3P250/M7ACP250<br>FG144<br>A3P1000<br>FG256<br>~~R~~|ii|
|Advance v0.4<br>~~BR~~|M7 device information is new.<br>~~R~~|N/A|
||The I/O counts in the "I/Os Per Package" table were updated.<br>~~R~~<br>~~ee~~|ii<br>~~ee~~|
|Advance v0.3<br>~~BR~~|The "I/Os Per Package" table was updated.<br>~~R~~<br>~~ee~~|ii<br>~~ee~~|
||M7 device information is new.<br>~~ee~~|N/A<br>~~ee~~|
||Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include<br>the number or rows in each top or bottom spine.|2-16|
||EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options.<br>~~a~~|2-24<br>~~a~~|
**Revision 18**
**5-12**
_Datasheet Information_
|**Revision**<br>~~ee~~|**Changes**<br>~~Re~~|**Page**<br>~~Re~~|
|---|---|---|
|Advance v0.3<br>~~ee~~<br>~~a~~|The "PLL Macro" section was updated. EXTFB information was removed from<br>this section.<br>~~Re~~|2-15<br>~~Re~~|
||The CCC Output Peak-to-Peak Period Jitter FCCC_OUTwas updated in Table 2-<br>11 • ProASIC3 CCC/PLL Specification|2-29|
||EXTFB was removed from Figure 2-27 • CCC/PLL Macro.<br>~~ee~~|2-28<br>~~ee~~|
||Table 2-13 • ProASIC3 I/O Features was updated.<br>~~ee~~|2-30<br>~~ee~~|
||The "Hot-Swap Support" section was updated.<br>~~ee~~|2-33<br>~~ee~~|
||The "Cold-Sparing Support" section was updated.<br>~~ee~~|2-34<br>~~ee~~|
||"Electrostatic Discharge (ESD) Protection" section was updated.|2-35<br>~~ee~~|
||The LVPECL specification in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance<br>Capabilities in ProASIC3 Devices was updated.<br>~~ee~~|2-64<br>~~ee~~<br>~~ee~~|
||In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was<br>changed to VCCIB1.|2-97<br>~~ee~~|
||The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"<br>section.|2-50|
||The "JTAG Pins" section was updated.<br>~~ee~~<br>~~a~~|2-51<br>~~ee~~<br>|
||"128-Bit AES Decryption" section was updated to include M7 device information.<br>~~a~~|2-53<br>|
||Table 3-6 was updated.<br>~~aee~~|3-6<br>~~ee~~|
||Table 3-7 was updated.<br>~~ee~~|3-6<br>~~ee~~|
||In Table 3-11, PAC4 was updated.<br>~~ee~~|3-93-8<br>~~ee~~|
||Table 3-20 was updated.<br>~~ee~~|3-20<br>~~ee~~|
||The note in Table 3-32 was updated.|3-27<br>~~ee~~|
||All Timing Characteristics tables were updated from LVTTL to Register Delays<br>~~ee~~|3-31 to 3-<br>73<br>~~ee~~<br>~~ee~~|
||The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.|3-85 to<br>3-90<br>~~ee~~|
||FTCKMAXwas updated in Table 3-110.<br>~~ee~~|3-97<br>~~ee~~|
|Advance v0.2<br>~~a~~<br>~~a~~|Figure 2-11 was updated.<br>~~ee~~<br>~~a~~|2-9<br>~~ee~~<br>|
||The "Clock Resources (VersaNets)" section was updated.<br>~~a~~|2-9<br>|
||The "VersaNet Global Networks and Spine Access" section was updated.<br>~~aee~~|2-9<br>~~ee~~|
||The "PLL Macro" section was updated.<br>~~ee~~|2-15<br>~~ee~~|
||Figure 2-27 was updated.<br>~~ee~~|2-28<br>~~ee~~|
||Figure 2-20 was updated.<br>~~ee~~|2-19<br>~~ee~~|
||Table 2-5 was updated.<br>~~ee~~<br>~~a~~|2-25<br>~~ee~~<br>|
||Table 2-6 was updated.<br>~~a~~|2-25<br>|
||The "FIFO Flag Usage Considerations" section was updated.<br>~~aee~~|2-27<br>~~ee~~|
||Table 2-13 was updated.<br>~~ee~~|2-30<br>~~ee~~|
||Figure 2-24 was updated.<br>~~ee~~|2-31<br>~~ee~~|
||The "Cold-Sparing Support" section is new.<br>~~ee~~|2-34<br>~~ee~~|
**5-13**
**Revision 18**
_ProASIC3 Flash Family FPGAs_
|**Revision**|**Changes**|**Page**|
|---|---|---|
|Advance v0.2,<br>(continued)|Table 2-43 was updated.|2-64|
||Table 2-18 was updated.|2-45|
||Pin descriptions in the "JTAG Pins" section were updated.|2-51|
||The "User I/O Naming Convention" section was updated.|2-48|
||Table 3-7 was updated.|3-6|
||The "Methodology" section was updated.|3-10|
||Table 3-40 and Table 3-39 were updated.|3-33,3-32|
||The A3P250 "100-Pin VQFP*" pin table was updated.|4-14|
||The A3P250 "208-Pin PQFP*" pin table was updated.|4-23|
||The A3P1000 "208-Pin PQFP*" pin table was updated.|4-29|
||The A3P250 "144-Pin FBGA*" pin table was updated.|4-36|
||The A3P1000 "144-Pin FBGA*" pin table was updated.|4-32|
||The A3P250 "256-Pin FBGA*" pin table was updated.|4-45|
||The A3P1000 "256-Pin FBGA*" pin table was updated.|4-54|
||The A3P1000 "484-Pin FBGA*" pin table was updated.|4-68|
**Revision 18**
**5-14**
_Datasheet Information_
## **Datasheet Categories**
## _**Categories**_
In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "ProASIC3 Device Status" table on page IV, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
## _**Product Brief**_
The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information.
## _**Advance**_
This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.
## _**Preliminary**_
The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
## _**Unmarked (production)**_
This version contains information that is considered to be final.
## **Export Administration Regulations (EAR)**
The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
## **Safety Critical, Life Support, and High-Reliability Applications Policy**
The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information.
**5-15**
**Revision 18**
Microsemi Corporation (MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet Solutions; Power-overEthernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 4,800 employees globally. Learn more at **www.microsemi.com** .
## **Microsemi Corporate Headquarters**
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## **E-mail: sales.support@microsemi.com**
© 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.
51700097-18/0316
Updated at June 9, 2026
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